Data processing method, device and related products

Abstract

The present disclosure relates to a data processing method and device, as well as related products. The product includes a control module, which includes: an instruction cache unit, an instruction processing unit, and a storage queue unit; the instruction cache unit is used to store calculation instructions associated with the artificial neural network operation; the instruction processing unit is used to parse the calculation instructions to obtain multiple operation instructions; the storage queue unit is used to store an instruction queue, which includes: multiple operation instructions or calculation instructions to be executed in the order of the queue. Through the above method, the present disclosure can improve the operational efficiency of related products when performing neural network model operations.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, and in particular to a data processing method and device and related products. Background Art

[0002] With the development of artificial intelligence technology, it has achieved remarkable results in fields such as image recognition. During the image recognition process, it may be necessary to process a large number of discrete data points (for example, performing interpolation operations). However, the processing of discrete data points in related technologies is relatively complex and has a high data overhead. Summary of the Invention

[0003] Based on this, it is necessary to provide a data processing method and device and related products to address the above technical issues.

[0004] According to one aspect of the present disclosure, there is provided a data processing method, comprising:

[0005] When the decoded processing instruction is a data transfer instruction, determining a transfer mode of the data transfer instruction;

[0006] When the data transfer instruction has a multi-vector transfer mode, determining first source data addresses and first destination data addresses of a plurality of first data points, and second source data addresses and second destination data addresses of a plurality of second data points in an operation domain of the data transfer instruction;

[0007] storing the first data point read from the first source data address to the first destination data address to obtain first vector data;

[0008] storing the second data point read from the second source data address to the second destination data address to obtain second vector data;

[0009] The first source data address and the second source data address include a plurality of discrete data addresses, and the first destination data address and the second destination data address include continuous data addresses.

[0010] According to another aspect of the present disclosure, there is provided a data processing apparatus, comprising:

[0011] a mode determination module, configured to determine a data transfer mode of the data transfer instruction when the decoded processing instruction is a data transfer instruction;

[0012] an address determination module configured to determine, when a transfer mode of the data transfer instruction is a multi-vector transfer mode, first source data addresses and first destination data addresses of a plurality of first data points in an operation domain of the data transfer instruction, and second source data addresses and second destination data addresses of a plurality of second data points;

[0013] A first storage module is configured to store a first data point read from the first source data address to the first destination data address to obtain first vector data;

[0014] A second storage module is configured to store the second data point read from the second source data address to the second destination data address to obtain second vector data;

[0015] The first source data address and the second source data address include a plurality of discrete data addresses, and the first destination data address and the second destination data address include continuous data addresses.

[0016] According to another aspect of the present disclosure, an artificial intelligence chip is provided, wherein the chip includes the above-mentioned data processing device.

[0017] According to another aspect of the present disclosure, an electronic device is provided, comprising the above-mentioned artificial intelligence chip.

[0018] According to another aspect of the present disclosure, a board is provided, comprising: a storage device, an interface device, a control device, and the above-mentioned artificial intelligence chip;

[0019] The artificial intelligence chip is connected to the memory device, the control device, and the interface device respectively; the memory device is used to store data;

[0020] The interface device is used to realize data transmission between the artificial intelligence chip and external equipment;

[0021] The control device is used to monitor the status of the artificial intelligence chip.

[0022] According to the embodiments of the present disclosure, discrete data can be moved to multiple consecutive data addresses through a data moving instruction to obtain multiple vector data for vector operations and other processing, thereby simplifying the processing process and reducing data overhead.

[0023] By deducing the technical features in the claims, the beneficial effects of the technical problems in the background technology can be achieved. Other features and aspects of the present disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate exemplary embodiments, features, and aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

[0025] Figure 1A schematic diagram illustrating a processor of a data processing method according to an embodiment of the present disclosure.

[0026] Figure 2 A flow chart of a data processing method according to an embodiment of the present disclosure is shown.

[0027] Figure 3 A block diagram illustrating a data processing device according to an embodiment of the present disclosure is shown.

[0028] Figure 4 A structural block diagram of a board according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0029] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the embodiments described are part of the embodiments of the present disclosure, not all of them. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without making any creative efforts shall fall within the scope of protection of the present disclosure.

[0030] It should be understood that the terms “include” and “comprising” used in the description and claims of the present disclosure indicate the presence of described features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or collections thereof.

[0031] It should also be understood that the terms used in this disclosure are for the purpose of describing specific embodiments only and are not intended to limit the present disclosure. As used in this disclosure and the claims, the singular forms "a," "an," and "the" are intended to include the plural forms unless the context clearly indicates otherwise. It should further be understood that the term "and / or" as used in this disclosure and the claims refers to any and all possible combinations of one or more of the associated listed items, including and including these combinations.

[0032] As used in this specification and claims, the term "if" can be interpreted as "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" can be interpreted as meaning "upon determination" or "in response to determining" or "upon detection of [described condition or event]" or "in response to detecting [described condition or event]," depending on the context.

[0033] The data processing method according to the embodiment of the present disclosure can be applied to a processor, which can be a general-purpose processor, such as a CPU (Central Processing Unit), or an artificial intelligence processor (IPU) for performing artificial intelligence operations. Artificial intelligence operations may include machine learning operations, brain-like operations, etc. Among them, machine learning operations include neural network operations, k-means operations, support vector machine operations, etc. The artificial intelligence processor may, for example, include one or a combination of GPU (Graphics Processing Unit), NPU (Neural-Network Processing Unit), DSP (Digital Signal Process), and Field-Programmable Gate Array (FPGA) chips. The present disclosure does not limit the specific type of processor.

[0034] In one possible implementation, the processor mentioned in this disclosure may include multiple processing units, each of which can independently execute various assigned tasks, such as convolution tasks, pooling tasks, or fully connected tasks. This disclosure does not limit the processing units or the tasks they execute.

[0035] Figure 1 Schematic diagram of a processor of a data processing method according to an embodiment of the present disclosure. Figure 1 As shown, processor 100 includes multiple processing units 101 and a storage unit 102. Multiple processing units 101 are used to execute instruction sequences, and storage unit 102 is used to store data, which may include random access memory (RAM) and a register file. Multiple processing units 101 in processor 100 can share some storage space, such as some RAM storage space and register file, or have their own storage space.

[0036] Figure 2 FIG. 1 is a flow chart showing a data processing method according to an embodiment of the present disclosure. Figure 2 As shown, the method includes:

[0037] In step S11: when the decoded processing instruction is a data transfer instruction, determining a transfer mode of the data transfer instruction;

[0038] In step S12: when the transfer mode of the data transfer instruction is the multi-vector transfer mode, first source data addresses and first destination data addresses of a plurality of first data points, and second source data addresses and second destination data addresses of a plurality of second data points in an operation domain of the data transfer instruction are determined.

[0039] In step S13, the first data point read from the first source data address is stored in the first destination data address to obtain first vector data;

[0040] In step S14, the second data point read from the second source data address is stored in the second destination data address to obtain second vector data;

[0041] The first source data address and the second source data address include a plurality of discrete data addresses, and the first destination data address and the second destination data address include continuous data addresses.

[0042] According to the embodiments of the present disclosure, discrete data can be moved to multiple consecutive data addresses through a data moving instruction to obtain multiple vector data for vector operations and other processing, thereby simplifying the processing process and reducing data overhead.

[0043] In a possible implementation, the method further includes: decoding the received processing instruction to obtain a decoded processing instruction, wherein the decoded processing instruction includes an operation code, and the operation code is used to instruct data transfer processing.

[0044] For example, when a processor receives a processing instruction, it may decode the received processing instruction to obtain a decoded processing instruction. The decoded processing instruction includes an opcode and an operation field. The opcode is used to indicate the processing type of the processing instruction, and the operation field is used to indicate the data to be processed and the data parameters. If the opcode of the decoded processing instruction indicates data transfer processing, the instruction is a data transfer instruction (Gather Load).

[0045] In a possible implementation, if the decoded processing instruction is a data transfer instruction, a transfer mode (for example, expressed as Gather Load Offset Mode) of the data transfer instruction may be determined in step S11.

[0046] In one possible implementation, the transport mode of the data transport instruction may be pre-set to include a single-vector transport mode (e.g., represented as Mode0), a multi-vector transport mode (e.g., represented as Mode1), etc. In the single-vector transport mode, the data transport instruction may aggregate multiple discrete data points into one vector data; in the multi-vector transport mode, the data transport instruction may aggregate multiple discrete data points into two or more vector data. The transport mode may be determined based on a field in the operation domain of the data transport instruction that indicates the transport mode, such as the field Mode0 or Mode1, and this disclosure does not impose any restrictions on this.

[0047] When it is necessary to move pairs or groups of discrete points for calculations (such as difference operations), since adjacent points are generally in the same cache space (cache line), the multi-vector transfer mode can be used to obtain two or more data points by taking a data point once, and ultimately generating two or more different vectors, which facilitate vector operations to produce the final result (such as a difference vector).

[0048] In one possible implementation, if the data transfer instruction uses a multi-vector transfer mode, the source data address and destination data address of each data point to be transferred can be determined in step S12. The source data address represents the current data storage address of the multiple data points in the data storage space and is a discrete plurality of data addresses; the destination data address represents the data address of the data storage space to which the multiple data points will be transferred and is a continuous data address. The data storage space where the source data address is located and the data storage space where the destination data address is located can be the same or different, and this disclosure is not limited thereto.

[0049] In one possible implementation, in a multi-vector transfer mode, at least two vectors may be obtained, the first vector may be set as first vector data, and the other vectors may be set as second vector data (including at least one vector data). A plurality of first data points corresponding to the first vector data have a first source data address and a first destination data address, and a plurality of second data points corresponding to the second vector data have a second source data address and a second destination data address.

[0050] In one possible implementation, after determining the source data address and destination data address of the first data point and the second data point, the processor may read a plurality of discrete first data points from the first source data address respectively in step S13, and store the read plurality of first data points in the first destination data address to obtain first vector data of a preset length, and the processor may read a plurality of discrete second data points from the second source data address respectively in step S14, and store the read plurality of second data points in the second destination data address to obtain second vector data of a preset length, thereby completing the multi-vector data handling process.

[0051] In one possible implementation, after completing the multi-vector data transfer, the multiple vector data can be further processed through data operation instructions, such as four arithmetic operations between two or more vector data, such as difference operations between two vector data.

[0052] In this way, when a large number of discrete paired data points need to be operated in application scenarios such as image recognition, discrete data pairs or discrete data groups can be moved to a continuous address space through a data transfer instruction and aggregated into two or more vector data for vector operation, thereby converting the operation of discrete data points into vector operation, simplifying the processing process and reducing data overhead.

[0053] In a possible implementation, step S12 may include:

[0054] determining source data addresses of the plurality of first data points respectively according to source data base addresses and data offset addresses of the plurality of first data points;

[0055] determining second source data addresses of the plurality of second data points respectively according to the first source data addresses and the offset step sizes of the plurality of first data points;

[0056] determining first destination data addresses of the plurality of first data points according to destination data base addresses and data sizes of the plurality of first data points;

[0057] The second destination data addresses of the plurality of second data points are determined according to the first destination data addresses and the destination base address step length of the plurality of first data points.

[0058] For example, the operation domain of a data transfer instruction may include the source data base address (Source Data Base Address), the destination data base address (Destination Data Base Address), the size of a single data point (Single Point Data Size), the number of single data points (Single Point Data Number), the data offset base address of a single data point (Offset Vector Base Address), the offset size (Offset Size), the offset step (Offset Stride), the destination base address step (Destination Base Address Stride), etc.

[0059] Among them, the source data base address can represent the base address of multiple discrete data points currently in the data storage space; the destination data base address can represent the base address in the data storage space to which multiple data points will be moved; the size of a single data point can represent the data size of each discrete data point (for example, 4 bits or 8 bits); the number of single data points can represent the number N of discrete data points (N is an integer greater than 1); the data offset base address of a single data point can respectively represent the base address of each discrete data point offset relative to the source data base address; the offset size can represent the width of the offset address corresponding to each discrete data point, for example, equal to the size of a single data point; the offset step size can represent the offset of the source data address of the second data point relative to the source data address of the first data point; the destination base address step size can represent the offset of the destination data base address of the second data point relative to the destination data base address of the first data point. The two parameters of offset step size and destination base address step size can be valid only in multi-vector transfer mode. The present disclosure does not limit the specific number and type of parameters in the operation domain of the data transfer instruction.

[0060] In one possible implementation, the data offset address (Offset Address) of each first data point can be determined based on the data offset base address and offset size of each first data point in the operation domain. For example, for the nth first data point (1≤n≤N), the data offset base address of the first data point is 24, the offset size is 4, and the data offset address Offset Address[n] of the first data point is [24,27]. In this way, based on the source data base address and the data offset address, the first source data address of the nth first data point can be determined. When two vectors are obtained by transfer, the first source data address can be expressed as:

[0061] Single Point Src Addr[2n] = Source Data Base Address + OffsetAddress[n] (1)

[0062] In formula (1), Single Point Src Addr[2n] represents the first source data address of the nth first data point. When the source data base address is, for example, Addr1

[15] and the data offset address is [24, 27], the first source data address of the nth first data point can be determined to be Addr1[39, 42].

[0063] In this way, the source data address of each first data point can be determined respectively, so as to read each first data point from the source data address.

[0064] In a possible implementation, step S12 may include: determining the second source data addresses of the plurality of second data points respectively according to the first source data addresses and the offset step sizes of the plurality of first data points.

[0065] For example, the operation field of a data transfer instruction may include a source data base address (Source Data Base Address), a data offset base address (Offset Vector Base Address) for a single data point, an offset size (Offset Size), an offset stride (Offset Stride), etc. In multi-vector transfer mode, the second source data address of a corresponding second data point can be directly obtained based on the first source data address of the first data point according to the offset stride.

[0066] Single Point Src Addr[2n+1]=Source Data Base Address+Offset Address[n]+Offset Stride(2)

[0067] In formula (2), Single Point Src Addr[2n+1] represents the second source data address of the second data point corresponding to the nth first data point. For example, if the first source data address of the nth first data point is determined to be Addr1[39,42] based on the source data base address and the data offset address, and the offset step is 8 bits, the second source data address of the nth second data point can be determined to be Addr1[47,50].

[0068] In one possible implementation, when multiple sets of second data points need to be read to form multiple second vectors, the offset step size can have multiple values, such as 4 bits, 8 bits, 12 bits, etc. Thus, the second source data address of each set of second data points can be determined based on different offset step sizes. Those skilled in the art can determine the number and value of the offset step size based on actual circumstances, and this disclosure does not impose any limitations thereon.

[0069] In this way, the source data address of the corresponding second data point can be directly determined based on the source data address and offset step of the first data point, so that two or more data points can be obtained through one reading, so that the instruction can read more data through fewer addresses (for example, reading 100 data points through the data offset base address of 50 data points), thereby significantly reducing data overhead.

[0070] In a possible implementation, step S12 may include: determining first destination data addresses of the plurality of first data points according to destination data base addresses and data sizes of the plurality of first data points.

[0071] For example, the operation field of a data transfer instruction may include the destination data base address (Destination DataBase Address), the size of a single data point (Single Point Data Size), etc. Since the destination data address is a continuous data address, the destination data address of each first data point can be directly determined in sequence based on the data size of the first data point and the sequence number of each first data point. In the case of transferring two vectors, the first destination data address can be expressed as:

[0072] Single Point Dest Addr[2n]=Destination Data Base Address+n*SinglePoint Data Size(3)

[0073] In formula (3), Single Point Dest Addr[n] represents the first destination data address of the nth first data point. If the destination data base address is, for example, Addr2[0, 3], the size of a single data point is 4 bits, and n is 3, the first destination data address of the third first data point can be determined to be Addr2[12, 15].

[0074] In this way, the first destination data address of each first data point can be determined respectively, so that each first data point read from the first source data address can be transferred to the first destination data address of each first data point respectively.

[0075] In a possible implementation, step S12 may include: determining second destination data addresses of the plurality of second data points according to the first destination data addresses and the destination base address steps of the plurality of first data points.

[0076] For example, the operation field of a data transfer instruction may include a destination data base address, a single point data size, a destination base address stride, etc. In multi-vector transfer mode, the second destination data address of a corresponding second data point can be directly obtained based on the first destination data address of the first data point according to the destination base address stride.

[0077] When two vectors are transferred, the second destination data address can be expressed as:

[0078] Single Point Dest Addr[2n+1]=Destination Data Base Address+n*SinglePoint Data Size+Destination Base Address Stride(4)

[0079] In formula (4), Single Point Dest Addr[2n+1] represents the second destination data address of the second data point corresponding to the nth first data point. For example, if the first destination data address of the nth first data point is determined to be Addr2[9,12] based on the destination data base address and the data size, and the destination base address step size is 48 bits, the second destination data address of the nth second data point can be determined to be Addr2[57,60].

[0080] In one possible implementation, when multiple groups of second data points need to be read to form multiple second vectors, the destination base address step size can have multiple values, such as a 48-bit or 96-bit destination base address step size, to store multiple vector data. Thus, the second destination data address of each group of second data points can be determined based on different destination base address step sizes. Those skilled in the art can determine the number and value of the destination base address step size based on actual circumstances, and this disclosure does not impose any limitations thereon.

[0081] In this way, the destination data address of the corresponding second data point can be directly determined based on the destination data address and destination base address step of the first data point, so as to store each data point of two or more vector data, significantly reducing data overhead.

[0082] In a possible implementation, step S13 may include:

[0083] Reading first data points from first source data addresses of respective first data points;

[0084] Each first data point is stored in the first destination data address in sequence to obtain first vector data.

[0085] For example, after determining the first source data address and the first destination data address of each first data point in the operation domain, each first data point can be read from the first source data address of each first data point, and each first data point can be stored in the first destination data address in sequence. For example, when n is 3, data is read from the first source data address Addr1[39,42] of the third first data point and stored in the first destination data address Addr2[9,12], thereby completing the data transfer of the first data point. In this way, each first data point is transferred in sequence to obtain N consecutive first data points stored in the first destination data address, realizing the process of aggregating discrete first data points into first vector data.

[0086] In this way, data transfer can be achieved, providing a data basis for subsequent processing.

[0087] In a possible implementation, step S14 may include:

[0088] Reading second data points from second source data addresses of respective second data points;

[0089] Each second data point is stored in the second destination data address in sequence to obtain second vector data.

[0090] For example, similarly, each second data point can be read from the second source data address of each second data point, and each second data point can be stored in sequence in the second destination data address. For example, when n is 3, data is read from the second source data address Addr1[47,50] of the third second data point and stored in the second destination data address Addr2[57,60], thereby completing the data transfer of the second data point. In this way, each second data point is transferred in sequence, resulting in N consecutive second data points stored in the second destination data address, thus completing the process of aggregating discrete second data points into second vector data.

[0091] In this way, data transfer can be achieved, providing a data basis for subsequent processing.

[0092] According to the data processing method of the embodiment of the present disclosure, discrete paired or grouped data can be moved to multiple continuous address spaces through data moving instructions in a multi-vector moving mode, and respectively aggregated into multiple vector data. Therefore, in application scenarios such as image recognition, when a large number of discrete paired (or grouped) data points need to be operated, multiple vector data involved in the operation can be directly obtained through one instruction, and the operation of discrete data points can be converted into vector operation, thereby simplifying the processing process and reducing data overhead.

[0093] It should be noted that for the aforementioned method embodiments, for simplicity of description, they are all expressed as a series of action combinations, but those skilled in the art should be aware that the present disclosure is not limited by the order of the actions described, because according to the present disclosure, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all optional embodiments, and the actions and modules involved are not necessarily required by the present disclosure.

[0094] It should be further noted that, although the various steps in the flowchart are shown in sequence as indicated by the arrows, these steps are not necessarily performed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps may be performed in other orders. Moreover, at least a portion of the steps in the flowchart may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily performed at the same time, but may be performed at different times. The execution order of these sub-steps or stages is not necessarily to be performed in sequence, but may be performed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

[0095] Figure 3 FIG. 1 is a block diagram of a data processing device according to an embodiment of the present disclosure. Figure 3 As shown, the data processing device includes:

[0096] a mode determination module 31 for determining a data transfer mode of the data transfer instruction when the decoded processing instruction is a data transfer instruction;

[0097] an address determination module 32 for determining, when the data transfer mode of the data transfer instruction is the multi-vector transfer mode, first source data addresses and first destination data addresses of a plurality of first data points in an operation domain of the data transfer instruction, and second source data addresses and second destination data addresses of a plurality of second data points;

[0098] A first storage module 33 is configured to store the first data point read from the first source data address to the first destination data address to obtain first vector data;

[0099] A second storage module 34 is configured to store the second data point read from the second source data address to the second destination data address to obtain second vector data;

[0100] The first source data address and the second source data address include a plurality of discrete data addresses, and the first destination data address and the second destination data address include continuous data addresses.

[0101] In a possible implementation, the address determination module includes:

[0102] a first source address determining submodule, configured to determine first source data addresses of the plurality of first data points respectively according to source data base addresses and data offset addresses of the plurality of first data points;

[0103] a second source address determining submodule, configured to respectively determine second source data addresses of the plurality of second data points according to the first source data addresses and the offset step sizes of the plurality of first data points;

[0104] a first destination address determining submodule, configured to determine first destination data addresses of the plurality of first data points according to destination data base addresses and data sizes of the plurality of first data points;

[0105] The second destination address determination submodule is configured to determine the second destination data addresses of the plurality of second data points according to the first destination data addresses and the destination base address step lengths of the plurality of first data points.

[0106] In a possible implementation, the first storage module includes:

[0107] A first reading submodule, configured to read first data points from first source data addresses of respective first data points;

[0108] The first storage submodule is used to store each first data point in sequence into the first destination data address to obtain first vector data.

[0109] In a possible implementation, the second storage module includes:

[0110] a second reading submodule, configured to read the second data points from the second source data addresses of the respective second data points;

[0111] The second storage submodule is used to store each second data point in sequence into the second destination data address to obtain second vector data.

[0112] In a possible implementation, the apparatus further includes:

[0113] The decoding module is used to decode the received processing instructions to obtain the decoded processing instructions.

[0114] The decoded processing instruction includes an operation code, and the operation code is used to instruct data handling processing.

[0115] It should be understood that the above-described device embodiments are merely illustrative, and the devices of the present disclosure may also be implemented in other ways. For example, the division of units / modules described in the above-described embodiments is merely a logical functional division, and actual implementations may employ other division methods. For example, multiple units, modules, or components may be combined or integrated into another system, or some features may be omitted or not implemented.

[0116] In addition, unless otherwise specified, the functional units / modules in the various embodiments of the present disclosure may be integrated into a single unit / module, each unit / module may exist physically separately, or two or more units / modules may be integrated together. The aforementioned integrated units / modules may be implemented in the form of hardware or software program modules.

[0117] If the integrated unit / module is implemented in hardware, the hardware may be a digital circuit, an analog circuit, or the like. The physical implementation of the hardware structure includes, but is not limited to, transistors, memristors, and the like. Unless otherwise specified, the artificial intelligence processor may be any appropriate hardware processor, such as a CPU, GPU, FPGA, DSP, and ASIC. Unless otherwise specified, the storage unit may be any appropriate magnetic storage medium or magneto-optical storage medium, such as resistive random access memory (RRAM), dynamic random access memory (DRAM), static random access memory (SRAM), enhanced dynamic random access memory (EDRAM), high-bandwidth memory (HBM), hybrid memory cube (HMC), and the like.

[0118] If the integrated unit / module is implemented in the form of a software program module and sold or used as an independent product, it can be stored in a computer-readable memory. Based on this understanding, the technical solution of the present disclosure is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a memory, including a number of instructions for enabling a computer device (which can be a personal computer, a server or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present disclosure. The aforementioned memory includes: various media that can store program codes, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.

[0119] In a possible implementation, an artificial intelligence chip is also disclosed, which includes the above-mentioned data processing device.

[0120] In a possible implementation, an electronic device is also disclosed, which includes the above-mentioned artificial intelligence chip.

[0121] In a possible implementation, a board is also disclosed, which includes a storage device, an interface device, a control device and the above-mentioned artificial intelligence chip; wherein the artificial intelligence chip is connected to the storage device, the control device and the interface device respectively; the storage device is used to store data; the interface device is used to realize data transmission between the artificial intelligence chip and an external device; and the control device is used to monitor the status of the artificial intelligence chip.

[0122] Figure 4 The structural block diagram of the board according to the embodiment of the present disclosure is shown. Figure 4 In addition to the chip 389, the board may also include other supporting components, including but not limited to: a storage device 390, an interface device 391 and a control device 392;

[0123] The memory device 390 is connected to the artificial intelligence chip via a bus and is used to store data. The memory device may include multiple groups of memory cells 393. Each group of memory cells is connected to the artificial intelligence chip via a bus. It is understood that each group of memory cells may be DDR SDRAM (Double Data Rate SDRAM).

[0124] DDR can double the speed of SDRAM without increasing the clock frequency. DDR allows data to be read out on the rising and falling edges of the clock pulse. The speed of DDR is twice that of standard SDRAM. In one embodiment, the storage device may include 4 groups of storage units. Each group of storage units may include multiple DDR4 particles (chips). In one embodiment, the artificial intelligence chip may include 4 72-bit DDR4 controllers, and 64 bits of the above 72-bit DDR4 controllers are used for data transmission and 8 bits are used for ECC verification. It can be understood that when DDR4-3200 particles are used in each group of storage units, the theoretical bandwidth of data transmission can reach 25600MB / s.

[0125] In one embodiment, each group of the memory cells includes a plurality of double data rate synchronous dynamic random access memories (DDRs) connected in parallel. DDRs can transmit data twice within one clock cycle. A controller for controlling the DDRs is provided in the chip to control data transmission and data storage in each of the memory cells.

[0126] The interface device is electrically connected to the artificial intelligence chip. The interface device is used to realize data transmission between the artificial intelligence chip and an external device (such as a server or a computer). For example, in one embodiment, the interface device can be a standard PCIE interface. For example, the data to be processed is transmitted to the chip by the server through the standard PCIE interface to realize data transfer. Preferably, when the PCIE 3.0X 16 interface is used for transmission, the theoretical bandwidth can reach 16000MB / s. In another embodiment, the interface device can also be other interfaces. The present disclosure does not limit the specific forms of expression of the above-mentioned other interfaces. The interface unit can realize the switching function. In addition, the calculation results of the artificial intelligence chip are still transmitted back to the external device (such as a server) by the interface device.

[0127] The control device is electrically connected to the artificial intelligence chip. The control device is used to monitor the status of the artificial intelligence chip. Specifically, the artificial intelligence chip and the control device can be electrically connected via an SPI interface. The control device may include a single-chip microcomputer (MCU). For example, the artificial intelligence chip may include multiple processing chips, multiple processing cores or multiple processing circuits, which can drive multiple loads. Therefore, the artificial intelligence chip can be in different working states such as multi-load and light load. The control device can realize the regulation of the working states of multiple processing chips, multiple processing and / or multiple processing circuits in the artificial intelligence chip.

[0128] In one possible implementation, an electronic device is disclosed that includes the aforementioned artificial intelligence chip. The electronic device includes a data processing device, a robot, a computer, a printer, a scanner, a tablet computer, a smart terminal, a mobile phone, a driving recorder, a navigation system, a sensor, a camera, a server, a cloud server, a camera, a video camera, a projector, a watch, headphones, mobile storage, a wearable device, a vehicle, a household appliance, and / or a medical device. The vehicle includes an airplane, a ship, and / or a car; the household appliance includes a television, an air conditioner, a microwave oven, a refrigerator, a rice cooker, a humidifier, a washing machine, an electric light, a gas stove, and a range hood; and the medical device includes an MRI scanner, an ultrasound machine, and / or an electrocardiograph.

[0129] In the above embodiments, the description of each embodiment has its own emphasis. For parts not described in detail in a particular embodiment, please refer to the relevant description of other embodiments. The technical features of the above embodiments can be combined in any way. To keep the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0130] The foregoing content can be better understood in accordance with the following terms:

[0131] Clause A1. A data processing method comprising:

[0132] When the decoded processing instruction is a data transfer instruction, determining a transfer mode of the data transfer instruction;

[0133] When the data transfer instruction has a multi-vector transfer mode, determining first source data addresses and first destination data addresses of a plurality of first data points, and second source data addresses and second destination data addresses of a plurality of second data points in an operation domain of the data transfer instruction;

[0134] storing the first data point read from the first source data address to the first destination data address to obtain first vector data;

[0135] storing the second data point read from the second source data address to the second destination data address to obtain second vector data;

[0136] The first source data address and the second source data address include a plurality of discrete data addresses, and the first destination data address and the second destination data address include continuous data addresses.

[0137] A2. According to the method described in A1, when the data transfer instruction is in a multi-vector transfer mode, determining first source data addresses and first destination data addresses of a plurality of first data points, and second source data addresses and second destination data addresses of a plurality of second data points in an operation domain of the data transfer instruction, comprises:

[0138] determining first source data addresses of the plurality of first data points respectively according to source data base addresses and data offset addresses of the plurality of first data points;

[0139] determining second source data addresses of the plurality of second data points respectively according to the first source data addresses and the offset step sizes of the plurality of first data points;

[0140] determining first destination data addresses of the plurality of first data points according to destination data base addresses and data sizes of the plurality of first data points;

[0141] The second destination data addresses of the plurality of second data points are determined according to the first destination data addresses and the destination base address step length of the plurality of first data points.

[0142] A3. According to the method described in A1 or A2, the first data point read from the first source data address is stored in the first destination data address to obtain first vector data, including:

[0143] Reading first data points from first source data addresses of respective first data points;

[0144] Each first data point is stored in the first destination data address in sequence to obtain first vector data.

[0145] A4. According to any one of the methods described in A1-A3, the second data point read from the second source data address is stored in the second destination data address to obtain second vector data, including:

[0146] Reading second data points from second source data addresses of respective second data points;

[0147] Each second data point is stored in the second destination data address in sequence to obtain second vector data.

[0148] A5. The method according to any one of A1 to A4, further comprising:

[0149] Decode the received processing instruction to obtain the decoded processing instruction,

[0150] The decoded processing instruction includes an operation code, and the operation code is used to instruct data handling processing.

[0151] A6. A data processing apparatus comprising:

[0152] a mode determination module, configured to determine a data transfer mode of the data transfer instruction when the decoded processing instruction is a data transfer instruction;

[0153] an address determination module configured to determine, when a transfer mode of the data transfer instruction is a multi-vector transfer mode, first source data addresses and first destination data addresses of a plurality of first data points in an operation domain of the data transfer instruction, and second source data addresses and second destination data addresses of a plurality of second data points;

[0154] A first storage module is configured to store a first data point read from the first source data address to the first destination data address to obtain first vector data;

[0155] A second storage module is configured to store the second data point read from the second source data address to the second destination data address to obtain second vector data;

[0156] The first source data address and the second source data address include a plurality of discrete data addresses, and the first destination data address and the second destination data address include continuous data addresses.

[0157] A7. The apparatus according to A6, wherein the address determination module comprises:

[0158] a first source address determining submodule, configured to determine first source data addresses of the plurality of first data points respectively according to source data base addresses and data offset addresses of the plurality of first data points;

[0159] a second source address determining submodule, configured to respectively determine second source data addresses of the plurality of second data points according to the first source data addresses and the offset step sizes of the plurality of first data points;

[0160] a first destination address determining submodule, configured to determine first destination data addresses of the plurality of first data points according to destination data base addresses and data sizes of the plurality of first data points;

[0161] The second destination address determination submodule is configured to determine the second destination data addresses of the plurality of second data points according to the first destination data addresses and the destination base address step lengths of the plurality of first data points.

[0162] A8. The apparatus according to A6 or A7, wherein the first storage module comprises:

[0163] A first reading submodule, configured to read first data points from first source data addresses of respective first data points;

[0164] The first storage submodule is used to store each first data point in sequence into the first destination data address to obtain first vector data.

[0165] A9. The apparatus according to any one of A6-A8, wherein the second storage module comprises:

[0166] a second reading submodule, configured to read the second data points from the second source data addresses of the respective second data points;

[0167] The second storage submodule is used to store each second data point in sequence into the second destination data address to obtain second vector data.

[0168] A10. The apparatus according to any one of A6-A9, further comprising:

[0169] The decoding module is used to decode the received processing instructions to obtain the decoded processing instructions.

[0170] The decoded processing instruction includes an operation code, and the operation code is used to instruct data handling processing.

[0171] A11. An artificial intelligence chip, comprising a data processing device as described in any one of A6-A10.

[0172] A12. An electronic device comprising the artificial intelligence chip described in A11.

[0173] A13. A board comprising: a memory device, an interface device, a control device, and an artificial intelligence chip as described in A11;

[0174] The artificial intelligence chip is connected to the storage device, the control device and the interface device respectively;

[0175] The storage device is used to store data;

[0176] The interface device is used to realize data transmission between the artificial intelligence chip and external equipment;

[0177] The control device is used to monitor the status of the artificial intelligence chip.

[0178] The embodiments of the present disclosure are described in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present disclosure. The description of the above embodiments is only used to help understand the method and core ideas of the present disclosure. At the same time, changes or modifications made by those skilled in the art based on the ideas of the present disclosure, on the specific implementation methods and application scope of the present disclosure, all fall within the scope of protection of the present disclosure. In summary, the contents of this specification should not be understood as limiting the present disclosure.

Claims

1. A data processing method, characterized in that: include: When the decoded processing instruction is a data transfer instruction, determining a transfer mode of the data transfer instruction; When the data transfer instruction has a multi-vector transfer mode, determining first source data addresses and first destination data addresses of a plurality of first data points, and second source data addresses and second destination data addresses of a plurality of second data points in an operation domain of the data transfer instruction; storing the first data point read from the first source data address to the first destination data address to obtain first vector data; storing the second data points read from the second source data address to the corresponding second destination data addresses respectively to obtain at least one second vector data; wherein the first source data address and the second source data address include a plurality of discrete data addresses, and the first destination data address and the second destination data address include continuous data addresses; Wherein, when the transfer mode of the data transfer instruction is the multi-vector transfer mode, determining first source data addresses and first destination data addresses of a plurality of first data points, and second source data addresses and second destination data addresses of a plurality of second data points in an operation domain of the data transfer instruction includes: determining first source data addresses of the plurality of first data points respectively according to source data base addresses and data offset addresses of the plurality of first data points; determining second source data addresses of the plurality of second data points respectively according to the first source data addresses and the offset step sizes of the plurality of first data points; determining first destination data addresses of the plurality of first data points according to destination data base addresses and data sizes of the plurality of first data points; determining second destination data addresses of the plurality of second data points according to the first destination data addresses and the destination base address step lengths of the plurality of first data points; Among them, the operation domain of the data transfer instruction includes the source data base address, the destination data base address, the size of a single data point, the number of single data points, the data offset base address of a single data point, the offset size, the offset step, and the destination base address step.

2. The method according to claim 1, characterized in that Storing the first data point read from the first source data address to the first destination data address to obtain first vector data includes: Reading first data points from first source data addresses of respective first data points; Each first data point is stored in the first destination data address in sequence to obtain first vector data.

3. The method according to any one of claims 1 to 2, characterized in that: Storing the second data point read from the second source data address to the second destination data address to obtain second vector data includes: Reading second data points from second source data addresses of respective second data points; Each second data point is stored in the second destination data address in sequence to obtain second vector data.

4. The method according to any one of claims 1 to 3, characterized in that The method further comprises: Decode the received processing instruction to obtain the decoded processing instruction, The decoded processing instruction includes an operation code, and the operation code is used to instruct data handling processing.

5. A data processing device, characterized in that: include: a mode determination module, configured to determine a data transfer mode of the data transfer instruction when the decoded processing instruction is a data transfer instruction; an address determination module configured to determine, when a transfer mode of the data transfer instruction is a multi-vector transfer mode, first source data addresses and first destination data addresses of a plurality of first data points in an operation domain of the data transfer instruction, and second source data addresses and second destination data addresses of a plurality of second data points; A first storage module is configured to store a first data point read from the first source data address to the first destination data address to obtain first vector data; A second storage module is configured to store the second data points read from the second source data address into the corresponding second destination data addresses, to obtain at least one second vector data; wherein the first source data address and the second source data address include a plurality of discrete data addresses, and the first destination data address and the second destination data address include continuous data addresses; Wherein, the address determination module includes: a first source address determining submodule, configured to determine first source data addresses of the plurality of first data points respectively according to source data base addresses and data offset addresses of the plurality of first data points; a second source address determining submodule, configured to respectively determine second source data addresses of the plurality of second data points according to the first source data addresses and the offset step sizes of the plurality of first data points; a first destination address determining submodule, configured to determine first destination data addresses of the plurality of first data points according to destination data base addresses and data sizes of the plurality of first data points; a second destination address determining submodule, configured to determine second destination data addresses of the plurality of second data points according to the first destination data addresses and the destination base address step lengths of the plurality of first data points; Among them, the operation domain of the data transfer instruction includes the source data base address, the destination data base address, the size of a single data point, the number of single data points, the data offset base address of a single data point, the offset size, the offset step, and the destination base address step.

6. The device according to claim 5, characterized in that The first storage module includes: A first reading submodule, configured to read first data points from first source data addresses of respective first data points; The first storage submodule is used to store each first data point in sequence into the first destination data address to obtain first vector data.

7. The device according to any one of claims 5-6, characterized in that The second storage module includes: a second reading submodule, configured to read the second data points from the second source data addresses of the respective second data points; The second storage submodule is used to store each second data point in sequence into the second destination data address to obtain second vector data.

8. The device according to any one of claims 5 to 7, characterized in that: The device further comprises: The decoding module is used to decode the received processing instructions to obtain the decoded processing instructions. The decoded processing instruction includes an operation code, and the operation code is used to instruct data handling processing.

9. An artificial intelligence chip, characterized in that: The chip includes the data processing device according to any one of claims 5 to 8.

10. An electronic device, characterized in that: The electronic device includes the artificial intelligence chip as claimed in claim 9.

11. A board, characterized in that: The board includes: a storage device, an interface device, a control device, and an artificial intelligence chip according to claim 9; The artificial intelligence chip is connected to the storage device, the control device and the interface device respectively; The storage device is used to store data; The interface device is used to realize data transmission between the artificial intelligence chip and external equipment; The control device is used to monitor the status of the artificial intelligence chip.

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