System components and applications of system components

Abstract

The invention relates to a system component having an interface for a data bus, wherein a defined communication protocol is used on the data bus, which defines a data sequence for sending and receiving an access request, wherein the data of the access request at least comprises information about the direction of the access (read or write access). The system component further comprises a register unit having data registers, wherein the register unit interprets the defined data of the access request as a register address on the basis of the data sequence. The system component further comprises a processing device for the data of the access request, wherein the interface can optionally be operated in a first operating mode or in a second operating mode, wherein in the first operating mode the data of the access request is supplied to the register unit for the recognition of the register address, so that a read or write access to the data register thus recognized is carried out accordingly, wherein in the second operating mode the data of the access request is supplied to the processing device and a corresponding read or write access is carried out by the processing device.

Description

Technical Field

[0001] This invention relates to a system component of a system and the application of such a system component. The invention also relates to a system component of a system having at least one master and at least one slave, the at least one master and the at least one slave communicating via a data bus. Background Technology

[0002] To enable data exchange between integrated circuits, various communication protocols can be used. Inter-Integrated Circuit (I-Integrated Circuit) communication protocols... 2 C) The protocol implements master-slave communication, where one integrated circuit acts as the master and requests data access to another integrated circuit (slave). Data access can include writing and reading one or more bytes. For this purpose, in I... 2 A C-bus typically has one master and multiple slaves; however, systems with multiple masters are also known, known as multi-master buses.

[0003] Each slave device is assigned a unique slave address, allowing the master to address different slave devices on the bus independently. During data access, in addition to this unique slave address, information about whether a write or read access is being performed is also transmitted. Data bytes representing the actual payload of the data access can also be transmitted.

[0004] Access to the slave device's registers is achieved through an interface. According to the first method, the register address can be directly analyzed and processed by the interface's logic unit, thus enabling hardware access to the register. According to the second method, the register address is not analyzed and processed by the interface's logic unit, but is instead passed to a microcontroller that interprets the register address. Therefore, the second method is implemented in software.

[0005] The first method achieves high efficiency and low power consumption; however, the register set is fixed. The second method is more flexible; however, it typically requires greater system overhead, for example, due to the need for a microcontroller. Summary of the Invention

[0006] This invention provides a system component and an application of the system component.

[0007] Preferred implementation methods are the subject of extended technical solutions.

[0008] According to a first aspect, the present invention therefore relates to a system component having an interface for a data bus for communicating with at least one other system component, wherein a defined communication protocol is used on the data bus to determine a data sequence for sending and receiving data, wherein the data of the access request includes at least information regarding the access direction—read access or write access. The system component further includes a register unit having a plurality of data registers addressable by register addresses and read from and / or written to via the data bus, wherein the register unit interprets the determined data of the access request as a register address based on the data sequence. Finally, the system component includes a processing means for processing the data of the access request, wherein the interface is optionally operable in a first operating mode or a second operating mode, wherein in the first operating mode, the data of the access request is provided to the register unit for identifying the register address, thereby performing a corresponding read access or write access to the thus identified data register; wherein in the second operating mode, the data of the access request is provided to the processing means, and the processing means performs the corresponding read access or write access.

[0009] According to a second aspect, the present invention relates to the application of a system component according to the invention, which serves as a slave in a system comprising at least one master and at least one slave, wherein the master and slave communicate with each other via a data bus and use a defined communication protocol on the data bus.

[0010] Advantages of the present invention

[0011] Because the interface can operate in two different modes, it can flexibly switch between a fixed register list and a flexible register list depending on the application. For example, a slave device can not only be implemented efficiently using hardware logic units with a fixed register set, but can also be constructed to handle any I / O. 2 The C protocol is used for configuration. This allows the interface to switch between the two methods depending on the application, enabling the use of the advantages of each method on a single piece of hardware.

[0012] A fixed register list corresponds to the first operating mode, where register addresses are directly identified by register cells. A flexible register list corresponds to the second operating mode, where the processing device performs read or write access based on the data of the access request. In the case of a flexible register list, register addresses are not analyzed and processed by the interface logic cells, but are treated as normal data bytes of the payload. For example, a microcontroller can analyze and process the payload as a processing device, and interpret the first byte as a register address. Therefore, access to different registers or resources can be implemented in software. Software implementation also allows for different interpretations of the payload, such as using two bytes as register addresses, or no register address at all. The first operating mode enables efficient and power-saving addressing of data registers, while the second operating mode enables flexible access to data registers.

[0013] By using different operating modes, system components can be universally used, thus covering a wide range of application scenarios.

[0014] According to one expansion scheme for the system components, the register unit is designed such that read or write access in the first operating mode of the interface is performed in hardware. This is understood to mean that the register address is directly analyzed and processed by the logic unit of the register unit. Therefore, the corresponding data registers can be accessed directly through the corresponding hardware circuitry, thereby enabling the system components to operate with very low power consumption.

[0015] According to one expansion scheme of the system components, the register unit is designed such that read or write access in the second operating mode of the interface is performed based on software. Therefore, the processing device can analyze the data sequence of the access request based on software to determine the register address.

[0016] According to one extension of the system components, the processing device is designed to, in a second operating mode of the interface, interpret access request data packet-by-packet in an interrupt-driven manner, and receive access request data in the case of a write access, and provide the requested data in the case of a read access. Specifically, an interrupt can be sent to the processing device after each transmitted byte to process that byte.

[0017] According to one system component expansion scheme, the processing device is equipped with a data memory containing a Direct Memory Access (DMA) controller. In a second operating mode of the interface, during write access, the DMA controller stores the requested data in the data memory, allowing the processing device to access the requested data. The processing device provides data in this data memory, and during read access, the DMA controller reads this data from the data memory. Therefore, the processing device can process this data after transferring multiple bytes.

[0018] According to one extension scheme of the system components, the processing device (optionally via a DMA controller) is coupled to at least one selected data register of the register unit, such that when the interface is running in a second operating mode, read or write access is performed through the register unit and at least one selected data register. Therefore, in the second operating mode, direct access to the selected data register is also possible.

[0019] According to one extension scheme of the system components, when the interface is running in a second operating mode, the processing device (optionally via a DMA controller) is coupled to at least one first selected data register for read access and to at least one second selected data register for write access. Therefore, different access modes are associated with different data registers to simplify access.

[0020] According to one extension scheme of the system components, the register unit interprets the access request data according to a first communication protocol. The processing device can be programmed to interpret the access request data as a read or write access using a second communication protocol and operate accordingly. The selection of the first or second operating mode for the interface depends on whether the first or second communication protocol is used on the data bus through which the system components communicate with other system components. Therefore, the present invention can be flexibly applied to various communication protocols.

[0021] According to one expansion scheme of system components, the register unit and / or processing device correspond to satisfying I 2 The C standard communication protocol is used to interpret access request data. The slave address can include, for example, 7 bits and is unique on the data bus. In I... 2In a C access, multiple bytes can be transmitted. The first byte includes the slave address and a read / write bit. This read / write bit indicates the access direction (read or write access), allowing the master to specify whether a write or read access should be performed. The first byte following the slave address can represent the register address, thus implementing I / O. 2 C access allows access to different registers in the slave device. However, this can also vary depending on the application. For example, two bytes can be used as the register address. Alternatively, no register address can be implemented. After (non-mandatory) passing the register address, one or more data bytes can optionally follow, representing the actual payload of the access.

[0022] In the case of read access, in I 2 In the C protocol, the last used register address for a write access can be used as the register address for a read access. If a register that wasn't previously written to (this represents the normal case) needs to be read, a write access without data bytes is first performed using the read register address. Therefore, only the device address and register address are transmitted. The read access is then performed. Reads can also be implemented using fixed and flexible register lists, where memory is reserved for the last passed register address. With a fixed register list, this can be implemented in hardware. With a flexible register list, this can be implemented as a variable in software.

[0023] According to one expansion scheme of the system components, the register unit and / or processing device interprets the access request data according to a communication protocol that conforms to the SPI standard. In the SPI protocol, the first byte containing the slave address is typically omitted, where this slave address is replaced by a separate chip select signal for each slave on the data bus. Besides the slave address, I... 2 The first byte in the C protocol also contains information about the access direction. In the SPI protocol, the access direction is transmitted along with the register address in the first byte of the access, thus limiting the register address to 7 bytes. With a fixed register list, taking into account the first byte (I 2 In the case of the omitted slave address (C), this method can be similar to I. 2The C protocol is used. Therefore, information about the access direction is passed in the register address byte, and then valid for the data direction from the second byte onwards. In the case of a flexible register list, the register address is not analyzed by the interface's logic unit, but is treated as normal data bytes of the payload. The processing device can analyze the payload, interpreting the first byte as the register address, and thus implement access to different registers or resources in software. Since the access direction does not need to be known at the beginning and can be downstream analyzed within the processing device, data can be received and sent simultaneously, for example, by the slave device. This can be done by using two First-In-First-Out (FIFO) memories or DMA channels, or by a special FIFO that fills the memory location freed by the sent bits with the received bits.

[0024] According to one extension, the system components include at least one sensor function, particularly at least one MEMS sensor element. This may include, for example, optical sensors, magnetic field sensors, chemical sensors, humidity sensors, acoustic sensors, inertial sensors, etc.

[0025] According to one extension scheme of the system components, the selection of the operating mode is performed once upon activation, and can be defined, for example, by values ​​in a memory used for adjusting parameters or by the level of an external connection.

[0026] According to one approach to system component expansion, the operating mode is selected during system operation and can be changed dynamically. For example, after a boot process in a fixed operating mode, it can switch to a flexible mode. Attached Figure Description

[0027] The attached diagram shows:

[0028] Figure 1 A schematic block diagram of a system having system components according to an embodiment of the present invention is shown;

[0029] Figure 2 Showing the corresponding condition for satisfying I 2 A schematic diagram of the data sequence of the C standard communication protocol;

[0030] Figure 3 A schematic diagram showing the data sequence corresponding to the communication protocol that meets the SPI standard;

[0031] Figure 4 A schematic block diagram showing a portion of a system having system components according to another embodiment of the invention;

[0032] Figure 5 A schematic block diagram showing a portion of a system having system components according to another embodiment of the invention;

[0033] Figure 6 A schematic block diagram showing a portion of a system having system components according to another embodiment of the invention; and

[0034] Figure 7 A schematic block diagram showing a portion of a system having system components according to another embodiment of the present invention.

[0035] In all the accompanying drawings, the same or functionally identical elements and devices are equipped with the same reference numerals. Detailed Implementation

[0036] Figure 1 A schematic block diagram of a system having system component 1 is shown. System component 1 can be a slave device of the system, wherein the system also includes multiple master devices as other system components 21 to 2n. The system can be part of a sensor, thereby enabling system component 1 to provide sensor functionality. In particular, system component 1 can include or be coupled to a MEMS sensor element.

[0037] System component 1 includes an interface 11 coupled to a data bus 3 and connected to other system components 21 to 2n via the data bus. Other system components 21 to 2n can pass access requests for sending and receiving data to interface 11 of system component 1 via the data bus 3. The access request may also include data to be transmitted.

[0038] Use the defined communication protocol, such as I, on data bus 3. 2 The system component 1 is designed to interact with the data bus 3, which uses any of a number of predefined communication protocols. Therefore, the system component 1 can be used in a variety of ways.

[0039] The communication protocol used on data bus 3 determines the data sequence for access requests used to send and receive data, i.e., the interpretation of the byte order. The access request data includes information about the access direction. Access directions include read access and write access.

[0040] System component 1 also includes register unit 12 having data registers 121 to 12m. Here, the number m of data registers can be arbitrarily predetermined, and the present invention is not limited to a fixed number. Other system components 21 to 2n can access data registers 121 to 12m through data bus 3 and interface 11.

[0041] System component 1 also includes a processing device 13 capable of processing data for access requests. The processing device 13 may include a microcontroller. The processing device 13 includes a data memory 131 having a direct memory access unit 1311. The processing device 13 may optionally be coupled to a register unit 12.

[0042] Interface 11 can optionally operate in a first operating mode or a second operating mode. In the first operating mode, data for an access request is provided to register unit 12. Register unit 12 identifies the register address based on the access request, taking into account the communication protocol of data bus 3. This identification is preferably performed in hardware. Subsequently, other system components 21 to 2n can access the data register corresponding to the register address identified by register unit 12 via data bus 3 and interface 11 in a read or write manner.

[0043] In the second operating mode, the access request data is passed to the processing device 13 without the aforementioned processing via interface 11. The processing device 13 performs read access or write access.

[0044] Furthermore, register unit 12 can be configured to interpret access request data according to a first communication protocol. Processing device 13 is programmed or can be programmed such that it interprets access request data as a read or write access according to a second communication protocol and operates accordingly. The selection of a first or second operating mode for interface 11 depends on whether the first or second communication protocol is used on data bus 3 (through which system component 1 communicates with other system components 21 to 2n).

[0045] Figure 2 Showing the corresponding condition for satisfying I 2 A schematic diagram of the data sequence of the C standard communication protocol. This data sequence is transmitted via the communication protocol used on data bus 3 (in this case, I). 2 The C protocol was determined.

[0046] exist Figure 2 a) Described according to I 2The first possible data sequence of the C protocol. This data sequence comprises multiple bytes, wherein the first byte B1 corresponds to the slave address, i.e., the address of system component 1 that other system components 21 to 2n want to access. The second byte B2 corresponds to the register address, i.e., the following data registers 121 to 12m of register unit 12 of system component 1: which other system components 21 to 2n need to access in a read or write manner. Other bytes B3 and Bi are optional and correspond to the data to be transmitted, i.e., the actual payload. The total number of bytes can be fixed and pre-given, wherein the invention is not limited to a specific number of bytes, which is expressed by the symbol "Bi".

[0047] exist Figure 2 b) describes the HID-over-I 2 The second possible data sequence for the C protocol, where the first byte B1 again corresponds to the slave address. In this case, the second byte B2 (“RegAddr Low”) and the third byte B3 (“RegAddr High”) together indicate the register address. The other bytes B4 and Bi again correspond to the actual payload.

[0048] exist Figure 2 c) Described according to I 2 The third possible data sequence of the C protocol, in which the register address is not specified. The first byte B1 again corresponds to the slave address, while the other bytes B2 and Bi correspond to the actual payload.

[0049] Figure 3 A schematic diagram showing the data sequence corresponding to the communication protocol that meets the SPI standard.

[0050] exist Figure 3 a1) and 3a2) describe a possible data sequence according to the SPI protocol when performing write access via register address. Figure 3 a1) corresponds to the "Master Out Slave In" (MOSI) signal, where data is transferred from the master to the slave. Here, the first byte B1 includes the first bit b1, which indicates whether a write or read access is involved. The remaining bits b2 of the first byte indicate the register address. The other bytes B2 and Bi correspond to the actual payload. Figure 3 a2) Corresponds to the "Master Input, Slave Output" signal (MISO), where data is transferred from the slave to the master. In this case, bytes B1, B2, and Bi are ignored.

[0051] exist Figure 3 b1) and 3b2) describe a possible data sequence according to the SPI protocol when performing read access via register address. Figure 3 b1 corresponds to the MOSI signal. The first byte B1 again includes the first bit b1, which indicates whether a write or read access is involved. The remaining bits b2 of the first byte indicate the register address. The other bytes B2 and Bi are ignored. Figure 3 b2) Corresponds to the MISO signal. The first byte B1 is ignored, and the other bytes B2 and Bi correspond to valid data.

[0052] exist Figure 3 c1) and 3c2) describe a possible data sequence according to the SPI protocol when performing write / read access without a register address. Figure 3 c1 corresponds to the MOSI signal. Bytes B1 and Bi correspond to the written data. Figure 3 c2) corresponds to the MISO signal, where bytes B1 and Bi correspond to the read data.

[0053] Figure 4 A schematic block diagram showing a portion of a system with system components, corresponding to an I-type system with fixed register allocation. 2 Interface C. As described above, interface 11 is connected to data bus 3. Here, interface 11 operates in the first operating mode, so that the register address is directly read from the logic unit of interface 11. During writing, the second byte B2 is provided to address decoder 7, which may be part of the aforementioned register unit 12. Address decoder 7 obtains the register address. During writing, other bytes B3 and Bi are written to data registers 121, 122, 123, etc., corresponding to the register addresses obtained by address decoder 7.

[0054] A read multiplexer 8 is also provided. During read access, the read multiplexer reads the second byte and other bytes B2 and Bi from data registers 121, 122, 123, etc., and transmits these bytes to interface 11.

[0055] Figure 5 A schematic block diagram of a portion of a system having a system component, including a microcontroller 4 as a processing device for processing data. As described above, interface 11 is connected to data bus 3. Interface 11 is also connected to microcontroller 4 via a buffer register, FIFO, or DMA controller 6.

[0056] In the second operating mode of interface 11, microcontroller 4 can interpret the access request data packet by packet in an interrupt-driven manner. In the case of a write access, microcontroller 4 receives the access request data. In the case of a read access, microcontroller 4 provides the requested data.

[0057] When using the DMA controller 6, in the second operating mode of interface 11, during write access, the requested data is stored in the data memory, allowing the microcontroller 6 to access it. After buffering multiple bytes in the data memory, the microcontroller 4 processes the transferred data. During read access, the microcontroller 4 reads the data from the data memory.

[0058] Figure 6 This diagram shows a schematic block diagram of a portion of a system with system components. As described above, interface 11 is connected to data bus 3. Also included are a microcontroller 4, buffer registers, a FIFO or DMA controller, an address decoder 7, a read multiplexer 8, and data registers 121, 122, 123, etc., as shown in the diagram. Figure 4 and Figure 5 As described in the description, three switching devices Sa, Sb, and Sc are provided, which can switch between first switching states A1, A3, and A5 and second switching states A2, A4, and A6, respectively. The first switching state corresponds to a first operating mode, in which data access is performed using data registers 121, 122, and 123, etc. The second switching state corresponds to a second operating mode, in which data access is performed using microcontroller 4.

[0059] Figure 7 A schematic block diagram of a portion of a system with system components is shown. As described above, interface 11 is connected to data bus 3. Microcontroller 4 is coupled to first data register 121 and second data register 122 via buffer register, FIFO, or DMA controller 6. When interface 11 is running in a second operating mode, read access is performed through first data register 121, and write access is performed through second data register 122. Switching device Sd is capable of switching between a first switch state A7 and a second switch state A8. First switch state A7 corresponds to the first operating mode, and second switch state A8 corresponds to the second operating mode. In the second operating mode, a write access or read access is determined based on the first byte. In this case, the fixed register set (i.e., the data registers starting from the third data register) is turned off. When using DMA controller, FIFO, or buffer register 6 and microcontroller 4, write access is performed through first data register 121. When using DMA controller, FIFO, or buffer register 6 and microcontroller 4, read access is performed through second data register 122. In the second operating mode, depending on the implementation, the second byte accessed can be ignored or used as the payload, and all bytes from the third byte onwards can be processed as the payload. This variant has the advantage of allowing for simpler switching between the two operating modes when necessary.

Claims

1. A system component (1), said system component comprising at least: a. An interface (11) for a data bus (3), the data bus being used to communicate with at least one other system component (21-2n), i. Wherein, a defined communication protocol is used on the data bus (3), the communication protocol determining the data sequence for sending and receiving data access requests, ii. The data in the access request must include at least information about the access direction—either a read access or a write access; b. Register unit (12), which has multiple data registers (121-12m), which can be addressed by register address and can be read and / or written by the data bus (3). Wherein, the register unit (12) interprets the determined data of the access request into a register address based on the data sequence; and c. A processing device (13) for accessing requested data; The interface (11) can optionally operate in either a first operating mode or a second operating mode. In the first operating mode, the access request data is provided to the register unit (12) to identify the register address, thereby enabling corresponding read or write access to the identified data registers (121-12m). In the second operating mode, the data of the access request is provided to the processing device (13), and the processing device (13) performs the corresponding read access or write access.

2. The system component (1) according to claim 1, wherein the register unit (12) is designed such that read access or write access in the first operating mode of the interface (11) is based on hardware.

3. The system component (1) according to any one of claims 1 or 2, wherein the processing device (13) is designed to, in a second operating mode of the interface (11), interpret the data of the access request packet by packet in an interrupt-driven manner, and receive the data of the access request in the case of a write access, and provide the requested data in the case of a read access.

4. The system component (1) according to any one of claims 1 or 2, wherein the system component has a data memory (131) having a direct memory access unit (1311) (Direct Memory Access DMA-Controller), the data memory being associated with the processing device (13), wherein, In the second operating mode of the interface (11), in the case of write access, the DMA controller saves the access request data in the data memory, so that the processing device (13) can access the access request data, and the processing device (13) provides data in the data memory (131). In the case of read access, the DMA controller reads the data from the data memory (131).

5. The system component (1) according to any one of claims 1 or 2, wherein the processing device (13) is coupled to at least one selected data register (121-12m) of the register unit (12) such that when the interface (11) is running in the second operating mode, read access or write access is performed through the register unit (12) and the at least one selected data register (121-12m).

6. The system component (1) according to claim 5, wherein when the interface (11) is running in the second operating mode, the processing device (13) is coupled to at least one first selected data register (121) for read access through the first selected data register, and the processing device (13) is coupled to at least one second selected data register (122) for write access through the at least one second selected data register.

7. The system component (1) according to any one of claims 1 or 2, wherein, The register unit (12) corresponds to the first communication protocol for interpreting the access request data, and The processing device (13) can be programmed to interpret the data of the access request as a read access or write access of the second communication protocol, and to operate accordingly. The selection of the first or second operating mode for the interface (11) depends on whether the first or second communication protocol is used on the data bus (3), wherein the system component (1) communicates with other system components (21-2n) through the data bus.

8. The system component (1) according to any one of claims 1 or 2, wherein, The register unit (12) and / or the processing device (13) correspond to satisfying I 2 The C standard communication protocol interprets access request data.

9. The system component (1) according to any one of claims 1 or 2, wherein the system component has at least one sensor function (14).

10. The system component (1) according to claim 9, wherein the system component comprises at least one MEMS sensor element.

11. A method of using the system component (1) according to any one of claims 1 to 10, wherein the system component is used as a slave in a system comprising at least one master and at least one slave, wherein, The master and slave communicate with each other via the data bus (3) and use a defined communication protocol on the data bus (3).

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