Apparatus and method for driving a display supporting a low power mode

Abstract

A device and method for driving a display supporting a low power mode. When driven in a low power mode, a display driving device supporting a low power mode according to one aspect of the present disclosure can minimize power consumption, and the display driving device includes: a plurality of output buffers, when driving precharged horizontal lines in a display panel, the plurality of output buffers are connected to data lines to precharge the data lines with a first data signal corresponding to a black image, the display panel includes a first area for displaying a standby image and a second area for displaying the black image, the precharged horizontal lines being included in the second area; and a gamma voltage generator, when driving other horizontal lines in the second area except the precharged horizontal lines, the gamma voltage generator is connected to the data lines to output the first data signal to the data lines.

Description

Technical Field

[0001] The present disclosure relates to a display device, and more particularly, to a display driving device and a display driving method. Background Art

[0002] As the information society develops, the demand for display devices for displaying images in various forms increases. According to such demand, various types of display devices such as organic light emitting display devices (OLED) and the like as well as conventional liquid crystal display devices (LCD) are being used.

[0003] The above-mentioned display device is also applied to mobile terminals such as mobile phones, smart phones, tablet computers, laptop computers, and wearable devices. Figure 1 As shown, recently developed mobile terminals support a low power mode such as an always on display (AoD) mode, in which a standby image 110 such as a clock, weather or calendar specified by a user is always displayed on the display device 100 when the mobile terminal is not in use.

[0004] When the mobile device operates in a low power mode, the display device 100 is divided into a first area 120 displaying a black image and a second area 130 displaying a standby image 110 to reduce power consumption.

[0005] At this time, the output buffer (not shown) of each source channel in the first area 120 displaying the black image is not turned off and remains turned on to represent a black voltage corresponding to a black grayscale. However, even if the output buffer of each source channel outputs a black voltage, power is continuously consumed, so there is a problem that there is a limit to the reduction of power consumption in the low power mode. Summary of the invention

[0006] An aspect of the present disclosure provides a display driving apparatus and a display driving method supporting a low power mode, which can minimize power consumption when driven in the low power mode.

[0007] In addition, another aspect of the present disclosure provides a display driving device and a display driving method supporting a low power mode, which can minimize the color difference between black represented in a first panel area and a second panel area when driven in the low power mode.

[0008] In addition, another aspect of the present disclosure provides a display driving device and a display driving method supporting a low power mode, which can reduce a panel load of a display device when driven in the low power mode.

[0009] In addition, another aspect of the present disclosure provides a display driving device and a display driving method supporting a low power mode, which can minimize leakage current generated by a gamma voltage generator that continuously outputs a voltage corresponding to a black grayscale when driven in the low power mode.

[0010] According to one aspect of the present disclosure, a display driving device supporting a low power mode includes: a plurality of output buffers, which are connected to data lines to precharge the data lines with a first data signal corresponding to a black image when driving precharged horizontal lines in a display panel, the display panel including a first area for displaying a standby image and a second area for displaying the black image, the precharged horizontal lines being included in the second area; and a gamma voltage generator, which is connected to the data lines to output the first data signal to each of the data lines when driving horizontal lines other than the precharged horizontal lines in the second area.

[0011] According to another aspect of the present disclosure, a display driving method supporting a low power mode includes the following steps: when driving a first area in a display panel displaying a standby image, connecting a plurality of output buffers to each of the data lines and supplying a data signal of the standby image to the data line; when driving a precharged horizontal line included in a second area displaying a black image, connecting the plurality of output buffers to the data line and precharging the data line with a data signal corresponding to the black image; and when driving other horizontal lines in the second area except the precharged horizontal line, connecting a gamma voltage generator to the data line and outputting a data signal corresponding to the black image to the data line. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this application. The accompanying drawings illustrate embodiments of the present disclosure and together with the description serve to explain the principles of the present disclosure. In the drawings:

[0013] Figure 1 is a diagram showing a display device driven in a low power mode according to the prior art;

[0014] Figure 2 is a diagram showing a configuration of a display system to which a display driving apparatus supporting a low power mode according to an embodiment of the present disclosure is applied;

[0015] Figure 3A is a diagram showing a specific configuration of a display driving device according to an embodiment of the present disclosure;

[0016] Figure 3B It is shown Figure 3A A diagram showing the operation timing of the display drive device;

[0017] Figure 4A is a diagram showing a specific configuration of a display driving device according to another embodiment of the present disclosure;

[0018] Figure 4B It is shown Figure 4A A diagram showing the operation timing of the display drive device;

[0019] Figure 5 is a diagram showing a specific configuration of a display driving device according to another embodiment of the present disclosure;

[0020] Fig. 6A is a diagram showing a specific configuration of a display driving device according to yet another embodiment of the present disclosure;

[0021] Figure 6B It is shown Fig. 6A A diagram showing the operation timing of the display driving device shown; and

[0022] Figure 7 is a flowchart illustrating a display driving method supporting a low power mode according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0023] In the specification, it should be noted that, whenever possible, the same reference numerals that have been used to represent the same elements in other drawings will be used for the elements. In the following description, when functions and configurations known to those skilled in the art are not related to the basic configuration of the present disclosure, their detailed descriptions will be omitted. The terms described in the specification should be understood as follows.

[0024] The advantages and features of the present disclosure and their implementation methods will be explained by the following embodiments described with reference to the accompanying drawings. However, the present disclosure can be implemented in different forms and should not be considered as being limited to the embodiments described herein. On the contrary, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art. In addition, the present disclosure is limited only by the scope of the claims.

[0025] The shapes, sizes, ratios, angles, and quantities disclosed in the accompanying drawings for describing the embodiments of the present disclosure are merely examples, and therefore, the present disclosure is not limited to the details shown. The same reference numerals represent the same elements throughout the specification. In the following description, when it is determined that the detailed description of related known functions or configurations will unnecessarily obscure the focus of the present disclosure, these detailed descriptions will be omitted.

[0026] In the case where “including,” “having,” and “comprising” described in the present specification are used, another part may be added unless “only…” is used. Terms in the singular form may include plural forms unless otherwise indicated.

[0027] When interpreting an element, even if there is no explicit description, the element is interpreted as including a range of errors.

[0028] When describing a time relationship, for example, when a time sequence is described as "after," "subsequently," "next," and "before," discontinuous cases may be included unless "only" or "directly" is used.

[0029] It should be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of the present disclosure.

[0030] The term "at least one" should be understood to include any and all combinations of one or more of the related listed items. For example, the meaning of "at least one of the first, second, and third items" means the combination of all items proposed from two or more of the first, second, and third items as well as the first, second, or third item.

[0031] The features of the various embodiments of the present disclosure may be partially or entirely connected or combined with each other, and may interoperate and be technically driven in various ways as those skilled in the art can fully understand. The embodiments of the present disclosure may be performed independently of each other, or may be performed together in an interdependent relationship.

[0032] Hereinafter, embodiments of the present specification will be described in detail with reference to the accompanying drawings.

[0033] Figure 2 and Figure 3A 2 is a diagram showing a configuration of a display system to which a display driving device supporting a low power mode according to an embodiment of the present disclosure is applied. Figure 2 and Figure 3A According to the present disclosure, a display system 200 includes a display panel 210 and a display driving device 220 for driving the display panel 210 .

[0034] The display panel 210 includes data lines DL, gate lines GL crossing the data lines DL, and pixels P defined by the data lines DL and the gate lines GL. The pixels P are arranged in a matrix form.

[0035] The data line DL supplies the data signal input from the display driving device 220 to the pixel P. The gate line GL supplies the gate signal input from the gate driver 230 to the pixel P. Each pixel P may include sub-pixels (not shown) with different colors for color realization. The sub-pixels may include red sub-pixels, green sub-pixels, and blue sub-pixels. In addition, each pixel P may also include a white sub-pixel.

[0036] In one embodiment, the display panel 210 according to the present disclosure may be an organic light emitting diode (OLED) display panel. In this case, each pixel P may include an organic light emitting diode (OLED), a driving transistor DT, at least one switching transistor, and at least one capacitor. The driving transistor DT controls the amount of current flowing through the organic light emitting diode (OLED). At least one switching transistor controls the operation of the driving transistor DT. In another embodiment, the display panel 210 according to the present disclosure may be a liquid crystal display (LCD) panel.

[0037] Meanwhile, according to the present disclosure, the gate driver 230 may be formed on the display panel 210. The gate driver 230 includes a shift register that outputs a gate pulse synchronized with a data signal in response to a gate timing control signal input through the display driving device 220.

[0038] The gate timing control signal includes a start pulse and a shift clock. The shift register sequentially supplies the gate pulse to the gate lines GL by shifting the start pulse according to the timing of the shift clock.

[0039] A switching transistor included in each pixel P of the display panel 210 is turned on according to a gate pulse to select a data line DL to which a data signal of an input image is inputted of the display panel 210. The shift register may be directly formed on a substrate of the display panel 210 in the same process as a transistor array of a pixel array.

[0040] Meanwhile, in the low power mode (or standby mode) in which the display system 200 is not activated, as shown in FIG. Figure 3A As shown, the display panel 210 according to the present disclosure displays a preset standby image in the first area 310 and a black image in the second area 320. In the normal mode of activating the display system 200, the display panel 210 displays normal images in the first area 310 and the second area 320.

[0041] exist Figure 3A In the embodiment, it is shown that a clock image is displayed as a standby image, but this is only an example, and the standby image may include a calendar image and a weather image, etc. In another embodiment, the standby image may include an image preset by a user.

[0042] The display driving device 220 drives the display panel 210 in the normal mode and the low power mode, supplies data signals of a normal image or a standby image to the data lines DL in the normal mode and the low power mode, and supplies a gate timing control signal including a clock signal CLK to the gate driver 230 .

[0043] To this end, the display driving device 220 includes a timing controller 222 and a data driver 224. Figure 3A As shown, the data driver 224 includes a digital processing unit 330 , an analog processing unit 340 , a gamma voltage generator 350 , and a plurality of first switching units 360 . Figure 3A It is shown that the timing controller 222 is included in the display driving device 220 , but this is merely an example, and the timing controller 222 may be installed separately from the display driving device 220 .

[0044] The timing controller 222 determines the operation mode of the display panel 210 as one of the normal mode and the low power mode, and controls the operations of the data driver 224 and the gate driver 230 according to the determined operation mode.

[0045] Specifically, when the display panel 210 operates in the normal mode, the timing controller 222 controls operations of the data driver 224 and the gate driver 230 so that a data signal of a normal image input from the host system can be supplied to all pixels P included in the display panel 210 .

[0046] In addition, when the display panel 210 operates in the low power mode, the timing controller 222 controls the operations of the data driver 224 and the gate driver 230 so that the data signal ( Figure 3B The data signal of the black image (“Data_SB” in FIG. 1 ) is supplied to the pixels P included in the first area 310 of the display panel 210, and the data signal of the black image ( Figure 3B “00” in ) is supplied to the pixels P included in the second area 320.

[0047] In particular, when the display panel 210 operates in the low power mode, the timing controller 222 according to the present disclosure can enable the analog processing unit 340 to supply the data signal of the black image to some pixels in the second area 320, and can enable the gamma voltage generator 350 to supply the data signal of the black image to the remaining pixels in the second area 320.

[0048] In the present disclosure, the reason why the timing controller 222 supplies the data signal of the black image to the pixels included in the second area 320 using the analog processing unit 340 and the gamma voltage generator 350 is to reduce the color difference between the black displayed in the first area 310 and the black displayed in the second area 320. Specifically, when the black image is displayed in the second area 320 by turning off the transistor of each pixel P by supplying a low potential driving voltage to the pixels P included in the display panel 210, the color difference inevitably occurs between the black displayed in the first area 310 and the black displayed in the second area 320. However, when the data signal of the black image is supplied to the pixels included in the second area 320 using the analog processing unit 340 and the gamma voltage generator 350 as in the present disclosure, the color difference between the black displayed in the first area 310 and the second area 320 does not occur.

[0049] According to the above-mentioned embodiment, the timing controller 222 according to the present disclosure can set one horizontal line among the multiple horizontal lines HL2_1 to HL2_m constituting the second area 320 as the pre-charge horizontal line PC_HL, so that the data signal of the black image can be supplied from the analog processing unit 340 to the pixels included in the pre-charge horizontal line PC_HL, and can enable the data signal of the black image to be supplied from the gamma voltage generator 350 to the pixels included in the other horizontal lines HL2_1 to HL2_i and HL2_j to HL2_m except the pre-charge horizontal line PC_HL.

[0050] In one embodiment, the precharge horizontal line PC_HL may be set as a horizontal line adjacent to the last horizontal line HL1_n of the horizontal lines HL1_1 to HL1_n constituting the first region 310. In this case, when the last horizontal line HL1_n constituting the first region 310 is driven, the analog processing unit 340 supplies the data signal of the standby image to each data line DL, and continuously, when the precharge horizontal line PC_HL is driven, the analog processing unit 340 supplies the data signal of the black image to each data line DL, thereby precharging each data line DL with the data signal of the black image by the analog processing unit 340.

[0051] As described above, in the present disclosure, the reason why the timing controller 222 precharges each data line DL with the data signal of the black image supplied from the analog processing unit 340 when driving the precharge horizontal line PC_HL, and when driving other horizontal lines HL2_j to HL2_m arranged after the precharge horizontal line PC_HL, the timing controller 222 enables the data signal of the black image to be supplied from the gamma voltage generator 350 to each data line DL is as follows.

[0052] When all horizontal lines HL2_1 to HL2_m constituting the second area 320 are driven, if the analog processing unit 340 supplies a data signal of a black image to each data line DL, the analog processing unit 340 has no choice but to continuously operate to provide the data signal of the black image even in the low power mode, so power consumption increases. In addition, when all horizontal lines HL2_1 to HL2_m constituting the second area 320 are driven, if the gamma voltage generator 350 supplies a data signal of a black image to each data line DL, one gamma voltage generator 350 should bear the entire load of the display panel 210, and thus may not meet the settling time required by the display panel 210.

[0053] Therefore, in the present disclosure, when driving the other horizontal lines HL2_1 to HL2_i and HL2_j to HL2_m except the precharge horizontal line PC_HL in the second area 320, the gamma voltage generator 350 supplies the data signal of the black image to each data line DL, and thus the operation of the analog processing unit 340 can be stopped during the corresponding period, thereby minimizing power consumption. In addition, when driving the precharge horizontal line PC_HL, since the analog processing unit 340 supplies the data signal of the black image to each data line DL, each data line DL can be precharged with the data signal of the black image in advance, thereby reducing the panel load that the gamma voltage generator 350 should bear, and thus, the stabilization time can be satisfied.

[0054] In the above embodiment, in the low power mode, the timing controller 222 according to the present disclosure can generate a first switching unit enable signal SW_EN, which turns on and off the multiple first switching units 360 to selectively connect the analog processing unit 340 and one of the gamma voltage generators 350 to each data line DL.

[0055] Specifically, Figure 3B As shown, when the precharge horizontal line PC_HL included in the second area 320 and the first area 310 are driven in the low power mode, the timing controller 222 generates a first switching unit enable signal SW_EN1 of a first logic level (low), and when driving other horizontal lines HL2_1 to HL2_i and HL2_j to HL2_m in the second area 320 except the precharge horizontal line PC_HL, the timing controller 222 generates a first switching unit enable signal SW_EN1 of a second logic level (high).

[0056] The timing controller 222 transmits the generated first switching unit enable signal SW_EN1 to the plurality of first switching units 360 and the analog processing unit 340 .

[0057] In the above embodiment, it is described that the timing controller 222 sets one horizontal line of the plurality of horizontal lines HL2_1 to HL2_m constituting the second area 320 as the precharge horizontal line PC_HL in one frame 1F. However, in another embodiment, the timing controller 222 may set the precharge horizontal line PC_HL according to the amount of leakage current such as Figure 4A As shown in FIG. 1 , a plurality of precharge horizontal lines PC_HL1 and PC_HL2 are set in a plurality of horizontal lines HL2_1 to HL2_m constituting the second region 320 in one frame 1F. For ease of description, Figure 4A It is illustrated that the timing controller 222 sets two precharge horizontal lines PC_HL1 and PC_HL2 , but this is only an example, and the timing controller 222 may also set three or more precharge horizontal lines.

[0058] According to this embodiment, the first precharge horizontal line PC_HL1 may be set as a horizontal line adjacent to the last horizontal line HL1_n of the horizontal lines HL1_1 to HL1_n constituting the first region 310, and the second precharge horizontal line PC_HL2 may be set as a horizontal line spaced apart from the first precharge horizontal line PC_HL1 by a plurality of horizontal lines.

[0059] In this case, if Figure 4B As shown, when the first pre-charge horizontal line PC_HL1 and the second pre-charge horizontal line PC_HL2 included in the second area 320 and the first area 310 are driven in the low power mode, the timing controller 222 generates a first switching unit enable signal SW_EN1 of a first logic level, and when driving other horizontal lines HL2_1 to HL2_i and HL2_j to HL2_m in the second area 320 except the first pre-charge horizontal line PC_HL1 and the second pre-charge horizontal line PC_HL2, the timing controller 222 generates a first switching unit enable signal SW_EN1 of a second logic level.

[0060] Meanwhile, the timing controller 222 receives a timing signal from the host system to display a normal image or a standby image, and generates a data timing control signal for controlling the operation timing of the data driver 224 and a gate timing control signal for controlling the operation timing of the gate driver 230. In one embodiment, the timing signal may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a dot clock CLK, a data enable signal DE, etc. The timing controller 222 supplies the data timing control signal together with the first switching unit enable signal SW_EN1 to the data driver 224, and supplies the gate timing control signal to the gate driver 230.

[0061] In an embodiment, the data timing control signal may include a source start pulse (SSP), a source sampling clock (SSC), a source output enable signal, etc., and the gate timing control signal may include a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal, etc.

[0062] Here, the source start pulse (SSP) is a signal for controlling the data sampling start timing of the digital processing unit 330 included in the data driver 224. The source sampling clock (SSC) is a clock signal for controlling the data sampling timing in the digital processing unit 330. The source output enable signal is a signal for controlling the output timing of the data signal.

[0063] The gate start pulse (GSP) is a signal for controlling the operation start timing of the gate driver 230. The gate shift clock (GSC) is a clock signal input to the gate driver 230 and is a signal for controlling the shift timing of the gate pulse. The gate output enable signal specifies the timing information of the gate driver 230.

[0064] The data driver 224 generates a data signal for a normal image, a data signal for a standby image, or a data signal for a black image according to the data timing control signal input from the timing controller 222 and the first switching unit enable signal SW_EN1 to supply the data signal to each pixel P of the display panel 210 through the data line DL.

[0065] Specifically, the digital processing unit 330 included in the data driver 224 latches a normal image in the normal mode, or latches a standby image or a black image in the low power mode to supply the image to the analog processing unit 340. To this end, the digital processing unit 330 may include a shift register (not shown) that sequentially generates a sampling clock by shifting a source start pulse (SSP) according to a source shift clock (SSC), and a latch (not shown) that sequentially latches a normal image, a standby image, or a black image according to the sampling clock.

[0066] The analog processing unit 340 included in the data driver 224 converts a normal image, a standby image, or a black image output from the digital processing unit 330 into a data signal in an analog format using a gamma voltage provided from the gamma voltage generator 350 and outputs the converted data signal to each data line DL.

[0067] To this end, the analog processing unit 340 may include a digital-to-analog converter 342 and multiple output buffers 344, wherein the digital-to-analog converter 342 converts a normal image, a standby image or a black image supplied to each data line DL into a data signal in an analog format, and the multiple output buffers 344 output the data signal to each data line DL.

[0068] According to this embodiment, when operating in the normal mode, each output buffer 344 supplies a data signal of a normal image to each data line DL, and when operating in the low power mode, Figure 3B As shown, when driving the horizontal lines HL1 to HLn included in the first area 310, each output buffer 344 supplies the data signal Data_SB of the standby image to each data line DL, and when driving the precharge horizontal line PC_HL included in the second area 320, each output buffer 344 supplies the data signal 00 of the black image to each data line DL.

[0069] At the same time, when operating in low power mode, such as Figure 3B As shown, when driving the other horizontal lines HL2_1 to HL2_i and HL2_j to HL2_m except the precharge horizontal line PC_HL in the second area 320, each output buffer 344 switches the output channel to a high impedance state according to the first switching unit enable signal SW_EN1 transmitted from the timing controller 222. Therefore, each output buffer 344 stops operating without being connected to the data line DL, thereby minimizing power consumption.

[0070] In the above embodiment, it is described that each output buffer 344 is connected to the data line DL or converted into a high impedance state according to the first switching unit enable signal SW_EN1 input from the timing controller 222. However, in another embodiment, the state of each output buffer 344 may be controlled according to a separate output buffer enable signal for controlling the state of the output buffer 344.

[0071] In this case, the timing controller 222 may generate an output buffer enable signal for controlling the state of the output buffer 344 to transmit the output buffer enable signal to each output buffer 344. In an embodiment, the timing controller 222 may generate the output buffer enable signal by inverting the first switching unit enable signal SW_EN1. That is, when the first switching unit enable signal SW_EN1 transitions from the second logic level to the first logic level, the output buffer enable signal transitions from the first logic level to the second logic level, and when the first switching unit enable signal SW_EN1 transitions from the first logic level to the second logic level, the output buffer enable signal transitions from the second logic level to the first logic level.

[0072] When operating in a normal mode or a low power mode, the gamma voltage generator 350 generates a plurality of gray voltages (eg, V0 to V255 ) using a resistor string for outputting a normal image or a standby image, and provides the generated plurality of gray voltages to the analog processing unit 340 .

[0073] In particular, when operating in low power mode, such as Figure 3B As shown, when driving other horizontal lines HL2_1 to HL2_i, HL2_j to HL2_m included in the second area 320 except the precharge horizontal line PC_HL, the gamma voltage generator 350 according to the present disclosure is connected to each data line DL through the first switching unit 360 to supply the data signal 00 of the black image to each data line DL.

[0074] At the same time, if Figure 3B As shown, when operating in the low power mode, when driving the precharge horizontal line PC_HL and the horizontal lines HL1 to HLn included in the first area 310, the gamma voltage generator 350 is separated from each data line DL.

[0075] In the above embodiment, it is described that when the analog processing unit 340 operates in the low power mode, when the precharge horizontal line PC_HL is driven, the analog processing unit 340 supplies the data signal of the black image not only to the first data line DL_1 connected to the first pixel adjacent to the first area 310 among the pixels of the precharge horizontal line PC_HL, but also to the second data line DL_2 connected to the second pixel other than the first pixel adjacent to the first area 310. This is because when the precharge horizontal line PC_HL is driven, the analog processing unit 340 also supplies the data signal of the black image to the second data line DL_2, so that the second data line DL_2 can also be precharged frame by frame, thereby preventing discharge due to leakage current.

[0076] Therefore, when the amount of leakage current is not large, the analog processing unit 340 supplies only the data signal of the black image to the first data line DL_1 and the gamma voltage generator 350 may supply the data signal of the black image to the second data line DL_2 when driving the precharge horizontal line PC_HL.

[0077] Refer again Figure 3A , the plurality of first switching units 360 are turned on and off according to the first switching unit enable signal SW_EN1 input from the timing controller 222 to selectively connect the gamma voltage generator 350 to each data line DL. Specifically, as Figure 3BAs shown, when the first switching unit enable signal SW_EN1 of the first logic level is input, the first switching unit 360 is turned off so that the gamma voltage generator 350 is separated from each data line DL. In addition, when the first switching unit enable signal SW_EN1 of the second logic level is input, the first switching unit 360 is turned on so that the gamma voltage generator 350 is connected to each data line DL.

[0078] At the same time, Figure 3A , it is described that the plurality of first switching units 360 are turned on and off according to the first switching unit enable signal SW_EN1 input from the timing controller 222 to selectively connect the gamma voltage generator 350 to each data line DL, and when the gamma voltage generator 350 is connected to the data line DL, the output buffer 344 is controlled to a high impedance state.

[0079] However, in another embodiment, if Figure 5 As shown, the plurality of first switching units 360 may selectively connect one of the gamma voltage generator 350 and the output buffer 344 to the data line DL according to the first switching unit enable signal SW_EN1 input from the timing controller 222. That is, when the first switching unit enable signal SW_EN1 of a first logic level is input, the first switching unit 360 may connect the output buffer 344 to each data line DL and may separate the gamma voltage generator 350 from the data line DL, and when the first switching unit enable signal SW_EN1 of a second logic level is input, the first switching unit 360 may connect the gamma voltage generator 350 to each data line DL and may separate the output buffer 344 from each data line DL.

[0080] As another example, Fig. 6A As shown, the data driver 224 may further include a plurality of second switching units 370 selectively connecting each output buffer 344 to each data line DL in addition to the first switching unit 360 selectively connecting the gamma voltage generator 350 to each data line DL.

[0081] According to this embodiment, the first switching unit 360 and the second switching unit 370 operate complementarily, and as Figure 6B As shown, the timing controller 222 may additionally generate a second switching unit enable signal SW_EN2 for controlling the second switching unit 370 .

[0082] Specifically, when operating in the low power mode, when driving the precharge horizontal line PC_HL included in the second region 320 and the first region 310, the timing controller 222 generates a first switching unit enable signal SW_EN1 of a first logic level (low) to supply the first switching unit enable signal SW_EN1 to the first switching unit 360, and generates a second switching unit enable signal SW_EN2 of a second logic level (high) to supply the second switching unit enable signal SW_EN2 to the second switching unit 370.

[0083] Therefore, the first switching unit 360 is turned off to separate the gamma voltage generator 350 from the data lines DL, and the second switching unit 370 is turned on to connect the output buffer 344 to each data line DL.

[0084] In addition, when operating in the low power mode, when driving other horizontal lines HL2_1 to HL2_i and HL2_j to HL2_m in the second area 320 except the pre-charge horizontal line PC_HL, the timing controller 222 generates a first switching unit enable signal SW_EN1 of a second logic level (high) to supply the first switching unit enable signal SW_EN1 to the first switching unit 360, and generates a second switching unit enable signal SW_EN2 of a first logic level (low) to supply the second switching unit enable signal SW_EN2 to the second switching unit 370.

[0085] Therefore, the first switching unit 360 is turned on to connect the gamma voltage generator 350 to the data lines DL, and the second switching unit 370 is turned off to separate the output buffer 344 from each data line DL.

[0086] The display system 200 according to the embodiment of the present disclosure as described above may be provided in a mobile terminal (not shown). In an embodiment, the mobile terminal may include a mobile phone, a smart phone, a tablet computer, or a wearable device, etc. In another embodiment, the display system 200 may be provided in a device such as a television (TV) or a monitor.

[0087] Hereinafter, a display driving method supporting a low power mode according to the present disclosure will be described.

[0088] Figure 7 is a flow chart showing a display driving method supporting a low power mode according to an embodiment of the present disclosure. Figure 7 The display driving method supporting the low power mode shown (hereinafter referred to as "display driving method") can be Figure 3A The display driver shown is executed.

[0089] The display driving device determines an operation mode of the display system (S700). In an embodiment, the operation mode of the display system may include a normal mode and a low power mode, in which a normal image is displayed in the first area and the second area of ​​the display panel, and in which a standby image is displayed in the first area of ​​the display panel and a black image is displayed in the second area of ​​the display panel. In this case, the standby image may include a clock image, a calendar image, a weather image, etc., or may include an image preset by a user.

[0090] In the above embodiment, when the mobile terminal to which the display system is applied is in an active state, the display driving device may determine the operation mode of the display system to be a normal mode, and when the mobile terminal is in an inactive state, the display driving device may determine the operation mode of the display system to be a low power mode.

[0091] When the operation mode of the display system is determined to be the normal mode, the display driving apparatus supplies a data signal of a normal image input from the host system to each data line of the display panel (S710).

[0092] Meanwhile, when the operation mode of the display system is determined to be the low power mode, the display driving apparatus determines whether the area to be driven of the display panel is a first area to display a standby image or a second area to display a black image (S720).

[0093] When the region to be driven is the first region, the display driving device connects each output buffer to the data line so that each output buffer supplies a data signal of a standby image to each data line (S730).

[0094] Meanwhile, when it is determined as a result of the determination in S720 that the region to be driven is the second region, the display driving device determines whether the horizontal line to be driven is a precharged horizontal line ( S740 ).

[0095] When it is determined as a result of the determination that the horizontal line to be driven is a precharge horizontal line, the display driving apparatus connects each output buffer to the data line so that each output buffer precharges each data line with a data signal of a black image (S750).

[0096] In an embodiment, the precharge horizontal line may be set to a horizontal line adjacent to the last horizontal line among the horizontal lines constituting the first region. In this case, when the last horizontal line constituting the first region is driven, the output buffer supplies the data signal of the standby image to each data line, and continuously, when the precharge horizontal line is driven, the output buffer supplies the data signal of the black image to each data line, so that each data line is precharged with the data signal of the black image through the output buffer.

[0097] Meanwhile, when it is determined as a result of the determination of S740 that the horizontal line to be driven is a horizontal line other than the precharged horizontal line, or when the precharge of the data line performed by S750 is completed, the display driving device connects the gamma voltage generator to each data line through the first switching unit so that the gamma voltage generator supplies the data signal of the black image to each data line (S760). In this case, the output buffer is controlled to be in a high impedance state and separated from the data line, and the operation is stopped.

[0098] As described above, in the present disclosure, after precharging each data line with the data signal of the black image provided from the output buffer when driving the precharge horizontal line, the display driving device supplies the data signal of the black image from the gamma voltage generator to each data line for the following reason.

[0099] When driving all the horizontal lines constituting the second area, if the output buffer supplies the data signal of the black image to each data line, the output buffer has no choice but to continuously operate to provide the data signal of the black image even in the low power mode, so the power consumption increases, and when driving all the horizontal lines constituting the second area, if the gamma voltage generator supplies the data signal of the black image to each data line, one gamma voltage generator should bear the entire load of the display panel, and thus may not be able to meet the stabilization time required for the display panel.

[0100] Therefore, in the present disclosure, when driving the precharged horizontal lines included in the second area, the output buffer precharges the data lines with the data signals of the black image, and then, when driving the other horizontal lines included in the second area, the gamma voltage generator supplies the data signals of the black image to the data lines, so that the panel load that the gamma voltage generator should bear can be reduced to meet the stabilization time, and the operation of the output buffer can be stopped during the period after the precharging of the precharged horizontal lines is completed, thereby minimizing power consumption.

[0101] In the above embodiment, it is described that there is one precharge horizontal line, but a plurality of precharge horizontal lines may be set according to the amount of leakage current. According to this embodiment, the first precharge horizontal line may be set to a horizontal line adjacent to the last horizontal line among the horizontal lines constituting the first region, and the second precharge horizontal line may be set to a horizontal line separated from the first precharge horizontal line by a plurality of horizontal lines.

[0102] In addition, in the above-mentioned embodiment, it is described that when the output buffer operates in the low power mode, when the precharge horizontal line is driven, the output buffer not only supplies the data signal of the black image to the first data line connected to the first pixel adjacent to the first area among the pixels of the precharge horizontal line, but also supplies the data signal of the black image to the second data line connected to the second pixel other than the first pixel adjacent to the first area. This is because when the precharge horizontal line is driven, the output buffer also supplies the data signal of the black image to the second data line, so that the second data line can also be precharged frame by frame, thereby preventing discharge due to leakage current.

[0103] Therefore, when the amount of leakage current is not large, the output buffer supplies only the data signal of the black image to the first data line and the gamma voltage generator may supply the data signal of the black image to the second data line when driving the precharge horizontal line.

[0104] According to the present disclosure, when driven in a low power mode, in a first panel area displaying a black image, a gamma voltage generator may supply a voltage corresponding to a black grayscale to each source channel to display a black image, and thus there is an effect that driving of an output buffer of each source channel may be stopped and power consumption may be reduced.

[0105] In addition, according to the present disclosure, when driven in a low power mode, a voltage corresponding to a black grayscale generated by a gamma voltage generator in the first panel area is supplied to each source channel, thereby having an effect of reducing the color difference between a black image displayed in the second panel area and a black image displayed in the first panel area.

[0106] In addition, according to the present disclosure, data lines connected to pixels included in pre-charged horizontal lines among horizontal lines included in the first panel area are pre-charged with a voltage corresponding to the black gray scale output from an output buffer, and therefore, even when a normal horizontal line adjacent to the pre-charged horizontal line is driven, the gamma voltage generator supplies a voltage corresponding to the black gray scale to each data line, and thus, an increase in the panel load is minimized, and thus, there is an effect that a stabilization time can be satisfied and degradation of image quality can be prevented.

[0107] In addition, according to the present disclosure, each data line can be precharged in units of precharge horizontal lines by setting a plurality of precharge horizontal lines, and thus the leakage current generated by the gamma voltage generator that continuously supplies a voltage corresponding to the black grayscale in the first panel area can be minimized, thereby having the effect of suppressing the increase in power consumption.

[0108] In addition, according to the present disclosure, data lines connected to pixels not adjacent to pixels included in the second panel area among pixels included in the precharge horizontal line can also be precharged through the output buffer, and thus there is an effect of maximally preventing leakage current from being generated.

[0109] It should be understood by those skilled in the art that the present disclosure may be implemented in other specific forms without changing the technical concept and essential features of the present disclosure.

[0110] All disclosed methods and processes described herein may be implemented at least in part using one or more computer programs or components. These components may be provided as a series of computer instructions by any conventional computer-readable medium or machine-readable medium including volatile and non-volatile memory such as random access memory (RAM), read-only memory (ROM), flash memory, disk or optical disk, optical memory or other storage medium. Instructions may be provided as software or firmware, and may be implemented in whole or in part in a hardware configuration such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP) or any other similar device. Instructions may be configured to be executed by one or more processors or other hardware configurations, and when executing a series of computer instructions, the processor or other hardware configuration executes all or part of the methods and processes disclosed herein.

[0111] Therefore, the above embodiments should be understood to be exemplary and not restrictive in every aspect. The scope of the present disclosure will be defined by the appended claims rather than the above specific description, and all changes and modifications derived from the meaning and scope of the claims and their equivalents should be understood to be included in the scope of the present disclosure.

[0112] CROSS-REFERENCE TO RELATED APPLICATIONS

[0113] This application claims the benefit of Korean Patent Application No. 10-2020-0054902, filed on May 8, 2020, which is hereby incorporated by reference as if fully set forth herein.

Claims

1. A display driving device supporting a low power mode, the display driving device comprising: a plurality of output buffers connected to the data lines to output first data signals corresponding to a black image to pixels included in the precharged horizontal lines when the precharged horizontal lines in the display panel are driven, the display panel including a first area displaying a standby image and a second area displaying the black image, the precharged horizontal lines being included in the second area; as well as A gamma voltage generator connected to the data line to output the first data signal to pixels included in the other horizontal lines except the precharge horizontal line in the second area when the other horizontal lines are driven.

2. The display driving device according to claim 1, wherein: The precharge horizontal line includes a first precharge horizontal line adjacent to a last horizontal line included in the first region among horizontal lines included in the second region.

3. The display driving device according to claim 2, wherein: The pre-charge levels further include at least one second pre-charge level that is spaced apart from the first pre-charge level by a predetermined number of levels.

4. The display driving device according to claim 1, further comprising: a plurality of first switching units configured to selectively connect the gamma voltage generator to the data line; as well as a timing controller configured to generate a first switching unit enable signal for on-off control of the plurality of first switching units, Wherein, when the first switching unit enable signal having a first logic level is input from the timing controller, the plurality of first switching units are turned off to separate the gamma voltage generator from the data line, and when the first switching unit enable signal having a second logic level is input, the plurality of first switching units are turned on to connect the gamma voltage generator to the data line.

5. The display driving device according to claim 4, wherein: When the first switching unit enable signal having the second logic level is input from the timing controller, the multiple output buffers are maintained in a high impedance state and stop driving, and when the first switching unit enable signal having the first logic level is input, the multiple output buffers supply the first data signal to each of the data lines.

6. The display driving device according to claim 1, further comprising: a plurality of first switching units configured to selectively connect one of the plurality of output buffers and the gamma voltage generator to the data line; as well as a timing controller configured to generate a first switching unit enable signal for controlling the plurality of first switching units, Wherein, when the first switching unit enable signal having a first logic level is input from the timing controller, the multiple first switching units connect the multiple output buffers to the data lines, and when the first switching unit enable signal having a second logic level is input, the multiple first switching units connect the gamma voltage generator to the data lines.

7. The display driving device according to claim 1, further comprising: a plurality of first switching units configured to selectively connect the gamma voltage generator to the data line; a plurality of second switching units configured to selectively connect the plurality of output buffers to the data lines; as well as a timing controller configured to generate a second switching unit enable signal for controlling the plurality of first switching units and the plurality of second switching units, wherein the plurality of first switching units and the plurality of second switching units operate complementarily, and when a second switching unit enable signal having a first logic level is input from the timing controller, the plurality of first switching units are turned off and the plurality of second switching units are turned on to connect the plurality of output buffers to the data lines, and when a second switching unit enable signal having a second logic level is input from the timing controller, the plurality of first switching units are turned on and the plurality of second switching units are turned off to connect the gamma voltage generator to the data lines.

8. The display driving device according to claim 1 further comprises a timing controller, wherein the timing controller is configured to operate the display panel in one of a low power mode and a normal mode, wherein the standby image is displayed in the first area and the black image is displayed in the second area in the low power mode, and a normal image is displayed in the first area and the second area in the normal mode.

9. The display driving device according to claim 1, wherein: When the first area is driven, the plurality of output buffers are connected to the data lines to output second data signals of the standby image to the data lines, and The gamma voltage generator generates gamma voltages corresponding to a plurality of grayscales representing the standby image to output the gamma voltages to the plurality of output buffers.

10. The display driving device according to claim 1, wherein: The precharge horizontal line is set to a horizontal line adjacent to a last horizontal line constituting the first area among a plurality of horizontal lines included in the second area, and When the precharge horizontal line is driven, the plurality of output buffers precharge a first data line connected to a first pixel adjacent to the first region among pixels included in the precharge horizontal line with the first data signal.

11. The display driving device according to claim 10, wherein: When driving the precharge horizontal line, the gamma voltage generator outputs the first data signal to a second data line connected to a second pixel other than the first pixel among pixels included in the precharge horizontal line.

12. A display driving method supporting a low power mode, the display driving method comprising the following steps: When driving a first area of ​​the display panel displaying a standby image, connecting a plurality of output buffers to the data lines, and supplying a data signal of the standby image to each of the data lines; When driving the precharged horizontal lines included in the second area displaying a black image, connecting the plurality of output buffers to the data lines to output first data signals corresponding to the black image to pixels included in the precharged horizontal lines; as well as When other horizontal lines except the precharge horizontal line in the second area are driven, a gamma voltage generator is connected to the data line to output the first data signal to pixels included in the other horizontal lines.

13. The display driving method according to claim 12, wherein: The precharge horizontal line includes a first precharge horizontal line adjacent to a last horizontal line included in the first region among horizontal lines included in the second region.

14. The display driving method according to claim 13, wherein: In the precharge operation, the plurality of output buffers precharge a first data line connected to a first pixel adjacent to the first region among pixels included in the first precharge horizontal line with the data signal corresponding to the black image.

15. The display driving method according to claim 13, wherein: The pre-charge levels further include at least one second pre-charge level that is spaced apart from the first pre-charge level by a predetermined number of levels.

16. The display driving method according to claim 12, wherein: In a precharge operation, the gamma voltage generator is separated from the data line according to a first switching unit enable signal having a first logic level, and In an output operation, the gamma voltage generator is connected to the data line according to the first switching unit enable signal having a second logic level, and the plurality of output buffers are maintained in a high impedance state.

17. The display driving method according to claim 12, wherein: In a precharge operation, the plurality of output buffers are connected to the data lines according to a first switching unit enable signal having a first logic level, and In an output operation, the gamma voltage generator is connected to the data line according to the first switching unit enable signal having a second logic level.

18. The display driving method according to claim 12, wherein: In a precharge operation, the gamma voltage generator is separated from the data line according to a first switching unit enable signal having a first logic level, and the plurality of output buffers are connected to the data line according to a second switching unit enable signal having a second logic level, and In an output operation, the gamma voltage generator is connected to the data line according to the first switching unit enable signal having a second logic level, and the plurality of output buffers are separated from the data line according to the second switching unit enable signal having a first logic level.

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