Memory device, integrated circuit device and operation method thereof

Abstract

Embodiments of the present invention provide a memory device, an integrated circuit device and an operation method thereof. The memory device includes at least one bit line, at least one source line, at least one programming word line, at least one reading word line and at least one memory cell including a programming transistor and a reading transistor. The programming transistor includes a gate terminal coupled to at least one programming word line, a first terminal coupled to at least one source line and a second terminal. The reading transistor includes a gate terminal coupled to at least one reading word line, a first terminal coupled to at least one bit line and a second terminal coupled to the programming transistor.

Description

Technical Field

[0001] Embodiments of the present invention relate to memory devices, integrated circuit devices and methods of operating the same. Background Art

[0002] An integrated circuit (IC) device includes a plurality of semiconductor devices represented by an IC layout diagram. The IC layout diagram is hierarchical and includes modules that perform higher-level functions according to semiconductor device design specifications. Modules are typically constructed by a combination of cells, each of which represents one or more semiconductor structures configured to perform a specific function. Cells (sometimes also referred to as standard cells) with pre-designed layout diagrams are stored in a standard cell library (hereinafter referred to as a "library" or "cell library" for simplicity) and can be accessed by various tools (e.g., electronic design automation (EDA) tools) to enable generation, optimization, and verification of IC designs. Examples of semiconductor devices and cells include memory devices and memory cells, respectively. Summary of the invention

[0003] According to one aspect of an embodiment of the present invention, a memory device is provided, comprising: at least one bit line; at least one source line; at least one programming word line; at least one reading word line; and at least one memory cell, comprising a programming transistor and a reading transistor.

[0004] wherein the programming transistor comprises: a gate terminal coupled to at least one programming word line, a first terminal coupled to at least one source line, and a second terminal, and

[0005] The read transistor includes a gate terminal coupled to at least one read word line, a first terminal coupled to at least one bit line, and a second terminal coupled to the programming transistor.

[0006] According to one aspect of an embodiment of the present invention, an integrated circuit (IC) device is provided, comprising: a first active region extending along a first direction; a first pair of gate regions extending across the first active region along a second direction transverse to the first direction, wherein the first pair of gate regions and the first active region configure a first programming transistor and a first reading transistor shares a common source / drain region; and

[0007] The first metal layer includes: a first programming word line pattern, which is above the gate region of the first programming transistor and coupled to the gate region of the first programming transistor, a first reading word line pattern, which is above the gate region of the first reading transistor and coupled to the gate region of the first reading transistor, a first source line pattern, which is coupled to another source / drain region of the first programming transistor, and a first bit line pattern, which is coupled to another source / drain region of the first reading transistor.

[0008] According to another aspect of an embodiment of the present invention, a method for operating a memory device is provided, comprising: in a programming operation of a memory cell having a programming transistor, applying a higher voltage to the source / drain of the programming transistor and applying a lower voltage to the gate of the programming transistor, wherein the voltage difference between the higher voltage and the lower voltage is equal to or higher than a predetermined breakdown voltage to break down the gate dielectric of the programming transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Various aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are for illustration purposes only. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0010] Figure 1 is a schematic block diagram of a memory device according to some embodiments.

[0011] Figure 2 is a schematic circuit diagram of a memory cell according to some embodiments.

[0012] FIG. 3A to FIG. 3B is a schematic circuit diagram of a memory device in various operations according to some embodiments.

[0013] Figure 4 is a schematic circuit diagram of a memory device according to some embodiments.

[0014] Figure 5A-Figure 5C is a schematic diagram at various layers in an IC layout diagram of a memory device according to some embodiments.

[0015] Fig. 6A is a schematic diagram of an IC layout diagram of a memory device according to some embodiments.

[0016] Figure 6B is a schematic diagram of an IC layout diagram of a memory device according to some embodiments.

[0017] Figure 7A-7C are various layouts of memory cells in a memory device according to some embodiments.

[0018] Figure 8 is a schematic cross-sectional view of an IC device according to some embodiments.

[0019] Fig. 9 is a flow chart of a method according to some embodiments.

[0020] Fig.10 is a flow chart of a method according to some embodiments.

[0021] Fig.11 is a flow chart of a method according to some embodiments.

[0022] Fig.12 is a block diagram of an EDA system according to some embodiments.

[0023] Fig.13 is a block diagram of an IC manufacturing system and an IC manufacturing flow associated therewith, according to some embodiments. DETAILED DESCRIPTION

[0024] The following disclosure provides many different embodiments or examples for realizing different features of the present invention. Specific embodiments or examples of components and arrangements are described below to simplify the present invention. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0025] In addition, for ease of description, spacing relation terms such as "below", "beneath", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. In addition to the orientation shown in the figures, the spacing relation terms are intended to encompass different orientations of the device in use or operating processes. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spacing relation descriptors used herein should be interpreted accordingly.

[0026] The memory cell includes a programming transistor and a reading transistor coupled in series with each other. In some embodiments, in a programming operation of the memory cell, a higher voltage is applied to the source or drain of the programming transistor, and a lower voltage is applied to the gate of the programming transistor. The voltage difference between the higher voltage and the lower voltage is applied to the gate dielectric of the programming transistor and is equal to or higher than a predetermined breakdown voltage sufficient to break down the gate dielectric. As a result, the memory cell is programmed to store a first data corresponding to the broken down gate dielectric. When the gate dielectric has not yet been broken down, the memory cell stores a second data different from the first data. In one example, the first data is a logic "0" and the second data is a logic "1". In another example, the first data is a logic "1" and the second data is a logic "0". Compared to other methods of applying a higher voltage to the gate terminal of the programming transistor instead of the source or drain in a programming operation, it is possible to achieve one or more improvements in at least one embodiment, including but not limited to reduced leakage current, increased reliability, etc.

[0027] Figure 1 1 is a schematic block diagram of a memory device 100 according to some embodiments. The memory device is a type of IC device. In at least one embodiment, the memory device is a separate IC device. In some embodiments, the memory device is included as part of a larger IC device that includes circuits for other functions in addition to the memory device.

[0028] The memory device 100 includes at least one memory cell MC and a controller (also referred to as a “control circuit”) 102, which is coupled to control the operation of the memory cell MC. Figure 1In an example configuration, the memory device 100 includes a plurality of memory cells MC arranged in a plurality of columns and rows in a memory array 104. The memory device 100 also includes a plurality of read word lines WLR0, WLR1 to WLRm and a plurality of programming word lines WLP0, WLP1 to WLPm extending along the rows of the memory array 104. The memory device 100 also includes a plurality of source lines SL0, SL1 to SLk and a plurality of bit lines BL0, BL1 to BLk extending along the columns of the memory array 104. The read word lines are generally referred to herein as WLR, the programming word lines are generally referred to herein as WLP, the read word lines WLR and the programming word lines WLP are generally referred to herein as word lines, the source lines are generally referred to herein as SL, and the bit lines are generally referred to herein as BL. Each memory cell MC is coupled to the controller 102 via a corresponding read word line WLR, a corresponding programming word line WLP, a corresponding source line SL, and a corresponding bit line BL. The read word line WLR and / or the programming word line WLP are configured to transmit addresses of memory cells MC to be read and / or written thereto, etc. The read word lines WLR and / or the program word lines WLP are sometimes referred to as "address lines". The source lines SL and / or the bit lines BL are configured to transmit data to be written to and / or read from the memory cells MC indicated by the addresses on the corresponding word lines WLR, WLP, etc. The source lines SL and / or the bit lines BL are sometimes referred to as "data lines". Various numbers of word lines WLR, WLP and / or bit lines BL and / or source lines SL in the memory device 100 are within the scope of various embodiments.

[0029] exist Figure 1 In an example configuration, the controller 102 includes a word line driver 112, a source line driver 114, a bit line driver 116, and a sense amplifier (SA) 118 configured to perform at least one of a read operation or a write operation. In at least one embodiment, the controller 102 also includes: one or more clock generators for providing clock signals to various components of the memory device 100; one or more input / output (I / O) circuits for exchanging data with external devices; and / or one or more controllers for controlling various operations in the memory device 100.

[0030] The word line driver 112 (also referred to as a "WL decoder") is coupled to the memory array 104 via word lines WLR, WLP. The word line driver 112 is configured to decode the row address of the memory cell MC selected for access in a read operation or a write operation. The word line driver 112 is configured to provide a set of voltages to the selected word lines WLR, WLP corresponding to the decoded row address, and to provide a different set of voltages to other unselected word lines WLR, WLP. The source line driver 114 (also referred to as a "SL decoder") is coupled to the memory array 104 via source lines SL. The bit line driver 116 (also referred to as a "BL decoder") is coupled to the memory array 104 via bit lines BL. The source line driver 114 and / or the bit line driver 116 are configured to decode the column address of the memory cell MC selected for access in a read operation or a write operation. The source line driver 114 and / or the bit line driver 116 are configured to provide a set of voltages to the selected source line SL and the selected bit line BL corresponding to the selected memory cell MC, and to provide a different set of voltages to other unselected source lines SL and bit lines BL. For example, in a write operation (also referred to as a "programming operation"), the source line driver 114 is configured to provide a write voltage (also referred to as a "programming voltage") to the selected source line SL. In a read operation, the source line driver 114 is configured to provide a read voltage to the selected source line SL. SA 118 is coupled to the memory array 104 via the bit line BL. In a read operation, SA 118 is configured to sense data read from the accessed memory cell MC and retrieved through the corresponding selected bit line BL. The described memory device configuration is an example, and other memory device configurations are within the scope of various embodiments. In at least one embodiment, the memory device 100 is a one-time programmable (OTP) non-volatile memory, and the memory cell MC is an OTP memory cell. Other types of memory are within the scope of various embodiments.

[0031] Figure 2 is a schematic circuit diagram of a memory cell 200 according to some embodiments. In at least one embodiment, the memory cell 200 corresponds to at least one of the memory cells MC in the memory device 100.

[0032] exist Figure 2, a memory cell 200 is coupled to a programming word line WLP, a reading word line WLR, a source line SL, and a bit line BL. The memory cell 200 includes a programming transistor TP and a reading transistor TR. The programming transistor TP includes a gate terminal 210 coupled to the programming word line WLP, a first terminal 211 coupled to the source line SL, and a second terminal 212. The reading transistor TR includes a gate terminal 220 coupled to the reading word line WLR, a first terminal 221 coupled to the bit line BL, and a second terminal 222 coupled to the second terminal 212 of the programming transistor TP. In other words, the programming transistor TP and the reading transistor TR are coupled to each other in series.

[0033] Examples of programming transistor TP and / or reading transistor TR include, but are not limited to, metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, P-channel metal oxide semiconductors (PMOS), N-channel metal oxide semiconductors (NMOS), bipolar junction transistors (BJTs), high voltage transistors, high frequency transistors, P-channel and / or N-channel field effect transistors (PFET / NFET), FinFETs, planar MOS transistors with elevated source / drain, nanosheet FETs, nanowire FETs, etc. The first terminal 211 is the source / drain of the programming transistor TP, and the second terminal 212 is another source / drain of the programming transistor TP. The first terminal 221 is the source / drain of the reading transistor TR, and the second terminal 222 is another source / drain of the reading transistor TR. In regard to Figure 2 In the described example configuration, the programming transistor TP and the reading transistor TR are NMOS transistors, the first terminal 211 is the source of the programming transistor TP, the second terminal 212 is the drain of the programming transistor TP, the first terminal 221 is the drain of the reading transistor TR, and the second terminal 222 is the source of the reading transistor TR. Other configurations including PMOS transistors instead of NMOS transistors are within the scope of various embodiments. In some embodiments described herein, the second terminal 212 of the programming transistor TP and the second terminal 222 of the reading transistor TR are the same, that is, the programming transistor TP and the reading transistor TR share a common source / drain. In at least one embodiment, the programming transistor TP and the reading transistor TR are configured identically. For example, the programming transistor TP and the reading transistor TR have the same size and are manufactured by the same process.

[0034] The programming transistor TP includes a gate dielectric (eg, Figure 8The gate dielectric described above is configured to be broken down when a predetermined breakdown voltage sufficient to break down the gate dielectric is applied to the gate dielectric. When the gate dielectric of the programming transistor TP is broken down, the broken down gate dielectric is configured as a resistor and corresponds to the first data stored in the memory cell 200, such as a logic "0". The memory cell 200 that has not yet broken down stores a different second data, such as a logic "1". Example materials for the gate dielectric include, but are not limited to, silicon dioxide, high-k dielectrics, and the like. Examples of high-k dielectrics include, but are not limited to, zirconium dioxide, hafnium dioxide, zirconium silicate, hafnium silicate, and the like. In some embodiments, the memory cell 200 is an anti-fuse memory cell, and the memory device includes a memory cell 200 that is an anti-fuse memory. Anti-fuse memory is a one-time programmable (OTP) non-volatile memory (NVM). Other memory configurations of the applicable memory cell 200 are within the scope of various embodiments.

[0035] In some embodiments, the operation of memory cell 200 is controlled by a controller, such as controller 102 of memory device 100. Controller 102 is coupled to memory cell 200 via program word lines WLP, read word lines WLR, source lines SL, and bit lines BL.

[0036] When the memory cell 200 is selected in a programming operation, the controller 102 is configured to apply a higher voltage to the first terminal 211 of the programming transistor T via the source line SL, and to apply a lower voltage to the gate terminal 210 of the programming transistor T via the programming word line WLP. The controller 102 is configured to turn off the read transistor TR in the programming operation. The voltage difference between the higher voltage on the first terminal 211 and the lower voltage on the gate terminal 210 is equal to or higher than a predetermined breakdown voltage sufficient to break through the gate dielectric of the programming transistor T. As a result, the gate dielectric of the programming transistor TP is broken down, the programming current Iprog flows from the source line SL through the programming transistor TP to the programming word line WLP, and the memory cell 200 is programmed. In an example, the lower voltage applied to the programming word line WLP is a ground voltage, and the higher voltage applied to the source line SL is a programming voltage of about 5V. Other voltage schemes are within the scope of various embodiments.

[0037] When the memory cell 200 is selected in a read operation, the controller 102 is configured to apply a turn-on voltage to the gate terminal 220 of the read transistor via the read word line WLR to turn on the read transistor TR. The controller 102 is also configured to apply a read voltage to the first terminal 211 and the gate terminal 210 of the programming transistor T via the source line SL and the programming word line WLP, respectively, to detect the data stored in the memory cell 200 while the read transistor TR is turned on. For example, the controller 102 is configured to sense the read current Iread flowing from the programming transistor TP through the turned-on read transistor TR to the bit line BL, for example, by using the SA 118. The current value of the read current Iread when the memory cell 200 has been pre-programmed to store a logic "0" is different from the current value of the read current Iread when the memory cell 200 has not been pre-programmed and still stores a logic "1". By sensing the current value of the read current Iread, the controller 102 is configured to detect the data stored in the memory cell 200. In an example, the turn-on voltage is a core voltage of about 0.75V, and the read voltage is about 1.5V. Other voltage schemes are within the scope of various embodiments.

[0038] Compared to other methods where a high programming voltage is applied to the gate terminal of the programming transistor, according to some embodiments, the programming voltage is applied to the source / drain of the programming transistor TP via the source line SL. Furthermore, in other methods, the programming current and the read current flow in the same current path from the programming transistor to the bit line. In contrast, according to some embodiments, the programming current Iprog and the read current Iread are connected in the same manner as in the example Figure 2 In at least one embodiment, one or more of the differences described from other methods may enable one or more improvements described herein.

[0039] Figure 3A-3B is a schematic circuit diagram of a memory device 300 in various operations according to some embodiments.

[0040] exist Figure 3A and Figure 3B, the memory device 300 includes a plurality of memory cells Bit 0, Bit 1, ... Bit 7. Each memory cell Bit 0, Bit 1, ... Bit 7 has the configuration of the memory cell 200. For example, the memory cells Bit 0, Bit 1, ... Bit 7 include programming transistors TP0, TP1, ..., TP7 and reading transistors TR0, TR1, ..., TR7, respectively. The gate terminals of the programming transistors TP0, TP2, TP4, TP6 are coupled to the programming word line WLP0, and the gate terminals of the programming transistors TP1, TP3, TP5, TP7 are coupled to the programming word line WLP1. The gate terminals of the reading transistors TR0, TR2, TR4, TR6 are coupled to the reading word line WLR0, and the gate terminals of the reading transistors TR1, TR3, TR5, TR7 are coupled to the reading word line WLR1. The first terminals of the programming transistors TP0, TP1 are coupled to the source line SL0, the first terminals of the programming transistors TP2, TP3 are coupled to the source line SL1, and the first terminals of the programming transistors TP4, TP5 are coupled to the source line SL2. The first terminals of the programming transistors TP6 and TP7 are coupled to the source line SL3. The first terminals of the read transistors TR0 and TR1 are coupled to the bit line BL0, the first terminals of the programming transistors TR2 and TR3 are coupled to the bit line BL1, and the first terminals of the programming transistors TR4 and TR5 are coupled to the bit line BL2. In the memory device 100, the first terminals of the programming transistors TR6 and TR7 are coupled to the bit line BL3. The second terminal of each of the programming transistors TP0, TP1, ... TP7 is coupled to the second terminal of the corresponding one of the read transistors TR0, TR1, ..., TR7. In at least one embodiment, each memory cell bit 0, bit 1, ... bit 7 corresponds to a memory cell MC, each bit line BL0, BL1, BL2, BL3 corresponds to a bit line BL, each source line SL0, SL1, SL2, SL3 corresponds to a source line SL, each programming word line WLP0, WLP1 corresponds to a programming word line WLP, and each read word line WLR0, WLR1 corresponds to a read word line WLR. Figure 3A-3B is an example. Other configurations are within the scope of various embodiments.

[0041] exist Figure 3A In the programming operation, memory cell bit 0 is selected, while other memory cells bit 1, bit 2, ... bit 7 are not selected. A controller of the memory device 300 (such as the controller 102) is configured to apply a programming voltage Vprog to a source line SL0 coupled to the selected memory cell bit 0, and to apply a reference voltage to other source lines SL1, SL2, SL3. Figure 3A In an example configuration of , the reference voltage is the ground voltage VSS, and the programming voltage Vprog is approximately 5 V. Other voltage schemes are within the scope of various embodiments.

[0042] The controller is also configured to apply a ground voltage VSS to a programming word line WLP0 coupled to a selected memory cell bit 0, and to apply a first voltage Vio to other programming word lines WLP1. The first voltage Vio is higher than the ground voltage VSS and lower than the programming voltage Vprog. In an example, the first voltage Vio is an input / output (I / O) voltage of approximately 1.8V. Other voltage schemes are within the scope of various embodiments.

[0043] The controller is also configured to float or apply a ground voltage VSS to each read word line WLR0, WLR1. As a result, the read transistors TR0, TR1, ... TR7 are turned off. The controller is also configured to apply a ground voltage VSS to the bit lines BL0, BL1, BL2, BL3.

[0044] The voltage difference (eg, 5V) between the program voltage Vprog and the ground voltage VSS is equal to or higher than a predetermined breakdown voltage and is sufficient to break down the gate dielectric of the programming transistor TP0 in the selected memory cell bit 0. As a result, the selected memory cell bit 0 is programmed.

[0045] The voltage difference between the programming voltage Vprog and the first voltage Vio, e.g., 3.2V, is below a predetermined breakdown voltage to avoid accidentally breaking down the gate dielectric of the programming transistor TP1 (if not already broken down) in the unselected memory cell bit 1, which is coupled to the same source line SL0 as the selected memory cell bit 0.

[0046] The voltage difference (eg, 1.8V) between the first voltage Vio and the ground voltage VSS is lower than a predetermined breakdown voltage to avoid accidental breakdown of the gate dielectrics of the programming transistors TP3, TP5, TP7 in the unselected memory cells Bit3, Bit5, Bit7 if they have not already been broken down.

[0047] In other methods where a high programming voltage is applied to the gate terminal of the programming transistor in the selected memory cell through the programming word line, other unselected memory cells coupled to the same programming word line may suffer from gate-induced drain leakage (GIDL) effects due to unwanted additional leakage current. In addition, the high programming voltage on the programming word line may produce unwanted high voltage stress on the programming transistors in other unselected memory cells and cause reduced reliability of the programming transistors in other unselected memory cells. In at least one embodiment, additional leakage current and / or reduced reliability can be avoided by applying the programming voltage Vprog to the source / drain of the programming transistor TP0 of the selected memory cell bit 0 instead of the gate terminal. In bits 2, 4, and 6 of another unselected memory cell, they are coupled to the same programming word line WLP0 as bit 0 of the selected memory cell. As a result, in one or more embodiments, performance and / or device reliability is improved.

[0048] exist Figure 3B , memory cell bit 0 is selected in the read operation, while other memory cells bit 1, bit 2, ... bit 7 are not selected. The controller is configured to apply a read voltage Vread to the source line SL0 coupled to the selected memory cell bit 0 and the programming word line WLP0, and to apply a ground voltage VSS to other source lines SL1, SL2, SL3 and another programming word line WLP1. In one example, the read voltage Vread is about 1.5V. Other voltage schemes are within the scope of various embodiments.

[0049] The controller is also configured to apply a second voltage Vcore higher than the ground voltage VSS to the read word line WLR0 coupled to the selected memory cell bit 0, and to apply the ground voltage VSS to the other read word line WLR1. The second voltage is also referred to as a turn-on voltage. In one example, the second voltage Vcore is a core voltage of approximately 0.75V. Other voltage schemes are within the scope of various embodiments.

[0050] The controller is configured to apply the ground voltage VSS to the bit line BL0 coupled to the selected memory cell bit 0. The controller is also configured to float or apply the ground voltage VSS to the other respective bit lines BL1, BL2, BL3.

[0051] The controller is also configured to couple bit line BL0 of the selected memory cell bit 0 to a sense amplifier such as SA118. The on voltage Vcore on read word line WLR0 turns on read transistor TR0, which allows read current to flow from programming transistor TP0 to bit line BL0 to be detected by SA.

[0052] Figure 4is a schematic circuit diagram of a memory device 400 according to some embodiments.

[0053] The memory device 400 includes Figure 3A-3B Memory cells bit 0, bit 1, ... bit 7 are described, and the corresponding programming word lines WLP0, WLP1, reading word lines WLR0, WLR1, source lines SL0, SL1, SL2, SL3, and bit lines BL0, BL1, BL2, BL3. For simplicity, some memory cells are shown in FIG. Figure 4 The source lines and bit lines are omitted. The memory device 400 also includes a WL decoder 412, a SL decoder 414, a BL decoder 416, and a SA 418, which together correspond to the Figure 3A-3B In at least one embodiment, the WL decoder 412, the SL decoder 414, the BL decoder 416, and the SA 418 correspond to the controller described in Figure 1 The word line driver 112, source line driver 114, bit line driver 116 and SA 118 are depicted.

[0054] The WL decoder 412 is configured to receive and decode the address of the selected memory cell, and apply various voltages to one or more of the program word lines WLP0, WLP1, read word lines WLR0, WLR1, and source lines SL0, SL1, SL2, SL3 according to the decoded address and the operation to be performed at the selected memory cell (e.g., a read operation or a program operation). For example, Figure 4 A programming voltage Vprog and transistors CT0, CT1 are shown through which the programming voltage Vprog is selectively applied to the source line SL. For simplicity, other voltages and / or transistors for selectively applying such voltages are omitted.

[0055] The SL decoder 414 is configured to receive and decode the address of the selected memory cell, and control the supply of various voltages from the WL decoder 412 to one or more of the source lines SL0, SL1, SL2, SL3 according to the decoded address and the operation to be performed on the selected memory cell. For example, the SL decoder 414 is coupled to the control terminal of the switch S1, which is coupled between the source line SL0 and the transistor CT0 in the WL decoder 412. Similarly, the SL decoder 414 is coupled to the control terminal of the switch S2, which is coupled between the source line SL3 and another transistor in the WL decoder 412. For simplicity, other switches coupled to be controlled by the SL decoder 414 are omitted. In at least one embodiment, each of the switches S1, S2 is a transistor, and the SL decoder 414 is coupled to the gate terminal of the transistor. In an example programming operation of a selected memory cell bit 0, SL decoder 414 is configured to close switch S1, and a programming voltage Vprog is provided to source line SL0 through transistor CT0 and closed switch S1 to program memory cell bit 0, as described herein.

[0056] The BL decoder 416 is configured to receive and decode the address of the selected memory cell and couple one or more of the bit lines BL0, BL1, BL2, BL3 to the ground voltage VSS or SA 418, or float one or more of the bit lines BL0, BL1, BL2, BL3 according to the decoded address and the operation to be performed at the selected memory cell. For example, the BL decoder 416 is coupled to the control terminals of switches S3-S6. Switch S3 is coupled between the gates of transistors T1 and T2. Transistor T1 has a first source / drain coupled to the bit line BL0. Transistor T2 has a first source / drain coupled to SA 418 and a second source / drain coupled to ground. Switch S4 is coupled between the second source / drain of transistor T1 and the output pin OUT. Switch S5 is coupled between the gates of transistors T3 and T2. Transistor T3 has a first source / drain coupled to the bit line BL3. Switch S6 is coupled between the second source / drain of transistor T3 and the output pin OUT. For simplicity, other switches coupled to be controlled by the BL decoder 416 are omitted. In at least one embodiment, each of the switches S3, S4, S5, S6 is a transistor, and the BL decoder 416 is coupled to the gate terminal of the transistor. In an example read operation of memory cell bit 0, the BL decoder 416 is configured to close switches S3, S4 to couple the bit line BL0 to the SA 418 for detecting the data stored in the memory cell bit 0 by the SA 418. In at least one embodiment, one or more advantages described herein can be achieved in the memory device 400.

[0057] Figure 5A-Figure 5C5 is a schematic diagram at various layers in an IC layout diagram 500 of a memory device according to some embodiments. In at least one embodiment, the IC layout diagram 500 corresponds to the IC layout diagram of the memory device 300.

[0058] IC layout diagram 500 includes memory cells bit 0, bit 1, ..., bit 7 arranged adjacent to each other. Figure 5A-Figure 5C The schematic diagrams 500A-500C of the layout above show the boundaries of the memory cell bit 0. For simplicity, Figure 5A-Figure 5C Boundaries of other memory cells bit 1, bit 2, ... bit 7 are omitted. In at least one embodiment, IC layout 500 and / or layouts of one or more memory cells bit 0, bit 1, ... bit 7 are stored in a standard cell library on a non-transitory computer-readable medium.

[0059] Figure 5A A schematic diagram 500A at a device level of an IC layout diagram 500 is included.

[0060] IC layout diagram 500 includes active areas OD1, OD2, OD3, OD4, gate areas PO1, PO2...PO6, and dummy gate areas DPO1, DPO2. Active areas OD1, OD2, OD3, OD4 extend along a first direction (i.e., the X direction). The active area is sometimes referred to as an oxide definition (OD) area and is schematically shown in the accompanying drawings with the label "OD". The X direction is sometimes referred to as the OD direction. The active area includes P-type dopants and / or N-type dopants to form one or more circuit elements or devices. Examples of circuit elements include, but are not limited to, transistors and diodes. An active area configured to form one or more PMOS devices therein is referred to as a "PMOS active area", and an active area configured to form one or more NMOS devices therein is referred to as an "NMOS active area". For example, active areas OD1, OD2, OD3, OD4 are all NMOS active areas configured to form NMOS transistors in memory cell bits 0, 1,..., 7.

[0061] The gate regions PO1, PO2, ... PO6 extend across the active regions OD1, OD2, OD3, OD4 along a second direction (ie, the Y direction) transverse to the X direction. Figure 5A-Figure 5C In the example configuration of , the Y direction is perpendicular to the X direction. Each of the gate regions PO1, PO2, ..., PO6 includes a conductive material such as polysilicon and is schematically shown in the drawings with the reference numeral "PO". The Y direction is sometimes referred to as the Poly direction. Other conductive materials (such as metals) for the gate regions are within the scope of various embodiments.

[0062] The programming transistor TP0 of the memory cell bit 0 (in Figure 5AThe programming transistor TP0 is configured by the gate region PO2 and the corresponding source / drain regions 511, 512 in the active region OD1. In the X direction, the source / drain regions 511, 512 of the programming transistor TP0 are adjacent to the gate region PO2 and are located on the opposite side of the gate region PO2. Figure 5A The programming transistor TP0 and the reading transistor TR0 of the memory cell bit 0 share a common source / drain region 512.

[0063] The programming transistors and reading transistors in the other memory cells bit 1, bit 2, ..., bit 7 are configured similarly to the programming transistor TP0 and reading transistor TR0 in the memory cell bit 0. Figure 5A The programming transistor TP1 is configured by the gate region PO5 and the corresponding source / drain regions 514, 515 in the active region OD1. In the X direction, the source / drain regions 514, 515 of the programming transistor TP1 are adjacent to the gate region PO5 and are located on the opposite side of the gate region PO5. The read transistor TR1 ( Figure 5A The programming transistor TP1 and the reading transistor TR1 of the memory cell bit 1 share a common source / drain region 514, and the reading transistor TR0 of the memory cell bit 0 and the reading transistor TR1 of the memory cell bit 1 share a common source / drain region 513.

[0064] exist Figure 5A In the example configuration in, gate regions PO1, PO6 are dummy gate regions. For example, gate regions PO1, PO6 correspond to conductive gates in a memory device manufactured based on IC layout diagram 500; however, such conductive gates do not configure transistors and / or are not electrically coupled to other circuit elements. In contrast, dummy gate regions DPO1, DPO2 correspond to non-conductive gates in a memory device manufactured based on IC layout diagram 500. In at least one embodiment, gate regions PO1, PO6 and / or dummy gate regions DPO1,...DPO2 are included in IC layout diagram 500 to meet one or more design and / or manufacturing requirements. In at least one embodiment, one or more of gate regions PO1, PO6 and / or dummy gate regions DPO1, DPO2 are omitted. In Figure 5AIn the exemplary configuration, the gate regions PO1, PO2, ...PO6 and the dummy gate regions DPO1, DPO2 are arranged at a constant pitch ( Figure 5A The gate length d1 is a dimension of the gate region or the dummy gate region in the X direction. In at least one embodiment, the gate length d1 is about 9 nm.

[0065] exist Figure 5A In the example configuration in FIG. 1 , the active regions OD1 , OD2 , OD3 , OD4 do not extend beyond the gate regions PO1 , PO6 in the X direction. Figure 5A When the memory cell bit 0 in OD1 is adjacent to the left side, the active area in another memory cell is discontinuous with the active area OD1, resulting in a discontinuous active area configuration. Other active area configurations are within the scope of various embodiments.

[0066] In some embodiments, the IC layout diagram 500 further includes cutting polysilicon regions ( Figure 5A (not shown in the figure), the cut polysilicon region extends in the X direction across the gate regions PO1, PO6 and corresponds to a region in which the gate regions PO1, PO6 are not formed.

[0067] In some embodiments, the IC layout diagram 500 further includes source / drain contact regions ( Figure 5A The source / drain contact regions are sometimes referred to as "MD regions". The MD regions are arranged alternately with the gate regions PO1, PO2...PO6 in the X direction.

[0068] IC layout 500 also includes conductive vias above and in electrical contact with the corresponding gate region or MD region. The vias above and in electrical contact with the MD region are sometimes referred to as to-device vias and are schematically illustrated in the figures with the reference numeral “VD”. The vias above and in electrical contact with the gate region are sometimes referred to as to-gate vias and are schematically illustrated in the figures with the reference numeral “VG”. Figure 5A In the example configuration of , IC layout diagram 500 includes vias VD1 , VD2 , . . . , VD12 and vias VG1 , VG2 , . . . , VG10 .

[0069] IC layout diagram 500 also includes multiple metal layers and via layers arranged sequentially and alternately above the VD and VG vias. The lowest metal layer above the VD and VG vias and in electrical contact therewith is the M0 layer, i.e., the zero metal (M0) layer, the next metal layer immediately above the M0 layer is the M1 layer, the next metal layer immediately above the M1 layer is the M2 layer, etc. The via layer VIAn is arranged between the Mn layer and the Mn+1 layer and electrically couples them, where n is an integer from zero upward. For example, the zero via (VIA0) layer is the lowest via layer arranged between the M0 layer and the M1 layer and electrically couples them. Other via layers are VIA1, VIA2, etc.

[0070] exist Figure 5A , various patterns in the M0 layer are schematically labeled "M0A" and "M0B". In at least one embodiment, the M0A pattern corresponds to one mask, and the M0B pattern corresponds to another mask. In at least one embodiment, the patterns in the M0 layer are separated into several masks to meet one or more design and / or manufacturing requirements. In some embodiments, all patterns in the M0 layer belong to the same mask. The M0A pattern includes a word line pattern, and the M0B pattern includes a source line and a bit line pattern.

[0071] Specifically, the M0A pattern includes programming word line patterns WLP0_1, WLP0_2, WLP0_3 each corresponding to the programming word line WLP0, and programming word line patterns WLP1_1, WLP1_2 each corresponding to the programming word line WLP1. The programming word line patterns WLP0_1, WLP0_2, WLP0_3 are above the gate area PO2 and coupled to the gate area PO2 through corresponding vias VG1, VG5, VG9. The programming word line patterns WLP1_1, WLP1_2 are above the gate area PO5 and coupled to the gate area PO5 through corresponding vias VG4, VG8. The M0A pattern also includes read word line patterns WLR0_1, WLR0_2 each corresponding to the read word line WLR0, and read word line patterns WLR1_1, WLR1_2, WLR1_3 each corresponding to the read word line WLR1. The read word line patterns WLR0_1, WLR0_2 are above the gate region PO3 and coupled to the gate region PO3 through corresponding vias VG3, VG7. The read word line patterns WLR1_1, WLR1_2, WLR1_3 are above the gate region PO4 and coupled to the gate region PO4 through corresponding vias VG2, VG6, VG10.

[0072] The M0B pattern includes source line patterns SL0_1, SL0_2 corresponding to the source line SL0, source line patterns SL1_1, SL1_2 corresponding to the source line SL1, source line patterns SL2_1, SL2_2 corresponding to the source line SL2, and source line patterns SL3_1, SL3_2 corresponding to the source line SL3. The M0B pattern includes bit line patterns BL0_1, BL1_1, BL2_1, BL3_1 corresponding to the bit lines BL0, BL1, BL2, BL3. The source line patterns SL0_1, SL0_2 and the bit line pattern BL0_1 are above the corresponding source / drain regions in the active region OD1 and are coupled to the corresponding source / drain regions in the active region OD1 through the corresponding vias VD1, VD3, VD2. The source line patterns SL1_1, SL_2 and the bit line pattern BL1_1 are above the corresponding source / drain regions in the active region OD2 and are coupled to the corresponding source / drain regions in the active region OD2 through the corresponding vias VD4, VD6, VD5. The source line patterns SL2_1, SL2_2 and the bit line pattern BL2_1 are above the corresponding source / drain regions in the active region OD2 and are coupled to the corresponding source / drain regions in the active region OD2 through the corresponding vias VD7, VD9, VD8. The source line patterns SL3_1, SL3_2 and the bit line pattern BL3_1 are above the corresponding source / drain regions in the active region OD1 and are coupled to the corresponding source / drain regions in the active region OD1 through the corresponding vias VD10, VD12, VD11.

[0073] The width w1 of each of the programming word line patterns WLP0_1, WLP0_2, WLP0_3, WLP1_1, WLP1_2 in the Y direction is greater than the width w2 of each of the reading word line patterns WLR0_1, WLR0_2, WLR1_1, WLR1_2, WLR1_3 in the Y direction. The reason is that as the width w1 increases, the resistance of the programming word line pattern decreases, which in turn increases the read current and improves the read operation. In at least one embodiment, the width w1 of the programming word line pattern is the same as the width w2 of the reading word line pattern.

[0074] The width w3 of each of the source line patterns SL0_1, SL0_2, SL1_1, SL1_2, SL2_1, SL2_2, SL3_1, and SL3_2 in the Y direction is greater than the width w1 of each of the programming word line patterns WLP0_1, WLP0_2, WLP0_3, WLP1_1, and WLP1_2 in the Y direction. The reason is that the programming voltage (e.g., 5V) applied to the source line pattern is greater than the voltage (e.g., 1.5V or 1.8V) applied to the programming word line pattern. As the width w3 increases, the resistance of the source line pattern decreases, thereby reducing the voltage drop on the source line pattern to ensure that sufficient programming voltage is applied to the gate dielectric to be broken down. As a result, a reliable programming operation can be achieved. In at least one embodiment, the width w3 of the source line pattern is the same as the width w1 of the programming word line pattern.

[0075] The source line patterns SL0_1, SL0_2, SL1_1, SL1_2, SL2_1, SL2_2, SL3_1, SL3_2, the programming word line patterns WLP0_1, WLP0_2, WLP0_3, WLP1_1, WLP1_2, and the read word line patterns WLR0_1, WLR0_2, WLR1_1, WLR1_2, WLR1_3 are elongated in the X direction, i.e., the size of each of the source line patterns, the programming word line patterns, and the read word line patterns in the X direction is greater than the size in the Y direction. The bit line patterns BL0_1, BL1_1, BL2_1, BL3_1 are elongated in the Y direction, i.e., the size of each of the bit line patterns in the Y direction is greater than the size in the X direction. Other configurations are within the scope of various embodiments.

[0076] In the memory cell, the source line pattern and the bit line pattern are arranged between the programming word line pattern and the reading word line pattern in the Y direction. For example, in the memory cell bit 0, the source line pattern SL0_1 and the bit line pattern BL0_1 are arranged between the corresponding programming word line pattern WLP0_1 and the reading word line pattern WLR0_1 in the Y direction, as shown in FIG. Figure 5A As shown, the programming word line pattern WLP0_1 and the reading word line pattern WLR0_1 are arranged on the boundary of the memory cell bit 0. Other configurations are within the scope of various embodiments. For example, in at least one embodiment, the source line pattern SL0_1 and the bit line pattern BL0_1 are arranged on the boundary of the memory cell bit 0, and the programming word line pattern WLP0_1 and the reading word line pattern WLR0_1 are arranged between the source line pattern SL0_1 and the bit line pattern BL0_1 in the Y direction.

[0077] In the X direction, the programming word line pattern and the read word line pattern of the memory cell overlap with the read word line pattern and the programming word line pattern of the adjacent memory cell, respectively. For example, in the X direction, the programming word line pattern WLP0_1 of the memory cell bit 0 overlaps with the read word line pattern WLR1_1 of the memory cell bit 1 adjacent to the memory cell bit 0. In at least one embodiment, the center line of the programming word line pattern WLP0_1 coincides with the center line of the read word line pattern WLR1_1. Similarly, in the X direction, the read word line pattern WLR0_1 of the memory cell bit 0 overlaps with the programming word line pattern WLP1_1 of the adjacent memory cell bit 1. In at least one embodiment, the center line WLR0_1 of the read word line pattern coincides with the center line of the programming word line pattern WLP1_1.

[0078] Over the same active area, the bit line pattern is arranged between the source line patterns in the X direction. For example, on the active area OD1, the bit line pattern BL0_1 is arranged between the source line patterns SL0_1, SL0_2 corresponding to the same source line SL0 in the X direction. Other configurations are within the scope of various embodiments. For example, in an alternative configuration according to some embodiments, Figure 5A The pattern BL0_1 in is configured as a source line pattern, and Figure 5A The patterns SL0_1, SL0_2 in are configured as bit line patterns corresponding to the same bit line BL0. In such an alternative configuration, a source line pattern is arranged between the bit line patterns in the X direction over the active area OD1. Furthermore, in the alternative configuration, the patterns WLP0_1 and WLP1_1 are configured as read word line patterns, and the patterns WLR0_1 and WLR1_1 are configured as program word line patterns.

[0079] In some embodiments, at least Figure 5A At the device level shown, bit 0, bit 1, ..., bit 7 of the memory cell have symmetrical configurations with each other. For example, the patterns and / or regions in the various layers in memory cell bit 2 are symmetrical in the X direction with the corresponding patterns and / or regions in the corresponding layers in memory cell bit 0. Bit 2 can be obtained by flipping memory cell bit 0 in the X direction. Memory cell bit 3 can be obtained by flipping memory cell bit 0 in the Y direction. Memory cell bit 1 can be obtained by flipping memory cell bit 3 in the X direction. Memory cell bit 4 is the same as memory cell bit 0, memory cell bit 5 is the same as memory cell bit 1, memory cell bit 6 is the same as memory cell bit 2, and memory cell bit 7 is the same as memory cell bit 3.

[0080] Figure 5B FIG. 5 is a schematic diagram 500B at the M2 layer of the IC layout diagram 500 .

[0081] Schematic diagram 500B also shows active regions OD1, OD2, OD3, OD4, gate regions PO1, PO2, ...PO6, and dummy gate regions DPO1, DPO2. Figure 5B The gate region and the dummy gate region are schematically shown by corresponding center lines (also referred to as "gate tracks"). The M2 layer includes various patterns coupled to corresponding patterns in the M0 layer through corresponding vias in the VIA0 layer, corresponding patterns in the M1 layer, and corresponding vias in the VIA1 layer. For simplicity, the VIA0 layer, the M1 layer, and the VIA1 layer are omitted.

[0082] exist Figure 5B , various patterns in the M2 layer are schematically labeled as "M2A" and "M2B". In at least one embodiment, the M2A pattern corresponds to one mask and the M2B pattern corresponds to another mask. In at least one embodiment, the patterns in the M2 layer are divided into several masks to meet one or more design and / or manufacturing requirements. In some embodiments, all patterns in the M2 layer belong to the same mask. The M2A pattern includes bit line and word line patterns, and the M2B pattern includes source line and other word line patterns.

[0083] Specifically, the M2A pattern includes bit lines BL0, BL1, BL2, BL3, which extend continuously across multiple memory cells in the X direction. In at least one embodiment, the bit lines BL0, BL1, BL2, BL3 in the M2 layer extend continuously across the entire memory array in the IC layout diagram 500 in the X direction. The M2A pattern also includes programming word line patterns WLP0_4, WLP0_5, WLP0_6, WLP0_6 each corresponding to the programming word line WLP0, and read word line patterns WLR1_4, WLR1_5, WLR1_6 each corresponding to the read word line WLR1.

[0084] The M2B pattern includes source lines SL0, SL1, SL2, SL3, which extend continuously across multiple memory cells in the X direction. In at least one embodiment, the source lines SL0, SL1, SL2, SL3 in the M2 layer extend continuously across the entire memory array in the IC layout diagram 500 along the X direction. The M2B pattern also includes programming word line patterns WLP1_3, WLP1_4, each corresponding to the programming word line WLP1, and read word line patterns WLR0_3, WLR0_4, each corresponding to the read word line WLR0.

[0085] Figure 5C FIG. 5 is a schematic diagram 500C at the M3 layer of the IC layout diagram 500 .

[0086] Schematic 500C also shows active regions OD1, OD2, OD3, OD4 and gate regions PO1, PO2...PO6 and dummy gate regions DPO1, DPO2 as gate traces. The M3 layer includes various patterns coupled to corresponding patterns in the M2 layer through corresponding vias in the VIA2 layer, which are omitted for simplicity.

[0087] The M3 layer includes programming word lines WLP0, WLP1 and reading word lines WLR0, WLR1, which extend continuously across multiple memory cells in the Y direction. In at least one embodiment, the programming word lines WLP0, WLP1 and reading word lines WLR0, WLR1 in the M3 layer extend continuously across the entire memory array in the IC layout diagram 500 in the Y direction. The M3 layer also includes various patterns 531-534 for coupling other circuit elements.

[0088] exist Figure 5B-Figure 5C In an example configuration, the bit lines and source lines are arranged in the M2 layer as conductive tracks extending in the X direction, while the programming word lines and read word lines are arranged in different M3 layers as conductive tracks extending in different Y directions. Other configurations are within the scope of various embodiments. For example, in some embodiments, the bit lines and source lines are arranged in the M3 layer, and the programming word lines and read word lines are arranged in the M2 layer. In another example, the bit lines and source lines are arranged in more than one metal layer, and / or in metal layers other than the M2 layer and the M3 layer. In another example, the programming word lines and read word lines are arranged in more than one metal layer, and / or in metal layers other than the M2 layer and the M3 layer. In at least one embodiment, one or more advantages described herein can be realized in a memory device corresponding to the IC layout diagram 500.

[0089] Fig. 6A 6 is a schematic diagram of an IC layout diagram 600A of a memory device according to some embodiments. In at least one embodiment, the IC layout diagram 600A corresponds to the IC layout diagram of the memory device 300 . Fig. 6A At the device level of IC layout 600A, the schematic diagram in FIG. Figure 5A The corresponding components of IC layout diagram 600A and IC layout diagram 500 are shown in FIG. Fig. 6A Zhong You and Figure 5A The same reference numerals are used to represent the differences between the IC layout diagram 500 and the IC layout diagram 600A.

[0090] The IC layout diagram 600A omits the gate regions PO1 and PO6 and the dummy gate regions DPO1 and DPO2 of the IC layout diagram 500 .

[0091] Active areas OD1, OD2, OD3, OD4 extend across multiple memory cells in the X direction. For example, active area OD1 extends continuously across memory cells Bit 0 and Bit 1 in the X direction, resulting in a continuous active area configuration. Other active area configurations are within the scope of various embodiments.

[0092] MD area MD1-MD5 in Fig. 6A , and are arranged alternately with gate regions PO2-PO5 in the X direction. Region MD1 overlaps and is configured to couple source line patterns SL0_1, SL1_1, SL2_1, SL3_1 to corresponding source / drain regions of corresponding programming transistors in bits 0, 2, 4, and 6 in corresponding memory cells in corresponding active regions OD1, OD2, OD3, and OD4. Region MD3 overlaps and is configured to couple bit line patterns BL0_1, BL1_1, BL2_1, BL3_1 to corresponding source / drain regions in corresponding active regions OD1, OD2, OD3, and OD4. Region MD5 overlaps and is configured to couple source line patterns SL0_2, SL1_2, SL2_2, SL3_2 to corresponding source / drain regions of corresponding programming transistors in bits 1, 3, 5, and 7 in corresponding memory cells in corresponding active regions OD1, OD2, OD3, and OD4. In some embodiments, the IC layout diagram 600A further includes a cutting MD region ( Fig. 6A ), to electrically isolate portions of each region MD1, MD3, MD5 in the corresponding memory cell from each other. The regions MD1, MD3, MD5 are arranged along the boundaries of the memory cell bits 0, 1, ... 7. The regions MD2, MD4 are not configured to electrically couple the underlying source / drain regions to other circuit elements.

[0093] In some embodiments, the source line pattern, bit line pattern, programming word line pattern, and read word line pattern of IC layout diagram 600A are coupled to corresponding source lines, bit lines, programming word lines, and read word lines in other metal layers, such as Figure 5B-Figure 5C as described.

[0094] Figure 6B 6 is a schematic diagram of an IC layout diagram 600B of a memory device according to some embodiments. In at least one embodiment, the IC layout diagram 600B corresponds to the IC layout diagram of the memory device 300 . Figure 6B At the device level of the IC layout diagram 600B, the schematic diagram in FIG. Figure 5A The corresponding components of IC layout diagram 600B and IC layout diagram 600A are shown in FIG. Figure 6B Zhong You and Fig. 6AThe same reference numerals are used to represent the differences between the IC layout diagram 600B and the IC layout diagram 600A.

[0095] exist Figure 6B In the IC layout diagram 600B, the programming word line patterns WLP0_1, WLP0_2, WLP1_1, WLP1_2 and the reading word line patterns WLR0_1, WLR0_2, WLR1_1, WLR1_2 are arranged above the corresponding active regions OD1, OD2, OD3, OD4. Fig. 6A The IC layout diagram 600A is different in Fig. 6A , source line patterns SL0_1, SL0_2, SL1_1, SL1_2, SL2_1, SL2_2, SL3_1, SL3_2 and bit line patterns BL0_1, BL1_1, BL2_1, BL3_1 are arranged over corresponding active regions OD1, OD2, OD3, OD4.

[0096] In at least one embodiment, the gate length of each gate region PO2-PO5 in IC layout 600A or 600B is about 55nm. Although the gate length in the example of IC layout 600A or 600B is greater than the gate length in the example of IC layout 500, various components such as pseudo gate regions are omitted from IC layout 600A or 600B, resulting in a chip area reduction of about 20% in some embodiments. In one or more embodiments, other effects of IC layout 600A or 600B include reducing resistance to programming current and / or read current. In at least one embodiment, one or more advantages described herein can be realized in a memory device corresponding to IC layout 600A or 600B.

[0097] return Fig. 6A , IC layout diagram 600A includes configuration A and configuration B for memory cells. For example, memory cells bit 0, bit 21, bit 4, bit 5 have configuration A, while memory cells bit 2, bit 3, bit 6, bit 7 have configuration B. The patterns and / or regions in the various layers in configuration B are symmetric across the X direction with the corresponding patterns and / or regions in the corresponding layers in configuration A. In other words, configuration B can be obtained by flipping configuration A in the X direction.

[0098] In IC layout diagram 600A, memory cells bit 0, bit 2, bit 4, bit 6 adjacent to each other in the Y direction have an alternating configuration "ABAB". Similarly, memory cells bit 1, bit 3, bit 5, bit 7 adjacent to each other in the Y direction also have an alternating configuration "ABAB". In some embodiments, assuming that memory cells adjacent to each other in the Y direction have an alternating configuration, for example, "ABAB" as described herein, memory cells adjacent to each other in the X direction have various possible patterns of configuration A and / or B, for example, as described with respect to Figure 7A-7C as described.

[0099] Figure 7A-7C 700A- 700C are various layouts of memory cells in a memory device according to some embodiments.

[0100] In each layout 700A-700C, various memory cells having configuration A and configuration B are arranged adjacent to each other in a repeating pattern. Layouts 700A-700C include a common arrangement in the Y direction, where adjacent memory cells have alternating configurations "ABAB". However, in the X direction, layouts 700A-700C include different arrangements, e.g. Fig. 7A In the layout 700A, "AAAA" and "BBBB" are Figure 7B "ABAB" and "BABA" in layout 700B, Figure 7C 700A-700C are examples. Other layouts of memory cells are within the scope of various embodiments. In at least one embodiment, in a memory device corresponding to each of the layouts 700A-700C, one or more advantages described herein can be achieved.

[0101] Figure 8 is a schematic cross-sectional view of an IC device 800 according to some embodiments. In at least one embodiment, the IC device 800 corresponds to one or more memory devices and / or IC layouts described herein.

[0102] The IC device 800 includes a substrate 810 and a programming transistor 820 and a reading transistor 830 on the substrate 810. In at least one embodiment, the programming transistor 820 corresponds to Figure 2 , Figure 5A , Fig. 6A , Figure 6B The one or more programming transistors described above, the read transistor 830 corresponds to the Figure 2 , Figure 5A , Fig. 6A , Figure 6B One or more corresponding read transistors are described.

[0103] In some embodiments, substrate 810 is a semiconductor substrate. N-type and P-type dopants are added to the substrate to form N-wells 811, 812, 813 and a P-well (not shown) respectively. In some embodiments, an isolation structure is formed between adjacent P-wells and N-wells. For simplicity, Figure 8 Some components are omitted, such as the P-well and isolation structures.

[0104] Each of the programming transistor 820 and the reading transistor 830 includes a gate region and a source / drain region. N-wells 811, 812 define the source / drain region of the programming transistor 820. N-wells 812, 813 define the source / drain region of the reading transistor 830. The source / drain region 812 is a common source / drain region of the P-type transistor 820 and the reading transistor 830. The gate region of the programming transistor 820 includes a stack of gate dielectric layers 823, 824 and a gate electrode 825. In a programming operation, the gate dielectric layers 823, 824 are configured to be broken down by a predetermined breakdown voltage, which is applied to the gate dielectric layers 823, 824 from the source line coupled to the source / drain region 811 to the programming word line coupled to the gate electrode 825. The gate region of the reading transistor 830 includes a stack of gate dielectric layers 833, 834 and a gate electrode 835. In at least one embodiment, each of the programming transistor 820 and the reading transistor 830 includes a gate dielectric layer instead of multiple gate dielectrics. Example materials for the one or more gate dielectric layers include HfO2, ZrO2, etc. Example materials for the gate electrodes 825, 835 include polysilicon, metal, etc.

[0105] IC device 800 also includes a contact structure. The contact structure includes MD regions 841, 842, 843 corresponding to being above and in electrical contact with source / drain regions 811, 812, 813. MD regions 841, 843 are configured to electrically couple the underlying source / drain regions 811, 813 to other circuits. MD region 842 is not configured to electrically couple the underlying source / drain region 812 to other circuit elements, for example, as described with respect to Fig. 6A Described by areas MD2 and MD4.

[0106] The contact structure also includes various vias. For example, VG vias 852, 853 are respectively above and electrically contact the gate electrodes 825, 835, and are configured to couple the gate electrodes 825, 835 to corresponding programming word lines and read word lines, as described herein. VD vias 861, 864 are respectively above and electrically contact the MD regions 841, 843. VD via 861 is configured to couple the source / drain region 811 of the programming transistor 820 to the source line, as described herein. VD via 864 is configured to couple the source / drain region 813 of the read transistor 830 to the bit line, as described herein.

[0107] IC device 800 also includes an interconnect structure 870. Interconnect structure 870 includes a plurality of metal layers M0, M1, etc., and a plurality of via layers VIA0, VIA1, etc. alternately arranged in the first layer. Interconnect structure 870 also includes various interlayer dielectric (ILD) layers (not numbered) in which metal layers and via layers are embedded. The metal layers and via layers of interconnect structure 870 are configured to electrically couple various elements or circuits of IC device 800 to each other and to external circuits. The M0 layer, M1 layer, and VIA0 layer of interconnect structure 870 are arranged in a plurality of layers. Figure 8 For simplicity, other metal layers and via layers are omitted.

[0108] exist Figure 8 In an example configuration of, the M0 layer includes M0 patterns 871-874 above and electrically contacting vias 861, 852, 853, 864, respectively. The M0 patterns 871-874 correspond to source line patterns, programming word line patterns, reading word line patterns, and bit line patterns, as described herein. The M0 patterns 871-874 are electrically coupled to corresponding M1 patterns 891-894 in the M1 layer through corresponding vias 881-884 in the VIA0 layer. Additional via layers and / or metal layers of the interconnect structure 870 electrically couple the M1 patterns 891-894 to corresponding source lines, programming word lines, reading word lines, and bit lines, as described herein. In at least one embodiment, one or more advantages described herein can be realized in the IC device 800.

[0109] Fig. 9 is a flow chart of a method 900 according to some embodiments. In at least one embodiment, the method 900 is used for one or more of: generating a layout diagram for a memory cell, or building a standard cell library including one or more memory cells.

[0110] In some embodiments, one or more operations of method 900 are performed as part of a method of forming one or more memory devices and / or IC devices described herein. In some embodiments, one or more operations of method 900 are performed as part of an automatic placement and routing (APR) method. In some embodiments, one or more operations of method 900 are performed by an APR system, e.g., with reference to Fig.12 In some embodiments, as described herein, Fig.10 The method 1000 described in part performs one or more operations of the method 900 to generate a layout diagram of an IC device. Fig.13 One or more operations of method 900 may be performed as part of a design process performed in a design studio as described herein. In some embodiments, one or more operations of method 900 are performed by a processor. For example, Fig.12 The processor of the EDA system described, for example Fig.12 In some embodiments, one or more operations of method 900 are performed by a processor (such as Fig.12 In some embodiments, one or more operations in the method 900 described herein are omitted.

[0111] At operation 905, an active region and a pair of gate regions are arranged within the boundaries of the memory cell to configure a programming transistor and a reading transistor that share a common source / drain region. Figure 5A and Fig. 6A As described, the active region OD1 and a pair of gate regions PO2, PO3 are arranged within the boundary of the memory cell bit 0 to configure the programming transistor and the reading transistor to share a common source / drain region 512, as described with respect to Figure 5A In at least one embodiment, the programming transistor and the reading transistor correspond to Figure 2 The transistors TP and TR described, and / or corresponding to Figure 3A-3B Transistors TP0 and TR0 are described.

[0112] At operation 915, several patterns are arranged in the metal layer. The patterns include a programming word line pattern over and coupled to the gate region of the programming transistor, a read word line pattern over and coupled to the gate region of the read transistor, a source line pattern coupled to another source / drain region of the programming transistor, and a bit line pattern connected to another source / drain region of the read transistor. For example, as described with respect to Figure 5A and Fig. 6AAs described, a programming word line pattern WLP0_1, a reading word line pattern WLR0_1, a source line pattern SL0_1, and a bit line pattern BL0_1 are arranged in the M0 layer. The programming word line pattern WLP0_1 is above the gate area PO2 of the programming transistor and is coupled to the gate area PO2. The reading word line pattern WLR0_1 is above the gate area PO3 of the reading transistor and is coupled to the gate area PO3. The source line pattern SL0_1 is coupled to another source / drain area 511 of the programming transistor. The bit line pattern BL0_1 is coupled to another source / drain area 513 of the reading transistor. As a result, a layout diagram of the memory cell is generated.

[0113] At operation 925, the generated layout diagram of the memory cell is stored in a standard cell library on a non-transitory computer readable medium. In some embodiments, various memory cells with different configurations are generated and stored in the standard cell library. Figure 5A A symmetrical layout diagram of one or more memory cells bit 0, bit 1, bit 2, bit 3 described is generated and stored in a standard cell library. In another example, as described with respect to Fig. 6A As described, configuration A and configuration B for various memory cells are generated and stored in a standard cell library.

[0114] At operation 935, based on the generated layout diagram, for example, Fig.13 As described, at least one of the components in the layers of the semiconductor mask or IC device is manufactured. In at least one embodiment, operation 935 is omitted.

[0115] In at least one embodiment, all operations of method 900 are performed automatically, such as by a processor as described herein, without user input or intervention.

[0116] Fig.10 is a flow chart of a method 1000 according to some embodiments. In at least one embodiment, the method 1000 is used to generate an IC layout of an IC device based on cells received from a standard cell library.

[0117] In some embodiments, one or more operations of method 1000 are performed to form part of one or more memory devices and / or IC devices described herein. In some embodiments, one or more operations of method 1000 are performed as part of an APR method. In some embodiments, one or more operations of method 1000 are performed by an APR system, e.g., with reference to Fig.12 In some embodiments, one or more operations of method 1000 are performed as described in connection with Fig.13In some embodiments, one or more operations of method 1000 are performed by a processor, such as a processor. Fig.12 Describe the processor of the EDA system.

[0118] At operation 1055, two or more memory cells having a symmetrical layout are placed adjacent to each other. In one example, a reference is read from a standard cell library. Figure 5A The memory cell bits 0, 1, 2, and 3 described in the embodiment of the present invention are arranged in an adjacent and repeating pattern along the X direction and the Y direction to obtain an IC layout diagram of a memory cell array for a memory device. In another example, configurations A and B for various memory cells are read from a standard cell library, such as Fig. 6A As described, and placed in an adjacent and repeating pattern along the X-direction and the Y-direction to obtain an IC layout diagram for a memory cell array of a memory device. Figure 7A-7C Examples of various repeating patterns for arranging memory cells are described.

[0119] At operation 1065, the generated IC layout diagram is stored on a non-transitory computer readable medium. For example, the IC layout diagrams 500, 600A, 600B are stored on a non-transitory computer readable medium.

[0120] At operation 1075, for example, referring to Fig.13 At least one of the components in the semiconductor mask or IC layer is manufactured based on the generated IC layout diagram. In at least one embodiment, operation 1075 is omitted. In at least one embodiment, all operations of method 1000 are automatically performed by a processor as described herein, for example, without user input or intervention.

[0121] In some embodiments, one or more of the units, IC devices, and methods described are applicable to various types of transistor or device technologies, including but not limited to planar transistor technology, FINFET technology, nanosheet FET technology, nanowire FET, etc.

[0122] Fig.11 is a flow chart of method 1100 according to some embodiments. In at least one embodiment, method 1100 is a method of operating a memory cell having a programming transistor.

[0123] Method 1100 includes a programming operation 1110 , which includes operations 1115 and 1117 .

[0124] At operation 1115, a higher voltage is applied to the source / drain of the programming transistor of the memory cell. In one example, the higher programming voltage Vprog is applied to the first terminal 211 of the programming transistor TP via the source line SL, which is the source / drain as described above. Figure 2 The programming voltage Vprog is applied to the source / drain of the programming transistor TP0 via the source line SL0, as described with respect to Figure 3A as described.

[0125] At operation 1117, a lower voltage is applied to the gate of the programming transistor. The voltage difference between the higher voltage and the lower voltage is equal to or higher than a predetermined breakdown voltage to break down the gate dielectric of the programming transistor. In an example, a reference voltage lower than the programming voltage Vprog is applied to the gate terminal 210 of the programming transistor TP via the programming word line WLP, as described with respect to Figure 2 In another example, a reference voltage is applied to the gate terminal of the programming transistor TP0 via the programming word line WLP0, as described with respect to Figure 3A As described. In at least one embodiment, the reference voltage is a ground voltage. Assuming a reference voltage other than ground voltage is within the scope of various embodiments, provided that the voltage difference between the higher programming voltage Vprog and the lower reference voltage is equal to or higher than a predetermined breakdown voltage sufficient to break down the gate dielectric of the programming transistors TP, TP0. The voltage difference causes the gate dielectric to break down and causes the programming current Iprog to flow from the source line SL through the programming transistor TP to the programming word line WLP, as described with respect to Figure 2 In some embodiments, the memory cell further includes a read transistor that is turned off during a programming operation, as described with respect to Figure 2 and Figure 3A as described.

[0126] Method 1100 also includes a read operation 1120 , which includes operations 1125 and 1127 .

[0127] At operation 1125, a turn-on voltage is applied to the gate of the read transistor of the memory cell. Figure 2 and Figure 3B As described, a turn-on voltage such as a core voltage Vcore is applied to the gate terminal of the read transistor TR, TR0 via the read word line WLR, WRL0. As a result, the read transistor is turned on.

[0128] At operation 1127, a read voltage is applied to the source / drain and gate of the programming transistor to detect the data stored in the memory cell while the read transistor is turned on. For example, a read voltage (e.g., Vread) is applied to the source / drain via source line SL / SL0 and to the gate of programming transistor TP, TP0 via programming word line WLP, WLP0 while the read transistor TR, TR0 is turned on, as described with respect to Figure 2 and Figure 3B The results, such as Figure 2 As described, the read current Iread flows from the programming transistor TP, TP0 through the turned-on read transistor TR, TR0 to the corresponding bit line BL, BL0. The bit line BL, BL0 is coupled to a sense amplifier that detects the read current Iread, and determines the data stored in the programming transistor TP, TP0 of the memory cell based on the detected read current Iread. Figure 2 As described, the current paths of the program current Iprog and the read current Iread are different from each other.

[0129] In at least one embodiment, because the high programming voltage Vprog is applied to the source line instead of the programming word line, one or more advantages including but not limited to reduced leakage current, improved device reliability, etc. are achievable as described herein.

[0130] Fig.12 is a block diagram of an electronic design automation (EDA) system 1200 according to some embodiments.

[0131] In some embodiments, the EDA system 1200 includes an APR system. According to one or more embodiments, the method of designing a layout diagram described herein may be implemented using, for example, the EDA system 1200 to represent a wire routing arrangement according to some embodiments.

[0132] In some embodiments, the EDA system 1200 is a general purpose computing device that includes a hardware processor 1202 and a non-transitory computer-readable storage medium 1204 .

[0133] The processor 1202 is electrically coupled to the computer-readable storage medium 1204 via a bus 1208. The processor 1202 is also electrically coupled to an I / O interface 1210 via the bus 1208. A network interface 1212 is also electrically coupled to the processor 1202 via the bus 1208. The network interface 1212 is connected to a network 1214 so that the processor 1202 and the computer-readable storage medium 1204 can be connected to external elements via the network 1214. The processor 1202 is configured to execute a computer program code 1206 encoded in the computer-readable storage medium 1204 so that the system 1200 can be used to perform part or all of the described processes and / or methods. In one or more embodiments, the processor 1202 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0134] In one or more embodiments, the computer-readable storage medium 1204 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or device). For example, the computer-readable storage medium 1204 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), rigid disk, and / or optical disk. In one or more embodiments using optical disks, the computer-readable storage medium 1204 includes a compact disk read-only memory (CD-ROM), a compact disk read / write (CD-R / W), and / or a digital video disk (DVD).

[0135] In one or more embodiments, the storage medium 1204 stores computer program code 1206 configured to cause the system 1200 (where such execution (at least in part) represents an EDA tool) to be used to perform part or all of the processes and / or methods mentioned. In one or more embodiments, the storage medium 1204 also stores information that facilitates the execution of part or all of the processes and / or methods. In one or more embodiments, the storage medium 1204 stores a library 1207 of standard cells, including the standard cells disclosed herein.

[0136] The EDA system 1200 includes an I / O interface 1210. The I / O interface 1210 is coupled to external circuits. In one or more embodiments, the I / O interface 1210 includes a keyboard, a keypad, a mouse, a trackball, a touchpad, a touch screen, and / or cursor direction keys for communicating information and commands to the processor 1202.

[0137] The EDA system 1200 also includes a network interface 1212 coupled to the processor 1202. The network interface 1212 allows the system 1200 to communicate with a network 1214 to which one or more other computer systems are connected. The network interface 1212 includes a wireless network interface such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA; or a wired network interface such as ETHERNET, USB, or IEEE-1364. In one or more embodiments, part or all of the process and / or method is implemented in two or more systems 1200.

[0138] The system 1200 is configured to receive information through the I / O interface 1210. The information received through the I / O interface 1210 includes one or more of instructions, data, design rules, libraries of standard cells, and / or other parameters for processing. The information is transmitted to the processor 1202 via the bus 1208 by the processor 1202. The EDA system 1200 is configured to receive information related to the UI through the I / O interface 1210. The information is stored in the computer readable medium 1204 as a user interface (UI) 1242.

[0139] In some embodiments, part or all of the processes and / or methods mentioned are implemented as a standalone software application for execution by a processor. In some embodiments, part or all of the processes and / or methods are implemented as a software application that is part of an additional software application. In some embodiments, part or all of the processes and / or methods are implemented as a plug-in to a software application. In some embodiments, at least one of the processes and / or methods mentioned is implemented as a software application that is part of an EDA tool. In some embodiments, part or all of the processes and / or methods are implemented as a software application used by the EDA system 1200. In some embodiments, using a processor such as A layout diagram including standard cells can be generated by a tool such as CADENCE DESIGN SYSTEMS, Inc. or other suitable layout generation tools.

[0140] In some embodiments, these processes are implemented as functions of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage or memory units, such as DVDs, magnetic disks such as hard disks, semiconductor memories such as ROMs, RAMs, memory cards, etc.

[0141] Fig.131 is a block diagram of an integrated circuit (IC) manufacturing system 1300 and an IC manufacturing flow associated therewith according to some embodiments. In some embodiments, based on a layout diagram, the manufacturing system 1300 is used to manufacture at least one of (A) one or more semiconductor masks or (B) at least one component in a layer of a semiconductor integrated circuit.

[0142] exist Fig.13 In the embodiment, the IC manufacturing system 1300 includes entities that interact with each other in design and development, such as a design studio 1320, a mask studio 1330, and an IC manufacturer / fab ("fab") 1350, as well as manufacturing cycles and / or services related to manufacturing IC devices 1360. The entities in the system 1300 are connected via a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to one or more other entities and / or receives services from one or more of the other entities. In some embodiments, two or more of the design studio 1320, the mask studio 1330, and the IC fab 1350 are owned by a single larger company. In some embodiments, two or more of the design room 1320, the mask room 1330, and the IC fab 1350 coexist in a common facility and use common resources.

[0143] The design office (or design team) 1320 generates an IC design layout 1322. The IC design layout 1322 includes various geometric patterns designed for the IC device 1360. The geometric patterns correspond to patterns of metal, oxide or semiconductor layers, which constitute various components of the IC device 1360 to be manufactured. The various layers are combined to form various IC functions. For example, parts of the IC design layout 1322 include various IC components, such as active areas, gate electrodes, source and drain, metal lines or through holes for interlayer interconnection, and openings for pads formed in semiconductors. Substrates (such as silicon wafers) and various material layers arranged on semiconductor substrates. The design office 1320 implements appropriate design processes to form the IC design layout 1322. The design process includes one or more of logic design, physical design or layout and routing operations. The IC design layout 1322 is presented in one or more data files with geometric pattern information. For example, the IC design layout 1322 can be expressed in a GDSII file format or a DFII file format.

[0144] The mask chamber 1330 includes data preparation 1332 and mask manufacturing 1344. The mask chamber 1330 uses the IC design layout drawing 1322 to manufacture one or more masks 1345 to manufacture various layers of the IC device 1360 according to the IC design layout drawing 1322. The mask chamber 1330 performs mask data preparation 1332, wherein the IC design layout drawing 1322 is translated into a representative data file ("RDF"). The mask data preparation 1332 provides the RDF for mask manufacturing 1344. The mask manufacturing 1344 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (reticle) 1345 or a semiconductor wafer 1353. The design layout drawing 1322 is processed by the mask data preparation 1332 to conform to the specific characteristics of the mask writer. In Fig.13 , mask data preparation 1332 and mask manufacturing 1344 are shown as separate elements. In some embodiments, mask data preparation 1332 and mask manufacturing 1344 may be collectively referred to as mask data preparation.

[0145] In some embodiments, mask data preparation 1332 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors, such as those that may be due to diffraction, interference, other processing effects, etc. OPC adjusts IC design layout 1322. In some embodiments, mask data preparation 1332 includes other resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist functions, phase shift masks, other suitable techniques, etc., or combinations thereof. In some embodiments, inverse lithography techniques (ILT) are also used, which treat OPC as an inverse imaging problem.

[0146] In some embodiments, mask data preparation 1332 includes a mask rule checker (MRC) that checks an IC design layout 1322 that has been processed in OPC using a set of mask creation rules that include ensuring sufficient margins to account for variability in semiconductor manufacturing processes, etc. In some embodiments, the MRC modifies the IC design layout 1322 to compensate for limitations during mask fabrication 1344, which can undo portions of the modifications performed by the OPC to satisfy the mask creation rules.

[0147] In some embodiments, mask data preparation 1332 includes a lithography process check (LPC), which simulates a process to be performed by IC fab 1350 to manufacture IC device 1360. LPC simulates the process based on IC design layout diagram 1322 to create a simulated LPC. Process parameters in the simulation may include parameters related to various processes of the IC manufacturing cycle, parameters related to tools used to manufacture ICs, and / or other aspects of the manufacturing process. LPC takes into account various factors, such as aerial image contrast, depth of focus ("DOF"), mask error enhancement factor ("MEEF"), other suitable factors, etc. or combinations thereof. In some embodiments, after LPC creates a simulated manufactured device, if the simulated device is not close enough in shape to meet the design rules, OPC and / or MRC are repeated to further refine the IC design layout diagram 1322.

[0148] It should be understood that the above description of mask data preparation 1332 has been simplified for the sake of clarity. In some embodiments, data preparation 1332 includes additional features such as logic operations (LOPs) to modify IC design layout 1322 according to manufacturing rules. In addition, the processing applied to IC design layout 1322 during data preparation 1332 can be performed in a variety of different orders.

[0149] After mask data preparation 1332 and during mask manufacturing 1344, a mask 1345 or a set of masks 1345 are manufactured based on the modified IC design layout 1322. In some embodiments, mask manufacturing 1344 includes one or more photolithography exposures based on an electron beam on the IC design layout 1322. In some embodiments, based on the modified IC design layout, an electron beam (e-beam) or a plurality of electron beam mechanisms are used to form a map 1322 on a mask (photomask or reticle) 1345. Mask 1345 can be formed with various techniques. In some embodiments, mask 1345 is formed using binary techniques. In some embodiments, the mask pattern includes opaque areas and transparent areas. A radiation beam, such as an ultraviolet (UV) beam, used to expose an image sensitive material layer (e.g., photoresist) that has been coated on a wafer is blocked by the opaque area and transmitted through the transparent area. In one example, a binary mask version of mask 1345 includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chromium) coated in the opaque areas of the binary mask. In another example, mask 1345 is formed using a phase shift technique. In a phase shift mask (PSM) version of mask 1345, various features in a pattern formed on the phase shift mask are configured to have an appropriate phase difference to enhance resolution and imaging quality. In various examples, the phase shift mask can be an attenuated PSM or an alternating PSM. Masks generated by mask manufacturing 1344 are used in a variety of processes. For example, such masks are used in ion implantation processes to form various doped regions in semiconductor wafer 1353, such masks are used in etching processes to form various etched regions in semiconductor wafer 1353, and / or in other suitable processes.

[0150] IC fab 1350 is an IC manufacturing enterprise that includes one or more manufacturing facilities for manufacturing a variety of different IC products. In some embodiments, IC Fab 1350 is a semiconductor foundry. For example, there may be one manufacturing plant for front-end manufacturing of multiple IC products (front-end (FEOL) manufacturing), while a second manufacturing plant may provide back-end manufacturing IC products for interconnection and packaging (back-end (BEOL) manufacturing), and a third manufacturing plant may provide other services for the foundry business.

[0151] IC fab 1350 includes fabrication tools 1352 configured to perform various fabrication operations on semiconductor wafer 1353 to fabricate IC devices 1360 according to masks such as mask 1345. In various embodiments, fabrication tools 1352 include wafer steppers, ion implanters, photoresist coaters, processing chambers (e.g., CVD chambers or LPCVD furnaces), CMP systems, plasma etching systems, wafer cleaning systems, or other systems capable of performing one or more of the fabrication processes or suitable fabrication processes for fabricating devices, as described herein.

[0152] IC fab 1350 uses mask 1345 manufactured by mask cover 1330 to manufacture IC device 1360. Therefore, IC fab 1350 at least indirectly uses IC design layout 1322 to manufacture IC device 1360. In some embodiments, semiconductor wafer 1353 is formed into IC device 1360 by IC fab 1350 using mask 1345. In some embodiments, IC manufacturing includes one or more photolithography exposures based at least indirectly on IC design layout 1322. Semiconductor wafer 1353 includes a silicon substrate or other suitable substrate with a material layer formed thereon. Semiconductor wafer 1353 further includes one or more of various doped regions, dielectric components, multi-layer interconnects, etc. (formed in subsequent manufacturing steps).

[0153] With respect to integrated circuit (IC) manufacturing systems (e.g., Fig.13 Details of the system 1300 and the IC manufacturing process associated therewith are found, for example, in U.S. Patent No. 9,256,709 issued on February 9, 2016, Pre-grant Publication No. 20150278429 issued on October 1, 2015, U.S. Pre-grant Publication No. 20140040838 issued on February 6, 2014, and U.S. Patent No. 7,260,442 issued on August 21, 2007, the entire contents of which are incorporated herein by reference.

[0154] For example, in U.S. Pat. No. 9,256,709, an IC design layout is generated in a design house (or design team). The IC design layout includes various geometric patterns designed for IC devices. The geometric patterns correspond to the patterns of metal, oxide or semiconductor layers that constitute the various components of the IC device to be manufactured. The various layers are combined to form various IC functions. For example, parts of the IC design layout include various IC components, such as active areas, gate electrodes, source and drain, metal lines or vias for interlayer interconnection, and openings for pads formed in semiconductors, which will be formed in semiconductor substrates (e.g., silicon wafers) and various material layers disposed on the semiconductor substrate. The design house performs appropriate design processes to form the IC design layout. The design process may include logic design, physical design and / or layout and wiring. The IC design layout is presented in one or more data files with geometric pattern information. The mask house uses the IC design layout to manufacture one or more masks, which are used to manufacture the various layers of the IC device according to the IC design layout. The mask room performs mask data preparation, in which the IC design layout is converted into a form that can be physically written by a mask writer, wherein the design layout prepared by the mask data preparation is modified to comply with a specific mask manufacturer and / or mask vendor, and then manufactured. In the present embodiment, mask data preparation and mask manufacturing are illustrated as separate elements, however, mask data preparation and mask manufacturing can be collectively referred to as mask data preparation. Mask data preparation typically includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference or other processing effects. Mask data preparation may include other resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase-shift masks, other suitable techniques or combinations thereof. Mask data preparation 132 also includes a mask rule checker (MRC), which uses a set of mask creation rules to check the IC design layout that has been processed in OPC, which mask creation rules may contain some geometric and connectivity restrictions to ensure sufficient margin.

[0155] For example, in U.S. pre-grant publication No. 20150278429, in one embodiment, an IC manufacturing system can employ maskless lithography, such as electron beam lithography or optical maskless lithography. In such a system, mask manufacturing is bypassed, and the IC design layout is modified by data preparation suitable for wafer processing using a specific maskless lithography technology. Data preparation modifies the design layout suitable for subsequent operations in the IC manufacturing system. The result of data preparation is represented by one or more data files, such as files in a GDSII file format or a DFII file format. One or more data files include information of geometric patterns, such as polygons representing main design patterns and / or auxiliary components. In the present embodiment, one or more data files also include auxiliary data generated by data preparation. The auxiliary data will be used to enhance various operations of the IC manufacturing system, such as mask manufacturing performed by a mask room and wafer exposure performed by an IC manufacturer.

[0156] For example, in the pre-grant publication No. 20140040838, the IC design layout is presented in one or more data files with geometric pattern information. In one example, the IC design layout is represented in a "GDS" format known in the art. In an alternative embodiment, the IC design layout can be transmitted between components in an IC manufacturing system in an alternative file format such as DFII, CIF, OASIS or any other suitable file type. The IC design layout 300 includes various geometric patterns representing components of an integrated circuit. For example, the IC design layout may include major IC components, such as active areas, gate electrodes, source and drain electrodes, metal lines, interlayer interconnection vias, and openings for pads formed in semiconductors, which will be formed in semiconductor substrates (e.g., silicon wafers) and various material layers disposed on semiconductor substrates. The IC design layout may also include some auxiliary components, such as those used for imaging effects, processing enhancements and / or mask identification information.

[0157] For example, in U.S. Pat. No. 7,260,442, a mask manufacturing system includes: a processing tool for processing a mask; a metrology tool connected to the processing tool for inspecting the mask and obtaining an inspection result; a controller coupled to the processing tool and the metrology tool for generating a manufacturing model of the processing tool and calibrating the manufacturing model according to the equipment data, material data, and inspection results of the mask. The mask manufacturing system may include at least one processing tool, a metrology tool, a controller, a database, and a manufacturing execution system. The processing tool may be an exposure tool, a developer, an etcher, or a photoresist stripper. The metrology tool performs a post-etch inspection or a post-strip inspection and obtains a post-etch inspection result or a post-strip inspection result, respectively. The controller is used for run-to-run control of the processing tool, including feedforward control and feedback control. The controller receives the post-etch or post-strip inspection result from the metrology tool and retrieves the device and material data from the database. The controller connected to the manufacturing execution system generates a manufacturing model of the processing tool and calibrates the manufacturing model according to the equipment data, material data, and inspection results of the mask.

[0158] In some embodiments, a memory device includes at least one bit line, at least one source line, at least one programming word line, at least one read word line, and at least one memory cell including a programming transistor and a read transistor. The programming transistor includes a gate terminal coupled to at least one programming word line, a first terminal coupled to at least one source line, and a second terminal. The read transistor includes a gate terminal coupled to at least one read word line, a first terminal coupled to at least one bit line, and a second terminal coupled to the second terminal of the programming transistor.

[0159] In the above-mentioned memory device, at least one memory cell is configured to store a reference having any of the following: a first value corresponding to the gate dielectric of the programming transistor, which is broken down by a previous application at or above a predetermined breakdown voltage; and a second value corresponding to the gate dielectric that is not broken down.

[0160] The programming transistor and the reading transistor are identically configured in the above-mentioned memory device.

[0161] The above-mentioned memory device also includes: a controller, which is coupled to at least one memory cell via at least one bit line, at least one source line, at least one programming word line and at least one read word line, wherein in a programming operation, the controller is configured to apply a higher voltage to the first terminal of the programming transistor via at least one source line, and to apply a lower voltage to the gate terminal of the programming transistor via at least one programming word line, wherein the voltage difference between the higher voltage and the lower voltage is equal to or higher than a predetermined breakdown voltage to break down the gate dielectric of the programming transistor.

[0162] In the memory device, in a read operation, the controller is configured to apply a turn-on voltage to a gate terminal of a read transistor via at least one read word line to turn on the read transistor, and when the read transistor is turned on, apply a read voltage via at least one source line and at least one programming word line and at least one programming word line corresponding to a first terminal and a gate terminal of the programming transistor for detection, wherein the reference is stored in at least one memory cell.

[0163] In the above memory device, at least one bit line is a plurality of bit lines, at least one source line is a plurality of source lines, at least one programming word line is a plurality of programming word lines, at least one read word line is a plurality of read word lines, at least one memory cell is a plurality of memory cells, each memory cell is coupled to a corresponding bit line among the plurality of bit lines, a corresponding source line among the plurality of source lines, a corresponding programming word line among the plurality of programming word lines, and a corresponding read word line among the plurality of read word lines, and the memory device further includes a controller coupled to the plurality of memory cells via the plurality of bit lines, the plurality of source lines, the plurality of programming word lines, and the plurality of read word lines, so as to and in a programming operation of a selected memory cell among a plurality of memory cells, the controller is configured to apply a programming voltage to a source line coupled to the selected memory cell and apply a reference voltage to other source lines among the plurality of source lines, apply a reference voltage to a programming word line coupled to the selected memory cell and apply a first voltage to other programming word lines among the plurality of programming word lines, wherein the first voltage is higher than the reference voltage and lower than the programming voltage, for each of a plurality of read word lines, apply a reference voltage to each read word line or each floating read word line, and apply a reference voltage to a plurality of bit lines.

[0164] In the above-mentioned memory device, the voltage difference between the programming voltage and the reference voltage is equal to or higher than a predetermined breakdown voltage to break down the gate dielectric of the programming transistor in the selected memory cell, the voltage difference between the programming voltage and the first voltage is lower than the predetermined breakdown voltage to avoid breaking down the gate dielectric of the programming transistor in unselected memory cells among the multiple memory cells, and the voltage difference between the first voltage and the reference voltage is lower than the predetermined breakdown voltage to avoid breaking down the gate dielectric of the programming transistor in the unselected memory cells.

[0165] In the above-mentioned memory device, in a read operation of a selected memory cell, the controller is configured to apply a read voltage to a source line and a programming word line coupled to the selected memory cell, and apply a reference voltage to other source lines and other programming word lines, apply a second voltage higher than the reference voltage to a read word line coupled to the selected memory cell, and apply the reference voltage to other read word lines among a plurality of read word lines, apply the reference voltage to a bit line coupled to the selected memory cell, and for each other bit lines among a plurality of bit lines, apply the reference voltage to each other bit lines or floating each other bit lines.

[0166] In the above memory device, the program voltage is greater than the first voltage, the first voltage is greater than the read voltage, the read voltage is greater than the second voltage, and the second voltage is greater than the reference voltage.

[0167] In the above-mentioned memory device, it also includes: a word line decoder, which is configured to provide a programming voltage in response to at least one memory cell to be programmed being selected; a switch, coupled between the word line decoder and at least one source line; and a source line decoder, which is configured to control the switch to be turned on in response to at least one selected memory cell to be programmed, so as to couple the programming voltage from the word line decoder to at least one source line.

[0168] In some embodiments, an integrated circuit (IC) device includes: a first active area extending along a first direction; a first pair of gate areas extending across the first active area along a second direction perpendicular to the first direction; and a first metal layer. The first pair of gate areas and the first active area constitute a first programming transistor and a first reading transistor that share a common source / drain area. The first metal layer includes a first programming word line pattern above and coupled to the gate area of ​​the first programming transistor, a first reading word line pattern above and coupled to the gate area of ​​the first reading transistor, and a first source line pattern coupled thereto. Another source / drain area of ​​the first programming transistor, and a first bit line pattern coupled to another source / drain area of ​​the first reading transistor.

[0169] In the above IC device, the first source line pattern and the first bit line pattern are arranged between the first program word line pattern and the first read word line pattern in the second direction.

[0170] In the above IC device, in the second direction, the first program word line pattern has a larger size than the first read word line pattern.

[0171] In the above IC device, the first program word line pattern, the first read word line pattern, and the first source line pattern are elongated in the first direction, and the first bit line pattern is elongated in the second direction.

[0172] In the above-mentioned IC device, it also includes: a second pair of gate regions, extending across the first active region in the second direction, wherein the second pair of gate regions and the first active region configure a second programming transistor and the second read transistor shares a common source / drain region, wherein the first metal layer also includes: a second programming word line pattern, above the gate region of the second programming transistor and coupled to the gate region of the second programming transistor, the second programming word line pattern overlaps with the first read word line pattern in the first direction, and a second read word line pattern, above the gate region of the second read transistor and coupled to the gate region of the second read transistor, the second read word line pattern overlaps with the first programming word line pattern in the first direction.

[0173] In the above-mentioned IC device, the first metal layer also includes a second source line pattern coupled to another source / drain region of the second programming transistor, the second reading transistor has another source / drain region which is another source / drain region of the first reading transistor, and the first bit line pattern is arranged between the first source line pattern and the second source line pattern in the first direction.

[0174] In the above-mentioned IC device, it also includes: a second metal layer, on the first metal layer, including: a programming word line, coupled to the first programming word line pattern, and a reading word line, coupled to the first reading word line pattern; and a third metal layer, on the first metal layer, including: a source line, coupled to the first source line pattern, and a bit line, coupled to the first bit line pattern, wherein the programming word line and the reading word line extend along one of the first direction and the second direction, and the source line and the bit line extend along the other of the first direction and the second direction.

[0175] The above-mentioned IC device also includes: a plurality of identical first memory cells and a plurality of identical second memory cells, which are arranged adjacent to each other in a repeating pattern, each of the plurality of second memory cells is symmetrical with any first memory cell between the plurality of first memory cells in the first direction, and each of the plurality of second memory cells is adjacent to at least one first memory cell among the plurality of first memory cells.

[0176] In some embodiments, a method includes, in a programming operation of a memory cell having a programming transistor, applying a higher voltage to a source / drain of the programming transistor and applying a lower voltage to a gate of the programming transistor. The voltage difference between the higher voltage and the lower voltage is equal to or higher than a predetermined breakdown voltage to break down a gate dielectric of the programming transistor.

[0177] In the above method, a current path of a program current flowing through a memory cell in a program operation is different from a current path of a read current flowing through a memory cell in a read operation.

[0178] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for realizing the same purpose of the embodiments introduced herein and / or realizing the same advantages thereof. Those skilled in the art will also appreciate that such equivalent structures do not deviate from the spirit and scope of the present invention, and they can make various changes, substitutions and changes in the present invention without deviating from the spirit and scope of the present invention.

Claims

1. A memory device, comprising: at least one bit line; at least one source line; at least one programming word line; at least one read word line; as well as at least one memory cell including a programming transistor and a reading transistor, a controller coupled to the at least one memory cell via the at least one bit line, the at least one source line, the at least one programming word line, and the at least one reading word line, wherein The programming transistor comprises: a gate terminal coupled to the at least one programming word line, a first terminal coupled to the at least one source line, and The second terminal, and The read transistor comprises: a gate terminal coupled to the at least one read word line, a first terminal coupled to the at least one bit line, and a second terminal coupled to the programming transistor, The controller is configured to: applying a first voltage to the first terminal of the programming transistor via the at least one source line, and A second voltage is applied to a gate terminal of the programming transistor via the at least one programming word line, wherein the first voltage is higher than the second voltage, and a voltage difference between the first voltage and the second voltage is equal to or higher than a predetermined breakdown voltage to break down a gate dielectric of the programming transistor.

2. The memory device according to claim 1, wherein The at least one memory unit is configured to store data having any of the following: a first value corresponding to a gate dielectric of the programming transistor that breaks down under a previous application of a predetermined breakdown voltage or above; and The second value corresponds to a gate dielectric that has not been broken down.

3. The memory device according to claim 1, wherein The programming transistor and the reading transistor are identically configured.

4. The memory device according to claim 1, wherein: The second voltage is a ground voltage.

5. The memory device according to claim 1, wherein In a read operation the controller is configured to: applying a turn-on voltage to the gate terminal of the read transistor via the at least one read word line to turn on the read transistor, A read voltage is applied via the at least one source line and the at least one programming word line corresponding to the first terminal and the gate terminal of the programming transistor to detect data stored in the at least one memory cell when the read transistor is turned on.

6. The memory device according to claim 1, wherein The at least one bit line is a plurality of bit lines, The at least one source line is a plurality of source lines, The at least one programming word line is a plurality of programming word lines, the at least one read word line is a plurality of read word lines, the at least one memory cell being a plurality of memory cells, each memory cell being coupled to a corresponding bit line of the plurality of bit lines, a respective source line of the plurality of source lines, a corresponding programming word line of the plurality of programming word lines, and a corresponding read word line of the plurality of read word lines, The memory device also includes a controller coupled to the plurality of memory cells via the plurality of bit lines, the plurality of source lines, the plurality of program word lines, and the plurality of read word lines, and In a programming operation of a selected memory cell among the plurality of memory cells, the controller is configured to: applying a programming voltage to the source line coupled to the selected memory cell and applying a reference voltage to other source lines of the plurality of source lines, The reference voltage is applied to a programming word line coupled to the selected memory cell, and a first voltage is applied to other programming word lines of the plurality of programming word lines, wherein: The first voltage is higher than the reference voltage and lower than the programming voltage, For each of the plurality of read word lines, applying the reference voltage to the each read word line or floating the each read word line, and The reference voltage is applied to the plurality of bit lines.

7. The memory device according to claim 6, wherein a voltage difference between the programming voltage and the reference voltage being equal to or higher than a predetermined breakdown voltage to break down a gate dielectric of the programming transistor in the selected memory cell, a voltage difference between the programming voltage and the first voltage being lower than the predetermined breakdown voltage to avoid breakdown of a gate dielectric of the programming transistor in unselected memory cells among the plurality of memory cells, A voltage difference between the first voltage and the reference voltage is lower than the predetermined breakdown voltage to avoid breaking down a gate dielectric of the programming transistor in the unselected memory cells.

8. The memory device according to claim 6, wherein In a read operation of the selected memory cell, the controller is configured to: applying a read voltage to the source line and the programming word line coupled to the selected memory cell, and applying the reference voltage to other source lines and other programming word lines, applying a second voltage higher than the reference voltage to the read word line coupled to the selected memory cell, and applying the reference voltage to other read word lines among the plurality of read word lines, applying the reference voltage to the bit line coupled to the selected memory cell, and For each other bit line of the plurality of bit lines, the reference voltage is applied to the each other bit line or the each other bit line is floated.

9. The memory device according to claim 8, wherein The programming voltage is greater than the first voltage, The first voltage is greater than the read voltage, The read voltage is greater than the second voltage, and The second voltage is greater than the reference voltage.

10. The memory device according to claim 1, further comprising: a word line decoder configured to provide a programming voltage in response to the at least one memory cell to be programmed being selected; a switch coupled between the word line decoder and the at least one source line; and A source line decoder is configured to control the switch to be turned on in response to the at least one memory cell being selected to be programmed to couple the program voltage from the word line decoder to the at least one source line.

11. An integrated circuit device comprising: A first active region extending along a first direction; a first pair of gate regions extending across the first active region along a second direction transverse to the first direction, wherein the first pair of gate regions and the first active region configure a first programming transistor and a first reading transistor sharing a common source / drain region; and The first metal layer includes: a first programming word line pattern over and coupled to the gate region of the first programming transistor, a first read word line pattern over the gate region of the first read transistor and coupled to the gate region of the first read transistor, a first source line pattern coupled to the other source / drain region of the first programming transistor, and a first bit line pattern coupled to the other source / drain region of the first read transistor; wherein a first voltage is applied to the other source / drain region of the first programming transistor via the first source line pattern, and A second voltage is applied to a gate region of the first programming transistor via the first programming word line pattern, wherein the first voltage is higher than the second voltage and a voltage difference between the first voltage and the second voltage is equal to or higher than a predetermined breakdown voltage to break down a gate dielectric of the first programming transistor.

12. The integrated circuit device according to claim 11, wherein The first source line pattern and the first bit line pattern are arranged between the first program word line pattern and the first read word line pattern in the second direction.

13. The integrated circuit device according to claim 11, wherein In the second direction, the first program word line pattern has a larger size than the first read word line pattern.

14. The integrated circuit device according to claim 11, wherein The first programming word line pattern, the first reading word line pattern and the first source line pattern are elongated in the first direction, and The first bit line pattern is elongated in the second direction.

15. The integrated circuit device according to claim 11, further comprising: a second pair of gate regions extending across the first active region in the second direction, wherein the second pair of gate regions and the first active region configure a second programming transistor and a second reading transistor sharing a common source / drain region, in, The first metal layer further comprises: a second programming word line pattern over the gate region of the second programming transistor and coupled to the gate region of the second programming transistor, the second programming word line pattern overlapping the first reading word line pattern in the first direction, and A second read word line pattern is above and coupled to the gate region of the second read transistor, and the second read word line pattern overlaps the first programming word line pattern in the first direction.

16. The integrated circuit device of claim 15, wherein The first metal layer further includes a second source line pattern coupled to the other source / drain region of the second programming transistor, the second read transistor having a further source / drain region which is the further source / drain region of the first read transistor, and The first bit line pattern is arranged between the first source line pattern and the second source line pattern in the first direction.

17. The integrated circuit device of claim 11, further comprising: A second metal layer, above the first metal layer, comprises: a programming word line coupled to the first programming word line pattern, and a read word line coupled to the first read word line pattern; and A third metal layer, above the first metal layer, comprises: a source line coupled to the first source line pattern, and a bit line coupled to the first bit line pattern, in, The programming word line and the reading word line extend along one of the first direction and the second direction, The source line and the bit line extend along the other of the first direction and the second direction.

18. The integrated circuit device of claim 11, further comprising: a plurality of identical first memory cells and a plurality of identical second memory cells arranged adjacent to each other in a repeating pattern, in, Across the first direction, each of the plurality of second memory cells is symmetrical to any first memory cell of the plurality of first memory cells, In the second direction, each of the plurality of second memory cells is adjacent to at least one first memory cell of the plurality of first memory cells.

19. A method of operating a memory device, comprising: In a programming operation of a memory cell having a programming transistor, Applying a higher voltage to the source / drain of the programming transistor, A lower voltage is applied to a gate of the programming transistor, wherein a voltage difference between the higher voltage and the lower voltage is equal to or higher than a predetermined breakdown voltage to break down a gate dielectric of the programming transistor.

20. The method according to claim 19, wherein A current path of a program current flowing through the memory cell in the program operation is different from a current path of a read current flowing through the memory cell in a read operation.

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