Gallium Nitride HEMT Chip Integrated Packaging Structure and Its Manufacturing Method

Abstract

It relates to a gallium nitride HEMT chip integrated packaging structure and its manufacturing method. The structure sequentially includes a heat dissipation carrier on the bottom surface of the package, a gallium nitride HEMT chip, a first encapsulation glue layer, a fan-out circuit layer, a MOSFET chip, a second encapsulation glue layer, and a metal island layer according to the packaging process. The first source inner island of the fan-out circuit layer is formed in a block deviating from the gallium nitride HEMT chip. One end of the drain circuit fans out and extends away from the gallium nitride HEMT chip. The gate circuit is located between the first source inner island and the drain circuit. The MOSFET chip is disposed on the first source inner island, so that the drain of the MOSFET chip is spaced and connected to the source of the gallium nitride HEMT chip. The second source inner island of the metal island layer conducts and interconnects the second source pad of the MOSFET chip and the gate circuit, so that the source of the MOSFET chip is short-path connected to the gate of the gallium nitride HEMT chip. The MOSFET chip is located in an encapsulation glue layer different from the gallium nitride HEMT chip. The structure has the effects of reducing parasitic inductance and improving the responsiveness of the MOSFET chip.

Description

[0001] The priority basis of the present invention includes: the invention application case with the application number 202110903994.8, the application date of August 6, 2021, and the patent name of "Gallium Nitride HEMT Chip Integrated Packaging Structure and Its Manufacturing Method". Technical Field

[0002] The present invention relates to the field of packaging technologies for gallium nitride HEMT chips, and particularly to a gallium nitride HEMT chip integrated packaging structure and its manufacturing method. Background Art

[0003] The base material of the working layer of a gallium nitride HEMT (High Electron Mobility Transistor) chip is gallium nitride (GaN), and the base material of the working layer of a MOSFET chip is silicon (Si). Due to the material characteristics, a PN junction cannot be set inside the gallium nitride HEMT chip. The conduction between the source and the drain is through the intermediate electron layer, and only when a sufficient negative voltage is applied to the gate can the gallium nitride HEMT chip be turned off. Therefore, compared with a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) chip, the gallium nitride HEMT chip has the advantage of fast switching speed. However, based on the structural characteristics, the switching conduction operation of the gate needs to be within the negative voltage working range. When the gate is grounded or at a voltage of 0 V, the gallium nitride HEMT chip is conducting, and a sufficiently large negative voltage needs to be applied for the source and drain of the gallium nitride HEMT chip to turn off. Therefore, there is a risk of power consumption leakage current. Thus, the primary problem to be solved for power devices of gallium nitride HEMT is how to perform switching conduction within the positive voltage (including a voltage of 0 V) working range, and achieve that the gallium nitride HEMT chip is turned off when the gate is grounded or at a voltage of 0 V. Currently, there are various existing technologies.

[0004] The invention patent publication number CN103872119A discloses a high electron mobility transistor and its manufacturing method. The HEMT includes: a substrate, a first gallium nitride layer, a P-type gallium nitride layer, a second gallium nitride layer, a barrier layer, a gate, a source, and a drain. Among them, the first gallium nitride layer is formed on the substrate. Viewed from a cross-sectional view, the first gallium nitride layer has a stepped profile, and the P-type gallium nitride layer is formed on the upper step surface of the stepped profile, which has enhanced sidewalls; the second gallium nitride layer is formed on the P-type gallium nitride layer, and the barrier layer is formed on the second gallium nitride layer to enable a two-dimensional electron gas (2DEG) to be formed between the barrier layer and the second gallium nitride layer. The gate is formed outside the enhanced sidewalls to receive a gate voltage and thereby turn on or off the HEMT. In related existing technologies, the technical solution for achieving gate switching conduction within the positive voltage working range is to perform a stepped process change within the chip structure, that is, it is necessary to change the internal chip structure of the current gallium nitride HEMT chip, and the reliability and other characteristics of the chip need to be re-verified.

[0005] The invention patent publication number CN112768427A discloses a packaging structure and a packaging method for a gallium nitride HEMT. The gallium nitride HEMT chip has a fast switching conduction speed but generates a high heat during use. In order to improve the heat dissipation performance of the packaging structure, the gallium nitride HEMT chip to be packaged is fixed and electrically connected to the heat dissipation area; the gate of the gallium nitride HEMT chip to be packaged is located between the source and the drain, reducing the parasitic inductance of the driving loop. The source is electrically connected to the second conductive pad through the fourth electrical connection component to form a Kelvin source. In the related prior art, the gallium nitride HEMT chip is commonly a single-chip packaging architecture and uses a leadless lead frame to increase the heat dissipation performance, but still cannot solve the technical problem of the gate switching conduction within the positive voltage operating range.

[0006] The invention patent publication number CN110504242A discloses a high-current cascaded enhanced GaN full-bridge power module packaging structure and a packaging method. The structure includes a packaging shell, a metal lead frame and pins. The packaging shell further includes: a first cascaded enhanced GaN HEMT device, a second cascaded enhanced GaN HEMT device, a third cascaded enhanced GaN HEMT device, a fourth cascaded enhanced GaN HEMT device, and a full-bridge gate drive circuit. In any cascaded enhanced GaN HEMT device provided in the module of this existing patent, a large current is achieved through the parallel connection of multiple GaN HEMT devices; in addition, a voltage adjustment circuit needs to be added to ensure that the internal high-voltage depletion-type GaN device operates in a safe area state. In the previous case of this existing patent, the purpose of achieving a large current is through the parallel connection of multiple GaN HEMTs; there is no specific disclosure on how to integrate the additional voltage adjustment circuit into the packaging structure. As can be seen from the figure, the traditional chip side-by-side and wire bonding connection method is still adopted. In the related prior art, the setting of a large number of wire bonding wires will inevitably generate a large parasitic inductance in the packaging structure, which is not conducive to improving the operating frequency of the gallium nitride HEMT power device. At the same time, the wire bonding method will have an internal resistance in the package, which will also cause electrical losses, and a larger package size is required to accommodate more than two chips, which is not conducive to the miniaturization of the packaging structure. In order to reduce the inductance, an additional DBC insulating sheet needs to be provided inside another similar type of packaging structure, and usually the insulating sheet is a poor conductor of heat, which is not conducive to the heat dissipation of the packaging structure.

[0007] In addition, the invention patent publication number CN104992964A discloses a GaN epitaxial structure with a PN junction. A PN junction is formed between an N-type GaN semiconductor layer and a P-type GaN semiconductor layer. The P-type GaN semiconductor layer is formed on a nucleation layer, and the N-type GaN semiconductor layer is formed on the P-type GaN semiconductor layer and forms a PN junction with the P-type GaN semiconductor layer. The material of the P-type GaN semiconductor layer is P-type GaN or P-type AlGaN, and the material of the N-type GaN semiconductor layer is N-type GaN or N-type AlGaN. The relevant prior art of this patent does not disclose specific doping substances. If aluminum (Al) is used as a dopant, the GaN semiconductor layer must be P-type. A PN junction composed solely of P-type GaN and N-type GaN will constitute a quantum well effect, which is the PN junction of the most basic structure of an LED and belongs to the field of semiconductor light emission. Therefore, there is no PN junction provided inside the gallium nitride HEMT chip in currently visible products. Summary of the Invention

[0008] One of the main objects of the present invention is to provide an integrated packaging structure for a gallium nitride HEMT chip, which has the effect of realizing switching conduction within a positive voltage operating range, so that the gallium nitride HEMT chip is turned off when the gate of the packaging structure is grounded or at a voltage of 0 V, without changing the internal chip structure of the current gallium nitride HEMT chip, and overcoming the problems of power consumption and leakage current caused by the gate being turned off only within a negative voltage operating range in the existing packaging structure of the gallium nitride HEMT chip. In an actual application, it can realize the 0V turn-off and 5V turn-on of the gallium nitride HEMT chip by the surface gate of the packaging structure.

[0009] Another main object of the present invention is to provide a manufacturing method for an integrated packaging structure of a gallium nitride HEMT chip, which can effectively integrate the gallium nitride HEMT chip and the MOSFET chip under the architecture that gives priority to heat dissipation of the gallium nitride HEMT chip, reduce the difficulty of heterogeneous chip integration in semiconductor packaging manufacturing, and improve the production smoothness of the packaging process.

[0010] The third main object of the present invention is to provide an electronic device, which can more quickly export the internal heat of the gallium nitride HEMT chip, and thus reduce the influence of the heat generation of the gallium nitride HEMT chip on the electrical performance of the MOSFET chip.

[0011] One of the main objects of the present invention is achieved through the following technical solutions:

[0012] An integrated packaging structure for a gallium nitride HEMT chip is proposed, including: a heat dissipation carrier located at the bottom of the package;

[0013] A gallium nitride HEMT chip, disposed on the heat dissipation carrier, such that the back surface of the gallium nitride HEMT chip is thermally coupled to the heat dissipation carrier, and a first source pad, a first gate pad, and a first drain pad are disposed on the front surface of the gallium nitride HEMT chip;

[0014] A first encapsulation glue layer is formed on the heat dissipation carrier to seal the gallium nitride HEMT chip. The first encapsulation glue layer has a first encapsulation height on the gallium nitride HEMT chip, and the first encapsulation glue layer is provided with a first through hole to expose the first source pad, the first gate pad and the first drain pad;

[0015] A fan-out circuit layer is formed on the first encapsulation glue layer. The fan-out circuit layer includes: a first source inner island with a through hole leading to the first source pad, a gate circuit with a through hole leading to the first gate pad, and a drain circuit with a through hole leading to the first drain pad. Among them, the first source inner island is formed in a block deviating from the gallium nitride HEMT chip, one end of the drain circuit fans out and extends away from the gallium nitride HEMT chip, and the gate circuit is located between the first source inner island and the drain circuit;

[0016] A MOSFET chip is disposed on the first source inner island, enabling the back drain layer of the MOSFET chip to be electrically connected to the first source pad, and a second source pad and a second gate pad are disposed on the front of the MOSFET chip;

[0017] A second encapsulation glue layer is formed on the first encapsulation glue layer and the fan-out circuit layer. The second encapsulation glue layer has a second encapsulation height on the MOSFET chip, and the second encapsulation glue layer is provided with a second through hole to expose the second source pad and the second gate pad;

[0018] A metal island layer is formed on the second encapsulation glue layer. The metal island layer includes: a second source inner island with a through hole for interconnecting the second source pad and the gate circuit, and a gate inner island with a through hole leading to the second gate pad;

[0019] Among them, the heat dissipation carrier is split into a source outer island around the heat dissipation main island and conducting to the second source inner island, a gate outer island conducting to the gate inner island, and a drain outer island conducting to the fan-out end of the drain circuit;

[0020] As the gate outer island turns on or off the MOSFET chip within the positive and negative voltage operating range (the negative voltage operating range includes 0 V), the potential of the first source pad of the gallium nitride HEMT chip can also be synchronously lowered or raised to synchronously turn on or off the gallium nitride HEMT chip.

[0021] By adopting the above technical solution, the second source pad of the MOSFET chip is shorted to the first gate pad of the gallium nitride HEMT chip by using the second source inner island to serve as the source connection of the entire packaging structure. The second gate pad of the MOSFET chip can serve as the gate connection of the entire packaging structure, so that the gate turn-off to turn-on operating voltage can be increased to a negative voltage turn-off including 0 V and a positive voltage turn-on not including 0 V. The gate voltage on the packaging surface is grounded or at 0 V potential, and it still remains in the power-saving constant-off state. Under the FOPLP (Fan-Out Panel Level Package) packaging architecture, the gallium nitride HEMT chip and the MOSFET chip are efficiently integrated. The MOSFET chip is disposed on the first source inner island on the first encapsulation adhesive layer, so that the back drain layer of the MOSFET chip is electrically connected to the first source pad of the gallium nitride HEMT chip. The MOSFET chip is relatively offset from the gallium nitride HEMT chip. The gallium nitride HEMT chip is disposed on the heat dissipation carrier. The gallium nitride HEMT chip has higher external thermal conductivity than the MOSFET chip, and the gallium nitride HEMT chip and the MOSFET chip are not directly thermally coupled, providing a faster external heat dissipation conduction path for the high-temperature energy of the gallium nitride HEMT chip than through the MOSFET chip.

[0022] In a preferred example of the present invention, it can be further configured as follows: through the drain outer island, the turn-off operating voltage of the first drain pad of the gallium nitride HEMT chip is between 100 and 600 V; by shorting the first gate pad of the gallium nitride HEMT chip and the second source pad of the MOSFET chip through the second source inner island, the turn-off and turn-on operating voltages of the first gate pad of the gallium nitride HEMT chip are both less than 0 V; through the gate outer island, when the source-drain of the MOSFET chip is turned off at a negative voltage (including 0 V), the voltage of the first source pad of the gallium nitride HEMT chip is passively raised, and the voltage of the first gate pad of the gallium nitride HEMT chip that is ≤ 0 V is still not sufficient to turn on the gallium nitride HEMT chip.

[0023] By adopting the above preferred technical features, the second gate pad of the MOSFET chip can be used as the gate connection of the entire packaging structure by using the outer gate island. In cooperation with using the second source inner island to short-circuit the second source pad of the MOSFET chip to the first gate pad of the gallium nitride HEMT chip, which also serves as the source connection of the entire packaging structure, the gate operating voltage of the integrated packaging structure of the gallium nitride HEMT chip is changed, and there is no interference from parasitic inductance. The integrated packaging structure of the gallium nitride HEMT chip can also be turned off when grounded or at 0 potential. The source-drain-gate arrangement from the gallium nitride HEMT chip to the bottom surface of the package is changed. The turn-off operating voltage of the first drain pad of the gallium nitride HEMT chip can operate at a high voltage between 100 and 600 V, that is, the turn-off and turn-on operating voltages of the first gate pad of the gallium nitride HEMT chip are both less than 0 V, belonging to high-power semiconductor devices. When the MOSFET chip is turned off between the source and the drain, the voltage of the first source pad of the gallium nitride HEMT chip is passively raised, and the voltage of ≦0 V of the first gate pad of the gallium nitride HEMT chip is not sufficient to turn on the gallium nitride HEMT chip, realizing the switching operation of synchronous turn-on and synchronous turn-off of the MOSFET chip to the gallium nitride HEMT chip.

[0024] In a preferred example of the present invention, it can be further configured that: the turn-off operating voltage of the outer gate island is ≦0 V, and the turn-on operating voltage of the outer gate island is 3 to 20 V; a Schottky diode is also reversely arranged inside the MOSFET chip.

[0025] By adopting the above preferred technical features, using the turn-off operating voltage of the outer gate island to be ≦0 V, when grounded or at 0 voltage, the source-drain connection of the MOSFET chip is still turned off, and the gallium nitride HEMT chip is also turned off synchronously; when the power switch is switched, the voltage of the second source inner island is stabilized at a negative voltage, and the voltage change of the outer drain island does not affect the voltage relatively far from the outer gate island. The turn-on operating voltage of the outer gate island can fluctuate between 3 and 20 V with a relatively stable value. And a Schottky diode is also reversely arranged inside the MOSFET chip to eliminate the parasitic capacitance of the MOSFET chip based on silicon.

[0026] In a preferred example of the present invention, it can be further configured that: the first source inner island is relatively deviated from the gallium nitride HEMT chip and has a size larger than that of the first source pad, and the size of the first source inner island is also larger than and the contour corresponds to the back surface of the MOSFET chip, so that the drain layer is substantially bonded to the first source inner island.

[0027] By adopting the above preferred technical features, in the integrated packaging structure, the first source inner island on the first encapsulation adhesive layer is relatively deviated from the gallium nitride HEMT chip and has a size larger than that of the first source pad, so that the MOSFET chip no longer needs to be directly placed on the first source pad of the gallium nitride HEMT chip. The size of the MOSFET chip can be larger than that of the first source pad of the gallium nitride HEMT chip, the size of the MOSFET chip is no longer restricted, and there is no increase in the conduction resistance of the in-package wire bonding leads, thus maintaining the current performance passing through the MOSFET chip.

[0028] In a preferred example of the present invention, it can be further configured that: the second source inner island is relatively deviated and has a size larger than that of the first source inner island, and the through holes of the first encapsulation adhesive layer electrically connecting the second source inner island and the through holes of the second encapsulation adhesive layer are in direct correspondence, so as to shorten the conduction path to less than 100 um; the in-package resistance of the integrated packaging structure of the gallium nitride HEMT chip is below 0.2 mΩ.

[0029] By adopting the above preferred technical features, the second source inner island is relatively deviated and has a size larger than that of the first source inner island, and the through holes of the first encapsulation adhesive layer electrically connecting the second source inner island on the first gate pad of the gallium nitride HEMT chip and the through holes of the second encapsulation adhesive layer are in direct correspondence, so as to shorten the conduction path to less than 100 um; the in-package resistance of the integrated packaging structure of the gallium nitride HEMT chip can also reach below 0.2 mΩ. Therefore, the transmission path between the first gate pad and the first source pad on the gallium nitride HEMT chip is short, and the configuration relationship between the chip and the packaging structure is interchanged between the gate and the source, changing from the form that the source of the chip is relatively far away from the drain to the form that the gate of the package is relatively far away from the drain.

[0030] Another technical solution for achieving the first main object of the present invention is as follows:

[0031] A gallium nitride HEMT chip integrated packaging structure is proposed, including: a heat dissipation carrier capable of establishing an external heat dissipation path, a gallium nitride HEMT chip disposed on the heat dissipation carrier, a MOSFET chip encapsulated in an FOPLP (Fan-Out Panel Level Packaging) encapsulation glue layer, and an FOPLP circuit structure. The FOPLP circuit structure includes a first source inner island and a second source inner island. The first source inner island is located in the FOPLP encapsulation glue layer and connects the source of the gallium nitride HEMT chip and the drain of the MOSFET chip in a sandwich manner. The second source inner island is located on a surface of the FOPLP encapsulation glue layer and shorts the gate of the gallium nitride HEMT chip and the source of the MOSFET chip in a long and short via manner. The heat dissipation carrier is split into: a source outer island conducting to the second source inner island, a gate outer island conducting to the gate inner island, and a drain outer island at the fan-out end of the drain line conducting to the FOPLP circuit structure.

[0032] By adopting the above technical solution, the source of the gallium nitride HEMT chip and the drain of the MOSFET chip are connected in a sandwich manner by the first source inner island in the FOPLP encapsulation glue layer, and the gate of the gallium nitride HEMT chip and the source of the MOSFET chip are shorted by the second source inner island on the top surface of the encapsulation in a long and short via manner, realizing the heterogeneous chip integrated packaging of a circuit structure with the gallium nitride HEMT chip in the off state when the gate is grounded or at voltage 0 V, and greatly reducing the parasitic inductance and improving the heat dissipation of the gallium nitride HEMT chip.

[0033] In a preferred example of the present invention, it can be further configured that: the heat dissipation carrier further includes a main heat dissipation island, the back surface of the gallium nitride HEMT chip is thermally coupled to the main heat dissipation island, the gate inner island is located on the same surface of the FOPLP encapsulation glue layer as the second source inner island, the gate inner island is originally connected to the gate of the MOSFET chip, and the drain outer island is originally connected to the drain of the gallium nitride HEMT chip.

[0034] By adopting the above preferred technical features, the drain of the gallium nitride HEMT chip is originally connected to the drain outer island and the gate of the MOSFET chip is originally connected to the gate inner island of the FOPLP encapsulation glue layer. No other active devices are connected between the drain outer island and the drain of the gallium nitride HEMT chip, and no other active devices are connected between the gate inner island and the gate of the MOSFET chip, shortening the external connection path of the chips inside the package, eliminating the need for complex and long wire bonding lengths, and using the gate function of the MOSFET chip as the gate function of the entire gallium nitride HEMT chip integrated packaging structure.

[0035] The second main object of the present invention is achieved through the following technical solutions:

[0036] A manufacturing method of a gallium nitride HEMT chip integrated packaging structure is proposed for manufacturing the gallium nitride HEMT chip integrated packaging structure that may be combined by any of the above technical solutions. The manufacturing method includes:

[0037] Provide a heat dissipation carrier wafer;

[0038] Set the gallium nitride HEMT chip on the heat dissipation carrier wafer, so that the back surface of the gallium nitride HEMT chip is thermally coupled to the heat dissipation carrier wafer. The front surface of the gallium nitride HEMT chip is provided with a first source pad, a first gate pad and a first drain pad;

[0039] Form a first encapsulation glue layer on the heat dissipation carrier wafer in a flat die encapsulation manner to seal the gallium nitride HEMT chip. The first encapsulation glue layer has a first die encapsulation height on the gallium nitride HEMT chip. The first encapsulation glue layer is provided with a first through hole to expose the first source pad, the first gate pad and the first drain pad;

[0040] Form a fan-out circuit layer on the first encapsulation glue layer. The fan-out circuit layer includes: a first source inner island with a through hole leading to the first source pad, a gate line with a through hole leading to the first gate pad, and a drain line with a through hole leading to the first drain pad. Among them, the first source inner island is formed in a block deviating from the gallium nitride HEMT chip. One end of the drain line fans out and extends away from the gallium nitride HEMT chip. The gate line is located between the first source inner island and the drain line;

[0041] Set the MOSFET chip on the first source inner island, so that the back surface drain layer of the MOSFET chip is electrically connected to the first source pad. The front surface of the MOSFET chip is provided with a second source pad and a second gate pad;

[0042] Form a second encapsulation glue layer on the first encapsulation glue layer and the fan-out circuit layer in a flat die encapsulation manner. The second encapsulation glue layer has a second die encapsulation height on the MOSFET chip. The second encapsulation glue layer is provided with a second through hole to expose the second source pad and the second gate pad;

[0043] Form a metal island layer on the second encapsulation glue layer. The metal island layer includes: a second source inner island with a through hole for interconnecting the second source pad and the gate line, and a gate inner island with a through hole leading to the second gate pad;

[0044] Among them, the heat dissipation carrier is split into a source outer island around the main heat dissipation island and conducting to the second source inner island, a gate outer island conducting to the gate inner island, and a drain outer island conducting to the drain line at the fan-out end.

[0045] By adopting the above technical solution, using FOPLP layer-by-layer packaging, first establish the main heat dissipation path of the gallium nitride HEMT chip and perform the first layer of packaging, then establish the circuit path for interconnecting the MOSFET chip and the second layer of packaging. The fan-out line layer is on the first encapsulation adhesive layer. The fan-out line layer includes a first source inner island with a through hole conducting to the first source pad. The first source inner island is formed in a block deviating from the gallium nitride HEMT chip. When setting the MOSFET chip, the back drain layer of the MOSFET chip can be electrically connected to the first source pad of the gallium nitride HEMT chip. The metal island layer includes a second source inner island interconnected with the second source pad and the gate line through a through hole. By operating the second gate switch of the MOSFET chip, the source-drain voltage difference of the gallium nitride HEMT chip is changed, thereby realizing the synchronous turn-on and synchronous turn-off of the source and drain of the gallium nitride HEMT chip. There is no need to connect the gallium nitride HEMT chip and the MOSFET chip with an external circuit, and it has the effect of miniaturizing and integrating the heat dissipation heterogeneous chip packaging.

[0046] In a preferred example of the present invention, it can be further configured as:

[0047] In the step of setting the gallium nitride HEMT chip, the first gate pad is arranged between the first source pad and the first drain pad;

[0048] Or / and, in the step of forming the first encapsulation adhesive layer in the flat die encapsulation method, the first encapsulation adhesive layer also covers the peripheral sides of the heat dissipation carrier; in the step of opening the first through hole, the first through hole is formed by laser or other known patterning etching methods;

[0049] Or / and, in the step of forming the fan-out line layer, the first source inner island is relatively deviated from the gallium nitride HEMT chip and has a size larger than the first source pad, and the size of the first source inner island is also larger than and the contour corresponds to the back of the MOSFET chip;

[0050] Or / and, in the step of setting the MOSFET chip on the first source inner island, the drain layer is fully and substantially bonded to the first source inner island;

[0051] Alternatively / and, in the step of forming the metal island layer, the inner island of the second source electrode is relatively offset and larger in size than the inner island of the first source electrode, and the through holes of the first encapsulation adhesive layer electrically connecting the inner island of the second source electrode and the through holes of the second encapsulation adhesive layer are in direct correspondence, so as to shorten the conduction path to less than 100 μm, thereby enabling the internal resistance of the encapsulation of the gallium nitride HEMT chip integrated encapsulation structure to be controlled below 0.2 mΩ;

[0052] Alternatively / and, the manufacturing method further includes a step of encapsulating and isolating to obtain an isolated gallium nitride HEMT chip integrated encapsulation structure; through the outer island of the drain electrode, the turn-off operating voltage of the first drain pad of the gallium nitride HEMT chip is between 100 V and 600 V; by short-circuiting the first gate pad of the gallium nitride HEMT chip and the second source pad of the MOSFET chip through the inner island of the second source electrode, the turn-off and turn-on operating voltages of the first gate pad of the gallium nitride HEMT chip are both less than 0 V; through the outer island of the gate electrode, when the source and drain of the MOSFET chip are turned off, the voltage of the first source pad of the gallium nitride HEMT chip is passively raised, and the voltage of the first gate pad of the gallium nitride HEMT chip less than or equal to 0 V is not sufficient to turn on the gallium nitride HEMT chip; preferably, the turn-off operating voltage of the outer island of the gate electrode is less than or equal to 0 V, and the turn-on operating voltage of the outer island of the gate electrode is 3 V to 20 V; a Schottky diode is also reversely arranged inside the MOSFET chip.

[0053] By adopting the above preferred technical features, the corresponding technical effects of the above device features can be achieved by using the above corresponding structural features or combinations of their possible structural features.

[0054] The third main object of the present invention is achieved through the following technical solutions:

[0055] An electronic device is provided, including: a printed circuit board and a gallium nitride HEMT chip integrated encapsulation structure combined with any possible combination of the above technical solutions on the printed circuit board. In the encapsulation bottom surface of the gallium nitride HEMT chip integrated encapsulation structure, the outer island of the source electrode, the outer island of the gate electrode, and the outer island of the drain electrode located on the same surface are respectively welded to the corresponding pin positions of the printed circuit board; the back surface of the MOSFET chip is not directly thermally coupled to the gallium nitride HEMT chip under the barrier of the encapsulation adhesive layer; the horizontal electrical connection path between the drain electrode of the MOSFET chip and the source electrode of the gallium nitride HEMT chip does not exceed the projection area of the MOSFET chip on the encapsulation bottom surface.

[0056] By adopting the above technical solutions, the electronic device can transfer the heat of the gallium nitride HEMT chip more quickly, and the heat dissipation carrier is only directly thermally coupled to the gallium nitride HEMT chip, so that the MOSFET chip receives less heat from the gallium nitride HEMT chip.

[0057] In summary, the technical solution of the present invention includes at least one of the following technical effects that contribute to the prior art:

[0058] 1. The first source pad of the gallium nitride HEMT chip is connected to the drain layer of the MOSFET chip through the first source inner island on the first through hole of the first encapsulation glue layer. The second source pad of the MOSFET chip is led out to the second source inner island on the encapsulation surface through the second through hole of the second encapsulation glue layer. The connection length of each layer of through holes can be less than or equal to 50 um (the first encapsulation height of the first encapsulation glue layer ≤ 50 um, the second encapsulation height of the second encapsulation glue layer ≤ 50 um), while the traditional wire bonding connection length is 1000 um - 2000 um. Compared with the wire bonding method, the internal chip interconnection length of the encapsulation is greatly reduced, and the parasitic inductance is one order of magnitude smaller than that of the traditional encapsulation;

[0059] 2. Since the second source pad of the MOSFET chip is connected to the second source inner island on the top surface of the encapsulation through the second through hole of the second encapsulation glue layer, the metal island layer including the second source inner island can increase the heat dissipation on the top surface of the encapsulation. When soldering the heat dissipation carrier to the external printed circuit board (PCB), both the conductive and heat conduction paths are very short. When the external connection length of the second source pad of the MOSFET chip passing through the second source inner island is less than 100 um, the conductive and heat conduction effects of the integrated encapsulation structure of the gallium nitride HEMT chip can be optimized;

[0060] 3. The encapsulation internal resistance of the integrated encapsulation structure of the gallium nitride HEMT chip exemplified in this application can be reduced to less than 0.2 milliohms, while the encapsulation internal resistance of the existing GaN HEMT encapsulation structure is above 1 milliohm;

[0061] 4. The chip size area of the MOSFET chip is no longer limited by the area size of the first source pad of the gallium nitride HEMT chip, and can be larger than the first source pad of the gallium nitride HEMT chip. A MOSFET chip with better conduction performance can be integrated in the encapsulation structure, further reducing the device internal resistance of the integrated encapsulation structure of the gallium nitride HEMT chip;

[0062] 5. The DBC insulating sheet for eliminating parasitic inductance is not required in the structure. The thermal resistance of the existing DBC insulating sheet is usually one order of magnitude higher than that of the metal. The back surface of the gallium nitride HEMT chip exemplified in the present invention is adhesively bonded to the heat dissipation carrier through an adhesive to form a thermal coupling. The thermal resistance of the encapsulation junction shell can be smaller. The heat generated by the gallium nitride HEMT chip is directly conducted through the heat dissipation main island of the heat dissipation carrier to the external printed circuit board at the bottom surface of the encapsulation, and can also dissipate heat through the second source inner island on the top surface of the encapsulation. The double-sided heat dissipation performance is better;

[0063] 6. Since the back surface of the gallium nitride HEMT chip in the packaging process is directly thermally coupled with the entire heat sink carrier by welding or thermally conductive bonding, the heat generated by the gallium nitride HEMT chip is conducted to the main heat sink island of the heat sink carrier that covers more than 50% of the bottom area of the package, resulting in a low thermal resistance inside the package; the heat sink carrier can be removed or retained in the product. If there is a higher heat dissipation requirement, an external heat sink can be externally installed on the top surface of the package. The top surface of the package is made of a thermally conductive metal, and the flattened third encapsulation adhesive layer provides a horizontal installation reference, which is more convenient when installing an external heat sink.

[0064] 7. Before covering the third encapsulation adhesive layer or in products where the third encapsulation adhesive layer does not need to be formed, the second power inner island and the gate inner island can be exposed on the top surface of the package. In some cases for in-line testing after device board mounting, the source and gate on the top surface of the package can be directly contacted with test probes for testing, without the need for additional wiring. BRIEF DESCRIPTION OF THE DRAWINGS

[0065] Figure 1 A cross-sectional view showing the integrated packaging structure of the gallium nitride HEMT chip according to some preferred embodiments of the present invention;

[0066] Figure 2 A top view (A) and a bottom view (B) of the package showing the integrated packaging structure of the gallium nitride HEMT chip according to some preferred embodiments of the present invention through the surface encapsulation adhesive layer;

[0067] Figure 3 A circuit diagram showing the integrated packaging structure of the gallium nitride HEMT chip according to some preferred embodiments of the present invention;

[0068] Figure 4 A schematic diagram showing the gallium nitride HEMT chip being disposed on the heat sink carrier in the gallium nitride HEMT chip integrated packaging method according to some preferred embodiments of the present invention;

[0069] Figure 5 A schematic diagram showing the first encapsulation adhesive layer being formed on the heat sink carrier by the flat die encapsulation method in the gallium nitride HEMT chip integrated packaging method according to some preferred embodiments of the present invention;

[0070] Figure 6 A schematic diagram showing the first through hole being opened in the first encapsulation adhesive layer in the gallium nitride HEMT chip integrated packaging method according to some preferred embodiments of the present invention;

[0071] Figure 7 A schematic diagram showing the first deposited metal layer forming the fan-out circuit layer being formed on the first encapsulation adhesive layer in the gallium nitride HEMT chip integrated packaging method according to some preferred embodiments of the present invention;

[0072] Figure 8 Schematic diagram showing the formation of a fan-out circuit layer in the integrated packaging method of a gallium nitride HEMT chip according to some preferred embodiments of the present invention;

[0073] Figure 9 Cross-sectional schematic diagram showing the setting of a MOSFET chip on a first source inner island in the integrated packaging method of a gallium nitride HEMT chip according to some preferred embodiments of the present invention;

[0074] Figure 10 Schematic diagram showing the formation of a second encapsulation glue layer on a first encapsulation glue layer by a flat die encapsulation method in the integrated packaging method of a gallium nitride HEMT chip according to some preferred embodiments of the present invention;

[0075] Figure 11 Schematic diagram showing the opening of a second through hole in the second encapsulation glue layer in the integrated packaging method of a gallium nitride HEMT chip according to some preferred embodiments of the present invention;

[0076] Figure 12 Schematic diagram showing the formation of a second precipitation metal layer for forming a metal island layer on the second encapsulation glue layer in the integrated packaging method of a gallium nitride HEMT chip according to some preferred embodiments of the present invention;

[0077] Figure 13 Schematic diagram showing the etching of the second precipitation metal layer to form a metal island layer in the integrated packaging method of a gallium nitride HEMT chip according to some preferred embodiments of the present invention;

[0078] Figure 14 Cross-sectional view showing the integrated packaging structure of a gallium nitride HEMT chip according to some other preferred embodiments of the present invention.

[0079] Reference numerals: 10, heat dissipation carrier; 10A, main heat dissipation island; 11, source outer island; 12, gate outer island; 13, drain outer island; 20, gallium nitride HEMT chip; 21, first source pad; 22, first gate pad; 23, first drain pad; 30, first encapsulation glue layer; 31, first through hole; 40, fan-out circuit layer; 40A, first precipitation metal layer; 41, first source inner island; 42, gate circuit; 43, drain circuit; 50, MOSFET chip; 51, second source pad; 52, second gate pad; 53, drain layer; 54, Schottky diode; 60, second encapsulation glue layer; 61, second through hole; 62, third through hole; 70, metal island layer; 70A, second precipitation metal layer; 71, second source inner island; 72, gate inner island; 80, third encapsulation glue layer. Detailed implementation manners

[0080] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments that are part of the inventive concept of understanding the present invention, and cannot represent all embodiments, nor are they interpreted as the only embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art on the premise of understanding the inventive concept of the present invention fall within the scope of protection of the present invention.

[0081] It should be noted that if there are directional indications (such as up, down, left, right, front, back...) involved in the embodiments of the present invention, then the directional indications are only used to explain the relative positional relationship and movement conditions between components in a certain specific posture. If the specific posture changes, the directional indications will also change accordingly. For the convenience of understanding the technical solutions of the present invention, the integrated packaging structure and manufacturing method of the gallium nitride HEMT chip of the present invention will be further described and explained in detail below, but it does not constitute the scope of protection defined by the present invention.

[0082] The "heat dissipation carrier" described in the specification refers to that the heat dissipation exposure area on the corresponding packaging surface of a certain heat dissipation object is more than 60%, specifically more than 80% (as Figure 1 shown), and usually does not exceed 100% of the area of the packaging bottom surface.

[0083] The "deviation" described in the specification means that the upper and lower objects projected from the packaging top surface to the packaging bottom surface do not have the center points aligned. The "fan-out" described in the specification means that the extension of an object is fanned out in the direction away from the center point of the gallium nitride HEMT chip. The "island" described in the specification is an electrical function with a "pad" but an area larger than the pad. The shape of the island can be more irregular and variable than the pad. Usually, the island is represented as a metal cushion layer not provided on the chip surface. The "native connection" described in the specification means that the electrical connection path between two electrically connected objects in the package does not add other active devices. Specifically, it is electrically connected solely by the lines formed in the wafer-level packaging, excluding wire bonding and not including other devices provided therebetween.

[0084] The drawings shown include parts common to multiple embodiments, and the parts with differences or distinctions in the variant embodiments are described in text separately. Therefore, based on the industrial characteristics and technical essence, those skilled in the art should correctly and reasonably understand and judge whether the following described individual technical features or any combination of them can be characterized in the same embodiment, or whether multiple technically mutually exclusive technical features can only be characterized in different variant embodiments respectively.

[0085] Figure 1 A cross-sectional view of the integrated packaging structure of the gallium nitride HEMT chip showing some preferred embodiments of the present invention Figure 2Perspective top view (A) and bottom view (B) of the encapsulation top surface of the encapsulation adhesive layer showing the integrated packaging structure of the gallium nitride HEMT chip Figure 3 Circuit diagram showing the integrated packaging structure of the gallium nitride HEMT chip Figures 4 to 13 Schematic cross-sectional view of components in the encapsulation process of the integrated packaging structure of the gallium nitride HEMT chip. "S" in the figure represents the source; "G" represents the gate; "D" represents the drain. In the example, the source is the starting point of the carriers, and the drain is the ending point of the carriers.

[0086] Refer to Figure 1 、 Figure 2 And Figure 3 In some preferred embodiments of the present invention, an integrated packaging structure of a gallium nitride HEMT chip is proposed, including: a heat dissipation carrier 10 located on the bottom surface of the package, a gallium nitride HEMT chip 20, a first encapsulation adhesive layer 30, a fan-out circuit layer 40, a MOSFET chip 50, a second encapsulation adhesive layer 60, and a metal island layer 70. One of the important effects of the present invention is to increase the turn-on operating voltage of the gallium nitride HEMT chip 20 to a positive voltage not including 0V, and it is turned off at a ground or reference potential of 0V (a specific application is 0V turn-off and 5V turn-on), and the parasitic inductance in the packaging structure is significantly reduced, stably achieving the technical effect of being able to turn off the source and drain of the gallium nitride HEMT chip 20 without applying a negative voltage.

[0087] Refer to Figure 1 The gallium nitride HEMT chip 20 is disposed on the heat dissipation carrier 10, such that the back surface of the gallium nitride HEMT chip 20 is thermally coupled to the heat dissipation carrier 10. A first source pad 21, a first gate pad 22, and a first drain pad 23 are provided on the front surface of the gallium nitride HEMT chip 20. The semiconductor substrate of the gallium nitride HEMT chip 20 is gallium nitride. In the example, the first gate pad 22 may be located between the first source pad 21 and the first drain pad 23. The material of the heat dissipation carrier 10 is specifically a highly thermally conductive metal such as copper.

[0088] The first encapsulation adhesive layer 30 is formed on the heat dissipation carrier 10 to seal the gallium nitride HEMT chip 20. The first encapsulation adhesive layer 30 has a first encapsulation height on the gallium nitride HEMT chip 20, for example, ≦50um. The first encapsulation adhesive layer 30 is provided with a first through hole 31 to expose the first source pad 21, the first gate pad 22, and the first drain pad 23. Specifically, a plurality of first through holes 31 may be provided on one of the first source pad 21 or the first drain pad 23. In the example, the outer surface of the heat dissipation carrier 10 may be slightly smaller than the bottom surface of the package (the bottom surface of the package is the inner surface of the package product bonded to the printed circuit board). Figure 1In the example, the bottom surface of the package faces downward and includes the exposed surface of the heat dissipation carrier 10, as well as Figure 2 (as shown in (B)); in the example, the top surface of the package faces upward, and the first encapsulation glue layer 30 can cover the peripheral sides of the heat dissipation carrier 10, which can hold the heat dissipation carrier 10 more stably. Figure 1 In [the example], it faces upward. The first encapsulation glue layer 30 can cover the peripheral sides of the heat dissipation carrier 10, which can hold the heat dissipation carrier 10 more stably.

[0089] The fan-out circuit layer 40 is formed on the first encapsulation glue layer 30. The fan-out circuit layer 40 includes: a first source inner island 41 with a through hole leading to the first source pad 21, a gate circuit 42 with a through hole leading to the first gate pad 22, and a drain circuit 43 with a through hole leading to the first drain pad 23. Among them, the first source inner island 41 is formed in a block deviating from the gallium nitride HEMT chip 20, one end of the drain circuit 43 fans out and extends away from the gallium nitride HEMT chip 20, and the gate circuit 42 is located between the first source inner island 41 and the drain circuit 43. The fan-out circuit layer 40 is usually a circuit formed during the wafer-level packaging process. The first source inner island 41 can be equal to or slightly larger than the MOSFET chip 50. The first source inner island 41, the gate circuit 42, and the drain circuit 43 of the fan-out circuit layer 40 can be integrally filled into the first through hole 31 under the corresponding covering area of the first encapsulation glue layer 30 to electrically connect to the corresponding first source pad 21, first gate pad 22, and first drain pad 23 respectively.

[0090] The MOSFET chip 50 is disposed on the first source inner island 41, such that the back drain layer 53 of the MOSFET chip 50 is electrically connected to the first source pad 21. The front surface of the MOSFET chip 50 is provided with a second source pad 51 and a second gate pad 52. The semiconductor substrate of the MOSFET chip 50 can be silicon or other non-gallium-nitride silicon-based semiconductors, such as silicon carbide. In the example, the back drain layer 53 is located on the back surface of the chip different from the front surface of the chip where the second source pad 51 and the second gate pad 52 are located. The back drain layer 53 can completely cover the back surface of the MOSFET chip 50. The size of the first source inner island 41 can be slightly larger than the back surface of the MOSFET chip 50.

[0091] The second encapsulation glue layer 60 is formed on the first encapsulation glue layer 30 and the fan-out circuit layer 40. The second encapsulation glue layer 60 has a second encapsulation height on the MOSFET chip 50, which is ≦50um in the example. The second encapsulation glue layer 60 is provided with a second through hole 61 to expose the second source pad 51 and the second gate pad 52. The first encapsulation glue layer 30 and the second encapsulation glue layer 60 are electrically insulating materials with a low coefficient of thermal expansion, which can be of the same material or different materials with the coefficient of thermal expansion within an adaptable adjustment range.

[0092] The metal island layer 70 is formed on the second encapsulation glue layer 60. The metal island layer 70 includes: a second source inner island 71 that conducts through vias to interconnect the second source pad 51 and the gate line 42, and a gate inner island 72 that conducts through vias to the second gate pad 52. A specific arrangement of the second source inner island 71 and the gate inner island 72 can be seen in Figure 2 (A).

[0093] Among them, the heat dissipation carrier 10 is split into a source outer island 11 that is around the heat dissipation main island 10A and conducts to the second source inner island 71 (as shown in Figure 2 ), a gate outer island 12 that conducts to the gate inner island 72, and a drain outer island 13 that conducts to the drain line 43 at the fan-out end. A specific arrangement of the source outer island 11, the gate outer island 12, and the drain outer island 13 can be seen in Figure 2 (B). The third via 62 can penetrate through the second encapsulation glue layer 60 and the first encapsulation glue layer 30, so that the second source inner island 71 can be electrically conducted longitudinally to the source outer island 11.

[0094] A circuit structure of the gallium nitride HEMT chip integrated encapsulation structure can be seen in Figure 3 . As the gate outer island 12 turns on or off the MOSFET chip 50 within the positive and negative voltage operating ranges (the negative voltage operating range includes 0 V), the potential of the first source pad 21 of the gallium nitride HEMT chip 20 can also be synchronously lowered or raised to synchronously turn on or off the gallium nitride HEMT chip 20.

[0095] The basic principle of this embodiment is as follows: The second source inner island 71 is used to short-circuit the second source pad 51 of the MOSFET chip 50 to the first gate pad 22 of the gallium nitride HEMT chip 20 to serve as the source connection of the entire package structure, eliminating the need for wire bonding. Through the gate outer island 12, the second gate pad 52 of the MOSFET chip 50 can serve as the gate connection of the entire package structure, enabling the turn-off to turn-on operating voltage of the gate to be increased to a negative voltage turn-off including 0 V and a positive voltage turn-on not including 0 V (the existing gallium nitride HEMT products operate with a negative voltage turn-on and turn-off not including 0 V and a turn-on at 0 V). When the gate voltage on the bottom surface of the package is grounded or at 0 V potential, the example of the present invention still remains in the power-saving constant off state. In a practical application, it is possible to achieve that the package structure turns off the gallium nitride HEMT chip 20 at 0 V on the surface gate and turns it on at 5 V. In the FOPLP (Fan-Out Panel Level Package) package architecture, the gallium nitride HEMT chip 20 and the MOSFET chip 50 are efficiently integrated. The MOSFET chip 50 is disposed on the first source inner island 41 on the first encapsulation adhesive layer 30, enabling the back drain layer 53 of the MOSFET chip 50 to be electrically connected to the first source pad 21 of the gallium nitride HEMT chip 20, reducing parasitic inductance and eliminating the need for the size of the back drain layer 53 to match to be less than that of the first source pad 21 of the gallium nitride HEMT chip 20. The MOSFET chip 50 is relatively offset from the gallium nitride HEMT chip 20. The gallium nitride HEMT chip 20 is disposed on the heat sink carrier 10. The gallium nitride HEMT chip 20 has better external heat conductivity than the MOSFET chip 50, and the gallium nitride HEMT chip 20 and the MOSFET chip 50 are not directly thermally coupled, providing a faster external heat dissipation conduction path for the high-temperature energy of the gallium nitride HEMT chip 20 than through the MOSFET chip 50.

[0096] In a preferred example, through the drain outer island 13, the turn-off operating voltage of the first drain pad 23 of the gallium nitride HEMT chip 20 is between 100 V and 600 V; by short-circuiting the first gate pad 22 of the gallium nitride HEMT chip 20 and the second source pad 51 of the MOSFET chip 50 through the second source inner island 71, both the turn-off and turn-on operating voltages of the first gate pad 22 of the gallium nitride HEMT chip 20 are less than 0 V. When the first gate pad 22 is at 0 V, the gallium nitride HEMT chip 20 is source-drain turned on; through the gate outer island 12, when the MOSFET chip 50 is source-drain turned off at less than or equal to 0 V, the voltage of the first source pad 21 of the gallium nitride HEMT chip 20 is passively elevated, and the voltage of the first gate pad 22 of the gallium nitride HEMT chip 20 less than or equal to 0 V is still not sufficient to turn on the gallium nitride HEMT chip 20.

[0097] Therefore, the gate outer island 12 is used to make the second gate pad 52 of the MOSFET chip 50 serve as the gate connection of the entire package structure, and the second source inner island 71 is used to short-circuit the second source pad 51 of the MOSFET chip 50 to the first gate pad 22 of the GaN HEMT chip 20, which also serves as the source connection of the entire package structure, thereby changing the gate operating voltage of the GaN HEMT chip integrated package structure without the interference of parasitic inductance, and the GaN HEMT chip integrated package structure can be turned off even at ground or 0 potential. The source-drain-gate arrangement of the GaN HEMT chip 20 to the bottom surface of the package is changed, and the first drain pad 23 of the GaN HEMT chip 20 can be operated at a high voltage of 100 to 600 V. Even if the turn-off and turn-on working voltages of the first gate pad 22 of the GaN HEMT chip 20 are both less than 0 V, when the source and drain of the MOSFET chip 50 are turned off, the voltage of the first source pad 21 of the GaN HEMT chip 20 is passively raised, and the voltage of the first gate pad 22 of the GaN HEMT chip 20 ≦0 V is insufficient to turn on the GaN HEMT chip 20, thereby realizing the switching operation of the MOSFET chip 50 to synchronously turn on and off the GaN HEMT chip 20.

[0098] In a preferred example, the present invention can be further configured as follows: the off working voltage of the gate outer island 12 is ≦0V, and the on working voltage of the gate outer island 12 is 3-20V; a Schottky diode 54 is also reversely arranged in the MOSFET chip 50. By using the off working voltage of the gate outer island 12 being ≦0V, under grounding or 0 voltage, the source-drain connection of the MOSFET chip 50 is still turned off, and the gallium nitride HEMT chip 20 is also turned off synchronously; when the power switch is switched, the voltage of the second source inner island 71 is stable at a negative voltage, and the voltage change of the drain outer island 13 does not affect the voltage relatively far away from the gate outer island 12 (such as Figure 2 (B)), the gate outer island 12 can be turned on at a relatively stable voltage between 3 and 20 V with little fluctuation. The MOSFET chip 50 also has a reversely arranged Schottky diode 54 (as shown in FIG. Figure 3 As shown), it is used to eliminate the parasitic capacitance of the MOSFET chip 50 which is based on silicon.

[0099] In a preferred example, the first source inner island 41 is relatively offset from the gallium nitride HEMT chip 20 and has a size larger than that of the first source pad 21, and the size of the first source inner island 41 is also larger than and the contour corresponds to the back surface of the MOSFET chip 50, so that the drain layer 53 is substantially bonded to the first source inner island 41. In the integrated packaging structure, the first source inner island 41 on the first encapsulation adhesive layer 30 is relatively offset from the gallium nitride HEMT chip 20 and has a size larger than that of the first source pad 21, so that the MOSFET chip 50 no longer needs to be directly placed on the first source pad 21 of the gallium nitride HEMT chip 20. The MOSFET chip 50 can be larger in size than the first source pad 21 of the gallium nitride HEMT chip 20, the size of the MOSFET chip 50 is no longer limited, and there is no increase in the conduction resistance of the in-package wire bonding leads, so as to maintain the current performance passing through the MOSFET chip 50.

[0100] In a preferred example, the second source inner island 71 is relatively offset and has a size larger than that of the first source inner island 41, and the through holes of the first encapsulation adhesive layer 30 electrically connected to the second source inner island 71 and the through holes of the second encapsulation adhesive layer 60 are in direct correspondence, so as to shorten the conduction path to less than 100 μm; the in-package resistance of the gallium nitride HEMT chip integrated packaging structure is below 0.2 mΩ. By using the second source inner island 71 which is relatively offset and has a size larger than that of the first source inner island 41, and the through holes of the first encapsulation adhesive layer 30 electrically connected to the second source inner island 71 on the first gate pad 22 of the gallium nitride HEMT chip 20 and the through holes of the second encapsulation adhesive layer 60 are in direct correspondence, so as to shorten the conduction path to less than 100 μm; the in-package resistance of the gallium nitride HEMT chip integrated packaging structure can also reach below 0.2 mΩ. Therefore, the transmission path between the first gate pad 22 and the first source pad 21 on the gallium nitride HEMT chip 20 is short, and the chip and the packaging structure realize the interchange of the configuration relationship between the gate and the source, changing from the form that the source of the chip is relatively far away from the drain to the form that the gate of the package is relatively far away from the drain.

[0101] Refer to Figures 4 to 12 , the present invention also provides a manufacturing method of a gallium nitride HEMT chip integrated packaging structure for manufacturing the gallium nitride HEMT chip integrated packaging structure that may be combined with any of the above technical solutions, and the manufacturing method includes the steps shown below.

[0102] Refer to Figure 4 , provide a heat dissipation carrier 10; the heat dissipation carrier 10 can be designed as a whole piece, in a trench pattern, or formed in, for example, a lead frame without pins or a mother board with pre-cut grooves.

[0103] Refer to Figure 4, the gallium nitride HEMT chip 20 is disposed on the heat dissipation carrier 10 such that the back surface of the gallium nitride HEMT chip 20 is thermally coupled to the heat dissipation carrier 10. The front surface of the gallium nitride HEMT chip 20 is provided with a first source pad 21, a first gate pad 22 and a first drain pad 23. In a preferred example, in the step of disposing the gallium nitride HEMT chip 20, the first gate pad 22 is disposed between the first source pad 21 and the first drain pad 23.

[0104] Refer to Figure 5 and Figure 6 , a first encapsulation glue layer 30 is formed on the heat dissipation carrier 10 by a flat die encapsulation method to seal the gallium nitride HEMT chip 20. The first encapsulation glue layer 30 has a first die encapsulation height on the gallium nitride HEMT chip 20. The first encapsulation glue layer 30 is provided with a first through hole 31 to expose the first source pad 21, the first gate pad 22 and the first drain pad 23. In a preferred example, in the step of forming the first encapsulation glue layer 30 by the flat die encapsulation method, the first encapsulation glue layer 30 also covers the peripheral side edges of the heat dissipation carrier 10. In the step of forming the first through hole 31, the first through hole 31 is formed by laser or other known patterning etching methods. In this example, some of the first through holes 31 formed in the periphery of the first encapsulation glue layer 30 expose the gate outer island 12 and the drain outer island 13 of the heat dissipation carrier 10, or the predetermined formation regions of the gate outer island and the drain outer island of the heat dissipation carrier 10. Refer to Figure 7 and Figure 8 , a fan-out circuit layer 40 is formed on the first encapsulation glue layer 30. The fan-out circuit layer 40 includes: a first source inner island 41 that is conductively connected to the first source pad 21 through a through hole, a gate line 42 that is conductively connected to the first gate pad 22 through a through hole, and a drain line 43 that is conductively connected to the first drain pad 23 through a through hole. Among them, the first source inner island 41 is formed in a block that deviates from the gallium nitride HEMT chip 20. One end of the drain line 43 fans out and extends away from the gallium nitride HEMT chip 20. The gate line 42 is located between the first source inner island 41 and the drain line 43. Refer to Figure 7, the precursor layer for forming the fan-out wiring layer 40 is the first deposited metal layer 40A. The first deposited metal layer 40A includes a metal main body layer such as a metal foil pre-formed on the first encapsulation glue layer 30 before the first through-hole 31 is opened and a via-fill metal formed by metal deposition after the first through-hole 31 is opened (not shown in the figure). The metal main body layer can prevent the contamination residues formed during the formation of the first through-hole 31 from adhering to the first encapsulation glue layer 30 and has the additional function of a hard mask; the fan-out wiring layer 40 is obtained by metal etching of the first deposited metal layer 40A, and the first source inner island 41 serves as the island block for bonding the MOSFET chip 50. In a preferred example, in the step of forming the fan-out wiring layer 40, the first source inner island 41 is relatively offset from the gallium nitride HEMT chip 20 and has a size larger than that of the first source pad 21, and the size of the first source inner island 41 is also larger than and the contour corresponds to the back surface of the MOSFET chip 50. In this example, the drain line 43 can be directly connected to the drain outer island 13 of the heat sink carrier 10 or the predetermined formation area of the drain outer island of the heat sink carrier 10.

[0105] Refer to Figure 9 , the MOSFET chip 50 is disposed on the first source inner island 41, so that the back drain layer 53 of the MOSFET chip 50 is electrically connected to the first source pad 21, and a second source pad 51 and a second gate pad 52 are provided on the front surface of the MOSFET chip 50; in a preferred example, in the step of disposing the MOSFET chip 50 on the first source inner island 41, the drain layer 53 is fully and substantially bonded to the first source inner island 41.

[0106] Refer to Figure 10 And Figure 11 , a second encapsulation glue layer 60 is formed in a flat die encapsulation manner on the first encapsulation glue layer 30 and the fan-out wiring layer 40. The second encapsulation glue layer 60 has a second die encapsulation height on the MOSFET chip 50. The second encapsulation glue layer 60 is provided with a second through-hole 61 to expose the gate line 42, the second source pad 51 and the second gate pad 52. The second encapsulation glue layer 60 is further provided with a third through-hole 62, and the third through-hole 62 penetrates through the second encapsulation glue layer 60 and the first encapsulation glue layer 30 and exposes to the source outer island 11 of the heat sink carrier 10 or the area where the source outer island is to be formed, so that the subsequently formed second source inner island 71 can be longitudinally electrically connected to the source outer island 11.

[0107] Refer to Figure 12 And Figure 13, a metal island layer 70 is formed on the second encapsulation adhesive layer 60. The metal island layer 70 includes: a second source inner island 71 that conducts through holes to interconnect the second source pad 51 and the gate line 42, and a gate inner island 72 that conducts through holes to the second gate pad 52. The second source inner island 71 can occupy an area of more than 70% of the top surface of the package (as shown in Figure 2 (A)). In this example, the second source inner island 71 is also electrically connected to the source outer island 11 of the heat dissipation carrier 10 or the predetermined formation area of the source outer island of the heat dissipation carrier 10; the gate inner island 72 is also electrically connected to the gate outer island 12 of the heat dissipation carrier 10 or the predetermined formation area of the gate outer island of the heat dissipation carrier 10. In a preferred example, referring to Figure 12 , similar to the formation method of the fan-out line layer 40, the precursor layer of the metal island layer 70 is a second deposited metal layer 70A. The second deposited metal layer 70A includes a metal main body layer such as a metal foil pre-formed on the first encapsulation adhesive layer 30 before the second through hole 61 is opened, and a filling metal formed by metal precipitation after the second through hole 61 is opened (not shown in the figure). The metal main body layer can protect the pollution residues generated during the formation of the second through hole 61 from adhering to the second encapsulation adhesive layer 60 and has the additional function of a hard mask; the metal island layer 70 is obtained by metal etching of the second deposited metal layer 70A. In a preferred example, in the step of forming the metal island layer 70, the second source inner island 71 is relatively offset and larger in size than the first source inner island 41, and the through holes in the first encapsulation adhesive layer 30 that are electrically connected to the second source inner island 71 and the through holes in the second encapsulation adhesive layer 60 are in direct correspondence, so as to shorten the conduction path to less than 100 μm, and further enable the in-package resistance of the gallium nitride HEMT chip integrated encapsulation structure to be controlled below 0.2 mΩ.

[0108] After that, referring to Figure 1 , the preferred steps further include: forming a third encapsulation adhesive layer 80 on the second encapsulation adhesive layer 60 to cover the metal island layer 70. The third encapsulation adhesive layer 80 is an optional layer and can be omitted in different embodiments; the product without the third encapsulation adhesive layer 80 has the second source inner island 71 and the gate inner island 72 exposed on the top surface of the package for direct contact by test probes to perform electrical tests as the second detection points of the source and the gate on the top surface of the package.

[0109] Referring to Figure 1 and Figure 2, wherein, the heat dissipation carrier 10 is severed into a source outer island 11 around the heat dissipation main island 10A and electrically connected to the second source inner island 71, a gate outer island 12 electrically connected to the gate inner island 72, and a drain outer island 13 electrically connected to the drain line 43 at the fan-out end. The severing step of the heat dissipation carrier 10 can be implemented in the step of providing the heat dissipation carrier 10, or can be implemented after the step of forming the metal island layer 70 or after the step of forming the third encapsulation adhesive layer 80; alternatively, the severing step of the heat dissipation carrier 10 can be split into two steps. The pre-step of severing the upper half of the heat dissipation carrier 10 is implemented in the step of providing the heat dissipation carrier 10, and the post-step of severing the lower half of the heat dissipation carrier 10 is implemented after the step of forming the third encapsulation adhesive layer 80 and before the encapsulation isolation step. The severing method of the heat dissipation carrier 10 can adopt one or a combination of punching, sawing and wet etching before molding encapsulation.

[0110] In a preferred example, the manufacturing method further includes an encapsulation isolation step to obtain an isolated gallium nitride HEMT chip integrated encapsulation structure; through the drain outer island 13, the turn-off operating voltage of the first drain pad 23 of the gallium nitride HEMT chip 20 is between 100 and 600 V; by short-circuiting the first gate pad 22 of the gallium nitride HEMT chip 20 and the second source pad 51 of the MOSFET chip 50 through the second source inner island 71, the turn-off and turn-on operating voltages of the first gate pad 22 of the gallium nitride HEMT chip 20 are both less than 0 V; through the gate outer island 12, when the source and drain of the MOSFET chip 50 are closed, the voltage of the first source pad 21 of the gallium nitride HEMT chip 20 is passively raised, and the voltage of the first gate pad 22 of the gallium nitride HEMT chip 20 less than or equal to 0 V is not sufficient to turn on the gallium nitride HEMT chip 20; preferably, the turn-off operating voltage of the gate outer island 12 is less than or equal to 0 V, and the turn-on operating voltage of the gate outer island 12 is 3 to 20 V; a Schottky diode 54 is also reversely arranged in the MOSFET chip 50 (as Figure 3 shown). The above corresponding Figures 4 to 12 steps are specifically the FOPLP encapsulation process. In the example, the isolated gallium nitride HEMT chip integrated encapsulation structure can specifically have corresponding encapsulation sizes such as DFN 4*4, DFN 5*6, DFN 8*8, etc.

[0111] The basic principle of this embodiment is as follows: Using FOPLP for layer-by-layer encapsulation, first establish the main heat dissipation path of the gallium nitride HEMT chip 20 and perform the first layer of encapsulation, then establish the circuit path for interconnecting the MOSFET chip 50 and the second layer of encapsulation. The fan-out line layer 40 is on the first encapsulation glue layer 30. The fan-out line layer 40 includes a first source inner island 41 that is conductively connected to the first source pad 21 through a via. The first source inner island 41 is formed in a block that deviates from the gallium nitride HEMT chip 20. When setting the MOSFET chip 50, the back drain layer 53 of the MOSFET chip 50 can be electrically connected to the first source pad 21 of the gallium nitride HEMT chip 20. The metal island layer 70 includes a second source inner island 71 that is conductively connected to the second source pad 51 and the gate line 42 through a via. By operating the second gate switch of the MOSFET chip 50, the source-drain voltage difference of the gallium nitride HEMT chip 20 is changed, thereby realizing the synchronous turn-on and synchronous turn-off of the source and drain of the gallium nitride HEMT chip 20. It is not necessary to connect the gallium nitride HEMT chip 20 and the MOSFET chip 50 with an external circuit, and it has the effect of miniaturizing and integrating the heat dissipation heterogeneous chips.

[0112] Referring to Figure 14 , some other embodiments of the present invention also propose a gallium nitride HEMT chip integrated packaging structure, including: a heat dissipation carrier 10 capable of establishing an external heat dissipation path, a gallium nitride HEMT chip 20 disposed on the heat dissipation carrier 10, a MOSFET chip 50 encapsulated in an FOPLP (Fan-Out Panel Level Packaging) encapsulation glue layer, and an FOPLP circuit structure. The FOPLP circuit structure includes a first source inner island 41 and a second source inner island 71. The first source inner island 41 is located in the FOPLP encapsulation glue layer and connects the source of the gallium nitride HEMT chip 20 and the drain of the MOSFET chip 50 in a sandwich manner. The second source inner island 71 is located on a surface of the FOPLP encapsulation glue layer and shorts the gate of the gallium nitride HEMT chip 20 and the source of the MOSFET chip 50 in a long and short via manner. The heat dissipation carrier 10 is cut into: a source outer island that conducts to the second source inner island 71, a gate outer island 12 that conducts to the gate inner island 72, and a drain outer island 13 at the fan-out end of the drain line 43 that conducts to the FOPLP circuit structure.

[0113] The basic principle of this embodiment is as follows: The source electrode of the gallium nitride HEMT chip 20 is connected to the drain electrode of the MOSFET chip 50 by means of the sandwich connection of the first source inner island 41 in the FOPLP encapsulation glue layer, and the gate electrode of the gallium nitride HEMT chip 20 is short-circuited to the source electrode of the MOSFET chip 50 by the second source inner island 71 on the top surface of the encapsulation through the long and short through-holes, so as to realize the heterogeneous chip integrated encapsulation of the circuit structure with the gallium nitride HEMT chip 20 turned off when the gate electrode is grounded or at voltage 0V, and greatly reduce the parasitic inductance and improve the heat dissipation of the gallium nitride HEMT chip 20.

[0114] In a preferred example, the heat dissipation carrier 10 further includes a heat dissipation main island 10A, the back surface of the gallium nitride HEMT chip 20 is thermally coupled to the heat dissipation main island 10A, the gate inner island 72 is located on the same surface of the FOPLP encapsulation glue layer as the second source inner island 71, the drain outer island 13 is originally connected to the drain electrode of the gallium nitride HEMT chip 20 (specifically the first drain pad 23), and the gate inner island 72 is originally connected to the gate electrode of the MOSFET chip 50 (specifically the second gate pad 52).

[0115] By adopting the above preferred technical features, the drain outer island 13 is originally connected to the drain electrode of the gallium nitride HEMT chip 20 (specifically the first drain pad 23), the second source inner island 71 on the same surface of the FOPLP encapsulation glue layer is originally connected to the gate electrode of the gallium nitride HEMT chip 20 (corresponding to the first gate pad 22) and the source electrode of the MOSFET chip 50 (corresponding to the second source pad 51), and the gate inner island 72 is originally connected to the gate electrode of the MOSFET chip 50 (corresponding to the second gate pad 52) and the gate outer island 12. No other active devices are connected between the drain outer island 13 and the drain electrode of the gallium nitride HEMT chip 20 (specifically the first drain pad 23), and no other active devices are connected between the gate inner island 72 and the gate electrode of the MOSFET chip 50 (corresponding to the second gate pad 52), so as to shorten the external connection path of the chips inside the encapsulation, without the need for complex and long wire bonding lengths, and use the gate function of the MOSFET chip 50 as the gate function of the entire gallium nitride HEMT chip integrated encapsulation structure.

[0116] Other examples of the present invention also propose an electronic device, including: a printed circuit board and a gallium nitride HEMT chip integrated encapsulation structure combined with any of the above technical solutions as described above (example structures such as Figure 1 or Figure 14As shown, in the package bottom surface of the gallium nitride HEMT chip integrated package structure, the source outer island 11, gate outer island 12, and drain outer island 13 located on the same surface are respectively soldered to the corresponding pin positions of the printed circuit board; located at or near the package top surface of the gallium nitride HEMT chip integrated package structure, the second source inner island 71 with an enlarged area can help with heat dissipation (as Figure 2 (shown in (A)); the back surface of the MOSFET chip 50 is not directly thermally coupled to the gallium nitride HEMT chip 20 under the barrier of the encapsulation adhesive layer; the horizontal electrical connection path between the drain of the MOSFET chip 50 and the source of the gallium nitride HEMT chip 20 does not extend beyond the projection area of the MOSFET chip 50 on the package bottom surface. Therefore, the electronic device can transfer the heat of the gallium nitride HEMT chip 20 more quickly, and the heat dissipation carrier 10 is only directly thermally coupled to the gallium nitride HEMT chip 20, so that the MOSFET chip 50 receives less heat from the gallium nitride HEMT chip 20.

[0117] The embodiments of this specific implementation manner are all preferred embodiments for conveniently understanding or implementing the technical solution of the present invention, and do not limit the protection scope of the present invention accordingly. Any equivalent changes made according to the structure, shape, and principle of the present invention should be covered within the scope of the claims of the present invention.

Claims

1. A GaN HEMT chip integrated packaging structure, characterized in that, it includes: a heat dissipation carrier located at the bottom of the package; a GaN HEMT chip, disposed on the heat dissipation carrier, such that the back surface of the GaN HEMT chip is thermally coupled to the heat dissipation carrier, and a first source pad, a first gate pad, and a first drain pad are disposed on the front surface of the GaN HEMT chip; a first encapsulation glue layer, formed on the heat dissipation carrier to seal the GaN HEMT chip, the first encapsulation glue layer having a first molding height on the GaN HEMT chip, and the first encapsulation glue layer being provided with a first through hole to expose the first source pad, the first gate pad, and the first drain pad; a fan-out circuit layer, formed on the first encapsulation glue layer, the fan-out circuit layer including: a first source inner island with a through hole conducting to the first source pad, a gate circuit with a through hole conducting to the first gate pad, and a drain circuit with a through hole conducting to the first drain pad, wherein the first source inner island is formed in a block deviating from the GaN HEMT chip, one end of the drain circuit is fanned out and extended away from the GaN HEMT chip, and the gate circuit is located between the first source inner island and the drain circuit; a MOSFET chip, disposed on the first source inner island, such that the back surface drain layer of the MOSFET chip is electrically connected to the first source pad, and a second source pad and a second gate pad are disposed on the front surface of the MOSFET chip; a second encapsulation glue layer, formed on the first encapsulation glue layer and the fan-out circuit layer, the second encapsulation glue layer having a second molding height on the MOSFET chip, and the second encapsulation glue layer being provided with a second through hole to expose the second source pad and the second gate pad; a metal island layer, formed on the second encapsulation glue layer, the metal island layer including: a second source inner island with a through hole conducting to interconnect the second source pad and the gate circuit, and a gate inner island with a through hole conducting to the second gate pad; wherein, the heat dissipation carrier is cut into a source outer island surrounding the heat dissipation main island and conducting to the second source inner island, a gate outer island conducting to the gate inner island, and a drain outer island conducting to the fan-out end of the drain circuit; as the gate outer island turns on or off the MOSFET chip within the positive and negative voltage operating range, the potential of the first source pad of the GaN HEMT chip can also be synchronously lowered or raised to synchronously turn on or off the GaN HEMT chip.

2. The GaN HEMT chip integrated packaging structure according to claim 1, characterized in that, Through the drain outer island, the turn-off operating voltage of the first drain pad of the gallium nitride HEMT chip is between 100 V and 600 V; by short-circuiting the first gate pad of the gallium nitride HEMT chip and the second source pad of the MOSFET chip through the second source inner island, both the turn-off and turn-on operating voltages of the first gate pad of the gallium nitride HEMT chip are less than 0 V; through the gate outer island, when the source-drain of the MOSFET chip is turned off, the voltage of the first source pad of the gallium nitride HEMT chip is passively raised, and the voltage of the first gate pad of the gallium nitride HEMT chip that is ≤ 0 V is not sufficient to turn on the gallium nitride HEMT chip.

3. The integrated packaging structure of a gallium nitride HEMT chip according to claim 1, wherein, the turn-off operating voltage of the gate outer island is ≤ 0 V, and the turn-on operating voltage of the gate outer island is 3 V to 20 V; a Schottky diode is also reversely arranged inside the MOSFET chip.

4. The integrated packaging structure of a gallium nitride HEMT chip according to any one of claims 1-3, wherein, the first source inner island is relatively deviated from the gallium nitride HEMT chip and has a size larger than that of the first source pad, and the size of the first source inner island is also larger than and the contour corresponds to the back surface of the MOSFET chip, so that the drain layer is substantially bonded to the first source inner island.

5. The integrated packaging structure of a gallium nitride HEMT chip according to claim 4, wherein, the integrated packaging structure of the gallium nitride HEMT chip further includes a third encapsulation glue layer formed on the second encapsulation glue layer to cover the metal island layer.

6. The integrated packaging structure of a gallium nitride HEMT chip according to claim 4, wherein, the second source inner island is relatively deviated and has a size larger than that of the first source inner island, and the through holes of the first encapsulation glue layer and the second encapsulation glue layer that are electrically connected to the second source inner island are directly corresponding, so as to shorten the conduction path to less than 100 μm; the internal resistance of the package of the integrated packaging structure of the gallium nitride HEMT chip is below 0.2 milliohms.

7. An integrated packaging structure of a gallium nitride HEMT chip, comprising: A heat dissipation carrier capable of establishing an external heat dissipation path, a gallium nitride HEMT chip disposed on the heat dissipation carrier, a MOSFET chip encapsulated in an FOPLP encapsulation adhesive layer, and an FOPLP circuit structure, characterized in that the FOPLP circuit structure includes a gate inner island, a first source inner island, and a second source inner island. The first source inner island is located in the FOPLP encapsulation adhesive layer and connects the source of the gallium nitride HEMT chip and the drain of the MOSFET chip in a sandwich manner. The second source inner island and the gate inner island are located on a surface of the FOPLP encapsulation adhesive layer and short-circuit the gate of the gallium nitride HEMT chip and the source of the MOSFET chip in a long and short via manner. The heat dissipation carrier is split into: a source outer island leading to the second source inner island, a gate outer island leading to the gate inner island, and a drain outer island at the fan-out end of the drain line leading to the FOPLP circuit structure.

8. The gallium nitride HEMT chip integrated packaging structure according to claim 7, characterized in that the heat dissipation carrier further includes a main heat dissipation island, the back surface of the gallium nitride HEMT chip is thermally coupled to the main heat dissipation island, the gate inner island is located on the same surface of the FOPLP encapsulation adhesive layer as the second source inner island, the gate inner island is originally connected to the gate of the MOSFET chip, and the drain outer island is originally connected to the drain of the gallium nitride HEMT chip.

9. A manufacturing method of a gallium nitride HEMT chip integrated packaging structure, characterized in that it includes: providing a heat dissipation carrier; disposing a gallium nitride HEMT chip on the heat dissipation carrier, thermally coupling the back surface of the gallium nitride HEMT chip to the heat dissipation carrier, and a first source pad, a first gate pad, and a first drain pad are disposed on the front surface of the gallium nitride HEMT chip; forming a first encapsulation adhesive layer on the heat dissipation carrier in a flat die encapsulation manner to seal the gallium nitride HEMT chip. The first encapsulation adhesive layer has a first die encapsulation height on the gallium nitride HEMT chip, and a first through hole is opened in the first encapsulation adhesive layer to expose the first source pad, the first gate pad, and the first drain pad; forming a fan-out circuit layer on the first encapsulation adhesive layer. The fan-out circuit layer includes: a first source inner island with a through hole leading to the first source pad, a gate line with a through hole leading to the first gate pad, and a drain line with a through hole leading to the first drain pad. Among them, the first source inner island is formed in a block deviating from the gallium nitride HEMT chip, one end of the drain line extends in a fan-out manner away from the gallium nitride HEMT chip, and the gate line is located between the first source inner island and the drain line; disposing a MOSFET chip on the first source inner island, electrically connecting the back surface drain layer of the MOSFET chip to the first source pad, and a second source pad and a second gate pad are disposed on the front surface of the MOSFET chip; The second encapsulation glue layer is formed in a flat die encapsulation manner on the first encapsulation glue layer and the fan-out circuit layer. The second encapsulation glue layer has a second die encapsulation height on the MOSFET chip. The second encapsulation glue layer is provided with a second through hole to expose the second source pad and the second gate pad; A metal island layer is formed on the second encapsulation glue layer. The metal island layer includes: a second source inner island that conducts through holes to interconnect the second source pad and the gate circuit, and a gate inner island that conducts through holes to the second gate pad; Wherein, the heat dissipation carrier is cut into a source outer island around the heat dissipation main island and conducting to the second source inner island, a gate outer island conducting to the gate inner island, and a drain outer island conducting to the drain circuit at the fan-out end.

10. The manufacturing method of the gallium nitride HEMT chip integrated packaging structure according to claim 9, Characterized in that: In the step of arranging the gallium nitride HEMT chip, the first gate pad is arranged between the first source pad and the first drain pad; Or / and, in the step of forming the first encapsulation glue layer in a flat die encapsulation manner, the first encapsulation glue layer also covers the peripheral sides of the heat dissipation carrier; in the step of opening the first through hole, the first through hole is formed by a laser method; Or / and, in the step of forming the fan-out circuit layer, the first source inner island is relatively deviated from the gallium nitride HEMT chip and has a size larger than that of the first source pad, and the size of the first source inner island is also larger than and the contour corresponds to the back surface of the MOSFET chip; Or / and, in the step of arranging the MOSFET chip on the first source inner island, the drain layer is fully and substantially bonded to the first source inner island; Or / and, in the step of forming the metal island layer, the second source inner island is relatively deviated and has a size larger than that of the first source inner island, and the through holes of the first encapsulation glue layer electrically connecting the second source inner island and the through holes of the second encapsulation glue layer are directly corresponding, so as to shorten the conduction path to less than 100 um, and further enable the in-package resistance of the gallium nitride HEMT chip integrated packaging structure to be controlled below 0.2 mΩ; Or / and, the manufacturing method further includes a step of encapsulating and isolating to obtain an isolated gallium nitride HEMT chip integrated packaging structure; through the drain outer island, the turn-off working voltage of the first drain pad of the gallium nitride HEMT chip is between 100 and 600 V; by short-circuiting the first gate pad of the gallium nitride HEMT chip and the second source pad of the MOSFET chip through the second source inner island, the turn-off and turn-on working voltages of the first gate pad of the gallium nitride HEMT chip are both less than 0 V.

11. The manufacturing method of the gallium nitride HEMT chip integrated packaging structure according to claim 9, Characterized in that, Through the gate outer island, when the source and drain of the MOSFET chip are turned off, the voltage of the first source pad of the gallium nitride HEMT chip is passively raised, and the voltage of ≦0 V of the first gate pad of the gallium nitride HEMT chip is not sufficient to turn on the gallium nitride HEMT chip.

12. The manufacturing method of the gallium nitride HEMT chip integrated packaging structure according to claim 10, characterized in that, the turn-off operating voltage of the gate outer island is ≤ 0 V, and the turn-on operating voltage of the gate outer island is 3 - 20 V; a Schottky diode is also reversely arranged in the MOSFET chip.

13. An electronic device, characterized in that, comprising: a printed circuit board and a gallium nitride HEMT chip integrated packaging structure as described in any one of claims 1 - 8 joined to the printed circuit board. In the packaging bottom surface of the gallium nitride HEMT chip integrated packaging structure, the source outer island, the gate outer island, and the drain outer island located on the same surface are respectively soldered to the corresponding pin positions of the printed circuit board; the back surface of the MOSFET chip is not directly thermally coupled to the gallium nitride HEMT chip under the barrier of the encapsulation adhesive layer; the horizontal electrical connection path between the drain of the MOSFET chip and the source of the gallium nitride HEMT chip does not exceed the projection area of the MOSFET chip on the packaging bottom surface.

Images