Method for manufacturing silicon-based solar cell unit and silicon-based solar cell unit

Abstract

Provided are a method for manufacturing a silicon-based solar cell unit and a cell unit manufactured by the method, the method comprising: providing a first-type substrate; forming a first doping source layer doped with first-type doping particles on a first surface of the silicon substrate; forming a passivation dielectric layer on a second surface of the silicon substrate; forming on the surface of the passivation dielectric layer facing away from the silicon substrate: a selective carrier transport pre-layer having second-type doping particles, or a stack of an intrinsic selective carrier transport pre-layer and a second doping source layer doped with second-type doping particles; and performing a high-temperature annealing treatment to activate the first-type doping particles to form a first doping layer in the first surface of the substrate, while activating the second-type doping particles and crystallizing the selective carrier transport pre-layer to form a selective carrier transport layer. The method avoids performing two high-temperature annealing treatments on both sides of the cell, simplifies the manufacturing process of the cell, and helps reduce manufacturing costs.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a method for manufacturing a silicon-based solar cell unit and a silicon-based solar cell unit. Background Art

[0002] Human survival and development are inseparable from energy. Solar energy is one of the renewable, abundant and clean energy sources. Silicon-based solar cells are a type of semiconductor device that directly converts light energy into electrical energy. The PERC (Passivated Emitter and Rear Cell) structure has become the mainstream direction of the development of silicon-based solar cell technology today due to its high photoelectric conversion efficiency. Compared with the conventional aluminum back field cell structure, the PERC cell structure is also provided with a back passivation layer, thereby reducing minority carrier recombination. For example, a silicon-based solar cell with a PERC structure has been proposed, which places the pn junction on the back of the cell, thereby greatly reducing the absorption of light by the amorphous silicon thin film and effectively improving the photoelectric conversion efficiency of the cell. However, the manufacturing steps of such silicon-based solar cells are complicated and costly. It is hoped that silicon-based solar cells will have simplified manufacturing steps and lower manufacturing costs. Summary of the invention

[0003] According to at least one embodiment of the present disclosure, a method for manufacturing a silicon-based solar cell unit is provided, comprising: providing a first-type silicon substrate, the silicon substrate having a first surface and a second surface opposite to the first surface; forming a first doping source layer doped with first-type doping particles on the first surface of the silicon substrate; forming a passivation dielectric layer on the second surface of the silicon substrate; forming on the surface of the passivation dielectric layer facing away from the silicon substrate: a selective carrier transport prelayer having second-type doping particles, or a stack of an intrinsic selective carrier transport prelayer and a second doping source layer doped with second-type doping particles; and performing high-temperature annealing on the silicon substrate forming the first doping source layer and the selective carrier transport prelayer to activate the first-type doping particles to form a first doping layer in the first surface of the substrate, and simultaneously activate the second-type doping particles and crystallize the selective carrier transport prelayer to form a selective carrier transport layer.

[0004] In the manufacturing method according to the embodiment of the present disclosure, by simultaneously performing high temperature annealing treatments for forming the first doping layer and the selective carrier transport layer, two high temperature annealing treatments are avoided, which simplifies the manufacturing process of the silicon-based solar cell unit and helps reduce manufacturing costs.

[0005] For example, in some embodiments, the selective carrier transport prelayer having the second type of doped particles or a stack of an intrinsic selective carrier transport prelayer and a second doping source layer doped with the second type of doped particles is formed on the surface of the passivation dielectric layer facing away from the silicon substrate by physical vapor deposition; and the first doping source layer doped with the first type of doping particles is formed on the first surface of the silicon substrate by physical vapor deposition.

[0006] For example, in some embodiments, the selective carrier transport prelayer having second-type doped particles includes a first selective carrier transport prelayer doped with second-type doped particles; or the selective carrier transport prelayer having second-type doped particles includes a first selective carrier transport prelayer doped with second-type doped particles and an intrinsic second selective carrier transport prelayer.

[0007] For example, in some embodiments, the silicon substrate is single crystal silicon or polycrystalline silicon.

[0008] For example, in some embodiments, the selective carrier transport layer and the selective carrier transport pre-layer include one or more of amorphous silicon, microcrystalline silicon, and polycrystalline silicon.

[0009] For example, in some embodiments, the second doping source layer includes an oxide layer or a single element slurry.

[0010] For example, in some embodiments, the first doping source layer includes amorphous silicon, microcrystalline silicon, polycrystalline silicon, an oxide layer, or a single element slurry.

[0011] For example, in some embodiments, the method further includes: forming a first passivation layer on a surface of the first doped layer facing away from the silicon substrate; and forming a second passivation layer on a surface of the selective carrier transport layer facing away from the silicon substrate.

[0012] For example, in some embodiments, the method further includes: forming a plurality of first contact electrodes passing through the first passivation layer and ohmically contacting the first doping layer; and forming a plurality of second contact electrodes passing through the second passivation layer and ohmically contacting the selective carrier transport layer.

[0013] For example, in some embodiments, the first passivation layer includes a single layer or a stack of one or more of a silicon oxide layer, an aluminum oxide layer, a gallium oxide layer, a titanium oxide layer, a silicon oxynitride layer, an aluminum oxynitride layer, a silicon layer, and a silicon carbide layer.

[0014] For example, in some embodiments, the second passivation layer includes a single layer or a stack of one or more of a silicon oxide layer, an aluminum oxide layer, a gallium oxide layer, a titanium oxide layer, a silicon oxynitride layer, an aluminum oxynitride layer, a silicon layer, and a silicon carbide layer.

[0015] For example, in some embodiments, the passivation dielectric layer includes a single layer or a stack of one or more of a silicon oxide layer, an aluminum oxide layer, a gallium oxide layer, a titanium oxide layer, a silicon oxynitride layer, an aluminum oxynitride layer, a silicon layer, and a silicon nitride layer.

[0016] For example, in some embodiments, before forming the first doping source layer, the method further includes: forming a first oxide layer on the first surface of the substrate.

[0017] For example, in some embodiments, the first oxide layer is formed by physical vapor deposition.

[0018] For example, in some embodiments, the first type is p-type and the second type is n-type.

[0019] For example, in some embodiments, the first type is n-type and the second type is p-type.

[0020] According to at least one embodiment of the present disclosure, a silicon-based solar cell unit is provided, which is manufactured according to the method as described above, and the cell unit includes: a first type silicon substrate having a first surface and a second surface relative to each other; a first doping layer formed in the first surface and doped with first type doping particles; a passivation dielectric layer formed on the second surface; and a selective carrier transport layer formed on a surface of the passivation dielectric layer facing away from the silicon substrate and doped with second type doping particles.

[0021] For example, in some embodiments, the first doping layer is formed along the entire surface of the first surface.

[0022] For example, in some embodiments, the first doping layer includes a plurality of dispersed first doping portions, and a concentration of the first type of doping particles in the first doping portions is higher than a concentration of the first type of doping particles in the silicon substrate.

[0023] For example, in some embodiments, the battery cell further includes: a first passivation layer formed on a surface of the first doped layer facing away from the silicon substrate; and a second passivation layer formed on a surface of the selective carrier transport layer facing away from the silicon substrate.

[0024] For example, in some embodiments, the battery cell further includes: a first contact electrode passing through the first passivation layer and in ohmic contact with the first doping layer; and a second contact electrode passing through the second passivation layer and in ohmic contact with the selective carrier transport layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present disclosure and therefore should not be regarded as limiting the scope of protection. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0026] Figure 1 is a schematic flow chart of a method for manufacturing a battery cell according to a first embodiment of the present disclosure;

[0027] Figure 2A-2I They are structural schematic diagrams corresponding to different steps of the method for manufacturing a battery unit according to the first embodiment of the present disclosure;

[0028] Figure 3 is a schematic flow chart of a method for manufacturing a battery cell according to a second embodiment of the present disclosure;

[0029] Figures 4A-4E They are structural schematic diagrams corresponding to different steps of the method for manufacturing a battery unit according to the second embodiment of the present disclosure;

[0030] Figure 5 is a schematic flow chart of a method for manufacturing a battery cell according to a third embodiment of the present disclosure;

[0031] Figure 6 is a schematic flow chart of a method for manufacturing a battery cell according to a fourth embodiment of the present disclosure;

[0032] Figure 7 is a schematic flow chart of a method for manufacturing a battery cell according to a fifth embodiment of the present disclosure;

[0033] Figure 8 is a schematic flow chart of a method for manufacturing a battery cell according to a sixth embodiment of the present disclosure;

[0034] Fig. 9 A schematic diagram of a structure after a first oxide layer and a first doping source layer are formed on a first surface of a silicon substrate, and a passivation dielectric layer, a second selective carrier transport pre-layer and a second doping source layer are formed on a second surface of the silicon substrate according to a sixth embodiment of the present disclosure;

[0035] Fig.10 is a schematic flow chart of a method for manufacturing a battery cell according to a seventh embodiment of the present disclosure;

[0036] Figures 11A-11H They are structural schematic diagrams of different steps of a method for manufacturing a battery unit according to a seventh embodiment of the present disclosure;

[0037] Fig.12is a schematic flow chart of a method for manufacturing a battery cell according to an eighth embodiment of the present disclosure;

[0038] Fig.13 is a schematic structural diagram of a battery unit manufactured using a manufacturing method according to an eighth embodiment of the present disclosure. DETAILED DESCRIPTION

[0039] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0040] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The words "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. The words "include" or "comprise" and the like mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0041] In this document, the front side and light-receiving side of the battery cell shown as the upper side of the battery cell in the drawings are used interchangeably, and the back side or backlight side of the battery cell shown as the lower side of the battery cell in the drawings are used interchangeably. In this document, "intrinsic" means not doped with doping particles.

[0042] Overview

[0043] A silicon-based solar cell unit comprises: a first-type silicon substrate having a first surface and a second surface relative to each other, a first doped layer formed in the first surface and doped with first-type doped particles, a passivation dielectric layer formed on the second surface, a selective carrier transport layer formed on the surface of the passivation dielectric layer facing away from the silicon substrate and doped with second-type doped particles, a first passivation layer formed on the surface of the first doped layer facing away from the silicon substrate, a second passivation layer formed on the surface of the selective carrier transport layer facing away from the silicon substrate, a first contact electrode passing through the first passivation layer and in ohmic contact with the first doped layer, and a second contact electrode passing through the second passivation layer and in ohmic contact with the selective carrier transport layer.

[0044] The first surface of the silicon substrate may be doped in the whole or in part. That is, the first doped layer may be formed along the entire surface of the first surface of the silicon substrate. Alternatively, the first doped layer may include a plurality of first doped portions arranged in a dispersed manner, wherein the concentration of the first type of doped particles in the first doped portions is higher than the concentration of the first type of doped particles in the silicon substrate.

[0045] The manufacturing method of the battery cell according to the embodiment of the present disclosure can be used to manufacture the above-mentioned battery cell. The method includes: providing a first type of silicon substrate, the silicon substrate having a first surface and a second surface opposite to the first surface; forming a first doping source layer doped with first type doping particles on the first surface of the silicon substrate; forming a passivation dielectric layer on the second surface of the silicon substrate; forming on the surface of the passivation dielectric layer facing away from the silicon substrate: a selective carrier transport pre-layer with second type doping particles, or a stack of an intrinsic selective carrier transport pre-layer and a second doping source layer doped with second type doping particles; and performing high temperature annealing on the silicon substrate forming the first doping source layer and the selective carrier transport pre-layer, activating the first type of doping particles to form a first doping layer in the first surface of the substrate, and activating the second type of doping particles and crystallizing the selective carrier transport pre-layer to form a selective carrier transport layer.

[0046] In the manufacturing method according to the embodiment of the present disclosure, high temperature annealing processes for forming the first doping layer and the selective carrier transport layer are performed simultaneously, thereby avoiding performing two high temperature annealing processes, which simplifies the manufacturing process of the battery cell.

[0047] In addition, in the steps of forming layers such as the first doping source layer and the selective carrier transport pre-layer, the problem of plating bypass may occur, that is, not only the target structural layer is formed on the target surface, but also the structural layer is formed on other unwanted surfaces, which requires additional steps to remove the unwanted structural layer.

[0048] In the manufacturing method according to some embodiments of the present disclosure, a selective carrier transport pre-layer having a second type of doped particles or a stack of an intrinsic selective carrier transport pre-layer and a second doping source layer doped with the second type of doped particles is formed on the surface of the passivation dielectric layer facing away from the silicon substrate by physical vapor deposition. In addition, a first doping source layer doped with the first type of doped particles is formed on the first surface of the silicon substrate by physical vapor deposition. This method only deposits on a single surface, and therefore, the generation of the problem of plating around can be avoided. In addition, the above-mentioned physical vapor deposition step can be allowed to be performed in the same device, avoiding the tool, manpower and time costs of transferring and transporting the parts to be processed during the manufacturing process.

[0049] The above and other aspects of the present disclosure will be described below by way of examples.

[0050] It should be noted that in this specification, the steps in the method do not have to be performed in the above order, and may also be performed in other orders, at least one step may be omitted, or at least one additional step may be added, and the present disclosure is not limited thereto. Without departing from the scope of the claims of the present disclosure, those skilled in the art may combine or modify the steps, features, processes, and parameters in the embodiments given herein to obtain other embodiments.

[0051] First embodiment

[0052] Figure 1 is a schematic flow chart of a method for manufacturing a battery cell according to a first embodiment of the present disclosure. Figure 2A-2I They are schematic diagrams of structures corresponding to different steps of the method for manufacturing a battery cell according to the first embodiment, wherein Fig.2I A schematic structural diagram of a battery unit manufactured using the manufacturing method is shown.

[0053] like Fig.2I As shown, the battery cell manufactured by the manufacturing method includes a first-type silicon substrate 111, a first doping layer 116 doped with first-type doping particles on the first surface of the silicon substrate 111, a first passivation layer 117 and a plurality of first contact electrodes 1191 on the first doping layer 116, a passivation dielectric layer 112 on the second surface of the silicon substrate 111, a selective carrier transport layer 113 doped with second-type doping particles on the passivation dielectric layer 112, and a second passivation layer 118 and a plurality of second contact electrodes 1192 on the selective carrier transport layer 113. The first doping layer 116 substantially completely (or in other words, the entire surface) covers the first surface of the silicon substrate 111. The first surface of the silicon substrate 111 may face the front side of the battery cell, and the second surface of the silicon substrate 111 may face the back side of the battery cell.

[0054] The passivation dielectric layer 112 and the selective carrier transport layer 113 constitute a passivation contact structure. Due to the different types of doping particles in the selective carrier transport layer 113 and the silicon substrate 111, the emitter is formed on the back of the battery cell. The passivation structure reduces metal contact recombination. The selective carrier transport layer 113 can selectively transport carriers, which helps to reduce back recombination and achieve high opening voltage performance. Compared with a battery cell in which a local passivation structure is formed, the structure of the battery cell can have a simplified manufacturing process. In addition, since the passivation contact structure is placed on the back of the battery cell, there is no problem of the passivation contact structure (such as the selective carrier transport layer 113 in the passivation contact structure) being arranged on the light-receiving surface to affect light absorption.

[0055] Specifically, in the present embodiment, the first type of silicon substrate 111 may be a p-type single crystal silicon substrate, but the present disclosure is not limited thereto. For example, the first type of silicon substrate 111 may also be an n-type substrate. For example, the first type of silicon substrate 111 may also be a polycrystalline silicon substrate. For example, the resistivity of the silicon substrate 111 may be in the range of 0.1-10Ω·cm, such as 1Ω·cm, 2Ω·cm, 3Ω·cm, etc. The thickness of the silicon substrate 111 may be in the range of 80-300μm.

[0056] In the following embodiments, the technical solution of the present disclosure is described by taking the case where the first type is p-type and the second type is n-type as an example, but the present disclosure is not limited thereto. The p-type first type may be replaced by n-type, and the n-type second type may be replaced by p-type. In this case, for example, instead of boron, the first type of doping particles may be phosphorus, and instead of phosphorus, the second type of doping particles may be boron.

[0057] In the case where the silicon substrate 111 is a p-type substrate, the cost of the silicon substrate 111 will be reduced, thereby reducing the cost of the battery unit.

[0058] When the silicon substrate 111 is an n-type substrate, the substrate life of the silicon substrate 111 is high, which is beneficial to improving the life of the battery unit.

[0059] In this embodiment, the first doping layer 116 doped with the first type of doping particles can be obtained by doping boron (B) into the silicon substrate 111, but is not limited thereto. The first doping layer 116 can also be doped with other Group III element particles. Alternatively, when the silicon substrate 111 is an n-type substrate, the first doping layer 116 can be doped with Group V element particles such as phosphorus (P).

[0060] In this embodiment, the passivation dielectric layer 112 is a silicon dioxide (SiO2) layer, but the present disclosure is not limited thereto. The passivation dielectric layer 112 may include silicon oxide (SiO x ) layer, silicon oxynitride (SiO x N 1-x ) layer, aluminum oxide (AlO x ) layer, titanium oxide (TiO x ) layer and gallium oxide (GaOx) layer, silicon carbide (SiC x ) layer, aluminum oxynitride layer or a single layer or a stacked layer of one or more of the above. For example, the thickness of the passivation dielectric layer 112 can be in the range of 0.1-10 nm, such as 0.1-5 nm, 0.5-2 nm, 1.5 nm, 1.8 nm, etc.

[0061] In the present embodiment, the selective carrier transport layer 113 doped with the second type of doped particles is a phosphorus (P) doped amorphous silicon thin film layer, but the present disclosure is not limited thereto. For example, the selective carrier transport layer 113 may include one or more of microcrystalline silicon, amorphous silicon and polycrystalline silicon. For example, the thickness of the selective carrier transport layer 113 is in the range of 1-300nm, such as 10-300nm, 10-100nm, 30-100nm, 50-100nm, 70nm, etc. For example, the selective carrier transport layer 113 may be doped with other Group V element particles. Alternatively, in the case where the silicon substrate 111 is an n-type silicon substrate 111, the selective carrier transport layer 113 is doped with Group III element particles such as phosphorus.

[0062] In the present embodiment, the first passivation layer 117 is a stack of an aluminum oxide (Al2O3) layer and a silicon nitride layer, but the present disclosure is not limited thereto. The first passivation layer 117 may include silicon oxide (SiO x ) layer, silicon oxynitride (SiO x N 1-x ) layer, aluminum oxide (AlO x ) layer, titanium oxide (TiO x ) layer and gallium oxide (GaOx) layer, silicon carbide layer, aluminum oxynitride layer, silicon layer (polycrystalline silicon or amorphous silicon or microcrystalline silicon) one or more single layer or stacked layer. For example, the thickness of the first passivation layer 117 can be 1-300nm, such as 10-300nm, 10-100nm, 30-100nm, 50-100nm, 70nm, etc. For example, the first passivation layer 117 can be designed to play an anti-reflection effect. When the material of each layer in the multilayer stack is different, the passivation effect and anti-reflection effect of each layer are different. Through multi-layer coordination, the first passivation layer 117 can be given a good passivation effect and anti-reflection effect.

[0063] Similar to the first passivation layer 117, the second passivation layer 118 includes a stack of an aluminum oxide (Al2O3) layer and a silicon nitride layer, but the present disclosure is not limited thereto. The second passivation layer 118 may be a silicon oxide (SiO x ) layer, silicon oxynitride (SiO x N 1-x ) layer, aluminum oxide (AlO x ) layer, titanium oxide (TiO x) layer and a single layer or stack of one or more of gallium oxide (GaOx), silicon carbide layer, aluminum oxynitride layer, silicon layer (polycrystalline silicon layer, amorphous silicon layer or microcrystalline silicon layer). For example, the thickness of the second passivation layer 118 can be 1-300nm, such as 10-300nm, 10-100nm, 30-100nm, 50-100nm, 70nm, etc. When the material of each layer in the multilayer stack is different, the passivation effect and anti-reflection effect of each layer are different. Through the multilayer coordination, the second passivation layer 118 can be given a good passivation effect and anti-reflection effect.

[0064] like Figure 1 and Figure 2A-2I As shown, in this embodiment, the method for manufacturing the silicon-based solar cell unit may include:

[0065] Step S11, providing a first type of silicon substrate 111 and performing surface treatment on the first surface and the second surface of the silicon substrate 111, such as Figure 2A As shown. Specifically, a p-type single crystal silicon substrate 111 is provided and the first surface and the second surface thereof are surface treated, and the resistivity of the silicon substrate 111 is 2Ω·cm. For example, the surface treatment includes using a sodium hydroxide (NaOH) or potassium hydroxide (KOH) solution to perform surface texturing on the first surface and the second surface of the silicon substrate 111 in a texturing tank to form a velvet structure including a plurality of pyramid-shaped substructures, and rounding the pyramid-shaped substructures with a mixed solution of nitric acid (HNO3) and hydrofluoric acid (HF), and polishing the second surface with a tetramethylammonium hydroxide (TMAH) solution. In other embodiments, for example, a mixed solution of ozone (O3) and HF may be used to round the pyramids of the velvet; for example, a mixed solution of HNO3 and HF, or a NaOH solution, or a KOH solution may be used to wet etch or polish the second surface.

[0066] Step S12, forming a passivation dielectric layer 112 on the second surface of the silicon substrate 111, such as Figure 2BAs shown. Specifically, a 1.8 nm silicon dioxide passivation dielectric layer 112 is formed on the back of the silicon substrate 111 by plasma enhanced chemical vapor deposition (PECVD). In addition, for example, the passivation dielectric layer 112 can be formed by a low-temperature furnace tube oxidation process, a nitric acid oxidation process, an ozone oxidation process, an atomic layer deposition (ALD) process (for example, including plasma enhanced atomic layer deposition (PEALD), etc.), a chemical vapor deposition (CVD) process (for example, including PECVD, low pressure chemical vapor deposition (LPCVD), atmospheric pressure chemical vapor deposition (APCVD), etc.), a physical vapor deposition (PVD) process (such as sputtering or evaporation), a rapid plasma deposition (RPD) process, etc.

[0067] Step S13, forming a first selective carrier transport pre-layer containing second type doping particles on the passivation dielectric layer. For example, by PVD, the first selective carrier transport pre-layer 113' is formed on the surface of the passivation dielectric layer 112 facing away from the silicon substrate 111. Figure 2C As shown. Specifically, a 70nm layer of phosphorus-doped amorphous silicon first selective carrier transport prelayer 113' is formed on the passivation dielectric layer 112. In the present embodiment, the first selective carrier transport prelayer 113' is in-situ doped, that is, it is a selective carrier transport prelayer that has been doped with second-type doping particles. The first selective carrier transport prelayer 113' has not undergone crystallization heat treatment, and the doped particles are not fully activated. In this article, "selective carrier transport prelayer" is used to distinguish it from a selective carrier transport layer that has undergone crystallization heat treatment. In other embodiments, the first selective carrier transport prelayer 113' may also be microcrystalline silicon or polycrystalline silicon.

[0068] Step S14, forming a first oxide layer on the first surface of the silicon substrate. For example, the first oxide layer 114 is formed on the first surface of the silicon substrate 111 by PVD. Specifically, the first oxide layer 114 of silicon dioxide with a thickness of 10 nm is formed on the first surface.

[0069] Step S15, forming a first doping source layer containing first-type doping particles on the first oxide layer. For example, by PVD, a first doping source layer 1151 doped with first-type doping particles is formed on the surface of the first oxide layer 114 facing away from the silicon substrate 111. Figure 2E As shown. Specifically, a first doping source layer 1151 of boron-doped amorphous silicon with a thickness of 40 nm is formed on the first oxide layer 114. In addition, the first doping source layer 1151 may also be a microcrystalline silicon layer or an amorphous silicon layer or a stack of the two. For example, the first doping source layer 1151 may also be doped with other Group III element particles. For example, the thickness of the first doping source layer 1151 may be in the range of 10-100 nm.

[0070] Step S16, performing a high temperature annealing treatment on the intermediate semiconductor structure formed in step S15 so as to activate the first type of doping particles in the first doping source layer 1151 to form a first doping layer 116 in the first surface of the silicon substrate 111, and simultaneously activate the second type of doping particles in the first selective carrier transport pre-layer 113' and crystallize the first selective carrier transport pre-layer 113' to form a selective carrier transport layer 113, such as Figure 2F In addition, during the high temperature annealing process, a second oxide layer 1152 is formed on the first doping source layer 1151, and a third oxide layer 1131 is formed on the selective carrier transport layer 113. For example, the high temperature annealing process includes performing a high temperature heat treatment on the intermediate semiconductor structure at 950° C. in an annealing furnace.

[0071] Step S17, removing the first oxide layer 114, the second oxide layer 1152, the third oxide layer 1131 and the first doping source layer 1151 located on the first oxide layer 114, as shown in FIG. Figure 2G Specifically, for example, the second oxide layer 1152 generated by the high temperature annealing process is first cleaned with an HF solution, and then the first doping source layer 1151 is cleaned with a KOH solution, or a NaOH solution, or a TMAH solution, or a mixed solution of an HNO3 solution and an HF solution, and finally the first oxide layer 114 and the third oxide layer 1131 generated by the high temperature annealing process are cleaned with an HF solution.

[0072] Step S18, forming a first passivation layer 117 and a second passivation layer 118 on the surface of the first doping layer 116 facing away from the silicon substrate 111 and on the surface of the selective carrier transport layer 113 facing away from the silicon substrate 111, respectively. Figure 2HAs shown. Specifically, the first passivation layer 117 and the second passivation layer 118 are formed on the surface of the first doping layer 116 and the selective carrier transport layer 113 respectively by tubular PECVD. Alternatively, for example, alternatively or additionally, the first passivation layer 117 and the second passivation layer 118 can be formed by ALD, PEALD, etc. For example, the first passivation layer 117 can be a stack of a silicon oxide layer and a silicon nitride layer. For example, the second passivation layer 118 can be a stack of a silicon oxide layer and a silicon nitride layer.

[0073] Step S19, forming a first contact electrode 1191 and a second contact electrode 1192, such as Fig.2I As shown. Specifically, metal contact paste such as aluminum paste and silver paste is printed on the surface of the first passivation layer 117 and the second passivation layer 118 by screen printing, and then the solidified first contact electrode 1191 and the second contact electrode 1192 are obtained by sintering. The first contact electrode 1191 penetrates the first passivation layer 117 and ohmically contacts the first doping layer 116, and the second contact electrode 1192 penetrates the second passivation layer 118 and ohmically contacts the selective carrier transport layer 113. Alternatively, the first contact electrode 1191 and the second contact electrode 1192 may also be formed by electroplating or the like.

[0074] In this embodiment, a high temperature annealing step (step S16) is used to simultaneously heat treat the front and back sides of the intermediate semiconductor structure, that is, on the front side, the first type of doping particles are activated to form the first doping layer 116; on the back side, the second type of doping particles are activated and the first selective carrier transport pre-layer 113' is crystallized to form the selective carrier transport layer 113. The manufacturing steps are simplified, the manufacturing cost is saved, and it is suitable for large-scale production.

[0075] In addition, in this embodiment, a PVD process is used to form the first selective carrier transport pre-layer 113', the first oxide layer 114 and the first doping source layer 1151. Compared with processes such as CVD, the PVD process can form a single-sided film layer only on the target surface, and will not form a film layer on the surface opposite to the target surface or the side surface, that is, avoid wrap-around plating. In this way, there is no need to perform additional manufacturing steps for removing the undesirable film layer generated by wrap-around plating, thereby improving production efficiency.

[0076] In addition, in this embodiment, since the first selective carrier transport pre-layer 113', the first oxide layer 114 and the first doping source layer 1151 are all formed by adopting a PVD process, by performing the steps of forming the first selective carrier transport pre-layer 113', the first oxide layer 114 and the first doping source layer 1151 in consecutive steps (for example, in the third embodiment), the first selective carrier transport pre-layer 113', the first oxide layer 114 and the first doping source layer 1151 can be formed in the same PVD equipment, which further simplifies the manufacturing steps and improves production efficiency.

[0077] Finally, in this embodiment, before forming the first doping source layer 1151, a first oxide layer 114 is formed on the first surface of the silicon substrate 111. The first oxide layer 114 helps to more accurately control the doping of the first type of doping particles on the silicon substrate 111, thereby more accurately controlling the formation of the first doping layer 116.

[0078] As described above, the steps in the method do not have to be performed in the above order, and may be performed in other orders, at least one step may be omitted, or at least one additional step may be added. For example, the following is a method for manufacturing a battery cell according to other embodiments of the present disclosure.

[0079] Second embodiment

[0080] Figure 3 is a schematic flow chart of a method for manufacturing a battery cell according to a second embodiment of the present disclosure. Figures 4A-4E They are schematic structural diagrams corresponding to different steps of the method for manufacturing a battery unit according to the second embodiment.

[0081] The structure of the battery cell manufactured by the manufacturing method according to the second embodiment is similar to that of the battery cell manufactured by the manufacturing method according to the second embodiment. Fig.2I The structures of the battery cells manufactured by the manufacturing method according to the first embodiment are basically the same and will not be described in detail herein.

[0082] The manufacturing method according to the second embodiment is different from the manufacturing method according to the first embodiment in that the intermediate semiconductor structure is different and is formed through steps S21 - S25 .

[0083] The manufacturing method according to the second embodiment of the present disclosure includes:

[0084] Step S21, providing a first type of silicon substrate 111 and performing surface treatment on the first surface and the second surface of the silicon substrate 111, such as Figure 4A Specifically, a p-type single crystal silicon substrate 111 is provided and surface treated, and the resistivity of the silicon substrate 111 is 1Ω·cm.

[0085] Step S22, forming a first oxide layer 114 on the first surface of the silicon substrate 111, such as Figure 4B Specifically, a first oxide layer 114 with a thickness of 1.5 nm is formed on the first surface by using a PVD process.

[0086] Step S23, forming a first doping source layer 1151 doped with first-type doping particles on the surface of the first oxide layer 114 facing away from the silicon substrate 111, such as Figure 4C Specifically, a first doping source layer 1151 of phosphorus-doped amorphous silicon with a thickness of 50 nm is formed on the first oxide layer 114 .

[0087] Step S24, forming a passivation dielectric layer 112 on the second surface of the silicon substrate 111, such as Figure 4D Specifically, a passivation dielectric layer 112 of aluminum oxide with a thickness of 1.5 nm is formed on the back of the silicon substrate 111 by ALD.

[0088] Step S25, forming a stack of a first selective carrier transport pre-layer containing second-type doped particles and an intrinsic second selective carrier transport pre-layer on the passivation dielectric layer. For example, a stack of a first selective carrier transport pre-layer 113' doped with second-type doped particles and an intrinsic second selective carrier transport pre-layer 113" is formed on the surface of the passivation dielectric layer 112 facing away from the silicon substrate 111 by PVD to serve as a selective carrier transport pre-layer, such as Figure 4E As shown. The difference between the first selective carrier transport prelayer 113' and the second selective carrier transport prelayer 113" is that the former is doped with second type doped particles, while the latter is intrinsic. Specifically, the first selective carrier transport prelayer 113' is an amorphous silicon thin film layer doped with phosphorus with a thickness of 40nm, and the second selective carrier transport prelayer 113" is an undoped amorphous silicon thin film layer with a thickness of 30nm. In other embodiments, the first selective carrier transport prelayer 113' and the second selective carrier transport prelayer 113" can be a microcrystalline silicon layer or an amorphous silicon layer or a stack of the two.

[0089] Different from the single-layer first selective carrier transport prelayer 113' in-situ doped with the second type of doping particles in the first embodiment, in the second embodiment, the intermediate semiconductor structure includes a stack of a first selective carrier transport prelayer 113' doped with the second type of doping particles and an intrinsic second selective carrier transport prelayer 113". The first selective carrier transport layer 113' is used as a second doping source layer, which provides doping particles for forming the selective carrier transport layer 113 and is crystallized to form a part of the selective carrier transport layer 113 in a subsequent high-temperature annealing treatment. The second selective carrier transport prelayer 113" receives the second type of doping particles from the first selective carrier transport layer 113' in a subsequent high-temperature annealing treatment and is also crystallized to form a part of the selective carrier transport layer 113.

[0090] The advantage of forming a single layer of the first selective carrier transport pre-layer 113 ′ in-situ doped with the second type of doping particles in the first embodiment is that only one step is required, and the operation is simpler.

[0091] The advantage of forming a stack of the first selective carrier transport prelayer 113' and the intrinsic second selective carrier transport prelayer 113" in the second embodiment is that the production efficiency is improved, because it takes a longer time to form the in-situ doped first selective carrier transport prelayer 113', and here the intrinsic second selective carrier transport prelayer 113" replaces a portion of the in-situ doped first selective carrier transport prelayer 113'.

[0092] In other embodiments, the positions of the first selective carrier transport pre-layer 113 ′ and the second selective carrier transport pre-layer 113 ″ may be interchanged.

[0093] In addition, the manufacturing method according to the second embodiment further includes the following steps which are the same as or similar to those of the manufacturing method of the first embodiment:

[0094] Step S26, performing high temperature annealing treatment on the intermediate semiconductor structure formed in step S25 so as to activate the first type of doped particles in the first doping source layer 1151 to form a first doped layer 116 in the first surface of the silicon substrate 111, and simultaneously activate the second type of doped particles in the first selective carrier transport pre-layer 113' and crystallize the first selective carrier transport pre-layer 113' and the second selective carrier transport pre-layer 113" to form a doped selective carrier transport layer 113. In addition, during the high temperature annealing treatment, a second oxide layer 1152 is formed on the first doping source layer 1151, and a third oxide layer 1131 is formed on the selective carrier transport layer 113.

[0095] In step S27 , the first oxide layer 114 , the second oxide layer 1152 , the third oxide layer 1131 and the first doping source layer 1151 on the first oxide layer 114 are removed.

[0096] Step S28, forming a first passivation layer 117 and a second passivation layer 118 on the surface of the first doping layer 116 facing away from the silicon substrate 111 and the surface of the selective carrier transport layer 113 facing away from the silicon substrate 111, respectively. Specifically, the first passivation layer 117 may be a stack of an aluminum oxide layer and a silicon nitride layer. Specifically, the second passivation layer 118 may be a stack of an aluminum oxide layer and a silicon nitride layer.

[0097] Step S29, forming a first contact electrode 1191 and a second contact electrode 1192, such as Fig.2I shown.

[0098] For the remaining descriptions of the manufacturing methods according to the second embodiment and the following third to eighth embodiments, reference may be made to the corresponding descriptions of the first embodiment.

[0099] Third embodiment

[0100] Figure 5 is a schematic flow chart of a method for manufacturing a battery cell according to a third embodiment of the present disclosure.

[0101] The manufacturing method according to the third embodiment is different from the manufacturing method according to the first embodiment in that an intermediate semiconductor structure is formed through steps S31 - S34 .

[0102] A manufacturing method according to a third embodiment of the present disclosure includes:

[0103] Step S31, providing a first type silicon substrate 111 and performing surface treatment on the first surface and the second surface of the silicon substrate 111. Specifically, providing a p-type single crystal silicon substrate 111 and performing surface treatment on the silicon substrate 111, the resistivity of the silicon substrate 111 is 3Ω·cm.

[0104] Step S32, using a furnace tube oxidation process to simultaneously form a first oxide layer 114 and a passivation dielectric layer 112 on the first surface and the second surface of the silicon substrate 111. Specifically, the thickness of the first oxide layer is 1.2 nm. Specifically, the thickness of the passivation dielectric layer is 1.2 nm.

[0105] Step S33, forming a stack of a first selective carrier transport prelayer containing second-type doped particles and an intrinsic second selective carrier transport prelayer on the passivation dielectric layer. A stack of a first selective carrier transport prelayer 113' doped with second-type doped particles and an intrinsic second selective carrier transport prelayer 113" is formed on the surface of the passivation dielectric layer 112 facing away from the silicon substrate 111 by PVD. Specifically, the thicknesses of the first selective carrier transport prelayer 113' and the second selective carrier transport prelayer 113" are 40nm and 30nm, respectively.

[0106] Step S34, forming a first doping source layer containing first-type doping particles on the first oxide layer. For example, a first doping source layer 1151 doped with first-type doping particles is formed on the surface of the first oxide layer 114 facing away from the silicon substrate 111 by PVD. Specifically, the first doping source layer 1151 is a boron-containing amorphous silicon layer with a thickness of 30 nm.

[0107] In this embodiment, in step S32 , a first oxide layer 114 and a passivation dielectric layer 112 are respectively formed simultaneously on the front side and the back side of the silicon substrate 111 through a one-step oxidation process.

[0108] In addition, since step S33 is adjacent to step S34, the stack of the first selective carrier transport pre-layer 113 ″ and the intrinsic second selective carrier transport pre-layer 113 ″ and the first doping source layer 1151 can be deposited in the same PVD equipment.

[0109] In addition, the manufacturing method according to the third embodiment further includes the following steps which are the same as or similar to those of the manufacturing method of the first embodiment:

[0110] Step S35, performing high temperature annealing treatment on the intermediate semiconductor structure formed in step S34 so as to activate the first type of doped particles in the first doping source layer 1151 to form a first doped layer 116 in the first surface of the silicon substrate 111, and activate the second type of doped particles in the first selective carrier transport pre-layer 113' and crystallize the first selective carrier transport pre-layer 113' and the second selective carrier transport pre-layer 113" to form a doped selective carrier transport layer 113. In addition, during the high temperature annealing treatment, a second oxide layer 1152 is formed on the first doping source layer 1151, and a third oxide layer 1131 is formed on the selective carrier transport layer 113.

[0111] In step S36 , the first oxide layer 114 , the second oxide layer 1152 , the third oxide layer 1131 and the first doping source layer 1151 on the first oxide layer 114 are removed.

[0112] Step S37, forming a first passivation layer 117 and a second passivation layer 118 on the surface of the first doping layer 116 facing away from the silicon substrate 111 and the surface of the selective carrier transport layer 113 facing away from the silicon substrate 111, respectively. Specifically, the first passivation layer 117 may be a stack of an aluminum oxide layer and a silicon nitride layer. Specifically, the second passivation layer 118 may be a stack of an aluminum oxide layer and a silicon nitride layer.

[0113] In step S38 , a first contact electrode 1191 and a second contact electrode 1192 are formed.

[0114] In the first to third embodiments described above, the first doping source layer 1151 providing the first type of doping particles for the first doping layer 116 is obtained by direct deposition, and the first doping source layer 1151 may be a microcrystalline silicon layer, an amorphous silicon layer, or a stack of the two. The first doping source layer 1151 may be provided in other ways and may be made of other materials, as long as the first doping source layer 1151 can provide doping particles for forming the first doping layer 116 in the first surface of the silicon substrate 111.

[0115] For example, instead of step S14 and step S15, step S22 and step S23, the first doping source layer 1151 can be formed in the first surface of the silicon substrate 111 by plasma implantation, or a slurry containing the first type of doping particles (for example, boron slurry) can be printed on the first surface of the silicon substrate 111 as the first doping source layer, or an oxide layer containing the first type of doping particles can be formed on the first surface of the silicon substrate 111 by CVD or PVD as the first doping source layer.

[0116] In the above-mentioned second embodiment and third embodiment, a stack of an intrinsic second selective carrier transport prelayer 113″ and a first selective carrier transport prelayer 113′ for providing second-type doping particles is obtained by a direct deposition method. The second-type doping particles may be provided in other ways, such as by providing a second doping source layer, and the second doping source layer may form at least a portion of the selective carrier transport layer 113 in subsequent processing or be removed in subsequent processing, as long as the second doping source layer can provide doping particles for forming the selective carrier transport layer 113.

[0117] For example, instead of step S13, step S25 and step S33, an intrinsic second selective carrier transport prelayer 113" can be formed and then a second doping source layer (a second selective carrier transport prelayer 113" doped with second-type doping particles) can be formed in the intrinsic second selective carrier transport prelayer 113" by plasma implantation. Alternatively, a slurry containing second-type doping particles can be printed on the surface of the intrinsic second selective carrier transport prelayer 113" as the second doping source layer. Alternatively, an oxide layer containing second-type doping particles can be formed on the surface of the intrinsic second selective carrier transport prelayer 113" by CVD or PVD as the second doping source.

[0118] In addition, the selective carrier transport pre-layers 113 ′, 113 ″, etc. are not limited to being formed by PVD, but may also be formed by other methods, such as CVD such as PECVD.

[0119] For example, exemplary description is given by the following fourth to sixth embodiments.

[0120] Fourth embodiment

[0121] Figure 6 is a schematic flow chart of a method for manufacturing a battery cell according to a fourth embodiment of the present disclosure. Figure 7 A schematic diagram showing steps of a manufacturing method according to this embodiment.

[0122] The manufacturing method according to the fourth embodiment is different from the manufacturing method according to the first embodiment in that the intermediate semiconductor structure is different and is formed through steps S41 - S45 .

[0123] A manufacturing method according to a fourth embodiment of the present disclosure includes:

[0124] Step S41, providing a first type silicon substrate 111 and performing surface treatment on a first surface and a second surface of the silicon substrate 111. For example, the silicon substrate is a p-type single crystal silicon substrate with a resistivity of 0.1-10Ω·m.

[0125] Step S42, forming a boron paste as a first doping source layer on the first surface of the silicon substrate, for example, forming a single element paste doped with a first type of doping particles, such as a boron paste, as the first doping source layer 1151 on the first surface of the silicon substrate 111 by printing.

[0126] Step S43: forming a passivation dielectric layer 112 on the second surface of the silicon substrate 111. Specifically, the passivation dielectric layer 112 is a silicon dioxide layer with a thickness of 1.8 nm.

[0127] Step S44, forming an undoped intrinsic second selective carrier transport pre-layer on the passivation dielectric layer, for example, forming an undoped intrinsic second selective carrier transport pre-layer 113 on the surface of the passivation dielectric layer 112 facing away from the silicon substrate 111 by PVD.

[0128] Step S45, adopts the method of plasma implantation to make a part of the intrinsic second selective carrier transport prelayer 113" doped with the second type of doping particles to transform into the first selective carrier transport prelayer 113'. Therefore, by the method of plasma implantation, the intrinsic second selective carrier transport prelayer 113" is formed into a stack of the intrinsic second selective carrier transport prelayer 113" and the second type of doping particles doped to transform into the first selective carrier transport prelayer 113'.

[0129] In addition, the manufacturing method according to the fourth embodiment further includes the following steps which are the same as or similar to those of the manufacturing method of the first embodiment:

[0130] Step S46, performing a high temperature annealing treatment on the intermediate semiconductor structure formed in step S45 so as to activate the first type of doped particles in the boron slurry serving as the first doping source layer 1151 to form a first doped layer 116 in the first surface of the silicon substrate 111, and activate the second type of doped particles in the first selective carrier transport pre-layer 113' and crystallize the first selective carrier transport pre-layer 113' and the second selective carrier transport pre-layer 113" to form a selective carrier transport layer 113. In addition, during the high temperature annealing treatment, a third oxide layer 1131 is formed on the selective carrier transport layer 113.

[0131] Step S47, removing the third oxide layer 1131 and the boron slurry serving as the first doping source layer 1151. Specifically, the third oxide layer 1131 may be removed using an HF solution.

[0132] Step S48, forming a first passivation layer 117 and a second passivation layer 118 on the surface of the first doping layer 116 facing away from the silicon substrate 111 and the surface of the selective carrier transport layer 113 facing away from the silicon substrate 111. The first passivation layer 117 and the second passivation layer 118 are, for example, stacked layers of an aluminum oxide layer and a silicon oxynitride layer, respectively.

[0133] Step S49, forming the first contact electrode 1191 and the second contact electrode 1192. Specifically, metal contact paste is printed on the first passivation layer 117 and the second passivation layer 118 respectively by screen printing to form the first contact electrode 1191 and the second contact electrode 1192.

[0134] Fifth embodiment

[0135] Figure 7 is a schematic flow chart of a method for manufacturing a battery cell according to a fifth embodiment of the present disclosure.

[0136] The manufacturing method according to the fifth embodiment is different from the manufacturing method according to the first embodiment in that the intermediate semiconductor structure is different and is formed through steps S51 - S55 .

[0137] A manufacturing method according to a fifth embodiment of the present disclosure includes:

[0138] Step S51, providing a first type silicon substrate 111 and performing surface treatment on a first surface and a second surface of the silicon substrate 111. For example, the silicon substrate is a p-type single crystal silicon substrate with a resistivity of 0.1-10Ω·m.

[0139] Step S52: forming a passivation dielectric layer 112 on the second surface of the silicon substrate 111. Specifically, the passivation dielectric layer 112 is a silicon dioxide layer with a thickness of 2.0 nm.

[0140] Step S53, forming a first selective carrier transport pre-layer 113' doped with second-type doping particles on the surface of the passivation dielectric layer 112 facing away from the silicon substrate 111 by PECVD. This step may also include removing an undesired film layer formed on the first surface of the silicon substrate 111 due to plating. Specifically, the first selective carrier transport pre-layer 113' may be an amorphous silicon layer with a thickness of 60nm.

[0141] Step S54 , forming a first doping source layer 1151 in the first surface of the silicon substrate 111 by plasma implantation.

[0142] In addition, the manufacturing method according to the fifth embodiment further includes the following steps which are the same as or similar to those of the manufacturing method of the first embodiment:

[0143] Step S55, high temperature annealing treatment is performed on the intermediate semiconductor structure formed in step S54 so as to activate the first type of doping particles in the first doping source layer 1151 to form a first doping layer 116 in the first surface of the silicon substrate 111, and activate the second type of doping particles in the first selective carrier transport pre-layer 113' and crystallize the first selective carrier transport pre-layer 113' to form a doped selective carrier transport layer 113. In addition, during the high temperature annealing treatment, a second oxide layer 1152 is formed on the first doping source layer 1151, and a third oxide layer 1131 is formed on the selective carrier transport layer 113.

[0144] Step S56, removing the second oxide layer 1152 and the third oxide layer 113. For example, HF solution may be used.

[0145] Step S57, forming a first passivation layer 117 and a second passivation layer 118 on the surface of the first doping layer 116 facing away from the silicon substrate 111 and the surface of the selective carrier transport layer 113 facing away from the silicon substrate 111. Specifically, the first passivation layer 117 and the second passivation layer 118 can be stacked layers of a potassium oxide layer, an aluminum oxide layer, and a silicon oxynitride layer, respectively.

[0146] Step S58, forming the first contact electrode 1191 and the second contact electrode 1192. Specifically, metal contact paste is printed on the first passivation layer 117 and the second passivation layer 118 respectively by screen printing to form the first contact electrode 1191 and the second contact electrode 1192.

[0147] Sixth embodiment

[0148] Figure 8 is a schematic flow chart of a method for manufacturing a battery cell according to a sixth embodiment of the present disclosure. Fig. 9 A schematic diagram of the structure after forming a first oxide layer 114 and a first doping source layer 1151 on the first surface of a silicon substrate, and forming a passivation dielectric layer 112, a second selective carrier transport pre-layer 113", and a second doping source layer 113'' on the second surface of the silicon substrate according to the sixth embodiment is shown.

[0149] The manufacturing method according to the sixth embodiment is different from the manufacturing method according to the first embodiment in that the intermediate semiconductor structure is different and is formed through steps S61 - S65 ′.

[0150] A manufacturing method according to a sixth embodiment of the present disclosure includes:

[0151] Step S61, providing a first type silicon substrate 111 and performing surface treatment on a first surface and a second surface of the silicon substrate 111. For example, the silicon substrate is a p-type single crystal silicon substrate with a resistivity of 0.1-10Ω·m.

[0152] Step S62 , forming a first oxide layer 114 on the first surface of the silicon substrate 111 , for example, forming the first oxide layer 114 on the first surface of the silicon substrate 111 by PVD.

[0153] Step S63 , forming a first doping source layer on the first oxide layer 114 , for example, forming the first doping source layer 1151 on the surface of the first oxide layer 114 facing away from the silicon substrate 111 by PVD.

[0154] Step S64, forming a passivation dielectric layer on the second surface of the silicon substrate, for example, forming a passivation dielectric layer 112 on the second surface of the silicon substrate 111 by ALD. For example, the passivation dielectric layer 112 is a stack of an aluminum oxide layer and a titanium oxide layer.

[0155] Step S65, forming an undoped intrinsic second selective carrier transport prelayer on the passivation dielectric layer, for example, forming an undoped intrinsic second selective carrier transport prelayer 113" on the surface of the passivation dielectric layer 112 facing away from the silicon substrate 111 by PVD. For example, the second selective carrier transport prelayer 113" can be an intrinsic amorphous silicon layer with a thickness of 70 nm.

[0156] Step S65', forming an oxide layer doped with the second type of doping particles on the second selective carrier transport pre-layer as a second doping source layer. A second doping source layer 113'' doped with the second type of doping particles is formed on the second selective carrier transport pre-layer 113'' by APCVD. Specifically, the second doping source layer 113'' is an oxide layer containing phosphorus, such as a silicon oxide layer, such as Fig. 9 shown.

[0157] Step S66, performing high temperature annealing treatment on the intermediate semiconductor structure formed in step S65' so as to activate the first type of doping particles in the first doping source layer 1151 to form a first doping layer 116 in the second surface of the silicon substrate 111, and activate the second type of doping particles in the second doping source layer 113"' and subject the second selective carrier transport pre-layer 113" to crystallization heat treatment to form a selective carrier transport layer 113. In addition, during the high temperature annealing treatment, a second oxide layer 1152 is also formed on the first doping source layer 1151. For example, the high temperature annealing treatment includes performing high temperature heat treatment on the intermediate semiconductor structure at 880°C in an annealing furnace tube.

[0158] Step S67 , removing the first oxide layer 114 , the second oxide layer 1152 , the second doping source layer 113 ″′, and the first doping source layer 1151 .

[0159] Step S68, forming a first passivation layer 117 and a second passivation layer 118 on the surface of the first doping layer 116 facing away from the silicon substrate 111 and the surface of the selective carrier transport layer 113 facing away from the silicon substrate 111. For example, the first passivation layer 117 and the second passivation layer 118 are stacked layers of a silicon oxide layer and a silicon nitride layer, respectively.

[0160] Step S69 , forming the first contact electrode 1191 and the second contact electrode 1192 . Specifically, metal contact paste is printed on the first passivation layer 117 and the second passivation layer 118 respectively by screen printing to form the first contact electrode 1191 and the second contact electrode 1192 .

[0161] In the first to sixth embodiments described above, the manufacturing method is used to form Fig.2IThe battery cell shown in FIG. 1 is a battery cell shown in FIG. 1 , but the present disclosure is not limited thereto. In other embodiments, Fig.2I For example, the first doping layer 116 may include a plurality of first doping portions separated from each other to be locally formed in the first surface of the silicon substrate 111. For example, a first doping source layer 1151 may be retained on the first doping layer 116.

[0162] For example, exemplary description is given by the following seventh to eighth embodiments.

[0163] Seventh embodiment

[0164] Fig.10 is a schematic flow chart of a method for manufacturing a battery cell according to a seventh embodiment of the present disclosure. Figures 11A-11H are schematic diagrams of the structures of different steps of the method for manufacturing a battery cell according to the seventh embodiment, wherein Fig.11H A schematic structural diagram of a battery unit manufactured using the manufacturing method is shown.

[0165] like Fig.11H As shown, the battery cell manufactured using the manufacturing method includes: a first-type silicon substrate 111; a first doping layer 116 doped with first-type doping particles in the first surface of the silicon substrate 111, the first doping layer 116 including a plurality of first doping parts separated from each other; a first passivation layer 117 on the first doping layer 116 and the first surface of the silicon substrate 111; a plurality of first contact electrodes 1191 that are in ohmic contact with the plurality of first doping parts of the first doping layer 116 respectively through the first passivation layer 117; a passivation dielectric layer 112 on the second surface of the first-type substrate; a selective carrier transport layer 113 on the passivation dielectric layer 112; and a second passivation layer 118 on the selective carrier transport layer 113 and a plurality of second contact electrodes 1192 that are in ohmic contact with the selective carrier transport layer 113 through the second passivation layer 118.

[0166] Since the battery cell adopts local doping (ie, a plurality of first doping layers 116 ) on the front side where the first surface is located, compared with full-surface doping, the front side surface recombination is significantly reduced.

[0167] like Fig.10 and Figures 11A-11H As shown, in this embodiment, the manufacturing method of the battery unit may include:

[0168] Step S71, providing a first type of silicon substrate 111 and performing surface treatment on the first surface and the second surface of the silicon substrate 111, such as Fig.11A For example, the silicon substrate is a p-type single crystal silicon substrate with a resistivity of 0.1-10Ω·m.

[0169] Step S72, using a mask to form a first doping source layer 1151 doped with first-type doping particles and including a plurality of first doping source portions separated from each other on the first surface of the silicon substrate 111, for example, by PVD. Fig. 11B Specifically, in this embodiment, the first doping source layer 1151 is an amorphous silicon layer containing boron. In addition, for example, the first doping source layer 1151 can also be an amorphous silicon layer, a microcrystalline silicon layer or a stack of the two.

[0170] Step S73, forming a passivation dielectric layer 112 on the second surface of the silicon substrate 111, such as Fig. 11C Specifically, in this embodiment, a passivation dielectric layer 112 of silicon dioxide with a thickness of 1.5 nm is formed on the back side of the silicon substrate 111 by PECVD.

[0171] Step S74, forming a first selective carrier transport pre-layer 113' doped with second type doping particles on the surface of the passivation dielectric layer 112 facing away from the silicon substrate 111, such as Fig.11D Specifically, in this embodiment, a phosphorus-doped amorphous silicon layer with a thickness of 70 nm is formed by a PVD process as the first selective carrier transport pre-layer 113 ′.

[0172] Step S75, activating the first type of doping particles in the first doping source layer 1151 by high temperature annealing to form a first doping layer 116 including a plurality of first doping portions in the second surface of the silicon substrate 111, and activating the second type of doping particles in the first selective carrier transport pre-layer 113' and crystallizing the first selective carrier transport pre-layer 113' to form a doped selective carrier transport layer 113, as shown in FIG. Fig.11E In addition, during the high temperature annealing process, a second oxide layer 1152 is formed on the first doping source layer 1151 and the first surface of the silicon substrate 111, and a third oxide layer 1131 is formed on the selective carrier transport layer 113. For example, the high temperature annealing process includes performing a high temperature heat treatment at 850° C. in an annealing furnace tube.

[0173] Step S76, removing the first doping source layer 1151, the second oxide layer 1152 and the third oxide layer 1131, as shown in FIG. Fig.11F shown.

[0174] Step S77, forming a first passivation layer 117 and a second passivation layer 118 on the surface of the first doping layer 116 facing away from the silicon substrate 111 and the first surface of the silicon substrate 111 and the surface of the selective carrier transport layer 113 facing away from the silicon substrate 111, respectively. Fig.11GSpecifically, the first passivation layer 117 and the second passivation layer 118 may be a stack of an aluminum oxide layer and a silicon nitride layer.

[0175] Step S78, forming a first contact electrode 1191 and a second contact electrode 1192, such as Fig.11H Specifically, metal contact paste is printed on the first passivation layer 117 and the second passivation layer 118 respectively by screen printing to form the first contact electrode 1191 and the second contact electrode 1192 .

[0176] Eighth embodiment

[0177] Fig.12 is a schematic flow chart of a method for manufacturing a battery cell according to an eighth embodiment of the present disclosure. Fig.13 is a schematic structural diagram of a battery unit manufactured using the manufacturing method according to this embodiment.

[0178] like Fig.13 As shown, the battery cell includes a first-type silicon substrate 111, a first doping layer 116 including a plurality of first doping portions separated from each other, a first doping source layer 1151 including a plurality of first doping source portions separated from each other, a plurality of first contact electrodes 1191, a first passivation layer 117, a passivation dielectric layer 112, a selective carrier transport layer 113, a plurality of second contact electrodes 1192, and a second passivation layer 118. The first doping layer 116 is formed in the first surface of the silicon substrate 111 and is doped with first-type doping particles. The plurality of first doping source portions of the first doping source layer 1151 are respectively formed on each of the plurality of first doping portions of the first doping layer 116 and are doped with first-type doping particles. The first passivation layer 117 is formed on the first surface of the silicon substrate 111 and the first doping source layer 1151. The plurality of first contact electrodes 1191 penetrate the first passivation layer 117 and ohmically contact the first doping source layer 1151. The passivation dielectric layer 112 is formed on the second surface of the silicon substrate 111. The selective carrier transport layer 113 is formed on the passivation dielectric layer 112 and doped with the second type of doping particles. The second passivation layer 118 is formed on the selective carrier transport layer 113. The plurality of second contact electrodes 1192 penetrate the second passivation layer 118 and ohmically contact the selective carrier transport layer 113.

[0179] In this embodiment, since the battery cell adopts local doping on the first surface, the first doping source layer 1151 only partially covers the silicon substrate 111, and will not significantly block the silicon substrate 111 to reduce the light conversion efficiency of the battery cell. Therefore, the first doping source layer 1151 is retained between the first contact electrode 1191 and the first doping layer 116 in the silicon substrate 111. In the process of manufacturing the battery cell, the first doping source layer 1151 can be used as a doping source to dope the silicon substrate 111 to form the first doping layer 116, but the first doping source layer 1151 does not need to be removed. Since the step of removing the first doping source layer 1151 is omitted, the manufacturing process of the battery cell is simplified and the manufacturing cost is reduced.

[0180] like Fig.12 As shown, in this embodiment, the manufacturing method of the battery unit may include:

[0181] Step S81, providing a first type silicon substrate 111 and performing surface treatment on a first surface and a second surface of the silicon substrate 111. For example, the silicon substrate is a p-type single crystal silicon substrate with a resistivity of 2Ω·m.

[0182] Step S82: forming a passivation dielectric layer 112 on the second surface of the silicon substrate 111. For example, the passivation dielectric layer 112 may be a silicon dioxide layer with a thickness of 1.8 nm.

[0183] Step S83, forming a first selective carrier transport pre-layer 113 doped with second type doping particles on the surface of the passivation dielectric layer 112 facing away from the silicon substrate 111. For example, a first selective carrier transport pre-layer 113 of amorphous silicon doped with phosphorus with a thickness of 70 nm is formed on the passivation dielectric layer 112 by PVD process.

[0184] Step S84, using a mask, locally forms a first doping source layer 1151 doped with first-type doping particles and including a plurality of first doping source portions on the first surface of the silicon substrate 111. For example, a first doping source layer 1151 doped with boron and including a plurality of first doping source portions with a thickness of 40 nm is locally formed on the first surface of the silicon substrate 111 using PVD combined with a mask.

[0185] Step S85, high temperature annealing treatment is performed on the intermediate semiconductor structure formed in step S84 so as to activate the first type of doping particles in the first doping source layer 1151 to form a first doping layer 116 including a plurality of first doping portions in the first surface of the silicon substrate 111, and simultaneously activate the second type of doping particles in the first selective carrier transport pre-layer 113 and crystallize the first selective carrier transport pre-layer 113 to form a doped selective carrier transport layer 113. In addition, during the high temperature annealing treatment, a second oxide layer 1152 is formed on the first doping source layer 1151 and the first surface of the silicon substrate 111, and a third oxide layer 1131 is formed on the selective carrier transport layer 113.

[0186] Step S86, removing the second oxide layer 1152 and the third oxide layer 1131. For example, using HF solution.

[0187] Step S87, forming a first passivation layer 117 on the first surface of the silicon substrate 111 and the surface of the first doping source layer 1151 facing away from the silicon substrate 111, and forming a second passivation layer 118 on the surface of the selective carrier transport layer 113 facing away from the silicon substrate 111. Specifically, the first passivation layer 117 and the second passivation layer 118 can be stacked layers of a silicon oxide layer and a silicon nitride layer, respectively.

[0188] Step S88, forming the first contact electrode 1191 and the second contact electrode 1192. Specifically, metal contact paste is printed on the first passivation layer 117 and the second passivation layer 118 respectively by screen printing to form the first contact electrode 1191 and the second contact electrode 1192.

[0189] The present disclosure also provides the following technical solutions:

[0190] Technical solution 1, a method for manufacturing a silicon-based solar cell unit, comprising:

[0191] Providing a first type of silicon substrate, the silicon substrate having a first surface and a second surface opposite to the first surface;

[0192] forming a first doping source layer doped with first-type doping particles on a first surface of the silicon substrate;

[0193] forming a passivation dielectric layer on the second surface of the silicon substrate;

[0194] On the surface of the passivation dielectric layer facing away from the silicon substrate, there is formed:

[0195] A selective carrier transport front layer having doped particles of the second type, or

[0196] A stack of an intrinsic selective carrier transport pre-layer and a second doping source layer doped with second type doping particles; and

[0197] The silicon substrate forming the first doping source layer and the selective carrier transport pre-layer is subjected to high temperature annealing treatment to activate the first type of doping particles to form a first doping layer in the first surface of the substrate, and simultaneously activate the second type of doping particles and crystallize the selective carrier transport pre-layer to form a selective carrier transport layer.

[0198] Technical solution 2. The method according to technical solution 1, wherein:

[0199] Forming a selective carrier transport pre-layer having second-type doping particles or a stack of an intrinsic selective carrier transport pre-layer and a second doping source layer doped with second-type doping particles on the surface of the passivation dielectric layer facing away from the silicon substrate by physical vapor deposition; and

[0200] A first doping source layer doped with first-type doping particles is formed on the first surface of the silicon substrate by physical vapor deposition.

[0201] Technical solution 3, according to the method of technical solution 1, wherein,

[0202] The selective carrier transport pre-layer having the second type of doping particles comprises a first selective carrier transport pre-layer doped with the second type of doping particles; or

[0203] The selective carrier transport pre-layer having the second type of doping particles includes a first selective carrier transport pre-layer doped with the second type of doping particles and an intrinsic second selective carrier transport pre-layer.

[0204] Technical solution 4. A method according to any one of technical solutions 1 to 3, wherein:

[0205] The silicon substrate is single crystal silicon or polycrystalline silicon.

[0206] Technical solution 5. A method according to any one of technical solutions 1 to 3, wherein:

[0207] The selective carrier transport layer and the selective carrier transport pre-layer include one or more of amorphous silicon, microcrystalline silicon and polycrystalline silicon.

[0208] Technical solution 6. A method according to any one of technical solutions 1 to 3, wherein:

[0209] The second doping source layer includes an oxide layer or a single element slurry.

[0210] Technical solution 7. A method according to any one of technical solutions 1 to 3, wherein:

[0211] The first doping source layer includes amorphous silicon, microcrystalline silicon, polycrystalline silicon, an oxide layer or a single element slurry.

[0212] Technical solution 8. The method according to any one of technical solutions 1-3 further includes:

[0213] forming a first passivation layer on a surface of the first doped layer facing away from the silicon substrate; and

[0214] A second passivation layer is formed on a surface of the selective carrier transport layer facing away from the silicon substrate.

[0215] Technical solution 9. The method according to technical solution 8 further includes:

[0216] forming a plurality of first contact electrodes passing through the first passivation layer and ohmically contacting the first doping layer; and

[0217] A plurality of second contact electrodes are formed through the second passivation layer and ohmically contact the selective carrier transport layer.

[0218] Technical solution 10. The method according to technical solution 8, wherein:

[0219] The first passivation layer includes a single layer or a stack of one or more of a silicon oxide layer, an aluminum oxide layer, a gallium oxide layer, a titanium oxide layer, a silicon oxynitride layer, an aluminum oxynitride layer, a silicon layer, and a silicon carbide layer, and

[0220] The second passivation layer includes a single layer or a stacked layer of one or more of a silicon oxide layer, an aluminum oxide layer, a gallium oxide layer, a titanium oxide layer, a silicon oxynitride layer, an aluminum oxynitride layer, a silicon layer, and a silicon carbide layer.

[0221] Technical solution 11. A method according to any one of technical solutions 1 to 3, wherein:

[0222] The passivation dielectric layer includes a single layer or a stack of one or more of a silicon oxide layer, an aluminum oxide layer, a gallium oxide layer, a titanium oxide layer, a silicon oxynitride layer, an aluminum oxynitride layer and a silicon nitride layer. The thickness of the passivation dielectric layer may be in the range of 0.1-10 nm.

[0223] Technical solution 12. A method according to any one of technical solutions 1 to 3, wherein:

[0224] Before forming the first doping source layer, the method further includes:

[0225] A first oxide layer is formed on the first surface of the silicon substrate.

[0226] Technical solution 13. The method according to technical solution 12, wherein:

[0227] The first oxide layer is formed by physical vapor deposition.

[0228] Technical solution 14. A method according to any one of technical solutions 1 to 3, wherein:

[0229] The first type is p-type, and

[0230] The second type is n-type.

[0231] Technical solution 15. A method according to any one of technical solutions 1 to 3, wherein:

[0232] The first type is n-type, and

[0233] The second type is p-type.

[0234] Technical solution 16. A silicon-based solar cell unit manufactured according to the method of any one of technical solutions 1 to 15, the cell unit comprising:

[0235] a silicon substrate of a first type having opposing first and second surfaces;

[0236] a first doping layer formed in the first surface and doped with first-type doping particles;

[0237] a passivation dielectric layer formed on the second surface; and

[0238] A selective carrier transport layer is formed on a surface of the passivation dielectric layer facing away from the silicon substrate and is doped with second-type doping particles.

[0239] Technical Solution 17. A battery cell according to Technical Solution 16, wherein the first doping layer is formed along the entire surface of the first surface.

[0240] Technical Solution 18. A battery cell according to Technical Solution 16, wherein the first doping layer includes a plurality of dispersed first doping parts, and the concentration of the first type of doping particles in the first doping parts is higher than the concentration of the first type of doping particles in the silicon substrate.

[0241] Technical Solution 19: The battery cell according to Technical Solution 16 further includes:

[0242] a first passivation layer formed on a surface of the first doped layer facing away from the silicon substrate; and

[0243] A second passivation layer is formed on a surface of the selective carrier transport layer facing away from the silicon substrate.

[0244] Technical solution 20. The battery cell according to technical solution 19 further includes:

[0245] A first contact electrode passing through the first passivation layer and in ohmic contact with the first doping layer; and

[0246] A second contact electrode passes through the second passivation layer and is in ohmic contact with the selective carrier transport layer.

[0247] The scope of the present disclosure is not limited by the above-described embodiments but by the appended claims and their equivalents.

Claims

1. A method for manufacturing a silicon-based solar cell unit, comprising: Providing a first type of silicon substrate, the silicon substrate having a first surface and a second surface opposite to the first surface; forming a first doping source layer doped with first-type doping particles on a first surface of the silicon substrate; forming a passivation dielectric layer on the second surface of the silicon substrate; On the surface of the passivation dielectric layer facing away from the silicon substrate, there is formed: A selective carrier transport front layer having doped particles of the second type, or A stack of an intrinsic selective carrier transport pre-layer and a second doping source layer doped with second type doping particles; and performing a high temperature annealing process on the silicon substrate forming the first doping source layer and the selective carrier transport pre-layer, activating the first type of doping particles to form a first doping layer in the first surface of the substrate, and activating the second type of doping particles and crystallizing the selective carrier transport pre-layer to form a selective carrier transport layer, Wherein, the selective carrier transport pre-layer having the second type of doping particles or the stacked layer of the intrinsic selective carrier transport pre-layer and the second doping source layer doped with the second type of doping particles is formed on the surface of the passivation dielectric layer facing away from the silicon substrate by physical vapor deposition; and forming a first doping source layer doped with the first type of doping particles on the first surface of the silicon substrate by physical vapor deposition, Furthermore, before forming the first doping source layer, the method further comprises: forming a first oxide layer on the first surface of the silicon substrate, Wherein, the first oxide layer is formed by physical vapor deposition.

2. The method according to claim 1, wherein: The selective carrier transport pre-layer having the second type of doping particles comprises a first selective carrier transport pre-layer doped with the second type of doping particles; or The selective carrier transport pre-layer having the second type of doping particles includes a first selective carrier transport pre-layer doped with the second type of doping particles and an intrinsic second selective carrier transport pre-layer.

3. The method according to claim 1 or 2, wherein: The silicon substrate is single crystal silicon or polycrystalline silicon.

4. The method according to claim 1 or 2, wherein: The selective carrier transport layer and the selective carrier transport pre-layer include one or more of amorphous silicon, microcrystalline silicon and polycrystalline silicon.

5. The method according to claim 1 or 2, wherein: The second doping source layer includes an oxide layer or a single element slurry.

6. The method according to claim 1 or 2, wherein: The first doping source layer includes amorphous silicon, microcrystalline silicon, polycrystalline silicon, an oxide layer or a single element slurry.

7. The method according to claim 1 or 2, further comprising: forming a first passivation layer on a surface of the first doped layer facing away from the silicon substrate; as well as A second passivation layer is formed on a surface of the selective carrier transport layer facing away from the silicon substrate.

8. The method according to claim 7, further comprising: forming a plurality of first contact electrodes passing through the first passivation layer and ohmically contacting the first doping layer; as well as A plurality of second contact electrodes are formed through the second passivation layer and ohmically contact the selective carrier transport layer.

9. The method according to claim 7, wherein: The first passivation layer includes a single layer or a stack of one or more of a silicon oxide layer, an aluminum oxide layer, a gallium oxide layer, a titanium oxide layer, a silicon oxynitride layer, an aluminum oxynitride layer, a silicon layer, and a silicon carbide layer, and The second passivation layer includes a single layer or a stacked layer of one or more of a silicon oxide layer, an aluminum oxide layer, a gallium oxide layer, a titanium oxide layer, a silicon oxynitride layer, an aluminum oxynitride layer, a silicon layer, and a silicon carbide layer.

10. The method according to claim 1 or 2, wherein: The passivation dielectric layer includes a single layer or a stack of one or more of a silicon oxide layer, an aluminum oxide layer, a gallium oxide layer, a titanium oxide layer, a silicon oxynitride layer, an aluminum oxynitride layer and a silicon nitride layer. The thickness of the passivation dielectric layer may be in the range of 0.1-10 nm.

11. The method according to claim 1 or 2, wherein: The first type is p-type, and The second type is n-type.

12. The method according to claim 1 or 2, wherein: The first type is n-type, and The second type is p-type.

13. A silicon-based solar cell unit manufactured according to the method of any one of claims 1 to 12, the cell unit comprising: a silicon substrate of a first type having opposing first and second surfaces; a first doping layer formed in the first surface and doped with first-type doping particles; a passivation dielectric layer formed on the second surface; as well as A selective carrier transport layer is formed on a surface of the passivation dielectric layer facing away from the silicon substrate and is doped with second-type doping particles.

14. The battery cell according to claim 13, wherein: The first doping layer is formed along the entire surface of the first surface.

15. The battery cell according to claim 13, wherein: The first doping layer includes a plurality of first doping parts that are dispersed, and the concentration of the first type of doping particles in the first doping parts is higher than the concentration of the first type of doping particles in the silicon substrate.

16. The battery cell according to claim 13, further comprising: A first passivation layer formed on a surface of the first doped layer facing away from the silicon substrate; as well as A second passivation layer is formed on a surface of the selective carrier transport layer facing away from the silicon substrate.

17. The battery cell according to claim 16, further comprising: A first contact electrode passing through the first passivation layer and in ohmic contact with the first doping layer; as well as A second contact electrode passes through the second passivation layer and is in ohmic contact with the selective carrier transport layer.

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