Method for planarizing the surface of an epitaxial lateral overgrowth layer

Abstract

A method for planarizing the surface on an epitaxial lateral overgrowth (ELO) layer, resulting in obtaining a smooth surface with island-shaped group-III nitride semiconductor layers. The island-shaped group-III nitride semiconductor layers are formed by stopping their growth before the ELO layers coalesce with each other. Then, a growth-limiting mask is removed before growing at least some group-III nitride device layers. Removing the mask reduces the excessive gas supply to the side facets of the island-shaped group-III nitride semiconductor layers, which helps to obtain a smooth surface on the island-shaped group-III nitride semiconductor layers. The method also avoids the compensation of the p-type layer by decomposed n-type dopants (such as silicon and oxygen atoms) from the mask.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims the benefit of the following co - pending and co - assigned applications under 35 U.S.C. § 119(e):

[0003] U.S. Provisional Application No. 62 / 812,453, filed on March 1, 2019, by Takeshi Kamikawa and Srinivas Gandrothula, entitled "METHOD FOR FLATTENING A SURFACE ON AN EPITAXIAL LATERAL GROWTH LAYER", Attorney Docket No. G&C 30794.0720USP1 (UC 2019 - 409 - 1);

[0004] This application is hereby incorporated by reference herein.

[0005] This application is related to the following co - pending and co - assigned applications:

[0006] U.S. Patent Application No. 16 / 608,071, filed on October 24, 2019, by Takeshi Kamikawa, Srinivas Gandrothula, Hongjian Li, and Daniel A. Cohen, titled "METHOD OF REMOVING A SUBSTRATE", with Attorney Docket No. 30794.0653USWO (UC 2017-621-1), which claims the benefit of PCT International Patent Application No. PCT / US18 / 31393, filed on May 7, 2018, by Takeshi Kamikawa, Srinivas Gandrothula, Hongjian Li, and Daniel A. Cohen, titled "METHOD OF REMOVING A SUBSTRATE", with Attorney Docket No. 30794.0653WOU1 (UC 2017-621-2), and which is co-pending and co-assigned, and which claims the benefit of U.S. Provisional Patent Application No. 62 / 502,205, filed on May 5, 2017, by Takeshi Kamikawa, Srinivas Gandrothula, Hongjian Li, and Daniel A. Cohen, titled "METHOD OF REMOVING A SUBSTRATE", with Attorney Docket No. 30794.0653USP1 (UC 2017-621-1) under 35 U.S.C. § 365(c);

[0007] PCT International Patent Application No. PCT / US18 / 51375, filed on September 17, 2018, by Takeshi Kamikawa, Srinivas Gandrothula, and Hongjian Li, titled "METHOD OF REMOVING A SUBSTRATE WITH A CLEAVING TECHNIQUE", docket number 30794.0659WOU1 (UC 2018-086-2), which claims the benefit of co-pending and co-assigned U.S. Provisional Patent Application No. 62 / 559,378, filed on September 15, 2017, by Takeshi Kamikawa, Srinivas Gandrothula, and Hongjian Li, titled "METHOD OF REMOVING A SUBSTRATE WITH A CLEAVING TECHNIQUE", docket number 30794.0659USP1 (UC 2018-086-1), under 35 U.S.C. § 119(e);

[0008] PCT International Patent Application No. PCT / US19 / 25187, filed on April 1, 2019, by Takeshi Kamikawa, Srinivas Gandrothula, and Hongjian Li, titled "METHOD OF FABRICATING NONPOLAR AND SEMIPOLAR DEVICES USING EPITAXIAL LATERAL OVERGROWTH", docket number 30794.0680WOU1 (UC 2018-427-2), which claims the benefit of co-pending and co-assigned U.S. Provisional Patent Application Serial No. 62 / 650,487, filed on March 30, 2018, by Takeshi Kamikawa, Srinivas Gandrothula, and Hongjian Li, titled "METHOD OF FABRICATING NONPOLAR AND SEMIPOLAR DEVICES USING EPITAXIAL LATERAL OVERGROWTH", docket number G&C 30794.0680USP1 (UC 2018-427-1), under 35 U.S.C. § 119(e);

[0009] PCT International Patent Application No. PCT / US19 / 32936, filed on May 17, 2019, by Takeshi Kamikawa and Srinivas Gandrothula, entitled "METHOD FOR DIVIDING A BAR OF ONE OR MORE DEVICES", docket number 30794.0681WOU1 (UC 2018-605-2), which claims the benefit of co-pending and co-assigned U.S. Provisional Application Serial No. 62 / 672,913, filed on May 17, 2018, by Takeshi Kamikawa and Srinivas Gandrothula, entitled "METHOD FOR DIVIDING A BAR OF ONE OR MORE DEVICES", docket number G&C 30794.0681USP1 (UC 2018-605-1), under 35 U.S.C. § 119(e);

[0010] PCT International Patent Application No. PCT / US19 / 34686, filed on May 30, 2019, by Srinivas Gandrothula and Takeshi Kamikawa, entitled "METHOD OF REMOVING SEMICONDUCTING LAYERS FROM A SEMICONDUCTING SUBSTRATE", docket number 30794.0682WOU1 (UC 2018-614-2), which claims the benefit of co-pending and co-assigned U.S. Provisional Application Serial No. 62 / 677,833, filed on May 30, 2018, by Srinivas Gandrothula and Takeshi Kamikawa, entitled "METHOD OF REMOVING SEMICONDUCTING LAYERS FROM A SEMICONDUCTING SUBSTRATE", docket number G&C 30794.0682USP1 (UC 2018-614-1), under 35 U.S.C. § 119(e);

[0011] PCT International Patent Application No. PCT / US19 / 59086, filed on October 31, 2019, by Takeshi Kamikawa and Srinivas Gandrothula, entitled "METHOD OF OBTAINING A SMOOTH SURFACE WITH EPITAXIAL LATERAL OVERGROWTH", Attorney Docket No. 30794.0693WOU1 (UC 2019-166-2), which claims the benefit of co-pending and co-assigned U.S. Provisional Application Serial No. 62 / 753,225, filed on October 31, 2018, by Takeshi Kamikawa and Srinivas Gandrothula, entitled "METHOD OF OBTAINING A SMOOTH SURFACE WITH EPITAXIAL LATERAL OVERGROWTH", Attorney Docket No. G&C 30794.0693USP1 (UC 2019-166-1) under 35 U.S.C. § 119(e); and

[0012] PCT International Patent Application No. PCT / US20 / 13934, filed on January 16, 2020, by Takeshi Kamikawa, Srinivas Gandrothula and Masahiro Araki, entitled "METHOD FOR REMOVAL OF DEVICES USING A TRENCH", Attorney Docket No. 30794.0713WOU1 (UC 2019-398-2), which claims the benefit of co-pending and co-assigned U.S. Provisional Application Serial No. 62 / 793,253, filed on January 16, 2019, by Takeshi Kamikawa, Srinivas Gandrothula and Masahiro Araki, entitled "METHOD FOR REMOVAL OF DEVICES USING A TRENCH", Attorney Docket No. G&C 30794.0713USP1 (UC 2019-398-1) under 35 U.S.C. § 119(e);

[0013] All of these applications are hereby incorporated by reference. BACKGROUND OF THE INVENTION FIELD OF THE INVENTION

[0015] The present invention relates to a method for planarizing the surface of an epitaxial laterally grown layer. Background Art

[0016] Currently, some device manufacturers use Group-III nitride-based substrates, such as GaN or AlN substrates, to produce laser diodes (LDs) and light-emitting diodes (LEDs) for lighting, optical storage, etc. However, it is well known that Group-III nitride-based substrates are very expensive.

[0017] Previously, attempts have been made to recover substrates by removing Group-III nitride-based semiconductor layers from Group-III nitride-based substrates. In one example, a Group-III nitride layer is first grown on a substrate using epitaxial lateral overgrowth (ELO) and a growth-limiting mask. The growth of the Group-III nitride layer is stopped before the Group-III nitride layers coalesce with each other. This makes it easy to remove the resulting island-shaped Group-III nitride semiconductor layer after performing a device process for forming a ridge structure on the island-shaped Group-III nitride semiconductor layer.

[0018] Using this method allows the growth of Group-III nitride device layers on discrete ELO Group-III nitride layers using metalorganic chemical vapor deposition (MOCVD). In conventional epitaxial growth using MOCVD, growth can be performed on a flat substrate or a flat substrate with a template layer. However, the Group-III nitride device layer is grown on discrete epitaxial layers, and such growth cannot obtain a flat surface epitaxial layer on a substrate with discrete ELO Group-III nitride layers.

[0019] Deteriorated surface roughness means an in-plane distribution of each layer having a thickness. To improve the characteristics of the device, this in-plane distribution of the thickness of each layer needs to be reduced. For example, if the in-plane distribution of the thickness is in the p layer, the optical confinement factor of each device is different. Improving the surface roughness reduces this in-plane distribution of the thickness.

[0020] On the other hand, the growth-limiting mask is typically SiO 2 , SiN, etc. In these cases, Si and O are n-type dopants for the GaN layer. If the growth-limiting mask is exposed or not covered by something, the n-type layer can be compensated when growing the p-type layer.

[0021] The object of the present invention is to obtain a smooth surface after the growth of Group-III nitride device layers. Summary of the Invention

[0022] To overcome the above limitations in the prior art and other limitations that will become apparent upon reading and understanding this specification, the present invention discloses a method for obtaining a smooth surface of a discrete ELO group III nitride layer. In addition, the present invention has successfully improved the surface roughness of the group III nitride device layer on the discrete ELO group III nitride layer.

[0023] On the other hand, this is crucial for mounting the device top-down to suppress edge growth at the edges of the stripes of the device. Uneven atomic supply from the material gas can cause this phenomenon. The present invention has successfully suppressed edge growth.

[0024] Specifically, the present invention performs the following steps: growing an ELO group III nitride layer on a substrate using a growth-limiting mask via MOCVD or other methods; keeping the ELO group III nitride layers separated and discrete from each other; removing the substrate from the MOCVD reactor to remove the growth-limiting mask; removing the growth-limiting mask by wet or dry etching; after removing the growth-limiting mask, growing a group III nitride device layer on the ELO group III nitride layer and the substrate, thereby obtaining an island-like group III nitride semiconductor layer; manufacturing a device using the island-like group III nitride semiconductor layer; removing the stripes of the device from the substrate; and using a cleavage method to divide the stripes of the device into chips or individual devices.

[0025] After growing the group III nitride device layer, it is difficult to planarize their surfaces. This is especially applicable to group III nitride semiconductor layers containing ternary and quaternary compound group III nitride semiconductor layers.

[0026] Research has disclosed that uneven growth is caused by uneven gas supply, which affects the flatness of the surface and results in an uneven emission pattern of the active layer. In addition, uneven growth occurs in the portions near the edges of the island-like group III nitride semiconductor layer, which is caused by the difference in the number of supplied atoms in each portion.

[0027] In the present invention, separating the ELO group III nitride layers exacerbates this problem of uneven growth, which increases the number of edges. In addition, since the width of the flat surface region is narrow compared to conventional growth using ordinary wafers, uneven growth is more likely to occur. In addition, removing the growth-limiting mask after growing the ELO group III nitride layer and before growing a group III nitride device layer (such as a p-type layer) makes uneven growth more likely to occur.

[0028] On the other hand, the group III nitride layer can be grown at a temperature higher than 700 °C; in some cases, the growth temperature exceeds 1000 °C to improve the crystal quality. This high growth temperature makes SiO 2The growth-limiting mask decomposes into Si atoms and O atoms, and the Si atoms and O atoms are released into the growth atmosphere. In this case, the Si atoms and O atoms decomposed during the growth of the p-type layer cause the p-type layer to be compensated by Si and O as n-type dopants. Unfortunately, this compensation results in an increase in the series resistance of the p-type layer. The present invention avoids this compensation of the p-type layer by removing the growth-limiting mask before the growth of the p-type layer.

[0029] Generally, in an emitting device, the group-III nitride device layers are grown in the following order: an n-type layer, an active layer, an electron blocking layer (EBL), and a p-type layer. Preferably, the growth-limiting mask is removed before growing the p-type layer. More preferably, the growth-limiting mask is removed after growing the ELO group-III nitride layer. By doing so, a smooth surface can be obtained for the island-shaped group-III nitride semiconductor layer after growing the group-III nitride device layers.

[0030] Therefore, removing the growth-limiting mask before the device process has two advantages. One advantage is to obtain a smooth surface. Another advantage is to avoid the compensation of the p-type layer due to the decomposition of the growth-limiting mask. These two problems can be solved by adopting the present invention. Description of the Drawings

[0031] Now refer to the drawings, where the same reference numerals always represent corresponding parts:

[0032] Figure 1(a) and 1(b) are schematic diagrams of a substrate, a growth-limiting mask, and an epitaxial layer according to an embodiment of the present invention.

[0033] Figure 2(a) 、 2(b) 、2(c), 2(d), 2(e), 2(f), 2(g), 2(h), and 2(i) are schematic diagrams and scanning electron microscope (SEM) images comparing the results obtained with and without a growth-limiting mask according to an embodiment of the present invention.

[0034] Figure 3(a) 、 3(b) 、3(c), 3(d), 3(e), and 3(f) are scanning electron microscope (SEM) images of an island-shaped group-III nitride-based semiconductor layer according to an embodiment of the present invention.

[0035] Figure 4 is a cross-sectional view of a laser diode device formed from an island-shaped group-III nitride-based semiconductor layer according to an embodiment of the present invention.

[0036] Figure 5(a) 、 5(b), Figures 5(c) and 5(d) illustrate how to form divided support regions along the stripes of a device with a periodic length according to an embodiment of the present invention.

[0037] Figure 6(a) and 6(b) also illustrate how to form divided support regions along the stripes of a device with a periodic length according to an embodiment of the present invention.

[0038] Figure 7(a) and 7(b) respectively show SEM images of the back side of the stripes of the device after the stripes of the device are removed and the surface of the substrate after the stripes of the device are removed for only the (1-100), (20-21), and (20-2-1) planes.

[0039] Figure 8(a) , 8(b) , Figures 8(c), 8(d), 8(e), 8(f), and 8(g) illustrate the process for removing the stripes of a device according to an embodiment of the present invention.

[0040] Figure 9(a) and 9(b) are SEM images of the stripes of the device from different substrate planes.

[0041] Figure 10(a) , 10(b) , Figures 10(c), 10(d), and 10(e) are SEM images of the stripes of the device from the c-plane (0001) substrate plane.

[0042] Figure 11(a) and 11(b) illustrates a growth-limiting mask for multiple stripes of multiple devices according to an embodiment of the present invention.

[0043] Figure 12(a) and 12(b) are SEM images of a very smooth surface of the (1-100) plane without misorientation after the stripes of the device are removed.

[0044] Figure 13(a) and 13(b) are SEM images of the surface of the substrate after the stripes of the device with a misorientation of 0.7 degrees towards the m-plane of the (0001) plane are removed.

[0045] Figure 14 shows SEM images of the surface of the (20-21) freestanding GaN substrate and the material properties after the stripes of the device are removed.

[0046] Figure 15(a) , 15(b), Figures 15(c), 15(d), 15(e) and 15(f) illustrate the process of dividing bars of a device after removing the bars from a substrate using a polymer tape according to an embodiment of the present invention.

[0047] Figure 16 Illustrates a coating process for facets of a device according to an embodiment of the present invention.

[0048] Figure 17(a) , 17(b) Figures 17(a) and 17(c) illustrate how wire bonds are attached to a device and how a heat sink is divided at a trench according to an embodiment of the present invention.

[0049] Figure 18(a) and 18(b) illustrates how a heat sink is divided into separate devices according to an embodiment of the present invention.

[0050] Figure 19(a) and 19(b) illustrates a test device for a device according to an embodiment of the present invention.

[0051] Figure 20 Illustrates a TO-can package for a laser diode device according to an embodiment of the present invention.

[0052] Figure 21 Illustrates a package for a device including a heat sink according to an embodiment of the present invention.

[0053] Figure 22(a) and 22(b) illustrates the etching of a layer in a layer bending region according to an embodiment of the present invention.

[0054] Figure 23(a) and 23(b) illustrates the structure of a polymer film according to an embodiment of the present invention.

[0055] Figure 24(a) , 24(b) Figures 24(a), 24(b) and 24(c) are schematic diagrams illustrating growth with and without a growth limiting mask according to an embodiment of the present invention.

[0056] Figure 25(a) , 25(b) , Figures 25(c) and 25(d) are schematic diagrams illustrating growth with and without a growth limiting mask according to an embodiment of the present invention.

[0057] Figure 26(a) and 26(b) are schematic diagrams illustrating growth with and without a growth limiting mask according to an embodiment of the present invention.

[0058] Figure 27(a) and 27(b) are SEM images and schematic diagrams showing the shapes of the remaining spaces after growing an ELO group-III nitride layer and a group-III nitride device layer with and without a growth-limiting mask according to an embodiment of the present invention.

[0059] Figure 28 shows a device mounted with its top surface facing downwards on a heat sink according to an embodiment of the present invention.

[0060] Figure 29(a) and 29(b) is an SEM image of the surface of a group-III nitride device layer according to an embodiment of the present invention.

[0061] Figure 30(a) and 30(b) is an SEM image of the connection of a group-III nitride device layer after removing a growth-limiting mask according to an embodiment of the present invention.

[0062] Figure 31 is a flowchart showing a method for dividing a bar for one or more devices. DETAILED DESCRIPTION

[0063] In the following description of the preferred embodiments, reference is made to specific embodiments in which the present invention may be practiced. It should be understood that other embodiments may be utilized and structural changes may be made without departing from the scope of the present invention.

[0064] Device Structure

[0065] Figure 1(a) and 1(b) is a cross-sectional view showing a device structure fabricated according to an embodiment of the present invention.

[0066] In the embodiment of FIG. 1(a), a group-III nitride-based substrate 101 (such as a bulk GaN substrate 101) is provided, and a growth-limiting mask 102 is formed on or above the substrate 101. Strip-shaped opening regions 103 are defined in the growth-limiting mask 102.

[0067] When the ELO group-III nitride layers 105 grown from adjacent opening regions 103 in the growth-limiting mask 102 do not coalesce on the top of the growth-limiting mask 102, non-growth regions 104 are created. Preferably, the growth conditions are optimized such that the lateral width of the ELO group-III nitride layer 105 in its wing region is 20 μm.

[0068] An additional group-III nitride device layer 106 is deposited on or above the ELO group-III nitride layer 105, and may include an active region 106a, an electron blocking layer (EBL) 106b, a cladding layer 106c, and other layers.

[0069] The thickness of the ELO group-III nitride layer 105 is important because it determines the width of one or more flat surface regions 107 and the layer bending region 108 at its edge adjacent to the non-growth region 104. The width of the flat surface region 107 is preferably at least 5 μm, more preferably 10 μm or greater, and most preferably 20 μm or greater.

[0070] The ELO group-III nitride layer 105 and the additional group-III nitride device layer 106 are referred to as island group-III nitride semiconductor layers 109, where adjacent island group-III nitride semiconductor layers 109 are separated by non-growth regions 104.

[0071] The width of the non-growth region 104 can control the decomposition amount of the growth-limiting mask 102. The narrower the width of the non-growth region 104, the less the decomposition amount of the growth-limiting mask 102. Reducing the decomposition amount can mitigate the compensation of the p-type layer of the group-III nitride device layer 106 caused by the decomposition of the growth-limiting mask 102.

[0072] The distance between adjacent island group-III nitride semiconductor layers 109 is the width of the non-growth region 104, which is typically 20 μm or less, and preferably 5 μm or less, but is not limited to these values. Each island group-III nitride semiconductor layer 109 can be processed into a separate device 110. The device 110 is processed on the flat surface region 107 and / or the opening region 103, and the device 110 can be an LED, an LD, a Schottky barrier diode, or a metal-oxide-semiconductor field-effect transistor. In addition, the shape of the device 110 generally includes a strip.

[0073] In the present invention, the bonding strength between the substrate 101 and the ELO group-III nitride layer 105 is weakened by the growth-limiting mask 102. In this case, the bonding area between the substrate 101 and the ELO group-III nitride layer 105 is the opening region 103. The width of the opening region 103 is narrower than the width of the island group-III nitride semiconductor layer 109. The bonding strength between the growth-limiting mask 102 and the island group-III nitride semiconductor layer 109 is weak. In addition, the island group-III nitride semiconductor layer 109 is generally bonded to the substrate 101 only at the opening region 103. Therefore, the growth-limiting mask 102 reduces the bonding region, making this method preferable for removing the island group-III nitride semiconductor layer 109.

[0074] Finally, there may be a bottom layer 111, and the bottom layer 111 may be formed in the non-growth region 104 between the island-shaped group III nitride semiconductor layers 109. If the island-shaped group III nitride semiconductor layer 109 is connected to the bottom layer 111, it may be difficult to remove the island-shaped semiconductor layer 109 from the substrate 101.

[0075] Device manufacturing

[0076] The steps for manufacturing the device 110 using the present invention are described below.

[0077] Step 1: A growth-limiting mask 102 having a plurality of opening regions 103 is formed directly or indirectly on a substrate 101, where the substrate 101 is a group III nitride substrate or a hetero-substrate.

[0078] Step 2: Use the growth-limiting mask 102 to grow an ELO group III nitride layer 105 on the substrate 101 such that the growth extends in a direction parallel to the strip-shaped opening regions 103 of the growth-limiting mask 102, where the ELO group III nitride layer 105 does not coalesce.

[0079] Step 3: Remove the substrate 101 with the ELO group III nitride layer 105 from the MOCVD reactor. Remove the growth-limiting mask 102 from the substrate 101 by a wet etching method using an etchant (such as hydrofluoric acid (HF) or buffered HF (BHF)).

[0080] Step 4: After removing the growth-limiting mask 102, grow a group III nitride device layer 106. Due to the removal of the growth-limiting mask 102, the group III nitride device layer 106 grows on or above the ELO group III nitride layer 105 and on or above the surface of the substrate 101 between the ELO group III nitride layers 105.

[0081] Step 5: Fabricate the device 110 at the flat surface region 107 using a conventional method, where a ridge structure, a p-electrode, a pad electrode, etc. are provided at predetermined positions on the island-shaped group III nitride semiconductor layer 109.

[0082] Step 6: Form a support structure for cleaving at the side split surface and the flat surface region 107 of the strip of the device 110.

[0083] Step 7: Remove the strip of the device 110 from the substrate 101.

[0084] Step 7.1: Attach a polymer film to the strip of the device 110.

[0085] Step 7.2: Apply pressure to the polymer film and the substrate 101.

[0086] Step 7.3: While applying pressure, reduce the temperature of the thin film and the substrate 101.

[0087] Step 7.4: Remove the bars of the device 110 by utilizing the difference in thermal coefficients between the materials of the polymer thin film and the substrate 101.

[0088] Step 8: Fabricate an n electrode at the separation region of the device 110.

[0089] Step 9: Break the bars into separated devices 110 or chips.

[0090] Step 10: Mount the device 110 on a heat sink.

[0091] Step 11: Coat the facets of the laser diode device 110.

[0092] Step 12: Divide the heat sink into separated devices 110.

[0093] Step 13: Screen the devices 110.

[0094] Step 14: Mount the device 110 on or in a package.

[0095] These steps will be explained in more detail below.

[0096] Step 1: Form a growth-limiting mask

[0097] A growth-limiting mask 102 composed of patterned SiO 2 is deposited on a substrate 101 (such as an m-plane GaN substrate 101). In one embodiment, the growth-limiting mask 102 includes stripes separated by open regions 103, where the stripes have a width of 50 μm, a spacing of 50 μm, and are oriented along the <0001> axis. The width of the open region 103 is designed to be about 2 μm - 180 μm, and more preferably 4 μm - 50 μm.

[0098] FIG. 1(b) illustrates an alternative embodiment where these techniques are used with a hetero-substrate 101, and a template layer 112 (such as a 2 - 10 μm GaN intermediate or lower layer) is grown on the hetero-substrate 101. However, it is not necessary to grow the template layer 112 on the hetero-substrate 101; alternatively, SiO of the growth-limiting mask 102 can be formed on the hetero-substrate 101 2 , and then an ELO group III nitride layer 105 can be directly grown on the growth-limiting mask 102 formed on the hetero-substrate 101.

[0099] Step 2: Grow an ELO group III nitride layer on the substrate

[0100] As Figure 1(a) and 1(b)As shown, the ELO group-III nitride layer 105 is grown on the growth-limiting mask 102. Preferably, the ELO group-III nitride layer 105 does not coalesce on top of the growth-limiting mask 102.

[0101] In one embodiment, MOCVD is used for the epitaxial growth of the ELO group-III nitride layer 105. The ELO group-III nitride layer 105 is preferably a GaN or AlGaN layer to obtain a smooth surface. Trimethylgallium (TMGa) and / or trimethylaluminum (TMAl) are used as group-III element sources; ammonia (NH 3 ) is used as a source gas to supply nitrogen; and hydrogen (H 2 ) and nitrogen (N 2 ) are used as carrier gases for the group-III element sources. It is important to include hydrogen in the carrier gas to obtain a smooth surface of the epitaxial layer. The thickness of the ELO group-III nitride layer 105 is about 3 μm - 100 μm.

[0102] Step 3: Remove the substrate with the ELO group-III nitride layer from the MOCVD reactor

[0103] After growing the ELO group-III nitride layer 105, the substrate 101 is removed from the MOCVD reactor to remove the growth-limiting mask 102. The growth-limiting mask 102 is removed by wet etching with HF or BHF, etc. By doing so, the area covered by the growth-limiting mask 102 can be used for growing the group-III nitride device layer 106. This increases the growth area on the substrate 101 compared to before removing the growth-limiting mask 102.

[0104] Step 4: Grow multiple group-III nitride device layers

[0105] After removing the growth-limiting mask 102, the substrate 101 is loaded back into the MOCVD reactor for the epitaxial growth of the group-III nitride device layer 106.

[0106] Trimethylgallium (TMGa), trimethylindium (TMIn), and trimethylaluminum (TMAl) are used as group-III element sources; ammonia (NH 3 ) is used as a source gas to supply nitrogen; and hydrogen (H 2 ) and nitrogen (N 2 ) are used as carrier gases for the group-III element sources. It is important to include hydrogen in the carrier gas to obtain a smooth surface of the epitaxial layer.

[0107] Salts and bis(cyclopentadienyl)magnesium (Cp 2 Mg) are used as n-type and p-type dopants. The pressure is typically set to 50 to 760 Torr. The group-III nitride device layer 106 is usually grown in a temperature range of 700 °C to 1250 °C.

[0108] For example, the growth parameters include the following: TMG is 12 sccm, NH 3 is 8 slm, the carrier gas is 3 slm, SiH 4 is 1.0 sccm, and the V / III ratio is approximately 7700. These growth conditions are an example; the conditions can be changed and optimized for each layer.

[0109] Compare the results with and without the growth-limiting mask

[0110] In Figure 2(a) , 2(b) , 2(c), 2(d), 2(e), 2(f), 2(g), 2(h), and 2(i) illustrate group-III nitride device layers 106 obtained with and without the growth-limiting mask 102. Specifically, these figures illustrate the results obtained by removing at least a portion of the growth-limiting mask 102.

[0111] As shown in FIG. 2(a), if the growth-limiting mask 102 remains in place during the growth of the group-III nitride device layer 106, supply gases such as TMGa, TEGa, TMIn, TMAl, NH 3 , etc. are not consumed at the exposed region 201 of the growth-limiting mask 102. Instead, a large amount of supply gas 202 is found near the edge of the ELO group-III nitride layer 105. This results in non-uniformity of the supply gas 202.

[0112] As shown in FIG. 2(b), after removing the growth-limiting mask 102, the supply gas 202 is consumed in the region 203 where the growth-limiting mask 102 is removed. The removal of the growth-limiting mask 102 reduces the amount of supply gas 202 near the edge of the ELO group-III nitride layer 105. This results in more uniform supply gas 202.

[0113] To confirm the above mechanism, two samples were prepared. The ELO group-III nitride layers 105 of the two samples were prepared simultaneously. Both samples had smooth surfaces. The first sample did not remove the growth-limiting mask 102 before growing the group-III nitride device layer 106, while the second sample removed the growth-limiting mask 102 before growing the group-III nitride device layer 106. The two samples were jointly loaded into the MOCVD chamber.

[0114] Without removing the growth-limiting mask 102, the excessive supply gas 202 at the edge of the ELO group-III nitride layer 105 causes non-uniform growth at the surface of the ELO group-III nitride layer 105. As shown in image (1) of FIG. 2(c), the edge region on the ELO group-III nitride layer 105 sometimes becomes thicker than the center of the layer. This results in a rough surface morphology.

[0115] In the case of removing the growth-limiting mask 102, the excessive supply gas 202 at the edge of the ELO group-III nitride layer 105 is reduced by eliminating the growth-limiting mask 102. The consumption of the supply gas 202 in the region 203 after the removal of the growth-limiting mask 102 can relieve the excessive supply gas 202 at the edge of the ELO group-III nitride layer 105. This results in obtaining a smooth surface as shown in image (2) of FIG. 2(c).

[0116] In addition, photoluminescence (PL) measurements were also performed on two samples. As shown in FIG. 2(d), the PL images are affected by the surface morphology. The sample with the growth-limiting mask 102 as shown in image (1) of FIG. 2(d) has strong fluctuations in the PL image. On the other hand, the sample without the growth-limiting mask 102 as shown in image (2) of FIG. 2(d) significantly reduces the fluctuations in the PL image. This indicates that the technique can improve the characteristics of the device 110.

[0117] As described above, the group-III nitride device layer 106 can include various types of layers. One type is a low-temperature growth layer or an In-containing layer (such as an active layer). Another type is an Al-containing layer (such as an AlGaN cladding layer and / or an EBL layer). Still another type is a p-type layer (such as a p-GaN layer, a p-InGaN contact layer, etc.). These layers are vulnerable to non-uniform supply gas. When growing these layers, the present invention is very effective.

[0118] Limited area epitaxy (LAE)

[0119] According to U.S. Patent Application Publication No. US2017 / 0092810A1, after growing an epitaxial layer, many conical mounds were observed on the surface of the m-plane film. In addition, a wavy surface and recessed portions appeared on the growth surface, which deteriorated the surface roughness. This is a very serious problem when manufacturing an LD structure on the surface. For this reason, it is better to grow an epitaxial layer on a non-polar and semi-polar substrate, which is known to be difficult.

[0120] For example, according to some papers, it is possible by controlling the off-angle (>1 degree) of the growth surface of the substrate and by using N 2Carrier gas conditions are used to obtain a smooth surface. However, due to high production costs, these are very limited conditions for large-scale production. In addition, the fluctuations of the GaN substrate from the diagonal to the origin are very large depending on its manufacturing method. For example, if the substrate has a large in-plane diagonal distribution, it has different surface morphologies at these points in the wafer. In this case, the large in-plane diagonal distribution reduces the yield. Therefore, the technology must be independent of the in-plane diagonal distribution.

[0121] The present invention solves these problems described below.

[0122] 1. The growth region is restricted by the growth-limiting mask region at the substrate edge.

[0123] 2. The patterned substrate is a non-polar or semi-polar substrate, and its diagonal orientation ranges from -16 degrees to +30 degrees from the m-plane towards the c-plane. In addition, the diagonal orientation of the hetero-substrate with a group-III nitride-based semiconductor layer ranges from +16 degrees to -30 degrees from the m-plane towards the c-plane.

[0124] 3. The island-shaped group-III nitride semiconductor layer 109 has a long side perpendicular to the a-axis of the group-III nitride-based semiconductor crystal.

[0125] 4. During MOCVD growth, a hydrogen atmosphere can be used.

[0126] 5. The island-shaped group-III nitride semiconductor layers 109 do not coalesce with each other.

[0127] At least using the above #1, #2, and #3, a strip with a smooth surface is obtained. It is more preferable to perform each of #1, #2, #3, #4, and #5.

[0128] As Figure 3(a) 、 3(b) shown in 3(c), 3(d), 3(e), and 3(f), the present invention can obtain an island-shaped group-III nitride semiconductor layer 109, and the smooth top surface of the island-shaped group-III nitride semiconductor layer 109 does not have conical mounds and recessed parts, and has various planes and various diagonals. The results are explained as follows.

[0129] Figure 3(a) shows an image of the island-shaped group-III nitride semiconductor layer 109 on an m-plane (1-100) with a misorientation of -1.0 degrees towards the c-axis.

[0130] Figure 3(b) shows images of the island-shaped group-III nitride semiconductor layer 109 with different misorientation orientations of the m-plane (1-100), including (1) 0 degrees, (2) -0.45 degrees, (3) -0.6 degrees, and (4) -1.0 degrees.

[0131] Figure 3(c) shows an image of the island-shaped group-III nitride semiconductor layer 109 having different tilt angles from the m-plane (1-100) toward the +c plane. The different tilt angles include (1) the (10-10) plane at 0 degrees, (2) the (30-31) plane at +10 degrees, and (3) the (20-21) plane at +15 degrees.

[0132] Figure 3(d) shows an image of the island-shaped group-III nitride semiconductor layer 109 having different tilt angles from the m-plane (1-100) toward the -c plane (0001). The different tilt angles include (1) the (10-10) plane at 0 degrees, (2) the (20-2-1) plane at -15 degrees, and (3) the (10-1-1) plane at -28 degrees.

[0133] Figure 3(e) shows an image of the island-shaped group-III nitride semiconductor layer 109 having different misorientation angles from the c-plane (0001) toward the m-plane (1-100). The different misorientation angles include (1) a 0.2-degree misorientation and (2) a 0.8-degree misorientation.

[0134] Figure 3(f) shows an image of the island-shaped group-III nitride semiconductor layer 109 having AlGaN layers on respective planes including (1-100), (20-21), (20-2-1), (1-100), (20-21), and (20-2-1), where the Al component of the AlGaN layer is 3%-5%. As shown in Figure 3(f), by using the AlGaN layer, a smooth surface of the island-shaped group-III nitride semiconductor layer 109 can be obtained.

[0135] These results have been obtained under the following growth conditions.

[0136] In one embodiment, the growth pressure ranges from 60 to 760 Torr, but preferably ranges from 100 to 300 Torr to obtain a wider width of the island-shaped group-III nitride semiconductor layer 109; the growth temperature ranges from 900 °C to 1200 °C; the V / III ratio ranges from 1000 - 30,000, and more preferably from 3000 - 10,000; TMG is 2 - 20 sccm; NH 3 ranges from 3 to 10 slm; and the carrier gas is only hydrogen, or both hydrogen and nitrogen. To obtain a smooth surface, the growth conditions for each plane need to be optimized by conventional methods.

[0137] After growing for about 2 - 8 hours, the ELO group-III nitride layer 105 has a thickness of about 8 - 50 μm and a stripe width of about 20 - 150 μm, where the stripe width includes the width of the island-shaped group-III nitride semiconductor layer 109.

[0138] This method can obtain a smooth surface of the ELO group-III nitride layer 105 using various semi-polar and non-polar planar substrates 101 as well as a polar c-plane substrate 101. Accordingly, the present invention can employ various planes that do not depend on the bevel angle of the substrate 101.

[0139] Group-III nitride device layer

[0140] Figure 4 is a cross-sectional side view of a group-III nitride semiconductor laser diode device 110 fabricated along a direction perpendicular to an optical resonator

[0141] The device 110 is fabricated by a conventional method in a flat surface region 107, where a ridge structure, p-electrode, n-electrode, pads, etc. are provided at predetermined positions of an island-shaped group-III nitride semiconductor layer 109. (The bending region 108 is not depicted in this figure.)

[0142] The laser diode device 110 includes the following group-III nitride device layers 106 grown on an ELO GaN-based layer 105 deposited on a growth-limiting mask 102 and stacked on top of each other in the mentioned order: n-Al 0.06 GaN cladding layer 401, n-GaN waveguide layer 402, InGaN / GaN multiple quantum well (MQW) active layer 403, AlGaN EBL layer 404, p-GaN waveguide layer 405, ITO cladding layer 406, SiO 2 current-limiting layer 407, and p-electrode 408.

[0143] MOCVD is used for the epitaxial growth of the group-III nitride device layer 106. Trimethylgallium (TMGa), triethylgallium (TEG), trimethylindium (TMIn), and trimethylaluminum (TMAl) are used as group-III element sources; ammonia (NH 3 ) is used as a source gas to supply nitrogen; and hydrogen (H 2 ) and nitrogen (N 2 ) are used as carrier gases for the group-III element sources. Salts and bis(cyclopentadienyl)magnesium (Cp2Mg) are used as n-type and p-type dopants, respectively. The pressure is typically set to 50 to 760 Torr. The group-III nitride device layer 106 is generally grown at a temperature in the range of 700 to 1250 °C. Other growth parameters include the following: TMG is 12 sccm, NH 3 is 8 slm, the carrier gas is 3 slm, SiH 4 is 1.0 sccm, and the V / III ratio is approximately 7700. These growth conditions are only an example, and the conditions for each of the above layers can be changed and optimized.

[0144] The optical resonator includes a ridge strip structure, where the ridge strip structure includes an ITO cladding layer 406, SiO2 A current-limiting layer 407 and a p-electrode 408. The optical resonator provides optical confinement in the horizontal direction. The width of the ridge strip structure is on the order of 1.0 to 30 μm, and typically 10 μm.

[0145] The ridge strip structure can be fabricated using conventional methods such as photolithography and dry etching. The ridge depth (from the surface to the bottom of the ridge) is in the p-GaN guiding layer 405. Before performing dry etching, the ridge depth is predetermined based on simulation or previous experimental data.

[0146] In one embodiment, the p-electrode 408 can be composed of one or more of the following materials: Pd, Ni, Ti, Pt, Mo, W, Ag, Au, etc. For example, the p-electrode 408 can include Pd-Ni-Au (with thicknesses of 3 - 30 - 300 nm). These materials can be deposited by electron beam evaporation, sputtering, thermal evaporation, etc. Additionally, the p-electrode 408 is typically deposited on the ITO coating layer 406.

[0147] Growth-limiting mask and group-III nitride device layer

[0148] There is a problem when removing the growth-limiting mask 102 before the growth of the group-III nitride device layer 106. This problem occurs when the island-shaped group-III nitride semiconductor layer 109 is connected to the underlying layer 111. If the two layers 109, 111 are connected to each other, it is difficult to remove the island-shaped group-III nitride semiconductor layer 109. However, Figure 2(f) and 2(g) Illustrates the case where the two layers 109, 111 are not connected to each other, where Fig. 2(f) shows the island-shaped group-III nitride semiconductor layer 109 separated from the underlying layer 111 through the bottom region 204, and Fig. 2(g) shows the island-shaped group-III nitride semiconductor layer 109 separated from the underlying layer 111 through the bottom regions 204a and 204b. In both cases, the underlying layer 111 does not grow at the edge of the growth-limiting mask 102, or the growth rate is very slow. This result occurs because the edge of the growth-limiting mask 102 shields the bottom region 204 from the supply gas 202 used in the growth of the island-shaped group-III nitride semiconductor layer 109.

[0149] Step 5: Device process

[0150] After step 4, the island-shaped group-III nitride semiconductor layers 109 are separated from each other. The present invention can use a group-III nitride substrate 101 or a hetero-substrate 101 (such as sapphire, SiC, LiAlO 2, Si, etc.), as long as the group III nitride substrate 101 or the hetero-substrate 101 can enable the growth of the ELO group III nitride layer 105 through the growth-limiting mask 102. In the case of using the group III nitride substrate 101, the present invention can obtain a high-quality ELO group III nitride layer 105 and avoid the bowing or bending of the substrate 101 caused by homoepitaxial growth during epitaxial growth. As a result, the present invention can also easily obtain a device 110 with a reduced defect density, such as dislocations and stacking faults.

[0151] Step 6: Form a structure for cleaving at the flat surface region and the side facets

[0152] As Figure 5(a) , 5(b) , as shown in FIGS. 5(c) and 5(d), the purpose of this step is to prepare for dividing the strip 501 of the device 110 before removing the strip 501 of the device 110 from the substrate 101. The dividing support regions 502 are formed at a periodic length, where each period is determined by the length of the device 110. For example, in the case of the laser diode device 110, one period is set to be 300 - 1200 μm.

[0153] The dividing support regions 502 are lines scribed by a diamond tip scriber or a laser scriber, as shown in FIG. 5(a); or trenches formed by dry etching such as RIE (reactive ion etching) or ICP (inductively coupled plasma), as shown in FIG. 5(b); but are not limited to these methods. The dividing support regions 502 can be formed on both sides or one side of the strip 501. The depth of the dividing support regions 502 is preferably 1 μm or more.

[0154] In both cases, the strip 501 can be divided into separate devices 110 at the dividing support regions 502 because the dividing support regions 502 are weaker than any other part. The dividing support regions 502 prevent the strip 501 from breaking at non-intended positions, so that the length of the device 110 can be accurately determined.

[0155] The dividing support regions 502 are created at the flat surface region 107 and the layer bending region 108 in a manner that avoids the current injection region 503 and the p-electrode 408 in the ridge structure, but it can cover at least part of the current limiting layer 407 in the SiO 2 current limiting layer 407.

[0156] As Figure 5(a) and 5(b) shown, the dividing support regions 502 are formed at the first facet 504 and optionally at the second facet 505 because they are flat regions and are easy to process. The third facet 506 can be avoided.

[0157] As shown in Fig. 5(c), the dividing support region 502 may preferably be formed only at the second sub-plane 505. In this case, it must use the small width of the island-shaped group III nitride semiconductor layer 109. In this case, it can accurately divide the strip 501 of the device 110.

[0158] In addition, as shown in Fig. 5(d), the p-electrode 408, the dielectric layer 407, the p-pad for wire bonding, etc. can avoid the dividing support region 502. By doing so, change Fig. 6(a) as in Fig. 6(b).

[0159] As shown in the SEM image of Fig. 7(a), the back side of the strip 501 has two different parts after being removed: one is the separation region between the two white dashed lines; the other is the wing region outside the separation region. The two different parts have different surface morphologies, which may be an opportunity to prevent the crack line from traveling straight. In addition, due to the interaction between the mask and the back side surface of the island-shaped group III nitride semiconductor layer 109, there are some fluctuations in the wing region. Fig. 7(b) shows the SEM image of the surface of the substrate 101 after the strip 501 has been removed.

[0160] Therefore, as Figure 5(a) 、 5(b) 、5(c) and 5(d) show, preferably, the dividing support region 502 is formed on the first sub-plane 504 and / or the second sub-plane 505. By doing so, the shape of the dividing support region 502 is formed uniformly. More preferably, the blade for breaking the strip 501 contacts the back side of the strip 501. By doing so, the cracking starts from the dividing support region 502 at the top surface of the strip 501.

[0161] Step 7: Removing the strip of the device from the substrate

[0162] Use Figure 8(a) 、 8(b) 、8(c), 8(d), 8(e), 8(f) and 8(g) to explain this step of removing the strip 501.

[0163] Step 7.1 includes attaching the polymer film 801 to the strip 501 of the device 110, as shown in Fig. 8(a). In this embodiment, the polymer film 801 is composed of a base film 802, an adhesive 803 and a back film 804.

[0164] Step 7.2 includes applying pressure 805 to the polymer film 801 and the substrate 101 using the plate 806, as shown in FIG. 8(b). The purpose of applying pressure 805 is to place the polymer film 801 between the bars 501 of the device 110. The polymer film 801 is softer than the bars 501 of the device 110, such that the polymer layer 801 can easily wrap around the bars 501 of the device 110. Preferably, the polymer film 801 is heated to soften it, which enables the polymer film 801 to easily cover the bars 501 of the device 110.

[0165] Step 7.3 includes reducing the temperature of the polymer film 801 and the substrate 101 while maintaining the applied pressure 805. It is not necessary to apply pressure 805 during the temperature change.

[0166] Step 7.4 includes removing the bars 501 of the device 110 by taking advantage of the difference in thermal expansion coefficients between the polymer film 801 and the substrate 101.

[0167] As shown in FIG. 8(c), the polymer film 801 shrinks as the temperature decreases. Accordingly, the bottom of the polymer film 801 is lower than the top of the bars 501 of the device 110, as shown in FIG. 8(d).

[0168] As shown in FIG. 8(c), the polymer film 801 can apply pressure 805 in the horizontal direction at the side split surface of the bars 501 of the device 110, exposing the crack point 807 and tilting the bars 501 of the device 110 downward 808. This pressure 805 applied from the side split surface allows the bars 501 of the device 110 to be effectively removed from the substrate 101. During the low temperature period, the polymer film 801 maintains the pressure 805 applied from the top of the polymer film 801 to the bars 501 of the device 110.

[0169] Various methods can be used to reduce the temperature. For example, the substrate 101 and the polymer film 801 can be placed into liquid N 2 simultaneously (e.g., at 77°K) while applying pressure 805. The temperature of the substrate 101 and the polymer film 801 can also be controlled using a piezoelectric transducer. Additionally, before and / or during contact with the polymer film 801, the plate 806 applying pressure 805 to the polymer film 801 can be cooled to a low temperature. By doing so, the polymer film 801 is cooled and can apply pressure 805 to the bars 501 of the device 110 due to its large coefficient of thermal expansion.

[0170] When the temperature is reduced, the substrate 101 and the polymer film 801 may be wetted by atmospheric humidity. In this case, the temperature reduction can be carried out in a dry air atmosphere or a dry N 2 atmosphere to avoid wetting the substrate 101 and the polymer film 801.

[0171] Thereafter, for example, the temperature is raised to room temperature, and the pressure 805 is no longer applied to the polymer film 801. At this time, the strip 501 of the device 110 has been removed from the substrate 101, and the polymer film 801 is then separated from the substrate 101. As shown in FIG. 8(e), when using the polymer film 801, especially the polymer film 801 having the adhesive 803, the polymer film 801 can be used to remove the strip 501 of the device 110 in a simple and rapid manner.

[0172] As shown in FIG. 8(f), depending on the growth conditions, there may be a situation where the strips 501 of the device 110 have different heights t between them. In this case, the removal method using the polymer film 801 is good at removing the strips 501 of different heights of the device 110 because these films 801 are flexible and soft, as shown in FIG. 8(g).

[0173] Method for removing strips

[0174] By utilizing the different coefficients of thermal expansion between the polymer film 801 and the semiconductor material of the device 110, pressure in the horizontal direction is uniformly applied to the entire substrate 101. The strip 501 of the device 110 can be removed from the substrate 101 without breaking the strip 501 of the device 110. This has been proven by the high yield achieved in removing the strip 501.

[0175] As Figure 9(a) 、 9(b) shown in the SEM images of FIGS. 10(a), 10(b), 10(c), 10(d) and 10(e), this method can remove the strip 501 of the device 110 from many different substrate 101 planes (such as only (1-100), (20-21), (20-2-1) and (0001)). In these examples, the length of the strip 501 is about 1.2 mm. In addition, even if the (20-21) and (20-2-1) planes are not the cleavage facets of the bulk GaN substrate 101, this method can remove the strip 501 in an easy manner without breaking the strip 501. In other words, the advantage of this method is that the strip 501 can be removed from different substrate 101 planes by the same method because this method does not depend on the substrate 101 plane. More preferably, when removing the strip 501, cleavage on the m-plane of the GaN crystal can be utilized. In the case where the substrate 101 is not an m-plane substrate 101 (such as (20-21), (20-2-1) or (0001)), the surface of the separation region after removal contains the m-plane as part of its surface, and the strip 501 can be removed by a smaller pressure.

[0176] As Figure 11(a) and 11(b)As shown, the strip 501 of the device 110 is a rectangular shape with a long side and a short side. As shown in FIG. 8(c), pressure is applied to the strip 501 of the device 110 having such a shape in the vertical direction and in the horizontal direction along the long side of the opposing strip 501. By doing so, an effective influence can be given to the cleavage point 807 that removes the strip 501 of the device 110 from the substrate 101. Before attaching the polymer film 801 to the strip 501 of the device 110, it is preferable to eliminate the growth-limiting mask 102 from the substrate 101 by wet etching or the like. Eliminating the growth-limiting mask 102 creates space for applying pressure at the cleavage point 807 below the strip 501 of the device 110, which can cause the strip 501 of the device 110 to tilt downward 808 as shown in FIG. 8(c).

[0177] This method of using the polymer film 801 can apply pressure 805 uniformly to the strip 501 of the device 110 over a large area and in an appropriate amount. By selecting the type and / or temperature of the polymer film 801, and the rate of increase and / or decrease of the temperature, the amount of pressure 805 applied to the strip 501 of the device 110 can be controlled. In addition, the present invention is not limited by the rate of increase and / or decrease of the temperature, and a thermosetting resin film can be used to remove the strip 501 of the device 110 when the temperature is raised. Again, this results in a high yield of removing the strip 501.

[0178] In mass production, it is sometimes difficult to remove each strip 501 of the device 110 on the substrate 101, especially for a substrate 101 having a large area. Sometimes, after removing one or more strips 501 of the element 110, there are cases where some strips 501 of the device 110 remain on the substrate 101. In the above prior art methods, due to the metal bonding process between the wafer and the support metal, it is difficult to repeat the removal process.

[0179] On the other hand, this removal method using the polymer film 801 and the substrate 101 with the ELO III-nitride layer 105 can be repeated multiple times. When some strips 501 of the device 110 remain on the substrate 101, repeating this method allows the remaining strips 501 of the device 110 to be completely removed from the substrate 101.

[0180] Since this removal method does not include catastrophic processes (such as metal bonding), it can be a repeatable process. By repeating this removal method, almost all strips 501 of the device 110 can be removed from the substrate 101, which includes substrates 101 such as 2-inch, 4-inch, or other wafer sizes.

[0181] Cleavage at the separation region of the m-plane

[0182] A cleavage method using the m-plane facet is illustrated herein. Figure 7(a) and7(b) SEM images of the back side of the device 110 after removal of the bars and the surface of the substrate 101 after removal of the bars 501 of the device 110 are shown for the (1-100), (20-21), and (20-2-1) planes, respectively. It can be seen that the back side of the bar 501 for the (1-100) plane as shown in FIG. 7(a) is a relatively smooth surface compared to other planes, and the same is true for the surface of the substrate 101 after removal of the bar 501 for the (1-100) plane as shown in FIG. 7(b).

[0183] As shown in the image of FIG. 12(a) and its enlarged view in FIG. 12(b), after removal of the bar 501 of the device 110, it is possible to obtain a very smooth surface for the (1-100) plane without any misorientation, where the surface is smooth enough to be used as a facet of a VCSEL. As shown in the image of FIG. 13(a) and its enlarged view in FIG. 13(b), the surface of the substrate 101 after removal of the bar 501 of the device 110 is pitted for the (0001) plane with a misorientation of 0.7 degrees towards the m plane.

[0184] As shown in FIG. 7(b), the back side of the bar 501 of the device 110 for the semi-polar (20-21) and (20-2-1) planes has periodic convex and concave shapes. In these results, the interface at the cleavage point is the m-plane facet. The cleavage interface is measured using a laser scanning confocal microscope (LSCM).

[0185] Including LSCM measurements Figure 14 The image shows the surface of the (20-21) freestanding GaN substrate 101 after removal of the bar 501 of the device 110. The surface of the recessed area is inclined 15 degrees from the surface of the (20-21) substrate 101, where the surface of the (20-21) substrate 101 is inclined 15 degrees from the m plane. Therefore, the surface of the recessed area is the m plane. The m plane of bulk GaN is well-known to have a highly cleavable facet, and it is very important and useful to utilize the cleavage of the m plane to remove the bar 501. Even though the semi-polar (20-21) substrate 101 does not have the m plane as its main surface, the method of removing the bar 501 can effectively utilize the cleavage of the m plane.

[0186] As Figure 14As shown, preferably, the strip 501 including a semi-polar group-III nitride-based semiconductor layer has a periodic convex shape and concave shape after being removed from the substrate 101. By being separated in this way, the strip 501 can avoid excessive and uneven stress. Therefore, the strip 501 can be divided from the substrate 101 without breaking into short sizes. More preferably, at least the back side of the strip 501 composed of a semi-polar group-III nitride-based semiconductor layer has an m-plane as part of the back surface. This method can also be applied to different semi-polar planes, which has important industrial significance.

[0187] Crack at the separation region of the c-plane

[0188] The present invention also tried this removal method on a c-plane GaN substrate 101, as shown in FIG. 10(a).

[0189] As Figure 10(b) and 10(c) shown, the growth-limiting mask 102 and the opening region 103 are designed as shown in FIG. 11 without a separation region. The length of the long side of the opening region 103 is set to 15 mm.

[0190] The enlarged image of FIG. 10(d) in FIG. 10(e) shows the surface of the substrate 101 after removing the strip 501 of the device 110. The c-plane is one of the cleavage planes in bulk GaN. Therefore, the separation region on the back side of the strip 501 is very smooth. This indicates that this removal method can also be used for the c-plane GaN substrate 101.

[0191] Avoid the connection between the underlying layer and the island-shaped semiconductor layer

[0192] In the present invention, the growth-limiting mask 102 is removed before growing the group-III nitride device layer 106. The thickness of the ELO group-III nitride layer 105 is at least more than 4 μm. The height of the ELO group-III nitride layer 105 prevents the growth of the underlying layer 111. In addition, the side facets of the ELO group-III nitride layer 105 form a gap between the island-shaped group-III nitride semiconductor layer 109 and the underlying layer 111 at the bottom region 204, as shown in images (1), (2), and (3) of FIG. 2(e). Due to the reduction of the supply gas, the growth rate of this region 204 is very low. Figure 2(f) 、 2(g) and FIG. 2(h) illustrate that the widths of the bottom regions 204a, 204b depend on the shape of the side facets of the ELO group-III nitride layer 105. Various shapes of the side facets of the ELO group-III nitride layer 105 are shown in FIG. 2(i).

[0193] However, as Figure 2(g) and 2(h)As shown, the Group-III nitride device layer 106 generally has two types of shapes for the side facets illustrated by 204a and 204b.

[0194] In one example, as shown in 204a, the edge of the side facet is located outside the bottom edge of the Group-III nitride device layer 106. The distance between the bottom edge and the edge of the side facet is the bottom region 204a.

[0195] In another example, as shown in 204b, the edge of the side facet is located at the bottom edge of the Group-III nitride device layer 106. The distance between the bottom edge and the edge of the side facet is the bottom region 204b.

[0196] The first example may be preferred because the additional distance makes it more likely to avoid the connection between the underlying layer 111 and the island Group-III nitride semiconductor layer 109.

[0197] Step 8: Fabricate an n-electrode at the separation region of the device

[0198] Steps 8, 9, 10, and 11 are illustrated by Figure 15(a) 、 15(b) 、15(c), 15(d), 15(e), 15(f), and Figure 16 illustrated.

[0199] After removing the strip 501 from the substrate 101, the strip 501 remains attached to the polymer film 801. As shown in FIG. 15(a), the strip 501 is positioned on the film 801 in an upside-down manner.

[0200] FIG. 15(b) shows both a schematic diagram and an SEM image of the back side of the strip 501, which has a separation region 1501 between the divided support regions 502. The separation region 1501 directly contacts the substrate 101 or the underlying layer, but not on the growth-limiting mask 102. A cleaving blade 1502 is used at the divided support regions 502.

[0201] Then, as shown in FIG. 15(c), a metal mask 1503 can be used to set an n-electrode 1504 on the back side of the device 110.

[0202] In the case of forming the n-electrode 1504 on the back side of the strip 501 after removing the strip 501 from the substrate 101, it is preferred to form the n-electrode 1504 on the separation region 1501. This separation region 1501 is maintained in good surface conditions so that the n-electrode 1504 obtains a low contact resistivity. The present invention keeps this region 1501 clean until the island Group-III nitride semiconductor layer 109 is removed.

[0203] The n-electrode 1504 can also be set on the top surface of the strip 501, which is the same surface made for the p-electrode 408.

[0204] Typically, the n - electrode 1504 includes the following materials: Ti, Hf, Cr, Al, Mo, W, Au. For example, the n - electrode may include Ti - Al - Pt - Au (with a thickness of 30 - 100 - 30 - 500 nm), but is not limited to these materials. The deposition of these materials can be performed by electron beam evaporation, sputtering, thermal evaporation, etc.

[0205] Step 9: Break the strip into separate devices

[0206] As shown in FIG. 15(d), after the n - electrode 1504 is set in step 8, each strip 501 is divided into a plurality of devices 110. As shown in FIG. 15(b), dividing the support region 502 helps to divide the strip 501 into devices 110. Fracture methods and other conventional methods can be used, but are not limited to these methods. Preferably, at the position of the dividing support region 502, the splitting blade 1502 contacts one side of the strip 501 that is not formed by the dividing support region 502.

[0207] As shown in FIG. 15(d), a plurality of laterally arranged strips 501 can be split and broken into separate devices 110 at the dividing support region 502. In addition, a plurality of laterally and longitudinally arranged strips 501 can be split at the dividing support region 502. Further, the dividing support region 502 can be provided on both sides or one side of the strip 501.

[0208] Step 10: Mount the device on a heat sink

[0209] After step 9, the divided strip 501 is still on the polymer film 801. In one embodiment, the polymer film 801 is an ultraviolet (UV) - sensitive dicing tape exposed to UV light, which can reduce the adhesion strength of the film 801, as shown in FIG. 15(e). This makes it easy to remove the device 110 from the film 801.

[0210] In this step, a heat sink 1505 including AlN is prepared. An Au - Sn solder 1506 is set on the heat sink 1505, the heat sink 1505 is heated to a temperature exceeding the melting temperature of the solder 1506, and the device 110 on the polymer film 801 is bonded to the heat sink 1505 using the Au - Sn solder 1506. The device 110 can be mounted on the heat sink 1505 in two ways: (1) with the n - electrode 1504 side down or (2) with the p - electrode 408 side down. FIG. 15(f) shows the device 110 mounted on the heat sink 1505 using the solder 1506 with the n - electrode 1504 side facing down. The trenches 1507 in the heat sink 1505 separate the devices 110, where the trenches 1507 are used to divide the heat sink 1505, as described in more detail below.

[0211] Step 11: Faceting of the device

[0212] Step 11 includes faceting 504 of device 110. When the laser diode device 110 is lasing, the light that penetrates through faceting 504 of device 110 to the outside of device 110 is absorbed by non-radiative recombination centers at faceting 504, causing the faceting temperature to continuously rise. Therefore, the temperature rise may cause catastrophic optical damage (COD) to faceting 504.

[0213] Faceting 504 coating can reduce non-radiative recombination centers. To prevent COD, it is necessary to use a dielectric layer (such as AlN, AlON, Al 2 O 3 , SiN, SiON, SiO 2 , ZrO 2 , TiO 2 , Ta 2 O 5 etc.) to coat faceting. Generally, the coating film is a multi-layer structure including the above materials. The structure and thickness of the layer are determined by a predetermined reflectivity.

[0214] In the present invention, it has been possible to divide strip 501 of device 110 in step 9 to obtain faceting 504 for multiple devices 110. Therefore, a method for simultaneously performing faceting 504 coating on multiple devices 110 in a simple manner is required. In one embodiment, devices 110 are mounted on heat sink 1505 in a horizontally offset manner, for example, towards one side of heat sink 1505, as shown in Fig. 15(f). Then, as Figure 16 shown, devices 110 and heat sink 1505 are placed on spacer 1601, and multiple spacers 1601 are stored in coating holder 1602.

[0215] Note that it is not always necessary to use spacer 1601, and heat sink 1505 can be used alone. Alternatively, heat sink 1505 can be mounted on another strip or plate and then placed on spacer 1601.

[0216] By doing so, faceting 504 of multiple devices 110 can be coated simultaneously. In one embodiment, faceting 504 coating is performed at least twice - once for the front faceting 504 of device 110 and once for the rear faceting 504 of device 110. The length of heat sink 1505 can be dimensioned to be approximately the cavity length of laser diode device 110, which enables faceting 504 coating to be performed quickly and easily twice.

[0217] Once the spacer 1601 is set in the coating holder 1602, the two facets 504 of the device 110 can be coated without setting the spacer 1601 in the coating holder 1602 again. In one embodiment, a first coating is performed on the front facet 504 that emits laser light, and a second coating is performed on the rear facet 504 that reflects laser light. Before the second coating is performed in the facility for depositing the coating film, the coating holder 1602 is flipped. This substantially reduces the lead time of the process.

[0218] Step 12: Divide the heat sink

[0219] In this step, as shown in FIG. 17(a), the wire bondings 1701 and 1702 are attached to the device 110, and then the heat sink 1505 is divided at the trench 1507 (e.g., between one or more devices 110). FIG. 17(b) is a top view of FIG. 17(a), which shows the relative placement and positions of the device 110, the trench 1507, and the bondings 1701, 1702. FIG. 17(c) shows the use of the separation probe 1703 and the wire bonding 1704 with the device 110.

[0220] Figure 18(a) and 18(b) Also shown is how the heat sink 1505 is divided to separate the devices 110, which may occur before or after attaching the wire bondings 1701, 1702. By doing so, it is easy to separate the devices 110 after the coating process has been completed.

[0221] Step 13: Screen the devices

[0222] This step differentiates between defective devices 110 and non-defective devices 110. First, various characteristics of the device 110 are inspected under given conditions; such as output power, voltage, current, resistivity, FFP (far-field pattern), slope efficiency, etc. At this time, the device 110 is already mounted on the heat sink 1505, so it is easy to inspect these characteristics.

[0223] In Figure 19(a) and 19(b) the test equipment 1901 is shown, where the p electrode 408 and the solder 1506 having electrical continuity with the n electrode 1504 are contacted by the probes 1902, 1903. Then, the non-defective devices 110 can be selected and screened through an aging test (life test).

[0224] In one embodiment, preferably, the test device 1901 includes a box or other container such that an aging test can be performed on the device 110 sealed in a dry gas or nitrogen atmosphere. Additionally, the heating stage 1904 can be used to maintain the temperature of the device 110 during the screening test, such as 60 degrees, 80 degrees, etc. The photodetector 1905 can be used to measure the optical output power 1906, which identifies a defect-free device 110 with a constant output power or a defective device 110.

[0225] Specifically, in the case of the group-III nitride-based semiconductor laser diode device 110, it is known that when the laser diode oscillates in a humid atmosphere, it deteriorates. This deterioration is caused by the humidity and siloxane in the gas, so it is necessary to seal the group-III nitride-based semiconductor laser diode device 110 in a dry gas during the aging test.

[0226] Therefore, as Figure 20 shown, when transporting the group-III nitride-based laser diode 2000 from the manufacturer, the chip 2001 itself is mounted on the header 2002 and sealed in a dry gas atmosphere using the TO-CAN package 2003, where the package 2003 includes a window 2004 for light emission.

[0227] Generally, screening or aging tests are performed before transportation to screen out defective devices 110. For example, the screening conditions are based on the specifications of the laser diode device 110 (such as high temperature and high power).

[0228] In addition, the aging test can be performed when the device 110 is mounted on / to the package 2000, where the package 2000 is sealed in dry air and / or dry nitrogen before screening. This fact limits the flexibility of packaging and mounting the laser device.

[0229] In the prior art, if a defective production occurs, the defective product is discarded as the entire TO-CAN package 2000, which is a huge loss for production. This makes it difficult to reduce the production cost of the laser diode device 110. It is necessary to detect defective devices 110 at an earlier step.

[0230] In the present invention, the facet 504 of the device 110 is coated with the heat sink 1505, multiple devices 110 can be mounted on the heat sink 1505 at a low level position, and then the heat sink 1505 and the device 110 are divided using the trench 1507 after the coating process, allowing the device 110 with the submount with the heat sink 1505 to be inspected in a screening test in a dry air or nitrogen atmosphere.

[0231] When performing the screening test, the device 110 already has two contacts, namely the p-electrode 408 and the solder 1506 on the heat sink 1505, or the n-electrode 1504 and the solder 1506 on the heat sink 1505 in the case of flip-chip bonding. In addition, when the device 110 includes only the chip and the submount, the present invention can use the screening test to select defective products. Therefore, in the case of discarding defective products, the present invention can reduce losses more than the prior art, which is of great value.

[0232] In the case of screening the high-power laser diode device 110, it may be preferable that the heat sink 1505 has two parts of the solder 1506 with no electrical continuity. One part of the solder 1506 is connected to the p-electrode 408 through a lead (not shown), and the other part of the solder 1506 is connected to the n-electrode 1504 through a lead (not shown). In addition, it may be preferable that the p-electrode 408 and the n-electrode 1504 are connected to the solder part 1506 through two or more leads. For example, as shown in FIG. 17(c), which shows the p-electrode 408 connected to the solder 1506 through two or more leads 1704. In this way, the probe 1703 for applying current to the device 110 can avoid directly contacting the p-electrode 808 (or the n-electrode 1504), which is crucial in the case of screening high-power laser diodes. Specifically, especially in the case of applying a high current density, the probe 1703 may break the contacting part.

[0233] Step 14: Mount the device on / into the package

[0234] In this step, as Figure 21 shown, the device 110 (including the heat sink 1505) can be mounted in the package 2101 using solder or other metals to bond the device 110 at the bottom of the package 2101. The pins 2102 of the package 2101 are connected to the device 110 through leads 2103. By doing so, current from an external power source can be applied to the device 110.

[0235] This is more preferable than using metals such as Au-Au, Au-In, etc. for bonding between the package 2101 and the heat sink 1505. This method requires flatness at the surface of the package 2101 and the back side of the heat sink 1505. However, in the absence of solder, this configuration achieves high thermal conductivity and low-temperature bonding, which is a great advantage for device processes.

[0236] Thereafter, the cover 2104 can enclose the package 2101. Additionally, the phosphor 2105 can be disposed outside and / or inside the package 2101, where the window 2106 allows light emission to leave the package 2101. By doing so, the package 2101 can be used as a bulb or a headlight for an automobile.

[0237] As described herein, these processes provide an improved method for obtaining the laser diode device 110. Additionally, once the device 110 is removed from the substrate 101, the substrate 101 can be recycled multiple times. This achieves the goal of environmentally friendly production and low-cost modules. These devices 110 can be used as lighting devices such as bulbs, data storage equipment, optical communication equipment such as Li-Fi, etc.

[0238] It is difficult to encapsulate multiple different types of laser devices 110 in one package 2101. However, since the aging test can be performed without encapsulation, this method can overcome this problem. Therefore, it is easy to mount different types of devices 110 in one package 2101.

[0239] Manufacturing LED Devices

[0240] In the case of manufacturing LED devices, the same process can be used until step 5. This discussion briefly explains how to manufacture two types of LEDs. Type 1 LEDs have two electrodes (p-electrode and n-electrode) on one side of the chip, while Type 2 LEDs have one electrode on the opposite side of the chip.

[0241] First, in the case of Type 1 LEDs, the p-electrode and n-electrode are formed on the top surface of the device in step 5. Then, steps 6 - 10 are the same process, and steps 11 - 13 are omitted. In step 14, the removed chip is mounted on the package and the heat sink. The back surface of the chip, the package, and the heat sink are joined using silver adhesive.

[0242] Second, in the case of Type 2 LEDs, almost the same process is used until step 5, and an ITO electrode is formed on the p-GaN contact layer. In this case, the method of the dividing bar is the same. Additionally, it is preferable to eliminate the layer bending region.

[0243] Term Definition

[0244] Group III Nitride-Based Substrate

[0245] The group-III nitride-based substrate 101 can include any type of group-III nitride-based substrate, as long as the group-III nitride-based substrate 101 can grow group-III nitride-based semiconductor layers 105, 106, 109 through the growth-limiting mask 102, any GaN substrate 101 sliced from bulk GaN and AlN crystals on planes such as {0001}, {11-22}, {1-100}, {20-21}, {20-2-1}, {10-11}, {10-1-1} planes or other planes can be used.

[0246] Heterogeneous substrate

[0247] In addition, the heterogeneous substrate 101 can also be used in the present invention. For example, before the growth-limiting mask 102, a GaN template 112 or other group-III nitride-based semiconductor layer 112 can be grown on the heterogeneous substrate 101 (such as sapphire, Si, GaAs, SiC, etc.). The GaN template 112 or other group-III nitride-based semiconductor layer 112 is typically grown to a thickness of about 2 - 6 μm on the heterogeneous substrate 101, and then the growth-limiting mask 102 is set on the GaN template 112 or other group-III nitride-based semiconductor layer 112.

[0248] Growth-limiting mask

[0249] The growth-limiting mask 102 includes a dielectric layer (such as SiO 2 , SiN, SiON, Al 2 O 3 , AlN, AlON, MgF, ZrO 2 , etc.), or refractory metals or noble metals (such as W, Mo, Ta, Nb, Rh, Ir, Ru, Os, Pt, etc.). The growth-limiting mask can be a laminated structure selected from the above materials. It can also be a multi-stack layer structure selected from the above materials.

[0250] In one embodiment, the thickness of the growth-limiting mask is about 0.05 - 3 μm. The width of the mask is preferably greater than 20 μm, and more preferably, the width is greater than 40 μm. The growth-limiting mask is deposited by sputtering, electron beam evaporation, plasma-enhanced chemical vapor deposition (PECVD), ion beam deposition (IBD), etc., but is not limited to these methods.

[0251] On the m-plane freestanding GaN substrate 101, Figure 11(a) and 11(b)The growth-limiting mask 102 shown in [Figure 0] includes a plurality of opening regions 103 that are arranged periodically at intervals p1 and p2 in a first direction parallel to the 11-20 direction of the substrate 101 and in a second direction parallel to the 0001 direction of the substrate 101, respectively. The plurality of opening regions 103 extend in the second direction. The length a of the opening region 103 is, for example, 200 to 35000 μm. The width b is, for example, 2 to 180 μm. The interval p1 of the opening region 102 is, for example, 20 to 180 μm, and the interval p2 is, for example, 200 to 35000 μm. The width b of the opening region 103 is typically constant in the second direction but may be changed in the second direction as needed.

[0252] On the c-plane freestanding GaN substrate 101, the opening regions 103 are arranged in a first direction parallel to the 11-20 direction of the substrate 101 and in a second direction parallel to the 1-100 direction of the substrate 101.

[0253] On the semi-polar (20-21) or (20-2-1) GaN substrate 101, the opening regions 103 are arranged in directions parallel to [-1014] and [10-14], respectively.

[0254] Alternatively, a hetero-substrate 101 can be used. When growing the c-plane GaN template 112 on the c-plane sapphire substrate 101, the opening regions 103 have the same direction as those on the c-plane freestanding GaN substrate; when growing the m-plane GaN template 112 on the m-plane sapphire substrate 101, the opening regions 103 have the same direction as those on the m-plane freestanding GaN substrate 101. By doing so, the m-plane cleavage plane can be used to divide the stripe 501 of the device 110 using the c-plane GaN template 112, and the c-plane cleavage plane can be used to divide the stripe 501 of the device 110 using the m-plane GaN template 112, which is more preferable.

[0255] Group-III nitride-based semiconductor layer

[0256] The ELO group-III nitride layer 105, the group-III nitride device layer 106, and the island-shaped group-III nitride semiconductor layer 109 may include In, Al, and / or B, as well as other impurities such as Mg, Si, Zn, O, C, H, etc.

[0257] The Group-III nitride device layer 106 generally includes more than two layers, which include at least one of an n-type layer, an undoped layer, and a p-type layer. The Group-III nitride device layer 106 specifically includes a GaN layer, an AlGaN layer, an AlGaInN layer, an InGaN layer, etc. In the case where the device has a plurality of semiconductor layers based on Group-III nitrides, the distance between adjacent island-shaped Group-III nitride semiconductor layers 109 is generally 30 μm or less, and preferably 10 μm or less, but is not limited to these numbers. In a semiconductor device, a plurality of electrodes according to the type of the semiconductor device are provided at predetermined positions.

[0258] Advantages of epitaxial lateral overgrowth

[0259] The crystallinity of the island-shaped Group-III nitride semiconductor layer 109 grown using epitaxial lateral overgrowth (ELO) from the strip-shaped opening region 103 of the growth-limiting mask 102 on the growth-limiting mask 102 is very high.

[0260] In addition, two advantages can be obtained by using a Group-III nitride-based substrate 101. One advantage is that compared with using a sapphire substrate 101, a high-quality island-shaped Group-III nitride semiconductor layer 109 can be obtained, such as having a very low defect density.

[0261] Another advantage of using similar or the same materials for both the epitaxial layers 105, 106, 109 and the substrate 101 is that it can reduce the strain in the epitaxial layers 105, 106, 109. Moreover, due to the similar or the same thermal expansion, this method can reduce the amount of bending of the substrate 101 during epitaxial growth. As described above, the effect is that the production yield can be very high so as to improve the temperature uniformity.

[0262] The use of a hetero-substrate 101 (such as sapphire (m-plane, c-plane), LiAlO 2 , SiC, Si, etc.) for the growth of the epitaxial layers 105, 106, 109 lies in that these substrates 101 are low-cost substrates. This is an important advantage for mass production.

[0263] When it comes to the quality of the device 110, for the reasons described above, it is more preferable to use a freestanding Group-III nitride-based substrate 101. On the other hand, due to the weaker bonding strength at the cleavage point 807, using a hetero-substrate 101 makes it easy to remove the Group-III nitride-based semiconductor layers 105, 106, 109.

[0264] Moreover, when growing multiple island-shaped group-III nitride semiconductor layers 109, these layers are separated from each other (i.e., formed in isolation), so the tensile stress or compressive stress generated in each island-shaped group-III nitride semiconductor layer 109 is confined within the layer 109, and the effect of the tensile stress or compressive stress is not reduced for other group-III nitride-based semiconductor layers.

[0265] Moreover, since the growth-limiting mask 102 and the ELO group-III nitride layer 105 are not chemically bonded, the stress in the ELO group-III nitride layer 105 can be relieved by the slip caused at the interface between the growth-limiting mask 102 and the ELO group-III nitride layer 105.

[0266] Moreover, as shown by the non-growth region 104, the presence of gaps between each island-shaped group-III nitride semiconductor layer 109 results in the substrate 101 having rows of multiple island-shaped group-III nitride semiconductor layers 109, which provides flexibility such that the substrate 101 can be easily deformed and bent when an external force is applied.

[0267] Therefore, even if slight warping, bending, or deformation occurs in the substrate 101, this can be easily corrected by a small external force, thus avoiding cracks. Therefore, the substrate 101 can be handled by a vacuum chuck, which makes the manufacturing process of the semiconductor device 110 easier to implement.

[0268] As described above, island-shaped group-III nitride semiconductor layers 109 made of high-quality semiconductor crystals can be grown by suppressing the bending of the substrate 101. In addition, even when the group-III nitride-based semiconductor layers 105, 106, 109 are very thick, the occurrence of cracks and the like can be suppressed, so that a large-area semiconductor device 110 can be easily realized.

[0269] Flat surface region

[0270] The flat surface region 107 is between the layer bending regions 108. In addition, the flat surface region 107 is on the growth-limiting mask 102.

[0271] The manufacturing of the semiconductor device 110 is mainly performed on the flat surface region 107. The width of the flat surface region 107 is preferably at least 5 μm, and more preferably 10 μm or more. The flat surface region 107 has high uniformity for the thickness of each semiconductor layer in the flat surface region 107.

[0272] There is no problem if the manufacturing of the semiconductor device is partially formed on the layer bending region 108. More preferably, the layer at the bent layer region 108 is removed by etching. For example, it is best to use an etching process (such as dry etching or wet etching) to remove at least part of the active layer in the layer bending region 108.

[0273] In the case where the semiconductor device includes the island-shaped group III nitride semiconductor layer 109, the distance between the adjacent island-shaped group III nitride semiconductor layers 109 is generally 20 μm or less, and preferably 5 μm or less, but is not limited to these values. The distance between the island-shaped group III nitride semiconductor layers 109 is the width of the non-growth region 104.

[0274] Layer bending region

[0275] Figure 22(a) and 22(b) Illustrated how the bent active region 2201 can be retained in the device 110. The layer bending region 108 is defined as the region including the bent active region 2201 outside the bent active region 2201.

[0276] If a non-polar or semi-polar substrate is used, the island-shaped group III nitride semiconductor layer 109 has two or three facets on one side of the island-shaped group III nitride semiconductor layer 109. The first facet is the main region for forming the ridge structure, while the second and third facets include the layer bending region 108.

[0277] If the layer bending region 108 including the active layer is retained in the LED chip, part of the light emitted from the active layer is reabsorbed. Therefore, it is preferable to remove at least part of the active layer in the layer bending region 108 by etching.

[0278] If the layer bending region 108 including the active layer is retained in the LD chip, the laser mode may be affected by the layer bending region 108 due to the low refractive index (e.g., InGaN layer). Therefore, it is preferable to remove at least part of the active layer in the layer bending region 108 by etching. Two etchings can be performed, where the first etching removes the active layer in the second facet region before removing the epitaxial layer from the substrate 101, and the second etching removes the active layer in the third facet region after removing the epitaxial layer from the substrate 101.

[0279] The emission region is the current injection region. In the case of a laser diode, the emission region is the ridge structure. In the case of an LED, the emission region is the region for forming the p-contact electrode.

[0280] For both the LD and the LED, the edge of the light-emitting region should be at least 1 μm or more, and more preferably 5 μm, from the edge of the layer bending region.

[0281] From another perspective, the epitaxial layer of the flat region 107 other than the opening region 103 has a lower defect density than the epitaxial layer of the opening region 103. Therefore, more preferably, the ridge strip structure should be formed in the flat region 107 including the wing region.

[0282] Semiconductor device

[0283] The semiconductor device 110 is, for example, a light-emitting diode, a laser diode, a Schottky diode, a photodiode, a transistor, etc., but is not limited to these devices. The present invention is particularly applicable to micro LEDs and laser diodes, such as edge-emitting lasers and vertical cavity surface-emitting lasers (VCSELs). The present invention is particularly applicable to semiconductor lasers having cleaved facets.

[0284] Polymer film

[0285] The polymer film 801 is used to remove the island group III nitride semiconductor layer 109 from the group III nitride-based substrate 101 or the GaN template 112 used together with the heterogeneous substrate 101. In the present invention, a dicing tape including a commercially available UV-sensitive dicing tape can be used as the polymer film 801. For example, the structure of the polymer film 801 may include three layers 802, 803, 804 or two layers 803, 804, as Figure 23(a) and 23(b) shown, but is not limited to these examples. The base film 802 material (for example, with a thickness of about 80 μm) can be made of polyvinyl chloride (PVC). The back film 804 material (for example, with a thickness of about 38 μm) can be made of polyethylene terephthalate (P.E.T.). The adhesive layer 803 (for example, with a thickness of about 15 μm) can be made of an acrylic UV-sensitive adhesive.

[0286] When the polymer film 801 is a UV-sensitive dicing tape and is exposed to UV light, the adhesiveness of the film 801 is drastically reduced. After removing the island group III nitride semiconductor layer 109 from the substrate 101, the polymer film 801 is exposed to UV light, which makes it easy to remove.

[0287] Heat sink

[0288] As described above, the removed strip 501 can be transferred to the heat sink 1505, and the heat sink 1505 can be AlN, SiC, Si, Cu, CuW, etc. As shown in FIG. 15(e), a solder 1506 for bonding is provided on the heat sink 1505, and the solder 1506 can be Au-Sn, Su-Ag-Cu, Ag adhesive, etc. Then, the n electrode 1504 or the p electrode 408 is bonded to the solder 1506. The device 110 can also be flip-chip bonded to the heat sink 1505.

[0289] In the case of bonding the LED device 110 to the heat sink 1505, the size of the heat sink 1505 is not important and can be designed as needed.

[0290] In the case of bonding the laser diode device 110 to the heat sink 1505, preferably, the length of the heat sink 1505 is equal to or shorter than the length of the laser diode device 110 for the facet 504 coating process, where the length of the laser diode device 110 is almost the same as the length of the laser cavity. By doing so, it is easy to coat the two facets 504 of the laser cavity. If the length of the heat sink 1505 is longer than the laser cavity, the heat sink 1505 will prevent the uniform coating of the laser facet 504.

[0291] Long-width heat sink

[0292] The long-width of the heat sink 1505 makes the process of manufacturing the laser device 110 more efficient. As Figure 16 shown, the heat sink 1505 is placed on the spacer 1601, and then both are stacked with other heat sinks 1505 and spacers 1601 in the coating holder 1602 for simultaneously coating multiple devices 110. Therefore, a single coating process can coat a large number of devices 110.

[0293] Heat sink with grooves

[0294] Preferably, the heat sink 1505 has grooves 1507 for partitioning the device 110 as Figure 15(e) and 15(f) shown. This structure is useful after the facet 504 coating process, where the heat sink 1505 is partitioned into one or more devices 110, such as a single device 110 or an array of devices 110. After partitioning the heat sink 1505, the device 110 can be made into a package or module, such as a lighting module. The grooves 1507 in the heat sink 1505 guide the formation of the partitioning of the device 110. The grooves 1507 can be formed by a wet etching method and mechanically processed before mounting the device 110 on the heat sink 1505. For example, if the heat sink 1505 is made of silicon, wet etching can be used to form the grooves 1507. Using the grooves 1507 in this way reduces the process lead time.

[0295] Heat sink with solder

[0296] As shown in FIG. 15(f), preferably, the length of the solder 1506 is shorter than the length of the device 110 on the heat sink 1505. This prevents any surrounding of the facet 504 by the solder 1506, which may cause deterioration of the device 110 characteristics. In particular, surrounding should be avoided for flip-chip mounting.

[0297] As shown in Fig. 17(b), after the coating process, the heat sink 1505 has a surrounding area, which is the area surrounded by the dashed line. The width W of the surrounding area is about 10–20 μm. The coating film will coat these areas. It is also difficult to avoid coating the solder 1506 with the coating film. Generally, the coating film is selected from one or more dielectric materials, which is why this area is not conductive. When bonding the lead 1702 to the solder 1506, this is a problem for both conductivity and adhesion. Therefore, preferably, the lead 1702 is placed to avoid the surrounding area. At least, the position of the lead bond body 1702 should be about 25 μm away from the edge of the heat sink 1505.

[0298] Alternative Embodiment

[0299] First Embodiment

[0300] Figure 24(a) 、 24(b) Fig. 24(c) illustrates a group-III nitride-based semiconductor device and a method of manufacturing the same according to the first embodiment.

[0301] In the first embodiment, a substrate 101 is first provided, and a growth-limiting mask 102 having a plurality of strip-shaped opening regions 103 is formed on the substrate 101. In this embodiment, the substrate 101 is an m-plane substrate made of a group-III nitride-based semiconductor, and the misorientation of the m-plane substrate toward the c-axis is -1.0 degree.

[0302] An ELO group-III nitride layer 105 is grown on or above the substrate 101 and the growth-limiting mask 102. As shown in images (4) of Figs. 3(a) and 3(b), the ELO group-III nitride layer 105 is largely uniform and has a very smooth surface.

[0303] After the growth of the ELO group-III nitride layer 105, the substrate 101 having the layer 105 is removed from the MOCVD reactor to remove the growth-limiting mask 102. As shown in Fig. 24(b), the growth-limiting mask 102 is removed by wet etching using an etchant such as HF, BHF, etc.

[0304] Then, as shown in Fig. 24(c), a group-III nitride device layer 106 is grown on the substrate 101. At this time, the group-III nitride device layer 106 is grown on the exposed portion of the substrate 101 where the ELO group-III nitride layer 105 and the growth-limiting mask 102 have been removed, thereby creating a bottom layer 111.

[0305] After the growth of the Group-III nitride device layer 106, sometimes the surface topography deteriorates, as shown in the image (1) of Fig. 2(c). It is generally considered that the deviation from the optimized growth conditions causes the deterioration of the surface roughness. The Group-III nitride device layer 106 includes many layers, and many of them are active layers or waveguide layers, making it difficult to control the growth conditions. It is noteworthy that the excessive supply of gas to the side facets of the island-shaped Group-III nitride semiconductor layer 109 makes this deviation from the optimized conditions more serious. Due to the gas from the side facets, it is difficult to optimize the growth conditions to avoid the deterioration of the surface roughness.

[0306] Therefore, in the present invention, in order to reduce the influence of the gas at the side facets of the ELO Group-III nitride layer 105, before growing the Group-III nitride device layer 106, at least before the active layer, the growth-limiting mask 102 is removed. By doing so, the gas at the side facets of the ELO Group-III nitride layer 105 is consumed at the exposed area where the growth-limiting mask 102 has been removed in the substrate 101 before reaching the side facets of the ELO Group-III nitride layer 105, which avoids the supply of excessive gas to the side facets.

[0307] By doing so, the in-plane distribution regarding the p-type layer thickness is improved, which can increase the yield of mass production. For example, the fluctuations of the p-type layer affect the characteristics of the resulting laser diode. Generally, when forming the ridge structure of the laser diode, a part of the p-type layer is etched by a dry etching method until above the active layer. If the thickness of the p-type layer has fluctuations, then the thickness of the remaining p-type layer after dry etching will also have fluctuations. This will affect the characteristics of the laser diode. Reducing the fluctuations of the p-type layer thickness is very important for improving the yield of mass production.

[0308] In addition, it is at least preferable to remove the growth-limiting mask 102 until the growth of the p-type layer is completed, because it avoids the incorporation of decomposition atoms (such as silicon and oxygen) from the growth-limiting mask 102, which compensates for the dopants of the p-type layer.

[0309] Thereafter, the island-shaped Group-III nitride semiconductor layer 109 can be processed by the remaining steps in steps 1-14 as described above to obtain a laser diode device.

[0310] Second Embodiment

[0311] Except for the etching of the growth-limiting mask 102, the second embodiment is almost the same as the first embodiment. In the first embodiment, the growth-limiting mask 102 is completely removed, as shown in Figure 24(a) and 24(b) However, the growth-limiting mask 102 can also be at least partially removed, as shown in Figure 25(a) , 25(b) , 25(c) and 25(d) andFigure 26(a) and 26(b) as shown in FIGS. 25(a) and 25(b). In both cases, the surface of the island-shaped group III nitride semiconductor layer 109 is substantially flat.

[0312] As Figure 25(a) , 25(b) and 25(c) show, at least a portion of the growth-limiting mask 102 is removed by wet etching. Preferably, the portion of the growth-limiting mask 102 that is not covered by the island-shaped group III nitride semiconductor layer 109 is removed, while the portion of the growth-limiting mask 102 that is covered by the island-shaped group III nitride semiconductor layer 109 is retained. As in the first embodiment, the removal of the growth-limiting mask 102 reduces the excess gas supplied to the side facets of the island-shaped group III nitride semiconductor layer 109. Further, when the island-shaped group III nitride semiconductor layer 109 is removed from the substrate 101, the portion of the growth-limiting mask 102 that remains below the ELO group III nitride layer 105 is useful. As shown in FIG. 25(d), after the group III nitride device layer 106 is grown, the remaining portion of the growth-limiting mask 102 can be removed by wet etching.

[0313] Figure 26(a) and 26(b) show alternative embodiments in which at least a portion of the growth-limiting mask 102 is removed by wet etching. However, in these examples, after etching, an additional portion of the growth-limiting mask 102 that is not covered by the island-shaped group III nitride semiconductor layer 109 is retained. As with Figure 25(a) , 25(b) , 25(c) and 25(d), the removal of the growth-limiting mask 102 reduces the excess gas supplied to the side facets of the island-shaped group III nitride semiconductor layer 109. Further, when the island-shaped group III nitride semiconductor layer 109 is removed from the substrate 101, the portion of the growth-limiting mask 102 that remains below the ELO group III nitride layer 105 is useful.

[0314] Before the growth-limiting mask 102 is removed, the shape at the edge of the growth-limiting mask 102 is sharp. Thus, the remaining space after removing the mask 102 is the same shape. When the group III nitride device layer 106 is grown, due to the high-temperature conditions during growth in MOCVD, the shape of the remaining space changes from sharp to circular, as Figure 27(a) and 27(b) show. Even with the change, the island-shaped group III nitride semiconductor layer 109 can be removed. More preferably, the shape of the remaining space is sharp to precisely define the breaking point and facilitate removal.

[0315] If the growth-limiting mask 102 is retained, the growth-limiting mask 102 prevents shape transformation at the edges. As shown in FIG. 25(c), when growing the group-III nitride device layer 106, a portion of the growth-limiting mask 102 remains on the substrate 101. However, since the mask 101 remains only under the ELO group-III nitride layer 105, the decomposition of the mask 102 is extremely reduced, which reduces the possibility of compensating the p-type layer. Before removing the island group-III nitride semiconductor layer 109, the remaining mask 102 located under the ELO group-III nitride layer 105 is removed.

[0316] Third Embodiment

[0317] In the third embodiment, a GaN layer is grown as the ELO group-III nitride layer 105 on various angled substrates 101. Figure 3(c) and 3(d) Three SEM images each including various angled substrates 101 used with the island group-III nitride semiconductor layer 109. From the m-plane towards the c-plane, the range of the angled orientation in FIG. 3(c) is from 0 to +15 degrees, and the angled orientation range in FIG. 3(d) is from 0 to -28 degrees. As Figure 9(a) and 9(b) shown, the present invention can remove the strips from various angled substrates 101 without breaking the strips.

[0318] When using a semi-polar substrate 101, the same effect as in the first embodiment can be obtained.

[0319] Fourth Embodiment

[0320] In the fourth embodiment, a GaN layer is grown as the ELO group-III nitride layer 105 on a c-plane substrate 101 having two different misorientation angles. FIG. 3(e) shows an SEM image of two different misorientation angle substrates 101 with the island group-III nitride semiconductor layer 109. The method shown in Figure 8(a)-8(e) has been used to remove the island group-III nitride semiconductor layer 109.

[0321] As Figure 5(a)-5(d) shown, when using a semi-polar substrate 101, the same effect as in the first embodiment can be obtained.

[0322] Fifth Embodiment

[0323] In the fifth embodiment, a sapphire substrate is used as the hetero-substrate 101. FIG. 1(b) shows the structure of the island-shaped group-III nitride semiconductor layer 109 on the substrate 101. This structure is almost the same as that of the first embodiment except for using the sapphire substrate 101 and the buffer layer 112. The buffer layer 112 is usually used together with a group-III nitride-based semiconductor layer grown on the sapphire substrate 101. In this embodiment, the buffer layer 112 includes a nucleation layer and an n-GaN layer or an undoped GaN layer. The buffer layer 112 is grown at a low temperature of about 500 - 700 °C. The n-GaN layer or the undoped GaN layer is grown at a higher temperature of about 900 - 1200 °C. The total thickness is about 1 - 3 μm. Then, a growth-limiting mask 102 is provided on the n-GaN layer or the undoped GaN layer. The remaining processes for completing the device are the same as those in the first embodiment.

[0324] On the other hand, it is not necessary to use the buffer layer 112. For example, the growth-limiting mask 102 can be directly provided on the hetero-substrate 101. After that, the ELO group-III nitride layer 105 and / or the group-III nitride device layer 106 can be grown. In this case, the interface between the surface of the hetero-substrate 101 and the bottom surface of the ELO group-III nitride layer 105 is likely to be divided due to the hetero-interface, and the hetero-interface includes many defects.

[0325] Sixth embodiment

[0326] As Figure 28 shown, in this embodiment, the top surface of the device is mounted downward onto the heat sink 1505. This embodiment can obtain a strip 501 without edge growth, as shown in the strip of FIG. 2(h).

[0327] The image (1) of FIG. 2(d) shows a strip with edge growth having a height. Preferably, the height is 0.3 μm or less. In the present invention, edge growth is defined as follows. It is located at the edge of the strip and has a height h exceeding 0.3 μm. The height is defined as the difference in height between the center of the strip 501 and the edge of the strip 501. By doing so, the top of the strip 501 can be made flat. As Figure 28 shown, in the case of downward-connected mounting, compared with the strip 501 having edge growth, there can be a wider contact area with the heat sink 1505.

[0328] This can improve the thermal conductivity. Furthermore, more preferably, suppressing edge growth can make the p-type layer thickness uniform.

[0329] Seventh embodiment

[0330] In this embodiment, the width of the mask 102 region is changed. In the image shown in Fig. 29(a), the width of the opening region 103 is 50 μm, and the width of the mask 102 region is 100 μm. On the other hand, in the image shown in Fig. 29(b), the width of the opening region 103 is 50 μm, and the width of the mask 102 region is 50 μm.

[0331] In the image of Fig. 29(a), this contrast almost disappears. It can be seen that the contrast with the surface of the strip is a strip, which is edge growth.

[0332] The wider width of the mask 102 region will increase the gas supply to the side facets of the strip, which enhances the edge growth. The image of Fig. 29(b) is evidence of this edge growth.

[0333] Therefore, the edge growth can be controlled by designing the width of the mask 102 region. More preferably, the width of the mask 102 region is 100 μm or less. By using the present invention, the height of the edge growth can be reduced.

[0334] Eighth Embodiment

[0335] The purpose of this embodiment is to avoid the connection between the group-III nitride semiconductor layer 109 and the substrate 101 at the edge of the strip 501 after removing the growth-limiting mask 102. When the total thickness of the group-III nitride device layer 106 is relatively thick or the thickness of the growth-limiting layer 102 is relatively thin, a part of the group-III nitride device layer 106 can be connected on the substrate 101, as Figure 29(a) and 29(b) shown. The p-layer doped with Mg as a p-type dopant tends to grow side facets on the strip.

[0336] Whether the two parts are connected depends on the thickness of the group-III nitride device layer 106 after removing the growth-limiting mask 102. Therefore, the growth of the group-III nitride device layer 106 can be stopped before connecting the two parts, as shown in the image of Fig. 30(a) and the enlarged view in Fig. 30(b). More preferably, the strip 501 is removed in this way. The thickness of the p-type layer is preferably less than 1 μm.

[0337] Process Step

[0338] Figure 31is a flowchart that illustrates a method of planarizing the surface of an ELO group-III nitride layer 105 to obtain a smooth surface with island-like group-III nitride semiconductor layers 109. The island-like group-III nitride semiconductor layers 109 are formed by stopping the growth of the ELO group-III nitride layers 105 before they coalesce with each other, and then one or more group-III nitride device layers 106 are grown on or above the ELO group-III nitride layers 106. The growth-limiting mask 102 is removed before growing at least some of the group-III nitride device layers 106 in order to reduce the excessive gas supplied to the side facets of the island-like group-III nitride semiconductor layers 109. The method also includes preventing the p-type layer of the group-III nitride device layer 106 from being compensated by the decomposed n-type dopant from the growth-limiting mask 102. The steps of the method are described in more detail below.

[0339] Block 3101 represents the step of providing a substrate 101. In one embodiment, the substrate 101 is a group-III nitride-based substrate 101 (such as a GaN-based substrate 101), or a hetero-substrate 101 (such as a sapphire substrate 101). This step may also include the optional step of depositing a template layer 112 on or above the substrate 101, where the template layer 11 may include a buffer layer or an intermediate layer, such as a GaN underlying layer.

[0340] Block 3102 represents the step of forming a growth-limiting mask 102 on or above the substrate 101 (i.e., on the substrate 101 itself or on the template layer 112). The growth-limiting mask 102 is patterned to include a plurality of strip-shaped opening regions 103.

[0341] Block 3103 represents the step of growing one or more group-III nitride-based layers 105 on or above the growth-limiting mask 102 using epitaxial lateral overgrowth (ELO). This step includes stopping the growth of the ELO group-III nitride layers 105 before adjacent ELO group-III nitride layers 105 coalesce with each other.

[0342] Block 3104 represents the step of growing one or more additional group-III nitride device layers 106 on or above the ELO group-III nitride layers 105, thereby forming a strip 501. These additional group-III nitride device layers 106 together with the ELO group-III nitride layers 105 create one or more of the island-like group-III nitride semiconductor layers 109. Preferably, the group-III nitride device layers 106 do not have edge growth.

[0343] This step may include removing at least a portion of the growth limiting mask 102 after growing the ELO group III nitride layer 105 and before growing at least some of the group III nitride device layers 106, so as to obtain a smooth surface of the group III nitride device layer 106.

[0344] The group III nitride device layer 106 may include a low temperature growth layer, an indium-containing layer, an aluminum-containing layer, and / or a p-type layer, and the growth limiting mask 102 may be removed before growing the low temperature growth layer, the indium-containing layer, the aluminum-containing layer, and / or the p-type layer. The growth limiting mask 102 may be removed before growing the p-type layer to avoid compensation of the p-type layer due to decomposition of the growth limiting mask 102. The growth limiting mask 102 may also be removed before growing at least the active layer of the group III nitride device layer 106.

[0345] The growth limiting mask 102 may be removed before growing the group III nitride device layer 106 to avoid non-uniformity of the supply gas near the edge of the ELO group III nitride layer 105 by reducing the amount of supply gas near the edge of the ELO group III nitride layer 105.

[0346] The growth limiting mask 102 may be removed before growing the group III nitride device layer 106 and the growth of the group III nitride device layer 106 results in the growth of the underlying layer 111, where the growth limiting mask 102 has been removed. Preferably, the underlying layer 111 is not connected to the island-like group III nitride semiconductor layer 109. The region of the underlying layer 111 at the edge of the growth limiting mask 102 does not grow or has a slow growth rate because the edge of the growth limiting mask 102 shields the region from the supply gas. In addition, the height of the ELO group III nitride layer 105 may prevent the underlying layer 111 from growing or slow down the growth of the underlying layer 111.

[0347] The side facets of the ELO group III nitride layer 105 may form a space at the bottom region, which reduces the supply gas to the underlying layer 111, where the width of the bottom region depends on the shape of the side facets. The edge of the side facet is located outside the bottom edge line, such that the edge of the side facet reduces the supply gas, which makes the width of the bottom region longer. Alternatively, the side facet does not have an edge located outside the bottom edge line, which makes the width of the bottom region shorter. The supply gas at the side facet is consumed at the growth region before reaching the side facet of the island-like group III nitride semiconductor layer 109, which avoids supplying excessive gas to the side facet.

[0348] Block 3105 represents the step of forming one or more divided support regions 502 along bar 501. The divided support regions 502 may be formed on the first facet 505 and / or the second facet 506 of bar 501. Additionally, the divided support regions 502 may be formed on one or both sides of bar 501. The divided support regions 502 are formed with a periodic length, where each period is determined by the length of the device, and each divided support region 502 includes scribed lines. Further, the divided support regions 502 are created at the flat surface region 107 in a manner that avoids the current injection region 503.

[0349] Block 3106 represents the step of removing device 110 from substrate 101. This step may include applying polymer film 801 to bar 501 on the surface of substrate 101 using a cleaving technique to remove bar 501 from substrate 101, and this step includes mechanically separating or peeling off the group III nitride semiconductor layer 109 of the island from substrate 101. The polymer film 801 is applied to bar 501 by applying pressure to the film 801 and substrate 101 using plate 806. The method may also include changing the temperature of the film 801 and substrate 101 while applying pressure, so as to utilize the difference in the thermal coefficients between the film 801 and substrate 101 to remove bar 501 from substrate 101. This step may include dividing bar 501 into one or more devices 110 by cleaving at the divided support regions 502 formed along bar 501. This step may also include creating one or more facets 504 on each laser diode device 110.

[0350] Block 3107 represents the step of mounting each device 110 on heat sink 1505 for coating one or more facets 504 of the device 110 created by cleaving. This step also includes separating the devices 110 by dividing the heat sink 1505 at the trenches 1507 in the heat sink 1505. The heat sink 1505 may be divided before or after the lead bondings 1701, 1702 are attached to the device 110.

[0351] Block 3108 represents the resulting product of the method, namely one or more group III nitride-based semiconductor devices 110 manufactured according to the method, and the substrate 101 that has been removed from the device 110 and can be used for recycling and reuse.

[0352] Device 110 may include one or more ELO Group III nitride layers 105 grown on or above a growth-limiting mask 102 on a substrate 101, where growth of the ELO Group III nitride layers 105 is stopped before adjacent ELO Group III nitride layers 105 coalesce with each other. Device 110 may also include one or more Group III nitride device layers 106 grown on the ELO Group III nitride layers 105 and on or above the substrate 101, where at least a portion of the growth-limiting mask 102 is removed after growth of the ELO Group III nitride layers 105 and before at least some of the Group III nitride device layers 106 are grown, so as to obtain a smooth surface of the Group III nitride device layers 106.

[0353] Modification and Replacement

[0354] Various modifications and substitutions can be made without departing from the scope of the present invention.

[0355] For example, the present invention can be used for Group III nitride substrates of various orientations, which include c-plane (0001), basal non-polar m-plane {1 0 -1 0} family; and semi-polar plane families having at least two non-zero Miller indices of h, i, or k and a non-zero Miller index of l, such as the {2 0 -2 -1} plane. The semi-polar substrate of (20 -2 -1) is particularly useful because the flat ELO-grown region is wide.

[0356] In another example, the present invention is described as being used for manufacturing different optoelectronic device structures, such as light-emitting diodes (LEDs), laser diodes (LDs), Schottky barrier diodes (SBDs), or metal-oxide-semiconductor field-effect transistors (MOSFETs). The present invention can also be used for manufacturing other optoelectronic devices, such as micro-LEDs, vertical-cavity surface-emitting lasers (VCSELs), edge-emitting laser diodes (EELDs), and solar cells.

[0357] Conclusion

[0358] This results in a description of the preferred embodiments of the present invention. The foregoing details of one or more embodiments of the present invention have been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the present invention to the precise form disclosed. Given the above teachings, many modifications and variations are possible. The scope of the present invention is intended to be limited not by this detailed description but by the appended claims.

Claims

1. A method for manufacturing a semiconductor layer, comprising: preparing a plurality of epitaxial laterally overgrown (ELO) group III nitride layers grown on or above a growth-limiting mask on a substrate, wherein adjacent ELO group III nitride layers among the plurality of ELO group III nitride layers are separated from each other; removing at least a portion of the growth-limiting mask; and growing a plurality of group III nitride device layers on or above the plurality of ELO group III nitride layers and the substrate, wherein the plurality of group III nitride device layers are separated from each other; wherein: the growth-limiting mask is removed after growing the plurality of ELO group III nitride layers and before growing at least some of the plurality of group III nitride device layers; growth of the underlying layer of the growth-limiting mask that is removed occurs during the growth of the plurality of group III nitride device layers; and the height of the plurality of ELO group III nitride layers prevents the underlying layer from connecting to the ELO group III nitride layers.

2. The method according to claim 1, wherein, the plurality of group III nitride device layers include a p-type layer.

3. The method according to claim 1, wherein, at least a portion of the growth-limiting mask removed in the growth-limiting mask includes at least a portion of the growth-limiting mask not covered by the plurality of ELO group III nitride layers.

4. The method according to claim 1, wherein, the plurality of group III nitride device layers include a low-temperature growth layer, an indium-containing layer, an aluminum-containing layer, and / or a p-type layer, and the growth-limiting mask is removed before growing the low-temperature growth layer, the indium-containing layer, the aluminum-containing layer, and / or the p-type layer.

5. The method according to claim 4, wherein, the growth-limiting mask is removed before growing the p-type layer to avoid compensating the p-type layer due to decomposition of the growth-limiting mask.

6. The method according to claim 1, wherein, the growth-limiting mask is removed before growing at least one active layer of the plurality of group III nitride device layers.

7. The method according to claim 1, wherein, the ELO group III nitride layers and the group III nitride device layers together include island-shaped group III nitride semiconductor layers, and the underlying layer is not connected to the island-shaped group III nitride semiconductor layers.

8. The method according to claim 7, wherein, the plurality of island-shaped group III nitride semiconductor layers are separated from the underlying layer by a bottom region; and the width of the bottom region depends on the shape of the side facets of each island-shaped group III nitride semiconductor layer.

9. The method according to claim 8, wherein, the edges of the side facets protrude towards adjacent island-shaped group III nitride semiconductor layers, such that the edges of the side facets reduce the supply of gas to the underlying layer during the growth of the plurality of group III nitride device layers, which makes the width of the bottom region longer.

10. A semiconductor substrate manufactured by the method of claim 1.

11. A semiconductor substrate, comprising: A substrate and a plurality of island semiconductor layers located on the substrate and separated from each other by non-growth regions, wherein each of the plurality of island semiconductor layers includes a group-III nitride device layer grown on an epitaxial lateral overgrowth (ELO) group-III nitride layer, a bottom layer is formed in the non-growth region during the growth of the group-III nitride device layer, the island semiconductor layer is separated from the bottom layer through a bottom region at the semiconductor substrate, and the ELO group-III nitride layer prevents the bottom layer from connecting with the island semiconductor layer.

12. The semiconductor substrate according to claim 11, wherein, a side dividing surface of each of the island semiconductor layers has an edge protruding toward an adjacent island semiconductor layer, and the edge is located at a position away from a bottom surface of the island semiconductor layer.

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