Clock generation circuit for driving pixels

Abstract

The present invention provides a clock generation circuit for driving pixels. According to an embodiment, when the frequency of a driving clock for driving pixels in a display device reaches a target frequency, a portion of delay circuits in the delay circuits is disabled, thereby reducing power consumption for generating the driving clock.

Description

Technical Field

[0001] The present disclosure relates to a technology for generating a clock for driving a light emitting diode included in a pixel of a display device. Background Art

[0002] Description of the Prior Art

[0003] A light emitting diode (LED) panel may include one or more light emitting diodes (LEDs) in each pixel.

[0004] The data driving device for driving the LED panel can represent the image data, i.e., the grayscale value, by adjusting the amount of power supplied to the light emitting diode in each pixel. The method for adjusting the amount of power supplied to the light emitting diode may include a method for adjusting the magnitude of the voltage supplied to the light emitting diode, a method for adjusting the magnitude of the current supplied to the light emitting diode, and a method for adjusting the time of the current supplied to the light emitting diode.

[0005] The method for adjusting the time of the current supplied to the light emitting diode may be referred to as a "pulse width modulation (PWM) method". In the PWM method, the data driving device counts the driving clock, and the data driving device may supply current to the light emitting diode in each pixel until the count value reaches a specific gray value of each pixel. In addition, when the count value reaches a specific gray value, the data driving device may reset the count value, and may re-count the driving clock for the next gray value.

[0006] The data driving device may receive a data clock from the controller and may receive image data corresponding to the data clock. In addition, the data driving device may generate a driving clock using the data clock.

[0007] However, in order to generate a driving clock using a data clock, a conventional data driving device includes a phase detector (PD) and a multi-stage delay chain, wherein the delay time is adjusted by an uplink signal or a downlink signal generated by the phase detector. However, this structure may have a problem of increased power consumption. A plurality of delay cells (or delay elements) for delaying an input signal by a predetermined unit are included in the multi-stage delay chain. This is due to the fact that in the multi-stage delay chain structure, all delay cells must always be driven according to the uplink / downlink signal, so that delay cells that do not need to be operated are also driven.

[0008] In this regard, the present embodiment provides a clock generation technology capable of generating a driving clock for controlling a voltage or a current to drive a light emitting diode and reducing power consumption for generating the driving clock by suppressing driving of unnecessary delay units. Summary of the invention

[0009] Against this background, in one aspect, the present disclosure provides a technique for generating a driving clock for controlling the provision of a driving signal to a pixel from a data clock for receiving image data.

[0010] In another aspect, the present disclosure provides a technology for generating a delayed signal by delaying a window signal, generating a sub-signal having at least one pulse from the delayed signal, and generating a driving clock by combining the sub-signals.

[0011] In another aspect, the present disclosure provides a technique for generating a driving clock having a frequency corresponding to P times (where “P” is a natural number of 1 or greater) a frequency of a data clock.

[0012] In another aspect, the present disclosure provides a technique for adjusting a degree of delay until a driving clock has a target frequency, and disabling some delay circuits if the frequency of the driving clock reaches the target frequency.

[0013] In view of the above, on the one hand, the present disclosure provides a clock generating circuit, comprising: a signal delay circuit, which is configured to receive a window signal corresponding to one cycle of a data clock received together with image data, and generate a plurality of delayed signals and a plurality of inverted delayed signals by delaying the window signal; a pulse generating circuit, which is configured to generate a plurality of sub-signals by respectively combining the plurality of delayed signals and the plurality of inverted delayed signals, each sub-signal having a pulse; and a signal combining circuit, which is configured to use the plurality of sub-signals to generate a driving clock for driving pixels.

[0014] In the clock generating circuit, the signal combining circuit can generate multiple clocks by combining a part of the multiple sub-signals, can output one of the multiple clocks as the driving clock, and can output another clock of the multiple clocks as a counter clock for counting the window signal.

[0015] In the clock generating circuit, the signal combining circuit may generate the driving clock so that the driving clock has a predetermined number of pulses in one cycle of the data clock or at a high level of the window signal.

[0016] The clock generating circuit may further include a calibration initialization circuit configured to generate a driving clock masking signal for initializing the signal combining circuit, and the signal combining circuit may stop generating the driving clock for initialization according to the driving clock masking signal.

[0017] In the clock generating circuit, in case of initialization, the signal combining circuit may generate a single level signal instead of the driving clock.

[0018] The clock generation circuit may further include a calibration selection circuit configured to receive a calibration start signal for starting to generate the driving clock, and transmit the window signal or the data clock to the signal delay circuit according to the calibration start signal.

[0019] In the clock generating circuit, the signal delay circuit may delay the data clock instead of the window signal when receiving the data clock to generate the plurality of delayed signals and the plurality of inverted delayed signals.

[0020] In the clock generating circuit, the signal delay circuit may include a plurality of delay units connected in series to each other, and in order to generate one delayed signal, one delay unit among the plurality of delay units delays another delayed signal received from another delay unit by one unit.

[0021] In the clock generating circuit, the one delay unit can generate an inverted delayed signal by inverting the one delayed signal, the other delay unit can generate another inverted delayed signal by inverting the other delayed signal, and the pulse generating circuit can use the pulse generating unit inside the pulse generating circuit to generate a sub-signal by combining the one inverted delayed signal and the other delayed signal.

[0022] In the clock generating circuit, the pulse generating unit may perform an AND operation on the one delayed signal and the other inverted delayed signal to generate the one sub-signal.

[0023] In the clock generating circuit, the pulse generating circuit may include a plurality of pulse generating units, and the signal combining circuit may include a first signal combining circuit and a second signal combining circuit, wherein the first signal combining circuit is configured to generate a first clock by combining sub-signals generated by odd-numbered pulse generating units, and the second signal combining circuit is configured to generate a second clock by combining sub-signals generated by even-numbered pulse generating units.

[0024] In the clock generating circuit, the signal combining circuit may output the first clock as the driving clock and may output the second clock as a counter clock for counting the window signal.

[0025] In the clock generating circuit, the driving clock may have a frequency corresponding to N times a frequency of the data clock, where N is a natural number of 1 or more.

[0026] Another embodiment provides a clock generation circuit for generating a second clock having a target frequency, wherein the target frequency corresponds to P times the frequency of the first clock, wherein P is a natural number of 1 or greater, and the clock generation circuit may include: a signal delay circuit, configured to receive a window signal having a pulse corresponding to one cycle of the first clock, and to generate a plurality of delayed signals and a plurality of inverted delayed signals by delaying the window signal; a pulse generation circuit, configured to generate a plurality of sub-signals by respectively combining the plurality of delayed signals and the plurality of inverted delayed signals, each sub-signal having a pulse; and a signal combination circuit, configured to generate a clock using the plurality of sub-signals and output the one clock as the second clock, wherein the signal delay circuit repeatedly adjusts the delay time for the window signal until the frequency of the one clock reaches the target frequency.

[0027] In the clock generation circuit, the first clock may be a communication clock for image data, and the second clock may be a drive clock for controlling supply of a drive signal for displaying an image using the image data.

[0028] In the clock generation circuit, the signal delay circuit may include a plurality of delay units configured to generate the plurality of delayed signals. Here, when the frequency of the one clock reaches the target frequency, a portion of the plurality of delay units may be disabled, and the second clock may be generated based on the delay signals generated by the enabled delay units among the plurality of delay units.

[0029] In the clock generation circuit, the pulse generation circuit may include a plurality of pulse generation units configured to generate the plurality of sub-signals. Here, when the frequency of the one clock reaches the target frequency, a portion of the plurality of pulse generation units may be disabled, and the second clock may be generated by a combination of sub-signals generated by the enabled pulse generation units among the plurality of pulse generation units.

[0030] In the clock generating circuit, when the frequency of the one clock reaches the target frequency, a portion of the odd-numbered pulse generating units among the multiple pulse generating units may be disabled, and the second clock may be generated by a combination of sub-signals generated by the enabled pulse generating units among the odd-numbered pulse generating units.

[0031] In the clock generation circuit, the signal delay circuit may include a plurality of delay units configured to delay the window signal by a unit time to generate the plurality of delayed signals, and each delay unit may include a plurality of delay subunits configured to determine the unit time. The unit time may be determined by enabling or disabling the plurality of delay subunits.

[0032] In the clock generating circuit, the signal delay circuit may enable only a delay subunit that first receives the window signal among the plurality of delay subunits to delay the window signal by a minimum value.

[0033] As described above, according to the present embodiment, when the frequency of the driving clock reaches the target frequency, some of the delay circuits are disabled, thereby reducing power consumption for generating the driving clock.

[0034] In addition, according to the present embodiment, the clock generation device can include only digital circuits, and this allows facilitation of its design. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 is a diagram illustrating a configuration of a display device according to an embodiment;

[0036] Figure 2 is a diagram illustrating a configuration of a data driving device according to an embodiment;

[0037] Figure 3 is a diagram illustrating a configuration of a clock generation circuit according to an embodiment;

[0038] Figure 4 is a diagram illustrating waveforms of clock signals including a data clock, a first clock, a second clock, and a driving clock, and a window signal according to an embodiment;

[0039] Figure 5 is a diagram illustrating a configuration of a clock generation circuit including a detailed configuration of a signal delay circuit according to an embodiment;

[0040] Figure 6 is a diagram illustrating a configuration of a clock generation circuit including detailed configurations of a signal delay circuit and a pulse generation circuit according to an embodiment;

[0041] Figure 7 is a diagram illustrating a configuration of a clock generation circuit including detailed configurations of a first signal combination circuit and a second signal combination circuit according to an embodiment;

[0042] Figure 8 is a diagram illustrating a configuration of a clock generation circuit including a detailed configuration of a third signal combination circuit according to an embodiment;

[0043] Fig. 9is a diagram illustrating waveforms of a window signal, a delay signal, and a sub-signal according to an embodiment;

[0044] Fig.10 is a diagram illustrating waveforms of a window signal, a sub-signal, a first clock, a second clock, and a driving clock according to an embodiment;

[0045] Fig.11 is a diagram illustrating a configuration of a clock generation circuit including a detailed configuration of a calibration selection circuit and a delay disable circuit according to an embodiment;

[0046] Fig.12 is a diagram illustrating a configuration of a delay unit according to an embodiment;

[0047] Fig.13 is a diagram illustrating a detailed configuration of a front end of a delay unit according to another embodiment;

[0048] Fig.14 is a diagram illustrating a detailed configuration of a back end of a delay unit according to another embodiment; and

[0049] Fig.15 is a diagram illustrating a delay subunit according to another embodiment. DETAILED DESCRIPTION

[0050] Figure 1 is a diagram illustrating a configuration of a display device according to an embodiment.

[0051] Reference Figure 1 , the display device 100 may include a controller 110 , a data driving device 120 , a gate driving device 130 , a panel 140 , and the like.

[0052] One or more light emitting diodes (LEDs) LED may be arranged in each pixel on the panel 140. The light emitting diodes LED may be arranged in a matrix form.

[0053] The data lines DL may be arranged on the panel 140 so as to be connected in one direction (eg, in Figure 1 The gate lines GL may extend in the vertical direction of the panel 140, and the gate lines GL may be arranged on the panel 140 so as to extend in another direction (eg, in the vertical direction of the panel 140). Figure 1 In addition, one electrode (eg, cathode) of the light emitting diode LED may be connected to the data line DL, and the other electrode (eg, anode) of the light emitting diode LED may be connected to the gate line GL.

[0054] The gate driving device 130 may select one gate line GL from among the plurality of gate lines GL and may provide a specific voltage (eg, a high driving voltage VDD or a low driving voltage VSS) to the one gate line.

[0055] Furthermore, the data driving device 120 may function as a source for supplying a driving current iled to the light emitting diode LED so that current flows through the light emitting diode LED connected to the gate line GL, or may function as a sink of the driving current iled from the light emitting diode LED.

[0056] The controller 110 may transmit the image data RGB and the data clock DCLK to the data driving device 120. In addition, the data driving device 120 may receive the image data RGB corresponding to the data clock DCLK, and may control the driving current iled to be provided to each pixel according to the image data RGB.

[0057] Figure 2 is a diagram illustrating a configuration of a data driving device according to an embodiment.

[0058] Reference Figure 2 The data driving device 120 may include a data receiving circuit 210, a clock generating circuit 220, a pixel driving circuit 230, and the like.

[0059] The data receiving circuit 210 may receive the image data RGB corresponding to the data clock DCLK received from the controller. Then, the data receiving circuit 210 may extract the pixel data DP corresponding to the gray value of each pixel from the image data RGB and may transmit the pixel data to the pixel driving circuit 230.

[0060] The pixel driving circuit 230 may identify the grayscale value of each pixel included in the pixel data DP, and may adjust the amount of driving power to be provided to each pixel according to the grayscale value. For example, the pixel driving circuit 230 may increase the amount of driving power as the grayscale value increases, and may reduce the amount of driving power as the grayscale value decreases.

[0061] Assuming that the driving voltage provided to the light emitting diode arranged in each pixel is constant, the amount of driving power provided to each pixel can be determined according to the size of the driving current iled provided to each pixel. In addition, the pixel driving circuit 230 can control the grayscale value of each pixel by adjusting the size of the driving current iled provided to each pixel.

[0062] The pixel driving circuit 230 can control the size of the driving current ILED provided to each pixel by adjusting the time for providing the driving current ILED within a predetermined time. This method may be referred to as a "pulse width modulation (PWM) method". In the PWM method, the ratio of the time for providing the driving current ILED to the predetermined time is sometimes referred to as a "duty cycle", and the pixel driving circuit 230 can control the gray value of each pixel by adjusting the duty cycle. For example, if the gray value is high, the pixel driving circuit 230 may increase the duty cycle, and if the gray value is low, the pixel driving circuit 230 may reduce the duty cycle.

[0063] The pixel driving circuit 230 can use a clock to implement a PWM method. The pixel driving circuit 230 can adjust the supply time of the driving current ILED by counting the clock, thereby controlling the size of the driving current ILED. When the gray value is high, the count value of the clock increases, and therefore the duty cycle and the driving current ILED can increase. When the gray value is low, the count value of the clock decreases, and therefore the duty cycle and the driving current ILED can decrease. Here, the pixel driving circuit 230 can use the pulse of the clock to count, and can count based on the rising edge or falling edge of the pulse. In addition, the count value of the clock (the number of counts) can be equal to the gray value or proportional to the gray value.

[0064] For example, the pixel driving circuit 230 can count the clock, the count value can be compared with the gray value (or a value proportional to the gray value), and the driving current ILED can be supplied to the pixel until the count value becomes equal to the gray value (or a value proportional to the gray value). In the case of 8-bit image data and gray values ​​of 0 to 255, the count value can be between 0 and 255. In order to count the 8-bit image data, the clock can include at least 255 pulses. When the count value becomes equal to a specific value, the pixel driving circuit 230 can reset the count, and the count can be restarted to drive another pixel. At this time, the pixel driving circuit 230 needs a clock, which can be referred to as a "drive clock GCLK".

[0065] The clock generation circuit 220 can generate the drive clock GCLK using the data clock DCLK. The period of transmitting / receiving image data and the period of driving the pixels arranged on the panel must be substantially the same, or must have a constant multiple relationship. To this end, the clock generation circuit 220 can use the data clock DCLK related to the period of transmitting / receiving image data to generate the drive clock GCLK related to the period of driving the pixels.

[0066] Figure 3 is a diagram illustrating a configuration of a clock generation circuit according to an embodiment.

[0067] Reference Figure 3The clock generation circuit 220 may include a first signal combination circuit 310, a second signal combination circuit 320, a third signal combination circuit 330, a calibration selection circuit 340, a calibration initialization circuit 350, a delay disabling circuit 360, a signal delay circuit 370 and a pulse generation circuit 380.

[0068] The clock generation circuit 220 may generate a drive clock GCLK from the data clock DCLK. The data clock DCLK may be synchronized with the image data and may be received by the clock generation circuit 220. The pixel driving circuit may read out image data corresponding to the data clock DCLK. The data clock DCLK may be a communication clock for image data. The drive clock GCLK may be used to control the supply of a drive signal (e.g., a drive voltage or a drive current) for displaying image data. Here, in order to generate the drive clock GCLK, the clock generation circuit 220 may use the data clock DCLK itself, but the present disclosure is not limited thereto, and the clock generation circuit 220 may use the window signal WIN. The window signal WIN may be a signal having a pulse corresponding to one cycle of the data clock DCLK, and may be a signal as a source for generating the drive clock GCLK.

[0069] The signal delay circuit 370 may receive a delayed input signal DLY_IN from the calibration selection circuit 340. The delayed input signal DLY_IN is a signal transmitted from the calibration selection circuit 340 to the signal delay circuit 370, and may include the data clock DCLK or the window signal WIN according to the selection of the calibration selection circuit 340. The signal delay circuit 370 may receive the delayed input signal DLY_IN, that is, any one of the data clock DCLK and the window signal WIN, and may perform delay.

[0070] Therefore, the signal delay circuit 370 may receive the data clock DCLK itself or the window signal WIN having a pulse corresponding to one cycle of the data clock DCLK from the calibration selection circuit 340. The signal delay circuit 370 may generate a plurality of delay signals DLY_xx by repeatedly delaying the data clock DCLK or the window signal WIN. The signal delay circuit 370 may generate a plurality of inverted delay signals DLY_xxb by inverting the corresponding delay signals. The signal delay circuit 370 may output the plurality of delay signals DLY_xx or the plurality of inverted delay signals DLY_xxb to the pulse generation circuit 380 or the third signal combination circuit 330.

[0071] In addition, the signal delay circuit 370 may receive a delay enable signal DLY_EN from the outside. The signal delay circuit 370 may receive a delay disable signal DLY_DIS from the delay disable circuit 360. The signal delay circuit 370 may enable or turn on some of the plurality of delay cells included in the signal delay circuit according to the delay enable signal DLY_EN, and may disable or turn off some of the plurality of delay cells according to the delay disable signal DLY_DIS.

[0072] In addition, the signal delay circuit 370 can adjust the delay degree of the delayed input signal DLY_IN according to the delay control signal DLY_CTR. The signal delay circuit 370 can delay the delayed input signal DLY_IN via a plurality of delay cells connected in series therein. The more delay cells enabled by the signal delay circuit 370, the more delay cells the delayed input signal DLY_IN passes through, thereby increasing the delay. The fewer delay cells enabled by the signal delay circuit 370, the fewer delay cells the delayed input signal DLY_IN passes through, thereby reducing the delay. As described above, the delayed input signal DLY_IN is delayed by a predetermined degree each time it passes through the delay cell, and the degree to which the delayed input signal DLY_IN is delayed by each delay cell (i.e., the delay unit) can be adjusted by the delay control signal DLY_CTR.

[0073] The pulse generation circuit 380 may receive a plurality of delayed signals DLY_xx and a plurality of inverted delayed signals DLY_xxb from the signal delay circuit 370. The pulse generation circuit 380 may generate a plurality of sub-signals SUB_CK having one or more pulses by combining the plurality of delayed signals DLY_xx and the plurality of inverted delayed signals DLY_xxb. In addition, the pulse generation circuit 380 may transmit the sub-signal SUB_CK to the first signal combination circuit 310 and the second signal combination circuit 320.

[0074] In addition, the pulse generating circuit 380 can enable or disable a plurality of pulse generating units included in the pulse generating circuit via a calibration start signal CALB_ON. In addition, the pulse generating circuit 380 can enable or disable a plurality of pulse generating units via a selection signal SEL. In some cases, one of the calibration start signal CALB_ON or the selection signal SEL can disable all pulse generating units, or the calibration start signal CALB_ON can disable some pulse generating units, and the selection signal SEL can disable the remaining pulse generating units. In the latter case, the calibration start signal CALB_ON can control the enabling of the even-numbered pulse generating units, and the selection signal SEL can control the enabling of the odd-numbered pulse generating units. Therefore, the calibration start signal CALB_ON or the selection signal SEL can disable (shield) some pulse generating units, thereby reducing the power consumption of the pulse generating circuit 380.

[0075] On the other hand, the signal delay circuit 370 can repeatedly adjust the delay of the delayed input signal DLY_IN until the frequency of the drive clock GCLK reaches the target frequency. In order to use the drive clock GCLK as a drive signal (e.g., a PWM signal) for driving pixels, it is necessary to count the drive signal including a large number of pulses. Therefore, the drive clock GCLK can have a target frequency corresponding to P times the frequency of the data clock DCLK (where "P" is a natural number of 1 or higher). That is, the drive clock GCLK can be multiplied. To this end, the drive clock GCLK must have enough pulses to count the drive signal, and the frequency must be increased accordingly. The signal delay circuit 370 can adjust the delay of the delayed input signal DLY_IN until the drive clock GCLK has enough pulses or the target frequency. Until this time, the signal delay circuit 370 can repeat the adjustment of the delay of the delayed input signal DLY_IN.

[0076] In addition, when the frequency of the driving clock GCLK reaches the target frequency, some delay cells of the signal delay circuit 370 may be disabled. This is due to the fact that the disabled delay cells no longer need to operate to generate the driving clock GCLK. The enabling and disabling of the delay cells of the signal delay circuit 370 may be determined by the delay enabling signal DLY_EN and the delay disabling signal DLY_DIS.

[0077] In addition, when the frequency of the driving clock GCLK reaches the target frequency, some pulse generating units of the pulse generating circuit 380 may be disabled. This is due to the fact that the disabled pulse generating units no longer need to operate to generate the driving clock GCLK. The enabling and disabling of the pulse generating units of the pulse generating circuit 380 may be determined by the selection signal SEL and the calibration start signal CALB_ON.

[0078] The signal combination circuits 310 to 330 may combine a plurality of delayed signals DLY_xx and a plurality of inverted delayed signals DLY_xxb to generate a driving clock GCLK so that the driving clock GCLK has a predetermined number of pulses. Specifically, the signal combination circuits 310 to 330 may receive a plurality of delayed signals DLY_xx and a plurality of inverted delayed signals DLY_xxb from the signal delay circuit 370, or may receive a plurality of sub-signals SUB_CK from the pulse generation circuit 380. The first signal combination circuit 310 of the signal combination circuits 310 to 330 may receive and combine a plurality of sub-signals SUB_CK to generate a first clock CLK_1. The second signal combination circuit 320 may receive and combine a plurality of sub-signals SUB_CK to generate a second clock CLK_2. The third signal combination circuit 330 may receive and combine a plurality of delayed signals DLY_xx and a plurality of inverted delayed signals DLY_xxb to generate a third clock CLK_3.

[0079] Here, the first signal combination circuit 310 may combine a plurality of sub-signals SUB_CK generated by odd-numbered pulse generation units to generate a first clock CLK_1, and the second signal combination circuit 320 may combine a plurality of sub-signals SUB_CK generated by even-numbered pulse generation units to generate a second clock CLK_2. The third signal combination circuit 330 may generate a third clock CLK_3 having a frequency twice that of the data clock DCLK.

[0080] The signal combination circuits 310 to 330 can generate a plurality of clocks, one of which can be used as a driving clock GCLK, and another of which can be used as a counter clock for counting the window signal WIN. In the figure, the first clock CLK_1 can be used as the driving clock GCLK, and the second clock CLK_2 can be used as the counter clock.

[0081] The calibration selection circuit 340 may receive the calibration start signal CALB_ON and may start generating the driving clock GCLK. This is due to the fact that the driving clock GCLK can be generated only when the calibration selection circuit 340 transmits one of the data clock DCLK and the window signal WIN to the signal delay circuit 370. The calibration selection circuit 340 may transmit any one of the data clock DCLK and the window signal WIN to the signal delay circuit 370 according to the calibration start signal CALB_ON. If the calibration start signal CALB_ON is 1, the window signal WIN may be output, and if the calibration start signal CALB_ON is 0, the data clock DCLK may be output.

[0082] The calibration initialization circuit 350 may initialize the signal combination circuits 310 to 330 via the drive clock masking signal GCLK_MASK. The signal combination circuits 310 to 330 may be initialized by stopping the generation of the drive clock GCLK when the drive clock masking signal GCLK_MASK is received. The signal combination circuits 310 to 330 may generate a single level signal (e.g., a signal having a low level or a high level for a predetermined time) instead of generating the clocks CLK_1 to CLK_3, and may output the single level signal. The calibration initialization circuit 350 may initialize only some of the signal combination circuits 310 to 330, and in the figure, the first signal combination circuit 310 may be initialized by the calibration initialization circuit 350.

[0083] The delay disabling circuit 360 may transmit a delay disabling signal DLY_DIS to the signal delay circuit 370. The delay enabling signal DLY_EN may enable or turn on some of the plurality of delay cells included in the signal delay circuit 370. The delay disabling signal DLY_DIS may disable or turn off some of the plurality of delay cells.

[0084] The delay disabling circuit 360 can determine the number of delay units that enable or disable the signal delay circuit 370 via the frequency multiplication signal MUL_X. The frequency multiplication signal MUL_X can indicate how many times the driving clock GCLK that will eventually be generated must be multiplied compared to the data clock DCLK. Here, multiplication can be understood as increasing the frequency of the driving clock GCLK to be higher than the frequency of the data clock DCLK. If the frequency multiplication signal MUL_X has a high frequency, the driving clock GCLK must have many pulses, and the signal must be delayed a lot, so many delay units can be enabled. On the other hand, if the frequency multiplication signal MUL_X has a low frequency, the driving clock GCLK must have few pulses and the signal must be delayed a little, so fewer delay units can be enabled.

[0085] On the other hand, the clock generation circuit 220 can generate a driving clock GCLK having a target frequency corresponding to P times the frequency of the data clock DCLK (where "P" is a natural number of 1 or higher). The clock generation circuit 220 can continuously generate the first clock CLK_1 selected as the driving clock GCLK until the first clock CLK_1 has the target frequency. During this time, the clock generation circuit 220 can receive the delay control signal DLY_CTR and can control the delay of the signal delay circuit 370. If the first clock CLK_1 does not reach the target frequency, the signal delay circuit 370 can adjust the delay unit according to the delay control signal DLY_CTR. The clock generation circuit 220 can repeat this operation until the first clock CLK_1 reaches the target frequency and can then be used as the driving clock GCLK.

[0086] In addition, when the first clock CLK_1 reaches the target frequency, that is, if the first clock CLK_1 has a plurality of pulses sufficient to count the PWM signal, the signal delay circuit 370 may disable some of the plurality of internal delay units for delaying the delayed input signal DLY_IN. When some of the plurality of delay units are disabled, the power consumption of the signal delay circuit 370 may be reduced accordingly. In addition, when the first clock CLK_1 reaches the target frequency, that is, if the first clock CLK_1 has a plurality of pulses sufficient to count the PWM signal, the pulse generation circuit 380 may disable some of the plurality of internal pulse generation units for generating sub-signals by combining the delayed signal and the inverted delayed signal. When some of the plurality of pulse generation units are disabled, the power consumption of the pulse generation circuit 380 may be reduced accordingly.

[0087] Figure 4 is a diagram illustrating waveforms of clock signals including a data clock, a first clock, a second clock, and a driving clock, and a window signal according to an embodiment.

[0088] Reference Figure 4 , illustrates waveforms of the data clock DCLK, the window signal WIN, the first clock CLK_1, the second clock CLK_2, and the driving clock GCLK.

[0089] The window signal WIN may include a period T corresponding to the period T of the data clock DCLK. DCLK The corresponding pulse P WIN . Pulse P WIN It can indicate the time period during which the signal rises from a low level to a high level and then remains at the changed high level. Therefore, the pulse width of the window signal WIN can be substantially the same as the period T of the data clock DCLK. DCLK same.

[0090] On the other hand, the first clock CLK_1 and the second clock CLK_2 may be configured such that the pulse P of the first clock CLK_1 CLK_1 The pulse P of the second clock CLK_2 CLK_2 That is, the phases of the first clock CLK_1 and the second clock CLK_2 may not be consistent with each other, so the first clock CLK_1 and the second clock CLK_2 may alternate with each other. This is due to the fact that the first clock CLK_1 is generated by the odd-numbered pulse generating units of the pulse generating circuit, and the second clock CLK_2 is generated by the even-numbered pulse generating units of the pulse generating circuit. This will refer to Fig. 9 and Fig.10 Give a description.

[0091] The driving clock GCLK may be any one of the multiple clocks generated by the signal combination circuit. One of the multiple clocks generated by the signal combination circuit may be used as the driving clock GCLK, and the remaining clocks may be used as counter clocks for counting the window signal WIN. Here, the first clock CLK_1 generated by the first signal combination circuit using the multiple sub-signals of the odd-numbered pulse generation unit may be used as the driving clock. The second clock CLK_2 generated by the second signal combination circuit using the multiple sub-signals of the even-numbered pulse generation unit may be used as the counter clock. Therefore, the pulses P of the driving clock GCLK are GCLK can be connected with the pulse P of the first clock CLK_1 CLK_1 Basically the same.

[0092] Figure 5 is a diagram illustrating a configuration of a clock generation circuit including a detailed configuration of a signal delay circuit according to an embodiment.

[0093] Reference Figure 5 The signal delay circuit 370 may include a plurality of delay units (DLY2N) 501, ..., 504, 505, ..., and 543 in the signal delay circuit. The plurality of delay units 501, ..., 504, 505, ..., and 543 may be connected in series to each other in a cascade manner.

[0094] One of the delay units 501, ..., 504, 505, ... and 543 can generate a delay signal by receiving another delay signal from the previous delay unit connected in series and delaying the other delay signal by a predetermined unit. A delay signal can be delayed by a predetermined unit by a subsequent delay unit to generate another delay signal. At the same time, each delay unit can generate an inverted delay signal by digitally inverting the delay signal. The inverted delay signal can have a logic level opposite to the delay signal.

[0095] exist Figure 5 , the fourth delay unit 504 may generate a fourth delayed signal DLY_04, and the fourth delayed signal may be transmitted to the fifth delay unit 505. At the same time, the fourth delay unit 504 may generate a fourth inverted delayed signal DLY_04b. Subsequently, the fifth delay unit 505 may delay the fourth delayed signal DLY_04 to generate a fifth delayed signal DLY_05, and the fifth delayed signal DLY_05 may be transmitted to the sixth delay unit (not shown). At the same time, the fifth delay unit 505 may generate a fifth inverted delayed signal DLY_05b. The above operations may be performed continuously through the first delay unit 501 to the 43rd delay unit 543. In addition, the signal delay circuit 370 may transmit a plurality of delayed signals DLY_xx and a plurality of inverted delayed signals DLY_xxb to the pulse generation circuit 380.

[0096] In addition, the plurality of delay units 501, ..., 504, 505, ... and 543 may receive a delay control signal DLY_CTR for adjusting the delay unit. The delay control signal DLY_CTR may adjust the delay unit of each delay unit according to data included in the delay control signal DLY_CTR.

[0097] On the other hand, the plurality of delay units 501, ..., 504, 505, ... and 543 may also include an AND gate AND between the delay units. The AND gate AND may be used to connect or disconnect the corresponding delay unit according to the logic values ​​of the delay enable signal DLY_EN and the delay disable signal DLY_DIS. The AND gate AND may receive the delay enable signal DLY_EN and the delay disable signal DLY_DIS according to its position.

[0098] For example, the AND gate AND connected to the first delay unit 501 to the third delay unit (not shown) can receive the delay enable signal DLY_EN, and the AND gate AND connected to the fourth delay unit 504 to the 43rd delay unit 543 can receive the delay disable signal DLY_DIS. If the delay enable signal DLY_EN has a logic value of 1, the first delay unit 501 to the fourth delay unit 504 can be enabled and then electrically connected to each other. If the delay enable signal DLY_EN has a logic value of 0, the first delay unit 501 to the fourth delay unit 504 can be disabled and then disconnected from each other. In addition, if the delay disable signal DLY_DIS has a logic value of 1, the fifth delay unit 505 to the 43rd delay unit 543 can be enabled and then connected to each other. If the delay disable signal DLY_DIS has a logic value of 0, the fifth delay unit 505 to the 43rd delay unit 543 can be disabled and then disconnected from each other.

[0099] Figure 6is a diagram illustrating a configuration of a clock generation circuit including detailed configurations of a signal delay circuit and a pulse generation circuit according to an embodiment.

[0100] Reference Figure 6 , the pulse generating circuit 380 may include a plurality of pulse generating units 601, ..., 630, 631, ..., and 642 in the pulse generating circuit. The plurality of pulse generating units 601, ..., 630, 631, ..., and 642 may be independently configured without being connected to each other, and may generate a plurality of sub-signals SUB_CK1, ..., SUB_CK30, SUB_CK31, ..., and SUB_CK42.

[0101] One of the plurality of pulse generating units 601, ..., 630, 631, ... and 642 can receive a delayed signal and an inverted delayed signal from two or more delay units in the plurality of delay units 501, ..., 504, 505, ... and 543. One pulse generating unit can generate a sub-signal by combining the delayed signal and the inverted delayed signal. In order to combine the delayed signal and the inverted delayed signal, one pulse generating unit can perform an AND operation using an AND gate AND. Then, one sub-signal can have one or more pulses. The sub-signals generated by the respective pulse generating units can have the same number of pulses, but their phases can be different from each other.

[0102] exist Figure 6 , the first pulse generating unit 601 may receive and combine the first delayed signal DLY_01 and the second inverted delayed signal DLY_02b. The first pulse generating unit 601 may generate the first sub-signal SUB_CK1 by performing an AND operation on the first delayed signal DLY_01 and the second inverted delayed signal DLY_02b. Similarly, the 30th pulse generating unit 630, the 31st pulse generating unit 631, and the 42nd pulse generating unit 642 may also generate the 30th sub-signal SUB_CK30, the 31st sub-signal SUB_CK31, and the 42nd sub-signal SUB_CK42 by performing an AND operation on the delayed signal and the inverted delayed signal, respectively.

[0103] On the other hand, the plurality of pulse generating units 601, ..., 630, 631, ... and 642 can enable or disable some or all of the plurality of pulse generating units included in the pulse generating units by the selection signal SEL and the calibration start signal CALB_ON. Here, the selection signal SEL can enable or disable the odd-numbered pulse generating units. The calibration start signal CALB_ON can enable or disable the even-numbered pulse generating units.

[0104] In addition, the plurality of pulse generating units 601, ..., 630, 631, ..., and 642 may perform an AND operation on the selection signal SEL and the calibration start signal CALB_ON as well as the delay signal and the inverted delay signal. Therefore, some or all of the plurality of pulse generating units 601, ..., 630, 631, ..., and 642 may be enabled or disabled according to the logic values ​​of the selection signal SEL and the calibration start signal CALB_ON.

[0105] Figure 7 is a diagram illustrating a configuration of a clock generation circuit including detailed configurations of a first signal combination circuit and a second signal combination circuit according to an embodiment.

[0106] Reference Figure 7 , the first signal combination circuit 310 can generate the first clock CLK_1 by combining some of the multiple sub-signals, and the second signal combination circuit 320 can generate the second clock CLK_2 by combining some of the multiple sub-signals. The first signal combination circuit 310 and the second signal combination circuit 320 may be collectively referred to as a “signal combination circuit”.

[0107] For example, the pulse generation circuit 380 may include M pulse generation units (where "M" is a natural number of 2 or more). Then, the first signal combination circuit 310 may generate the first clock CLK_1 by combining the sub-signals generated by the X-th pulse generation unit (where "X" is an odd number less than or equal to M). The second signal combination circuit 320 may generate the second clock CLK_2 by combining the sub-signals generated by the Y-th pulse generation unit (where "Y" is an even number less than or equal to M).

[0108] exist Figure 7 , the first pulse generating unit 601 and the 31st pulse generating unit 631 are illustrated as odd-numbered pulse generating units, and the 30th pulse generating unit 630 and the 42nd pulse generating unit 642 are illustrated as even-numbered pulse generating units. In addition, the 1st, 3rd, 5th, ... and 41st sub-signals SUB_CK1, 3, 5, ... and 41 are illustrated as odd-numbered sub-signals generated by odd-numbered pulse generating units, and the 2nd, 4th, 6th, ... and 42nd sub-signals SUB_CK2, 4, 6, ... and 42 are illustrated as even-numbered sub-signals generated by even-numbered pulse generating units.

[0109] Then, the signal combination circuit may generate a clock by combining the plurality of sub-signals. The signal combination circuit may perform an OR operation on the plurality of sub-signals to combine the plurality of sub-signals.

[0110] For example, the first signal combination circuit 310 may receive the 1st, 3rd, 5th, ... and 41st sub-signals SUB_CK1, 3, 5, ... and 41 as odd-numbered sub-signals, and may perform an OR operation on these sub-signals. Since each sub-signal has one or more pulses with different phases, a first clock CLK_1 with multiple pulses may be generated by combining multiple sub-signals. Similarly, the second signal combination circuit 320 may receive the 2nd, 4th, 6th, ... and 42nd sub-signals SUB_CK2, 4, 6, ... and 42 as even-numbered sub-signals, and may perform an OR operation on these sub-signals. Since each sub-signal has one or more pulses with different phases, a second clock CLK_2 with multiple pulses may be generated by combining multiple sub-signals. Then, the first clock CLK_1 may be used as a drive clock GCLK, and the second clock CLK_2 may be used as a counter clock.

[0111] On the other hand, the first signal combination circuit 310 may receive the driving clock masking signal GCLK_MASK so as to mask the first signal combination circuit 310. Here, the first signal combination circuit 310 may perform an OR operation on the driving clock masking signal GCLK_MASK. If the logic value of the driving clock masking signal GCLK_MASK is 1, the first clock CLK_1 may output a single level. That is, the first signal combination circuit 310 may be initialized. This initialization operation may be performed in advance before generating the driving clock GCLK.

[0112] Figure 8 is a diagram illustrating a configuration of a clock generation circuit including a detailed configuration of a third signal combination circuit according to the embodiment.

[0113] Reference Figure 8 , the third signal combination circuit 330 can generate the third clock CLK_3 by combining some of the plurality of sub-signals. The first signal combination circuit 310, the second signal combination circuit 320, and the third signal combination circuit 330 can be collectively referred to as a “signal combination circuit”.

[0114] Similar to the first signal combination circuit and the second signal combination circuit, the third signal combination circuit 330 can also generate the third clock CLK_3 by combining multiple sub-signals. However, the third signal combination circuit 330 can only receive and combine some specific delayed signals and inverted delayed signals. For example, this is due to the fact that when the frequency of the driving clock GCLK is not much higher than the frequency of the data clock DCLK, it is not necessary to generate many sub-signals when generating countless delayed signals. That is, even if there are some delayed signals and inverted delayed signals to generate the driving clock GCLK, multiple pulses sufficient to count the PWM signal can be generated. Therefore, if the frequency of the driving clock GCLK is only twice the frequency of the data clock DCLK, the third signal combination circuit 330 can generate the clock by combining the delayed signal and the inverted signal.

[0115] exist Figure 8 , the third signal combination circuit 330 can generate one sub-signal by performing an AND operation on the first delayed signal DLY_01 and the fourth inverted delayed signal DLY_04b, and can generate another sub-signal by performing an AND operation on the first inverted delayed signal DLY_01b and the fourth delayed signal DLY_04. One sub-signal and another sub-signal may have pulses with different phases from each other. The third signal combination circuit 330 can generate a third clock CLK_3 by performing an OR operation on one sub-signal and another sub-signal.

[0116] Fig. 9 2 is a diagram illustrating waveforms of a window signal, a delay signal, and a sub signal according to an embodiment.

[0117] Reference Fig. 9 , the window signal WIN, the delay signals DLY_01 to DLY_43, and the sub-signals SUB_CK1 and SUB_CK2 may have different phases. The delay signals DLY_01 to DLY_43 may be generated at any time when the window signal WIN is repeatedly delayed. The sub-signals SUB_CK1 and SUB_CK2 may have one or more pulses by a combination of the delay signals DLY_01 to DLY_43 and their inverted signals.

[0118] When the window signal WIN passes through the first delay unit of the signal delay circuit, the window signal WIN may be delayed by t1 to generate a first delayed signal DLY_01. The first delayed signal DLY_01 may have a phase difference of t1 with the window signal WIN.

[0119] When the first delayed signal DLY_01 passes through the second delay unit of the signal delay circuit, the first delayed signal DLY_01 may be delayed by t2 to generate a second delayed signal DLY_02. The second delayed signal DLY_02 may have a phase difference of t2 with the first delayed signal DLY_01.

[0120] Similarly, the second delayed signal DLY_02 may be delayed by t3 to generate a third delayed signal DLY_03, and the third delayed signal DLY_03 may be delayed by t4 to generate a fourth delayed signal DLY_04. When the window signal WIN passes through all delay units of the signal delay circuit, a 43rd delayed signal DLY_43 may be generated eventually.

[0121] Here, the delay time t1 to t4 of each delay signal may correspond to the delay unit of the first delay unit to the fourth delay unit. The delay units of each delay unit may be the same or different from each other. Preferably, since a clock having a pulse at a predetermined interval must be generated, the delay units of each delay unit may be the same. The delay unit of each delay unit may be determined by a delay control signal received from the outside.

[0122] On the other hand, a sub-signal may be generated by a combination of a delayed signal and an inverted delayed signal. For example, the first sub-signal SUB_CK1 may be generated by performing an AND operation on the first delayed signal DLY_01 and the second inverted delayed signal (not shown) (the inverted signal of the second delayed signal DLY_02). Then, the first sub-signal SUB_CK1 may be generated to have a pulse at a position where the first delayed signal DLY_01 and the second inverted delayed signal (not shown) overlap.

[0123] Similarly, the second sub-signal SUB_CK2 may be generated by performing an AND operation on the second delayed signal DLY_02 and the third inverted delayed signal (not shown) (the inverted signal of the third delayed signal DLY_03). Then, the second sub-signal SUB_CK2 may be generated as a pulse having a position where the second delayed signal DLY_02 and the third inverted delayed signal (not shown) overlap.

[0124] Fig.10 2 is a diagram illustrating waveforms of a window signal, a sub signal, a first clock, a second clock, and a driving clock according to an embodiment.

[0125] Reference Fig.10, the window signal WIN and the sub-signals SUB_CK1, SUB_CK2, SUB_CK3, and SUB_CK4 may have different phases. The sub-signals SUB_CK1, SUB_CK2, SUB_CK3, and SUB_CK4 may include at least one pulse. Since the sub-signals SUB_CK1, SUB_CK2, SUB_CK3, and SUB_CK4 are generated by combining delayed signals, the pulses of the respective sub-signals may have different phases.

[0126] For example, the first sub-signal SUB_CK1 may be generated by performing an AND operation on the first delayed signal and the second inverted delayed signal, and may be delayed by t1 compared to the window signal WIN. The second sub-signal SUB_CK2 may be generated by performing an AND operation on the second delayed signal and the third inverted delayed signal, and may be delayed by t2 compared to the first sub-signal SUB_CK1. The third sub-signal SUB_CK3 may be generated by performing an AND operation on the third delayed signal and the fourth inverted delayed signal, and may be delayed by t3 compared to the second sub-signal SUB_CK2. The fourth sub-signal SUB_CK4 may be generated by performing an AND operation on the fourth delayed signal and the fifth inverted delayed signal, and may be delayed by t4 compared to the third sub-signal SUB_CK3.

[0127] On the other hand, the first clock CLK_1 and the second clock CLK_2 may be generated by a combination of a plurality of sub-signals. Here, only a portion of the sub-signals may be used to generate the clocks instead of using all the sub-signals.

[0128] For example, the first signal combination circuit may receive an odd-numbered sub-signal from an odd-numbered pulse generation unit of the pulse generation circuit, and may combine only the odd-numbered sub-signals, thereby generating the first clock CLK_1. Therefore, the first clock CLK_1 may have a pulse at the same position as a pulse of the first sub-signal SUB_CK1, and may also have a pulse at the same position as a pulse of the third sub-signal SUB_CK3. In addition, the second signal combination circuit may receive an even-numbered sub-signal from an even-numbered pulse generation unit of the pulse generation circuit, and may combine only the even-numbered sub-signals, thereby generating the second clock CLK_2. Therefore, the second clock CLK_2 may have a pulse at the same position as a pulse of the second sub-signal SUB_CK2, and may also have a pulse at the same position as a pulse of the fourth sub-signal SUB_CK4.

[0129] One of the first clock CLK_1 and the second clock CLK_2 can be used as the driving clock GCLK. Fig.10In the embodiment of the present invention, the first clock CLK_1 having the pulses of the odd-numbered sub-signals may be used as the driving clock GCLK. Therefore, the driving clock GCLK may be the same as the first clock CLK_1.

[0130] Fig.11 is a diagram illustrating a configuration of a clock generation circuit including a detailed configuration of a calibration selection circuit and a delay disable circuit according to an embodiment.

[0131] Reference Fig.11 The calibration selection circuit 340 may include a multiplexer MUX and an AND gate AND in the calibration selection circuit. The calibration selection circuit 340 may receive the data clock DCLK, the window signal WIN, and the calibration start signal CALB_ON through the multiplexer MUX. The calibration selection circuit 340 may select the window signal WIN or the data clock DCLK according to the calibration start signal CALB_ON.

[0132] In addition, the calibration selection circuit 340 may receive the delay enable signal DLY_EN and the output of the multiplexer MUX through the AND gate AND. The calibration selection circuit 340 may output or not output the data clock DCLK or the window signal WIN to the signal delay circuit 370 according to the delay enable signal DLY_EN.

[0133] On the other hand, the delay disabling circuit 360 may include an AND gate AND in the delay disabling circuit. The delay disabling circuit 360 may generate a delay disabling signal DLY_DIS through the AND gate AND. The delay disabling circuit 360 may output a result of performing an AND operation on the logic values ​​of the frequency multiplication signal MUL_X and the delay enabling signal DLY_EN as the delay disabling signal DLY_DIS.

[0134] Fig.12 is a diagram illustrating a configuration of a delay unit according to an embodiment.

[0135] Reference Fig.12 , the delay unit may include one or more delay subunits 1201 to 1232, a delay masking circuit 1290, and a multiplexer MUX. The delay unit may delay the delayed input signal DLY_IN through the delay subunits 1201 to 1232. One delay unit may receive a window signal of the delayed input signal DLY_IN, and may delay the window signal by one unit. Another delay unit may continuously delay the window signal that has been delayed by one unit. Here, the delay subunits 1201 to 1232 may determine the one unit, and the one unit may be determined by enabling or disabling some of the delay subunits 1201 to 1232 by the delay masking circuit 1290.

[0136] For example, in the case of the first delay unit 501, the delay subunits 1201 to 1232 may receive a delayed input signal DLY_IN. The delayed input signal DLY_IN may be a window signal or a data clock. Here, the following description will be made under the assumption that the window signal is the delayed input signal DLY_IN. The first delay subunit 1201 may generate a first small delay signal by delaying the window signal. The first small delay signal may be transmitted to the first input terminal of the multiplexer MUX. Subsequently, the second delay subunit 1202 may generate a second small delay signal by delaying the first small delay signal. The second small delay signal may be transmitted to the second input terminal of the multiplexer MUX. The remaining delay subunits may also operate in the same manner. Finally, the 32nd delay subunit 1232 may generate a 32nd small delay signal by delaying the 31st small delay signal, and the 32nd small delay signal may be transmitted to the 32nd input terminal of the multiplexer MUX. When the window signal passes through each delay subunit, the window signal may be delayed longer. When the window signal passes through the last delay subunit (e.g., the 32nd delay subunit 1232), the window signal is delayed by the maximum value that can be delayed by the first delay unit 501. On the other hand, when the window signal passes through only the first delay subunit (e.g., the first delay subunit 1201), the window signal is delayed by the minimum value that can be delayed by the first delay unit 501. The multiplexer MUX can select one of the first to 32nd small delay signals according to the delay control signal DLY_CTR.

[0137] If the first delay unit 501 does not delay the window signal by a maximum value, that is, if the first delay unit 501 outputs a small delay signal other than the 32nd small delay signal as the first delay signal DLY_01, the delay masking circuit 1290 may disable some of the delay subunits 1201 to 1232.

[0138] For example, if the first delay unit 501 outputs the second small delay signal as the first delay signal DLY_01, the delay masking circuit 1290 may disable the third delay subunit (not shown) to the 32nd delay subunit 1232. The delay masking circuit 1290 may receive the delay control signal DLY_CTR, and may enable or disable the delay subunits 1201 to 1232 according to the delay control signal DLY_CTR. At the same time, the multiplexer MUX may also receive the delay control signal DLY_CTR, and may output one of the first small delay signal to the 32nd small delay signal as the first delay signal DLY_01 according to the delay control signal DLY_CTR.

[0139] As described above, each delay unit can adjust the delay unit used to delay the signal according to the delay control signal DLY_CTR. This can be achieved by enabling or disabling some of the delay subunits in the corresponding delay unit. Therefore, the user can easily set the delay unit, and the power consumption of the components not used for delay can be reduced.

[0140] Fig.13 is a diagram illustrating a detailed configuration of a front end of a delay unit according to another embodiment, and Fig.14 is a diagram illustrating a detailed configuration of a back end of a delay unit according to another embodiment.

[0141] Reference Fig.13 and Fig.14 , a delay unit according to another embodiment of the present disclosure may include multiple delay sub-units capable of extending the delay. A delay sub-unit included in a delay unit can extend or reduce the degree of small delay. Here, for ease of explanation, the delay of a delay unit may be referred to as a "large delay", and the delay of a delay sub-unit may be referred to as a "small delay". That is, the large delay may be understood as the degree to which the delayed input signal DLY_IN is to be delayed when it passes through a delay unit, and the small delay may be understood as the degree to which the delayed input signal DLY_IN is to be delayed when it passes through a delay sub-unit. A delay sub-unit may include an AND gate AND, multiple micro-delay units DL2, and a multiplexer MUX in the delay sub-unit to extend or reduce the small delay. Fig.13 Only three delay sub-units included in the front end of the delay unit are illustrated, and Fig.14 Only two delay sub-units included in the back end of the delay unit are illustrated.

[0142] For example, the second delay subunit 1302 can receive a first small delay signal from the first delay subunit 1301. The first small delay signal can pass through an AND gate AND, a plurality of micro-delay units DL2, and a multiplexer MUX. The second delay subunit 1302 can delay the first small delay signal by a small delay to generate a second small delay signal. Here, in order to adjust the degree of small delay, the second delay subunit 1302 can use only one micro-delay unit DL2 or two or more micro-delay units DL2 to delay the first small delay signal. The more micro-delay units DL2 the first small delay signal passes through, the longer the signal is delayed. In the accompanying drawings, only two micro-delay units DL2 can be used. The multiplexer MUX of the first delay subunit 1301 can select the first delay signal that has passed through one micro-delay unit DL2 or the first delay signal that has passed through two micro-delay units DL2.

[0143] Furthermore, the second delay subunit 1302 may receive the delay extension signal DLY_EXT and may select one of the first delayed signal having passed through one micro delay unit DL2 and the first delayed signal having passed through two micro delay units DL2 according to the delay extension signal DLY_EXT.

[0144] In addition, each delay sub-unit may receive a masking signal through an inverter logic gate from the delay masking circuit 1290. The delay sub-unit receiving the masking signal may be enabled or disabled.

[0145] Fig.15 is a diagram illustrating a delay subunit according to another embodiment.

[0146] Reference Fig.15 According to another embodiment, only the delay cell that initially receives the delayed input signal DLY_IN among the delay cells may be enabled, and the remaining delay cells may be disabled. The signal delay circuit may enable only the first delay cell so as to delay the delayed input signal DLY_IN (window signal or data clock) by a minimum value.

[0147] For example, the first delay subunit 1501 may first receive the delayed input signal DLY_IN. The first delay subunit 1501 may include a plurality of micro-delay units DL2 and a multiplexer MUX. The micro-delay unit DL2 may delay the delayed input signal DLY_IN, and the degree of delay of the delayed input signal DLY_IN may vary according to the number of micro-delay units DL2 used. Fig.15 In the embodiment, two micro delay units DL2 and three micro delay units DL2 may be included in the first delay sub-unit 1501. The delayed input signal DLY_IN is delayed longer when passing through three micro delay units DL2 than when passing through two micro delay units DL2.

[0148] In addition, the first delay subunit 1501 may receive a minimum delay signal DLY_MIN, and may select one of a signal that has passed through two micro delay units DL2 and a signal that has passed through three micro delay units DL2 according to the minimum delay signal DLY_MIN. The minimum delay signal DLY_MIN is a signal for driving only the first delay unit, and may control the first delay unit 501 to delay the signal by a minimum value. At the same time, all remaining delay subunits including the second delay subunit 1502 may be disabled.

[0149] CROSS-REFERENCE TO RELATED APPLICATIONS

[0150] This application claims priority to Korean Patent Application No. 10-2020-0055908, filed on May 11, 2020, which is hereby incorporated by reference in its entirety.

Claims

1. A clock generation circuit, comprising: a signal delay circuit configured to receive a window signal corresponding to one cycle of a data clock received together with image data, and to generate a plurality of delay signals and a plurality of inverse delay signals by delaying the window signal; a pulse generating circuit configured to generate a plurality of sub-signals each having one pulse by respectively combining the plurality of delayed signals and the plurality of inverted delayed signals; and a signal combining circuit configured to generate a driving clock for driving a pixel using the plurality of sub-signals, The signal delay circuit includes a plurality of delay units configured to generate the plurality of delayed signals. When the frequency of the driving clock reaches the target frequency, a portion of the delay units among the plurality of delay units are disabled.

2. The clock generation circuit according to claim 1, wherein: The signal combining circuit generates a plurality of clocks by combining a part of the plurality of sub-signals, outputs one of the plurality of clocks as the driving clock, and outputs another of the plurality of clocks as a counter clock for counting the window signal.

3. The clock generation circuit according to claim 1, wherein: The signal combining circuit generates the driving clock so that the driving clock has a predetermined number of pulses in one cycle of the data clock or at a high level of the window signal.

4. The clock generating circuit according to claim 1, further comprising a calibration initialization circuit, wherein the calibration initialization circuit is configured to generate a driving clock masking signal for initializing the signal combining circuit, wherein: The signal combination circuit stops generating the driving clock for initialization according to the driving clock masking signal.

5. The clock generation circuit according to claim 4, wherein: In case of initialization, the signal combining circuit generates a single-level signal instead of the driving clock.

6. The clock generating circuit according to claim 1, further comprising a calibration selection circuit, wherein the calibration selection circuit is configured to receive a calibration start signal for starting to generate the driving clock, and transmit the window signal or the data clock to the signal delay circuit according to the calibration start signal.

7. The clock generation circuit according to claim 6, wherein: The signal delay circuit delays the data clock instead of the window signal when receiving the data clock to generate the plurality of delayed signals and the plurality of inverted delayed signals.

8. The clock generation circuit according to claim 1, wherein: The signal delay circuit includes a plurality of delay units connected in series to each other, wherein, in order to generate one delayed signal, one delay unit among the plurality of delay units delays another delayed signal received from another delay unit by one unit.

9. The clock generation circuit according to claim 8, wherein: The one delay unit generates an inverted delayed signal by inverting the one delayed signal, the other delay unit generates another inverted delayed signal by inverting the other delayed signal, and the pulse generating circuit generates a sub-signal by combining the one inverted delayed signal and the other delayed signal using the pulse generating unit inside the pulse generating circuit.

10. The clock generation circuit according to claim 9, wherein: The pulse generating unit performs an AND operation on the one delayed signal and the other inverted delayed signal to generate the one sub-signal.

11. The clock generation circuit according to claim 9, wherein: The pulse generating circuit includes a plurality of pulse generating units, and Wherein, the signal combination circuit includes a first signal combination circuit and a second signal combination circuit, the first signal combination circuit is configured to generate a first clock by combining sub-signals generated by odd-numbered pulse generation units, and the second signal combination circuit is configured to generate a second clock by combining sub-signals generated by even-numbered pulse generation units.

12. The clock generation circuit according to claim 11, wherein: The signal combining circuit outputs the first clock as the driving clock and outputs the second clock as a counter clock for counting the window signal.

13. The clock generation circuit according to claim 1, wherein: The driving clock has a frequency corresponding to N times a frequency of the data clock, where N is a natural number of 1 or more.

14. A clock generation circuit for generating a second clock having a target frequency, the target frequency corresponding to P times the frequency of the first clock, wherein: P is a natural number of 1 or greater, and the clock generation circuit includes: a signal delay circuit configured to receive a window signal having a pulse corresponding to one cycle of the first clock, and generate a plurality of delayed signals and a plurality of inverted delayed signals by delaying the window signal; a pulse generating circuit configured to generate a plurality of sub-signals each having one pulse by respectively combining the plurality of delayed signals and the plurality of inverted delayed signals; and a signal combining circuit configured to generate one clock using the plurality of sub-signals and output the one clock as the second clock, wherein the signal delay circuit repeatedly adjusts the delay time for the window signal until the frequency of the one clock reaches the target frequency, The signal delay circuit includes a plurality of delay units configured to generate the plurality of delayed signals. When the frequency of the one clock reaches the target frequency, a portion of the delay units in the plurality of delay units are disabled, and The first clock is a communication clock for image data.

15. The clock generation circuit according to claim 14, wherein: The second clock is a driving clock for controlling supply of a driving signal for displaying an image using the image data.

16. The clock generation circuit according to claim 14, wherein: The second clock is generated based on a delay signal generated by an enabled delay cell among the plurality of delay cells.

17. The clock generation circuit according to claim 14, wherein: The pulse generating circuit includes a plurality of pulse generating units configured to generate the plurality of sub-signals, When the frequency of the one clock reaches the target frequency, a portion of the plurality of pulse generating units are disabled, and the second clock is generated by a combination of sub-signals generated by enabled pulse generating units among the plurality of pulse generating units.

18. The clock generation circuit according to claim 17, wherein: When the frequency of the one clock reaches the target frequency, a portion of odd-numbered pulse generating units among the plurality of pulse generating units are disabled, and the second clock is generated by a combination of sub-signals generated by enabled pulse generating units among the odd-numbered pulse generating units.

19. The clock generation circuit according to claim 14, wherein: The signal delay circuit includes a plurality of delay units configured to delay the window signal by a unit time to generate the plurality of delayed signals. Each delay unit includes a plurality of delay subunits configured to determine the unit time. The unit time is determined by enabling or disabling the plurality of delay sub-units.

20. The clock generation circuit according to claim 19, wherein: The signal delay circuit enables only a delay subunit that first receives the window signal among the plurality of delay subunits to delay the window signal by a minimum value.

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