Multi-channel high-precision PAF signal synchronous acquisition system and method

Abstract

The invention discloses a multichannel high-precision PAF signal synchronous acquisition system and a multichannel high-precision PAF signal synchronous acquisition method, and relates to the technical field of phased array signal acquisition and processing, the multichannel high-precision PAF signal synchronous acquisition system is characterized in that a hydrogen atomic clock time-frequency distribution module is in signal connection with a plurality of signal acquisition processing boards, and each signal acquisition processing board comprises a double-loop phase determination clock circuit and an RFSoC circuit; and the double-loop phase determination clock circuit is in signal connection with the RFSoC circuit. The time-frequency distribution module adopts a time-frequency signal output by a hydrogen atomic clock as a reference, so that the synchronization precision is ensured; the clock architecture of the acquisition processing board card adopts a phase determination mode, so that a Tile clock and a PL logic clock in the board are strictly in phase with an external input reference clock, and ADC acquisition synchronization of all channels is ensured; a phase clock circuit design is determined by adopting double loops, and all output clocks and an input reference clock keep a strict phase relationship; the system adopts a three-step synchronization process, so that the synchronous acquisition of hundreds of paths of PAF signals reaches the ps-level precision.

Description

Technical Field

[0001] The present invention relates to the technical field of phased array signal acquisition and processing, and more specifically, to a multi-channel high-precision PAF signal synchronous acquisition system and method. Background Art

[0002] A phased array (PAF) receiver can increase the observation field of view of a radio telescope and form a continuous sky coverage, which is a cutting-edge tool for radio astronomy to carry out sky surveys. The digital beamformer is the core of PAF signal processing and the basis for realizing the fast electronic scanning of the phased array antenna and forming multiple synchronous beams. Its basic principle is to adjust the phase of the signals within the array so that the phase of the element signals in a specific direction is aligned, and then add the signals within the array to obtain a beam in a fixed direction. Processing the array signals in multiple directions can form multiple beams.

[0003] To improve the signal acquisition fidelity and reduce the fluctuations brought by factors such as environmental temperature changes in the transmission link, the digital beamformer uses highly integrated and high-performance chips to directly acquire radio frequency signals at the receiver end, and then transmits them to a high-performance computing center through a high-speed Ethernet network for digital beamforming.

[0004] Digital beamforming has high requirements for the quality of the acquired element signals and needs to ensure that the phases of the acquired signals are highly consistent. If the signals in each channel are not synchronized during acquisition, it will bring phase deviation between channels, resulting in inaccurate beam pointing and unable to be compensated by algorithms. Therefore, the high-precision synchronous acquisition of signals between array channels is crucial. With the increase in the number of PAF elements and bandwidth in the new generation, it poses a greater challenge to the high-fidelity acquisition of signals. Due to the large number of PAF elements, multiple boards are generally required for acquisition, and the board often consists of multiple groups of analog-to-digital converters (ADCs) internally. It is very difficult to ensure that each signal is acquired by the ADC at the same moment.

[0005] Therefore, how to propose a multi-channel high-precision PAF signal synchronous acquisition system and method, perform high-precision time-frequency signal distribution and phase-zero-delay clock frequency doubling design for the PAF system, and ensure the synchronous acquisition of multi-channel signals within the signal acquisition board and between acquisition boards is an urgent problem for those skilled in the art. Summary of the Invention

[0006] In view of this, the present invention provides a multi-channel high-precision PAF signal synchronous acquisition system and method. Aiming at the characteristics of the PAF system with a large number of signal channels and high rates, through high-precision time-frequency signal distribution and phase-zero-delay clock frequency doubling design for the PAF system, it ensures the synchronous acquisition of multi-channel signals within the signal acquisition board and between acquisition boards. To achieve the above object, the present invention adopts the following technical solutions:

[0007] A multi-channel high-precision PAF signal synchronous acquisition system, comprising: a signal acquisition and processing board and a hydrogen atomic clock time-frequency distribution module, the hydrogen atomic clock time-frequency distribution module is signal-connected to a plurality of signal acquisition and processing boards, the signal acquisition and processing board includes a dual-loop phase-determining clock circuit and an RFSoC circuit, and the dual-loop phase-determining clock circuit and the RFSoC circuit are signal-connected.

[0008] Optionally, m ADCs are integrated inside the RFSoC circuit, and an FPGA is included in the hydrogen atomic clock time-frequency distribution module.

[0009] Optionally, the signal acquisition and processing board includes a ChipRF-PAF acquisition and processing board, a single ChipRF-PAF acquisition and processing board acquires m channels of signals, and m*n channels of analog signals are synchronously acquired through n signal acquisition and processing boards.

[0010] Optionally, the RFSoC circuit is an RFSoC XCZU49DR chip, and a high-performance ADC is embedded in the RFSoC XCZU49DR chip.

[0011] Optionally, the phase-determining clock circuit includes a system clock generation module and a sampling clock generation module, and signals are mutually communicated between the system clock generation module and the sampling clock generation module.

[0012] Optionally, a plurality of the signal acquisition and processing boards adopt the same clock architecture, the clock architecture supports the phase-determining mode, and the Tile clock and the PL logic clock in the signal acquisition and processing board are in phase with the externally input reference clock.

[0013] Optionally, it further includes: a reference clock (synchronous signal Trigger and 1PPS pulse signal are input to the RFSOC) is input to the system clock generation module through an external interface, the system clock generation module adopts a dual-loop phase-determining mode, and all output clocks of the system clock generation module have a fixed phase relationship with the input reference clock under the dual-loop phase-determining mode, and automatically reach the synchronous state after power-on configuration.

[0014] Optionally, the input reference clock of the system clock generation module is set to X MHz, the system clock generation module outputs two paths of X MHz SYSREF, one path is used to synchronize the analog part of the ADC, and the other path synchronizes the digital link part of the ADC; at the same time, two paths of Y MHz reference clocks are output, one path is used as the digital link reference clock of the RFSoC, and the other path is sent to the sampling clock generation module, and the sampling clock generation module locks and distributes the clock to multiple ADC Tiles as the analog reference clock, and the on-board Tile clock is synchronized through the system clock generation module outputting the homologous reference clock and the SYSREF signal.

[0015] Optionally, it further includes: when the 1PPS pulse signal is input into the hydrogen atomic clock time-frequency distribution module through the optical fiber interface, the hydrogen atomic clock time-frequency distribution module synchronously distributes the 1PPS pulse signal into n paths. After receiving the Trigger generation instruction, the FPGA generates n paths of synchronous Trigger signals. The n paths of Trigger signals and the n paths of 1PPS pulse signals are transmitted to n signal acquisition and processing boards through the optical fiber interface. After the signal acquisition and processing board recognizes the synchronous Trigger pulse, it will select and sample the data of each ADC channel at the rising edge of the next 1PPS pulse signal to perform synchronous processing of all channel data.

[0016] Optionally, a multi-channel high-precision PAF signal synchronous acquisition method is applied to a multi-channel high-precision PAF signal synchronous acquisition system, including:

[0017] Reference clock synchronization: The hydrogen atomic clock time-frequency distribution module provides a homologous reference clock to multiple signal acquisition and processing boards for inter-board reference clock synchronization;

[0018] Tile clock synchronization: The dual-loop determines the phase clock circuit to output a homologous reference clock and a SYSREF signal for in-board Tile clock synchronization;

[0019] Acquisition trigger synchronization: The hydrogen atomic clock time-frequency distribution module provides synchronous Trigger signals and 1PPS pulse signals to multiple signal acquisition and processing boards for multi-channel synchronous trigger acquisition.

[0020] Through the above technical solutions, compared with the prior art, the present invention discloses a multi-channel high-precision PAF signal synchronous acquisition system and method, which has the following beneficial effects:

[0021] The present invention proposes a multi-channel high-precision PAF signal synchronous acquisition system, including: a signal acquisition and processing board and a hydrogen atomic clock time-frequency distribution module. The hydrogen atomic clock time-frequency distribution module is signal-connected to multiple signal acquisition and processing boards. The signal acquisition and processing board includes a dual-loop determines the phase clock circuit and an RFSoC circuit, and the dual-loop determines the phase clock circuit and the RFSoC circuit are signal-connected. The time-frequency distribution module of the present invention uses the time-frequency signal output by the hydrogen atomic clock as a reference, providing extremely high synchronization accuracy. The clock architecture of the acquisition and processing board card adopts a determined phase mode, making the in-board Tile clock, PL logic clock and the externally input reference clock strictly in phase, ensuring the synchronization of all channel ADC acquisitions. Using the dual-loop determines the phase clock circuit design, all output clocks maintain a strict phase relationship with the input reference clock, without other synchronization signals, and can automatically reach the synchronous state after power-on configuration, improving the system synchronization stability. The system adopts a three-step synchronization process, enabling the synchronous acquisition of hundreds of PAF signals to reach ps-level accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on the provided drawings.

[0023] Figure 1 It is a framework diagram of a multi-channel high-precision PAF signal synchronous acquisition system provided by the present invention.

[0024] Figure 2 It is an inter-board reference clock synchronization diagram provided by the present invention.

[0025] Figure 3 It is a system clock architecture diagram provided by the present invention.

[0026] Figure 4 It is a multi-channel acquisition trigger synchronization provided by the present invention.

[0027] Figure 5 It is a signal acquisition trigger synchronization timing diagram provided by the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0028] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0029] An embodiment of the present invention discloses a multi-channel high-precision PAF signal synchronous acquisition system, including: a signal acquisition and processing board and a hydrogen atomic clock time-frequency distribution module. The hydrogen atomic clock time-frequency distribution module is signal-connected to a plurality of signal acquisition and processing boards. The signal acquisition and processing board includes a dual-loop phase-determining clock circuit and an RFSoC circuit, and the dual-loop phase-determining clock circuit is signal-connected to the RFSoC circuit.

[0030] Further, m ADCs are integrated inside the RFSoC circuit, and an FPGA is included in the hydrogen atomic clock time-frequency distribution module.

[0031] Further, the signal acquisition and processing board includes a ChipRF-PAF acquisition and processing board. A single ChipRF-PAF acquisition and processing board acquires m signals, and m*n-channel analog signal synchronous acquisition is performed through n signal acquisition and processing boards.

[0032] Furthermore, the RFSoC circuit is an RFSoC XCZU49DR chip, and the RFSoC XCZU49DR chip is embedded with a high-performance ADC.

[0033] Furthermore, the phase determination clock circuit includes a system clock generation module and a sampling clock generation module, and there is signal communication between the system clock generation module and the sampling clock generation module.

[0034] Furthermore, multiple signal acquisition and processing boards adopt the same clock architecture, the clock architecture supports the phase determination mode, and the Tile clock and PL logic clock in the signal acquisition and processing board are in phase with the externally input reference clock.

[0035] Furthermore, it also includes: The reference clock (the synchronization signal Trigger and the 1PPS pulse signal are input to the RFSOC) is input to the system clock generation module through an external interface. The system clock generation module adopts a dual-loop phase determination mode. Under the dual-loop phase determination mode, all output clocks of the system clock generation module have a fixed phase relationship with the input reference clock and automatically reach the synchronization state after power-on configuration.

[0036] Furthermore, the input reference clock of the system clock generation module is set to X MHz. The system clock generation module outputs two paths of X MHz SYSREF, one for synchronizing the analog part of the ADC and the other for synchronizing the digital link part of the ADC; at the same time, it outputs two paths of Y MHz reference clocks, one as the RFSoC digital link reference clock and the other is sent to the sampling clock generation module. The sampling clock generation module locks and distributes the clock to multiple ADC Tiles as the analog reference clock, and synchronizes the Tile clock in the board by outputting the homologous reference clock and SYSREF signal through the system clock generation module.

[0037] Furthermore, it also includes: The 1PPS pulse signal is input to the hydrogen atomic clock time and frequency distribution module through an optical fiber interface. The hydrogen atomic clock time and frequency distribution module synchronously distributes the 1PPS pulse signal into n paths. After receiving the Trigger generation instruction, the FPGA generates n paths of synchronous Trigger signals. The n paths of Trigger signals and the n paths of 1PPS pulse signals are transmitted to n signal acquisition and processing boards through the optical fiber interface; after the signal acquisition and processing board recognizes the synchronous Trigger pulse, it will select and sample the data of each ADC channel at the rising edge of the next 1PPS pulse signal to perform all-channel data synchronization processing.

[0038] In a specific embodiment, a multi-channel high-precision PAF signal synchronous acquisition method is applied to a multi-channel high-precision PAF signal synchronous acquisition system, including:

[0039] Reference clock synchronization: The hydrogen atomic clock time-frequency distribution module provides a homologous reference clock to multiple signal acquisition and processing boards for inter-board reference clock synchronization.

[0040] Tile clock synchronization: The dual-loop determines the phase clock circuit to output a homologous reference clock and SYSREF signal for intra-board Tile clock synchronization.

[0041] Acquisition trigger synchronization: The hydrogen atomic clock time-frequency distribution module provides a synchronous Trigger signal and 1PPS pulse signal to multiple signal acquisition and processing boards for multi-channel synchronous trigger acquisition.

[0042] The time-frequency distribution module described in the present invention uses the time-frequency signal output by the hydrogen atomic clock as a reference, providing extremely high synchronization accuracy. The clock architecture of the acquisition and processing board adopts a determined phase mode, making the intra-board Tile clock, PL logic clock strictly in phase with the externally input reference clock, ensuring the synchronization of all-channel ADC acquisitions. With the design of the dual-loop determined phase clock circuit, a strict phase relationship is maintained between all output clocks and the input reference clock. Without other synchronization signals, it can automatically reach the synchronous state after power-on configuration, improving the system synchronization stability. The system adopts a three-step synchronization process, enabling the synchronous acquisition of hundreds of PAF signals to reach ps-level accuracy.

[0043] In the specific implementation, a multi-channel high-precision PAF signal synchronous acquisition system, as Figure 1 shown, includes: a signal acquisition and processing board and a hydrogen atomic clock time-frequency distribution module. Among them, the signal acquisition and processing board includes: an RFSoC circuit integrating a high-performance ADC and a dual-loop determined phase clock circuit, etc.

[0044] The system realizes synchronous acquisition of 192 analog signals. Each single acquisition and processing module collects 16 signals by one ChipRF-PAF acquisition and processing board, and a total of 12 acquisition and processing modules are required. Therefore, both intra-board synchronization and inter-board synchronization need to be realized.

[0045] The system synchronous acquisition process is completed by integrating components such as the RFSoC XCZU49DR chip embedded with a high-performance ADC, a system clock generation module, a sampling clock generation module, and an external input interface.

[0046] Specifically, the synchronous implementation process can be subdivided into: (1) reference clock synchronization; (2) Tile clock synchronization; (3) acquisition trigger synchronization.

[0047] In the specific implementation, the reference clock synchronization specifically includes: The hydrogen atomic clock time-frequency distribution module provides a homologous reference clock to 12 acquisition and processing boards to achieve inter-board reference clock synchronization, as Figure 2As shown in the figure, to achieve the synchronization of the reference clock between boards, the hydrogen atomic clock time and frequency distribution module provides a homologous external reference clock to ensure that the reference clocks input by all acquisition and processing boards are strictly in phase.

[0048] In the specific implementation manner, the Tile clock synchronization specifically includes: on the basis that the reference clocks input outside all acquisition and processing boards in the system are in phase, each acquisition and processing board uses the same clock architecture, and this clock architecture supports the determination of the phase mode to ensure that the Tile clock and PL logic clock inside the board are strictly in phase with the externally input reference clock, ensuring the synchronization of ADC acquisitions for all channels.

[0049] The system realizes the synchronization of the Tile clock inside the board by the way that the RFSoC external PLL system clock generation module outputs a homologous reference clock and a SYSREF signal, and the system clock architecture is as Figure 3 shown.

[0050] Specifically, the reference clock is input to the system clock generation module through an external interface. The system clock generation module adopts a dual-loop phase determination mode. In this mode, there is a strict phase relationship between all output clocks of the system clock generation module and the input reference clock, and no other synchronization signals are required. It can automatically reach the synchronization state after power-on configuration, improving the synchronization stability of the system.

[0051] Furthermore, according to the requirements of the phase determination mode and the RFDC synchronization requirements, the reference clock input to the system clock generation module is set to 8 MHz. After optimized configuration, the system clock generation module will output two 8-MHz SYSREFs, one for synchronizing the analog part of the ADC and the other for synchronizing the digital link part of the ADC; at the same time, it outputs two 256-MHz reference clocks, one as the reference clock for the RFSoC digital link and the other is sent to the sampling clock generation module, and the sampling clock generation module locks and distributes the clock to multiple ADC Tiles as the analog reference clock.

[0052] In the specific implementation manner, the acquisition trigger synchronization specifically includes:

[0053] After ensuring the synchronous acquisition of 192 ADCs during the reference clock synchronization and Tile clock synchronization processes, all channels of the system also need to synchronously start the processing flow of the acquisition signal.

[0054] The multi-channel synchronous trigger acquisition is realized by the way that the hydrogen atomic clock time and frequency distribution module provides synchronous Trigger signals and 1PPS pulse signals to 12 acquisition and processing modules as Figure 4 shown.

[0055] The system monitoring unit generates a Trigger signal through the Gigabit Ethernet to configure the time-frequency distribution module of the hydrogen atomic clock. There is an FPGA in the time-frequency distribution module of the hydrogen atomic clock. After receiving the Trigger generation instruction, the FPGA generates 12 synchronous Trigger signals. The 1PPS pulse signal is input into the time-frequency distribution module of the hydrogen atomic clock through the optical fiber interface, and the module synchronously distributes the 1PPS pulse signal into 12 channels. The 12 Trigger signals and the 12 1PPS pulse signals are transmitted to 12 acquisition and processing modules through the optical fiber interface. After the acquisition and processing module recognizes the synchronous Trigger pulse, it will select and sample the data of each ADC channel at the rising edge of the next 1PPS pulse signal to ensure synchronous processing of all channel data. The specific processing timing is as Figure 5 shown.

[0056] The various embodiments in this specification are described in a progressive manner. The key point of each embodiment is to illustrate the differences from other embodiments. For the same or similar parts among the embodiments, reference can be made to each other. For the devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple. For the relevant parts, reference can be made to the description in the method section.

[0057] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present invention. Various modifications to these embodiments will be obvious to those skilled in the art. The general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to these embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A multi-channel high-precision PAF signal synchronous acquisition system, characterized in that, Including: A signal acquisition and processing board and a hydrogen atomic clock time-frequency distribution module. The hydrogen atomic clock time-frequency distribution module is signal-connected to multiple signal acquisition and processing boards. The signal acquisition and processing board includes a dual-loop phase-determining clock circuit and an RFSoC circuit, and the dual-loop phase-determining clock circuit is signal-connected to the RFSoC circuit.

2. The multi-channel high-precision PAF signal synchronous acquisition system according to claim 1, wherein The RFSoC circuit integrates m ADCs internally, and the hydrogen atomic clock time-frequency distribution module contains an FPGA.

3. A multi-channel high-precision PAF signal synchronous acquisition system according to claim 1, characterized in that, The signal acquisition and processing board includes a ChipRF-PAF acquisition and processing board. A single ChipRF-PAF acquisition and processing board acquires m signals, and m*n-channel analog signal synchronous acquisition is performed through n signal acquisition and processing boards.

4. A multi-channel high-precision PAF signal synchronous acquisition system according to claim 2, wherein, The RFSoC circuit is an RFSoC XCZU49DR chip, and the RFSoC XCZU49DR chip embeds a high-performance ADC.

5. A multi-channel high-precision PAF signal synchronous acquisition system according to claim 2, wherein, The phase-determining clock circuit includes a system clock generation module and a sampling clock generation module, and there is signal communication between the system clock generation module and the sampling clock generation module.

6. A multi-channel high-precision PAF signal synchronous acquisition system according to claim 1, characterized in that, Multiple signal acquisition and processing boards adopt the same clock architecture. The clock architecture supports the phase-determining mode, and the Tile clock and the PL logic clock in the signal acquisition and processing board are in phase with the externally input reference clock.

7. A multi-channel high-precision PAF signal synchronous acquisition system according to claim 5, characterized in that, Also including: The reference clock is input to the system clock generation module through an external interface. The system clock generation module adopts a dual-loop phase-determining mode. Under the dual-loop phase-determining mode, all output clocks of the system clock generation module have a fixed phase relationship with the input reference clock and automatically reach the synchronous state after power-on configuration.

8. A multi-channel high-precision PAF signal synchronous acquisition system according to claim 5, characterized in that, The input reference clock of the system clock generation module is set to X MHz. The system clock generation module outputs two SYSREFs of X MHz, one for synchronizing the analog part of the ADC and the other for synchronizing the digital link part of the ADC; at the same time, it outputs two reference clocks of Y MHz, one as the digital link reference clock of the RFSoC and the other is sent to the sampling clock generation module. The sampling clock generation module locks and distributes the clock to multiple ADC Tiles as the analog reference clock, and synchronizes the Tile clocks in the board through the system clock generation module outputting the homologous reference clock and SYSREF signal.

9. A multi-channel high-precision PAF signal synchronous acquisition system according to claim 2, wherein Also including: The 1PPS pulse signal is input to the hydrogen atomic clock time-frequency distribution module through an optical fiber interface. The hydrogen atomic clock time-frequency distribution module synchronously distributes the 1PPS pulse signal into n channels. After receiving the Trigger generation instruction, the FPGA generates n synchronous Trigger signals. The n Trigger signals and the n 1PPS pulse signals are transmitted to n signal acquisition and processing boards through the optical fiber interface; after the signal acquisition and processing board recognizes the synchronous Trigger pulse, it will select and sample the data of each ADC channel at the rising edge of the next 1PPS pulse signal to perform all-channel data synchronization processing.

10. A multi-channel high-precision PAF signal synchronous acquisition method, applied to any one of the multi-channel high-precision PAF signal synchronous acquisition systems in claims 1-9, characterized in that, Including: Reference clock synchronization, providing a homologous reference clock for multiple signal acquisition and processing boards through the hydrogen atomic clock time-frequency distribution module to perform inter-board reference clock synchronization; Tile clock synchronization, determining the phase clock circuit output of the same-source reference clock and SYSREF signal through a dual loop to perform in-board Tile clock synchronization; Acquisition trigger synchronization, providing synchronous Trigger signals and 1PPS pulse signals to multiple signal acquisition and processing boards through the hydrogen atomic clock time-frequency distribution module for multi-channel synchronous trigger acquisition.

Images