Emission Control Driver

Abstract

An emission control driver is disclosed. The emission control driver includes: a plurality of stages, each having: a first circuit portion configured to generate a first control signal at a first node and a second control signal at a second node; a second circuit portion configured to control a voltage level of the first control signal; a third circuit portion configured to generate a third control signal based on the first control signal, the second control signal, and a second clock signal; a first output transistor configured to output a first voltage as an emission control signal in response to the first control signal; and a second output transistor configured to output a second voltage as the emission control signal, wherein the third circuit portion includes a first capacitor configured to maintain a substantially constant voltage between two electrodes while each of the plurality of stages outputs an emission control signal.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2020-0051052, filed on April 27, 2020, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] Aspects of one or more example embodiments relate to an emission control driver and a display device including the same. Background Art

[0003] Organic light-emitting display devices use organic light-emitting diodes (OLEDs) to display images. These OLEDs generate light through the recombination of electrons and holes. Organic light-emitting display devices have relatively fast response times and can be driven with relatively low power consumption. An organic light-emitting display device may include a pixel drive circuit arranged in a matrix and display elements (e.g., OLEDs) connected to the pixel drive circuit.

[0004] The pixel driving circuit can be connected to a scan line for transmitting a scan signal, a data line for transmitting a data signal, a control line for transmitting an emission control signal, and a power line for transmitting a pixel driving voltage. The data signal can be applied to the pixel driving circuit in synchronization with the scan signal, and the brightness of the display device can be adjusted according to the amplitude of the data signal applied to the pixel driving circuit. The emission timing of the display device can be determined according to the emission control signal applied to the pixel driving circuit. The organic light-emitting display device may include a scan driver for supplying a scan signal, a data driver for supplying a data signal, an emission control driver for supplying an emission control signal, and a timing controller for controlling the scan driver, the data driver, and the emission control driver. The emission control driver can control the brightness of the display panel by controlling the width of the emission control signal.

[0005] Portable electronic devices such as smartphones, tablet PCs, digital cameras, laptop computers, and navigation devices may include organic light-emitting display devices for displaying images. Because portable electronic devices are typically powered by one or more batteries, it is desirable to reduce or minimize the power consumption of organic light-emitting display devices as much as possible.

[0006] The above information disclosed in this Background section is only for enhancement of understanding of the background and therefore the information discussed in this Background section does not necessarily constitute prior art. Summary of the Invention

[0007] Aspects of some example embodiments include an emission control driver that may generate an emission control signal while reducing or minimizing power consumption (eg, reducing unnecessary power consumption).

[0008] Aspects of some example embodiments include a display device including an emission control driver that may generate an emission control signal while reducing or minimizing power consumption (eg, reducing unnecessary power consumption).

[0009] The technical features according to the embodiments of the present disclosure are not limited to the above-mentioned features, and other technical features not mentioned herein will be clearly understood by those skilled in the art through the disclosed description.

[0010] According to one or more example embodiments, an emission control driver includes a plurality of stages connected in cascade to one another and sequentially outputting emission control signals. Each of the plurality of stages includes: a first circuit portion configured to generate a first control signal at a first node and a second control signal at a second node based on an input signal and a first clock signal; a second circuit portion configured to control a voltage level of the first control signal based on the first control signal and the second clock signal; a third circuit portion configured to generate a third control signal based on the first control signal, the second control signal, and the second clock signal; a first output transistor configured to output a first voltage as the emission control signal in response to the first control signal; and a second output transistor configured to output a second voltage as the emission control signal in response to the third control signal. The third circuit portion includes a first capacitor configured to maintain a substantially constant voltage between two electrodes while each of the plurality of stages outputs an emission control signal.

[0011] According to one or more example embodiments, a display device includes: a display panel including a plurality of pixels; a scan driver configured to supply a scan signal to the plurality of pixels; a data driver configured to supply a data signal to the plurality of pixels; an emission control driver configured to supply an emission control signal to the plurality of pixels; and a timing controller configured to generate a control signal to control the scan driver, the data driver, and the emission control driver. The emission control driver includes a plurality of stages connected in cascade to each other and sequentially outputting emission control signals.

[0012] According to some example embodiments, each of the plurality of stages includes: a first circuit section configured to generate a first control signal at a first node and a second control signal at a second node based on an input signal and a first clock signal; a second circuit section configured to control a voltage level of the first control signal based on the first control signal and the second clock signal; a third circuit section configured to generate a third control signal based on the first control signal, the second control signal, and the second clock signal; a first output transistor configured to output a first voltage as an emission control signal in response to the first control signal; and a second output transistor configured to output a second voltage as an emission control signal in response to the third control signal. The third circuit section includes a first capacitor configured to maintain a substantially constant voltage between two electrodes while each of the plurality of stages outputs an emission control signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The above and other aspects, features, and characteristics of certain example embodiments disclosed will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0014] Figure 1 is a block diagram of an emission control driver according to some example embodiments;

[0015] Figure 2 is a circuit diagram of a stage included in an emission control driver according to some example embodiments;

[0016] Figure 3 yes Figure 2 Timing diagram of the operation of the level;

[0017] Figure 4 is a circuit diagram of a stage included in an emission control driver according to some example embodiments;

[0018] Figure 5 yes Figure 4 The voltage waveforms of the main nodes of the circuit diagram;

[0019] Figure 6 is a circuit diagram of a stage included in an emission control driver according to a comparative example;

[0020] Figure 7 yes Figure 6 The voltage waveforms of the main nodes of the circuit diagram;

[0021] Figure 8 is a block diagram of a display device according to some example embodiments;

[0022] Figure 9 is included in Figure 8 a circuit diagram of an example of a pixel in a display device;

[0023] Figure 10 is included Figure 8 A block diagram of an electronic device of a display device; and

[0024] Figure 11 Shown Figure 10 The electronic device is implemented as an example of a smart phone. DETAILED DESCRIPTION

[0025] The various aspects of some example embodiments shown in the accompanying drawings will now be referred to in more detail, wherein the same reference numerals represent the same elements throughout. In this respect, the present embodiment can have different forms and should not be construed as being limited to the description set forth herein. Therefore, the exemplary embodiments will be described below only by reference to the accompanying drawings to explain the various aspects of this specification. As used herein, the term "and / or" includes any combination and all combinations of one or more of the relevant listed items. Throughout the disclosure, the expression "at least one of a, b, and c" means only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0026] Various modifications may be applied to this exemplary embodiment, and specific embodiments will be shown in the accompanying drawings and described in the detailed description. The effects and features of this embodiment and methods for implementing the same will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. However, embodiments according to the present disclosure may be implemented in various forms and are not limited to the exemplary embodiments presented below.

[0027] Hereinafter, an exemplary embodiment according to the present disclosure will be described in more detail by explaining the disclosed exemplary embodiments with reference to the accompanying drawings. In order to more clearly describe the embodiments according to the present disclosure, descriptions of specific aspects that are not necessary for a person of ordinary skill in the art to understand the invention may be omitted. In the description with reference to the accompanying drawings, identical or corresponding components are represented by the same reference numerals, and redundant descriptions thereof may be omitted.

[0028] In the following embodiments, it will be understood that, although the terms "first", "second" and the like may be used herein to describe different components, these components should not be limited by these terms. In the following embodiments, unless the context clearly indicates otherwise, the singular forms "one", "a(kind / person)" and "the(said)" are also intended to include plural forms. In the specification, when a constituent element is "connected" or "connected" to another constituent element, it can be interpreted not only as the constituent element being directly in contact with or connected to the other constituent element, but also as being electrically contacted or electrically connected to the other constituent element by at least one other constituent element placed therebetween. Moreover, when a component can "include" a specific constituent element, unless otherwise stated, the component may not be interpreted as excluding another constituent element, but may be interpreted as also including other constituent elements.

[0029] Figure 1 is a block diagram of an emission control driver 1000 according to some example embodiments.

[0030] Reference Figure 1 , the emission control driver 1000 may include a first stage to an n-th stage (eg, a first stage 1100, a second stage 1200, and a third stage 1300) connected to each other in a cascade structure. Here, n is a natural number and may correspond to the number of pixel rows of the display panel. Although Figure 1 Only the first stage 1100, the second stage 1200, and the third stage 1300 are shown, but the emission control driver 1000 may include the first to n-th stages, and for example, the fourth to n-th stages are connected to each other in the same manner as the first stage 1100, the second stage 1200, and the third stage 1300 are connected to each other.

[0031] The first stage 1100, the second stage 1200, and the third stage 1300 are connected to each other in a cascade structure and can sequentially output the first emission control signal to the nth emission control signal (e.g., the first emission control signal EM1, the second emission control signal EM2, and the third emission control signal EM3). The first emission control signal EM1, the second emission control signal EM2, and the third emission control signal EM3 can be supplied to the pixels of the display panel (e.g., the pixel driving circuit) via the first emission control line EML1, the second emission control line EML2, and the third emission control line EML3.

[0032] One of the first stage 1100, the second stage 1200, and the third stage 1300 (e.g., the first stage 1100) may receive a start signal FLM via a start signal line L1. Each of the first stage 1100, the second stage 1200, and the third stage 1300 may receive a first clock signal CLK1 via a first clock signal line L2 and a second clock signal CLK2 via a second clock signal line L3. Some of the first stage 1100, the second stage 1200, and the third stage 1300 (e.g., the second stage 1200 and the third stage 1300) may receive a carry signal CARRY from a previous stage via a carry signal line L4 (see FIG. 1 ). Figure 2 For example, the kth stage may receive a carry signal CARRY from the (k-1)th stage.

[0033] The start signal FLM and the carry signal CARRY received by the first stage 1100, the second stage 1200, and the third stage 1300 may be referred to as input signals. For example, the input signal input to the first stage 1100 may be the start signal FLM, and the input signal input to the second to n-th stages (e.g., the second stage 1200 and the third stage 1300) may be the carry signal CARRY output from the previous stage (i.e., the first to (n-1)-th stages, e.g., the first stage 1100, the second stage 1200, and the third stage 1300).

[0034] According to some example embodiments, each of the first stage 1100, the second stage 1200, and the third stage 1300 may receive a first voltage VGL (see FIG. 1 ) via a first voltage line. Figure 2 ), and receives the second voltage VGH (see Figure 2 ). In this state, the first voltage VGL may be a voltage having a low level, and the second voltage VGH may be a voltage having a high level.

[0035] The first stage 1100 can be based on the slave timing controller ( Figure 8 The first emission control signal EM1 is generated by receiving a start signal FLM and a first clock signal CLK1 and a second clock signal CLK2 from a first stage 1100 (e.g., a first emission control line 550). The first emission control signal EM1 can be supplied to pixels connected to the first emission control line EML1 via a first emission control line EML1. The first stage 1100 can generate a first carry signal CARRY1 and supply the first carry signal CARRY1 to the second stage 1200 via a carry signal line L4. The first carry signal CARRY1 and the first emission control signal EM1 can be substantially the same signal (i.e., a signal having the same level at the same timing).

[0036] The second stage 1200 may generate a second emission control signal EM2 based on the first carry signal CARRY1 received from the first stage 1100 and the first and second clock signals CLK1 and CLK2 received from the timing controller. The second emission control signal EM2 may be supplied to the pixels connected to the second emission control line EML2 via the second emission control line EML2. The second stage 1200 may generate a second carry signal CARRY2 and supply the second carry signal CARRY2 to the third stage 1300.

[0037] The third stage 1300 may generate a third emission control signal EM3 based on the second carry signal CARRY2 received from the second stage 1200 and the first clock signal CLK1 and the second clock signal CLK2 received from the timing controller. The third emission control signal EM3 may be supplied to the pixels connected to the third emission control line EML3 via the third emission control line EML3. The third stage 1300 may generate the third carry signal CARRY3 to be supplied to the next stage (i.e., the fourth stage).

[0038] The first stage 1100, the second stage 1200, and the third stage 1300 of the emission control driver 1000 are connected in cascade connection to each other in such a manner that the first emission control signal EM1, the second emission control signal EM2, and the third emission control signal EM3 can be sequentially output. The first stage 1100 can generate the first emission control signal EM1 based on the start signal FLM, the first clock signal CLK1, and the second clock signal CLK2. The kth stage can generate the kth emission control signal EMk based on the (k-1)th carry signal CARRY(k-1), the first clock signal CLK1, and the second clock signal CLK2. In this case, k is a natural number greater than or equal to 2 and less than or equal to n.

[0039] Figure 2 is a circuit diagram of the stage 100 included in the emission control driver 1000 according to some example embodiments.

[0040] Reference Figure 2 The stage 100 may include a first circuit section 110, a second circuit section 120, a third circuit section 130, a first output transistor M1 and a second output transistor M2. Figure 1 The first stage 1100 , the second stage 1200 and the third stage 1300 correspond to one of the first stage 1100 , the second stage 1200 and the third stage 1300 .

[0041] The input signal FLM / CARRY is input to the stage 100. The first clock signal CLK1 and the second clock signal CLK2 are input to the stage 100, and the low-level first voltage VGL and the high-level second voltage VGH are applied to the stage 100. The stage 100 outputs the emission control signal EM based on the input signal FLM / CARRY and the first clock signal CLK1 and the second clock signal CLK2.

[0042] The input signal FLM / CARRY has a low-level voltage corresponding to the first voltage VGL or a high-level voltage corresponding to the second voltage VGH, depending on the timing. The first clock signal CLK1 and the second clock signal CLK2 each also have a low-level voltage corresponding to the first voltage VGL or a high-level voltage corresponding to the second voltage VGH, depending on the timing. The first clock signal CLK1 and the second clock signal CLK2 may have the same period and may alternately have a low-level voltage. According to some example embodiments, the first clock signal CLK1 and the second clock signal CLK2 may have the same duty cycle, which may be 50% or greater. The first clock signal CLK1 and the second clock signal CLK2 may not have a low-level voltage at the same time.

[0043] The first circuit unit 110 can generate a first control signal SC1 at a first node N1 and a second control signal SC2 at a second node N2 based on the input signal FLM / CARRY and the first clock signal CLK1. The first control signal SC1 and the second control signal SC2 can have a low-level voltage or a high-level voltage to control the operation of the switching transistor. The first control signal SC1 can correspond to the voltage of the first node N1, and the second control signal SC2 can correspond to the voltage of the second node N2.

[0044] When level 100 is Figure 1 When the first stage 1100 is in the state of Figure 1 When one of the second stage 1200 and the third stage 1300 is executed, the carry signal CARRY output from the previous stage may be input to the first circuit portion 110 as an input signal.

[0045] The second circuit section 120 may control the voltage level of the first control signal SC1 based on the first control signal SC1 and the second clock signal CLK2. The third circuit section 130 may generate a third control signal SC3 at the second output node NQB based on the first control signal SC1, the second control signal SC2 and the second clock signal CLK2. According to some example embodiments, the third circuit section 130 may include a first capacitor C1 that maintains a substantially constant voltage between both electrodes of the first capacitor C1 while the stage 100 outputs the emission control signal EM.

[0046] The first output transistor M1 can output a low-level first voltage VGL as the emission control signal EM in response to the first control signal SC1, and the second output transistor M2 can output a high-level second voltage VGH as the emission control signal EM in response to the third control signal SC3. The third control signal SC3 can have a low-level voltage or a high-level voltage to control the operation of the second output transistor M2. The third control signal SC3 can correspond to the voltage of the second output node NQB.

[0047] like Figure 2 As shown in FIG, the first output transistor M1 may be a p-type metal oxide semiconductor field effect transistor (MOSFET). The second output transistor M2 may also be a p-type MOSFET. However, the embodiments of the present disclosure are not limited thereto, and at least one of the first output transistor M1 and the second output transistor M2 may be an n-type MOSFET.

[0048] According to some example embodiments, the third circuit portion 130 of the stage 100 may further include a floating transistor FT connected between the second node N2 and the first capacitor C1. The floating transistor FT may connect the second node N2 and the first capacitor C1 to each other or disconnect them from each other in response to the first control signal SC1. The floating transistor FT may be a Figure 2 That is, the conductivity type of the floating transistor FT is opposite to the conductivity type of the second output transistor M2.

[0049] According to some example embodiments, the stage 100 may further include a second capacitor C2 and a third capacitor C3 and at least one of the first to eighth switching transistors T1 to T8. Although the first to eighth switching transistors T1 to T8 may be p-type MOSFETs, the embodiments of the present disclosure are not limited thereto. In the following description, as Figure 2 As shown in , it is assumed that the first and second output transistors M1 and M2 and the first to eighth switching transistors T1 to T8 are p-type MOSFETs, and the floating transistor FT is an n-type MOSFET.

[0050] like Figure 2 As shown in FIG, the stage 100 has a plurality of nodes, some of which are referred to as first to fifth nodes N1 to N5 and first and second output nodes NQ and NQB.

[0051] The first circuit portion 110 may include a first switching transistor T1 , a second switching transistor T2 , and a third switching transistor T3 .

[0052] The first switching transistor T1 is configured to transmit the input signal FLM / CARRY to the first node N1 in response to the first clock signal CLK1. The first switching transistor T1, which is turned on in response to the first clock signal CLK1 having a low-level voltage, may be configured to transmit the input signal FLM / CARRY to the first node N1. The first switching transistor T1 is turned off in response to the first clock signal CLK1 having a high-level voltage, so the input signal FLM / CARRY is not transmitted to the first node N1.

[0053] The second switching transistor T2 is configured to transmit the first clock signal CLK1 to the second node N2 in response to the first control signal SC1 (i.e., according to the voltage of the first node N1). The second switching transistor T2, which is turned on in response to the voltage of the first node N1 having a low level, can be configured to transmit the first clock signal CLK1 to the second node N2. The second switching transistor T2 is turned off in response to the voltage of the first node N1 having a high level, and thus the first clock signal CLK1 is not transmitted to the second node N2.

[0054] The third switching transistor T3 can apply the low-level first voltage VGL to the second node N2 in response to the first clock signal CLK1. The third switching transistor T3, which is turned on in response to the first clock signal CLK1 having a low level, can apply the low-level first voltage VGL to the second node N2. The third switching transistor T3 is turned off in response to the first clock signal CLK1 having a high level, so the low-level first voltage VGL is not applied to the second node N2.

[0055] The voltage of the first node N1 may be input to the second circuit portion 120 and the third circuit portion 130 as the first control signal SC1 , and the voltage of the second node N2 may be input to the third circuit portion 130 as the second control signal SC2 .

[0056] The second circuit portion 120 may include a fourth switching transistor T4 , a fifth switching transistor T5 , and a second capacitor C2 .

[0057] The fourth switching transistor T4 is configured to transmit the second clock signal CLK2 to the third node N3 in response to the first control signal SC1 (i.e., according to the voltage of the first output node NQ). ​​The fourth switching transistor T4, which is turned on in response to the voltage of the first output node NQ having a low level, can be configured to transmit the second clock signal CLK2 to the third node N3. The fourth switching transistor T4 is turned off in response to the voltage of the first output node NQ having a high level, and thus the second clock signal CLK2 is not transmitted to the third node N3.

[0058] The fifth switching transistor T5 applies the high-level second voltage VGH to the third node N3 in response to the second control signal SC2 (i.e., according to the voltage of the second node N2). The fifth switching transistor T5, which is turned on in response to the low-level voltage of the second node N2, can apply the high-level second voltage VGH to the third node N3. The fifth switching transistor T5 is turned off in response to the high-level voltage of the second node N2, so the high-level second voltage VGH is not applied to the third node N3.

[0059] The second capacitor C2 may include a first electrode connected to the third node N3 and a second electrode connected to the first output node NQ. When charges are charged into or discharged from the second capacitor C2, the voltage of the first output node NQ (i.e., the voltage level of the first control signal SC1) may be adjusted.

[0060] In a partial period, a high-level voltage corresponding to the second voltage VGH may be applied to the first electrode of the second capacitor C2, and a low-level voltage corresponding to the first voltage VGL may be applied to the second electrode of the second capacitor C2. In another partial period, due to the charge corresponding to the difference between the high-level voltage and the low-level voltage stored in the second capacitor C2, the voltage difference between the high-level voltage and the low-level voltage may be maintained between the first electrode and the second electrode of the second capacitor C2.

[0061] In another partial period, a high-level voltage corresponding to the second voltage VGH is applied to both the first electrode and the second electrode of the second capacitor C2, so that substantially zero charge can be stored in the second capacitor C2. In another partial period, due to the substantially zero charge stored in the second capacitor C2, a substantially zero voltage difference can be maintained between the first electrode and the second electrode of the second capacitor C2.

[0062] The third circuit section 130 may include a sixth switching transistor T6 , a first capacitor C1 , a floating transistor FT, a seventh switching transistor T7 , a third capacitor C3 , and an eighth switching transistor T8 .

[0063] The sixth switching transistor T6 is configured to transmit the second clock signal CLK2 to the fourth node N4 in response to the second control signal SC2. The sixth switching transistor T6, which is turned on in response to the second control signal SC2 having a low-level voltage, can be configured to transmit the second clock signal CLK2 to the fourth node N4. The sixth switching transistor T6 is turned off in response to the second control signal SC2 having a high-level voltage, so the second clock signal CLK2 is not transmitted to the fourth node N4.

[0064] The first capacitor C1 may include a first electrode connected to the fourth node N4 and a second electrode connected to the fifth node N5. The third circuit unit 130 may adjust the voltage of the second output node NQB (i.e., the voltage level of the third control signal SC3) by using at least the charge stored in the first capacitor C1. A substantially constant voltage may be maintained between the first electrode and the second electrode of the first capacitor C1. The substantially constant voltage may correspond to the difference between a high-level voltage corresponding to the second voltage VGH and a low-level voltage corresponding to the first voltage VGL.

[0065] When a high-level input signal FLM / CARRY, a low-level first clock signal CLK1, and a high-level second clock signal CLK2 are input to the stage 100, a high-level voltage is applied to the first electrode of the first capacitor C1, and a low-level voltage is applied to the second electrode of the first capacitor C1. The first capacitor C1 can then continuously store a charge corresponding to the difference between the high-level voltage and the low-level voltage.

[0066] When a low-level input signal FLM / CARRY, a high-level first clock signal CLK1, and a high-level second clock signal CLK2 are input to stage 100, both the first electrode and the second electrode of the first capacitor C1 may be in a floating state, and the first capacitor C1 may continuously store charges corresponding to the difference between the high-level voltage and the low-level voltage.

[0067] The floating transistor FT can connect or disconnect the second node N2 and the fifth node N5 to each other in response to a first control signal SC1 (i.e., according to the voltage of the first node N1). The floating transistor FT, which can be implemented as an n-type MOSFET, is turned on in response to a high voltage at the first node N1 and can connect the second node N2 and the fifth node N5 to each other. The floating transistor FT, which is turned off in response to a low voltage at the first node N1, can disconnect the second node N2 and the fifth node N5 from each other. In this state, when the sixth switching transistor T6 and the seventh switching transistor T7 are turned off, both the fourth node N4 and the fifth node N5 are substantially in a floating state.

[0068] The seventh switching transistor T7 can connect or disconnect the fourth node N4 and the second output node NQB to each other in response to the second clock signal CLK2. The seventh switching transistor T7, which is turned on in response to the second clock signal CLK2 having a low voltage level, can connect the fourth node N4 and the second output node NQB to each other. The seventh switching transistor T7, which is turned off in response to the second clock signal CLK2 having a high voltage level, can disconnect the fourth node N4 and the second output node NQB from each other.

[0069] The third capacitor C3 may include a first electrode to which the high-level second voltage VGH is applied and a second electrode connected to the second output node NQB. The third circuit unit 130 may adjust the voltage of the second output node NQB (i.e., the voltage level of the third control signal SC3) by using at least the charge stored in the third capacitor C3.

[0070] A high-level second voltage VGH is applied to the first electrode of the third capacitor C3. During a partial period, a low-level voltage corresponding to the first voltage VGL may be applied to the second electrode of the third capacitor C3. During another partial period, due to the charge corresponding to the difference between the high-level voltage and the low-level voltage stored in the third capacitor C3, a voltage difference between the high-level voltage and the low-level voltage may be maintained between the first and second electrodes of the third capacitor C3. During another partial period, a high-level voltage corresponding to the second voltage VGH is applied to the second electrode of the third capacitor C3, so that substantially zero charge may be stored in the third capacitor C3. During another partial period, due to the substantially zero charge stored in the third capacitor C3, a substantially zero voltage difference may be maintained between the first and second electrodes of the third capacitor C3.

[0071] The eighth switching transistor T8 applies the high-level second voltage VGH to the second output node NQB (i.e., the gate of the second output transistor M2) in response to the first control signal SC1 (i.e., based on the voltage of the first node N1). The eighth switching transistor T8, which is turned on in response to the low-level voltage of the first node N1, can apply the high-level second voltage VGH to the second output node NQB and connect the first electrode and the second electrode of the third capacitor C3 to each other. The eighth switching transistor T8 is turned off in response to the high-level voltage of the first node N1, so that the high-level second voltage VGH is not applied to the second output node NQB.

[0072] For example, in response to the first control signal SC1, the first output transistor M1 can output a low-level first voltage VGL as the emission control signal EM at the stage output node NO according to the voltage of the first output node NQ. The second output transistor M2 can output a high-level second voltage VGH as the emission control signal EM at the stage output node NO in response to the voltage of the second output node NQB (i.e., the third control signal SC3).

[0073] The stage output node NO outputs a low-level first voltage VGL as the emission control signal EM when the first output transistor M1 is turned on, and outputs a high-level second voltage VGH as the emission control signal EM when the second output transistor M2 is turned on. The first output transistor M1 and the second output transistor M2 are not turned on at the same time.

[0074] Refer to the following Figure 3 The operation of stage 100 is described.

[0075] Figure 3 yes Figure 2 A timing diagram of the operation of stage 100 is shown.

[0076] Reference Figure 3 The input signal FLM / CARRY may have a low-level voltage LV corresponding to the time during which the display device of the pixel emits light, and a high-level voltage HV corresponding to the time during which the display device of the pixel does not emit light within one frame period. During the time during which the display device does not emit light, a data signal corresponding to the grayscale to be displayed for the next frame period may be input to the pixel driving circuit.

[0077] The low-level voltage LV corresponds to the first voltage VGL, and the high-level voltage HV corresponds to the second voltage VGH. In this case, the low-level voltage LV and the high-level voltage HV corresponding to the first voltage VGL and the second voltage VGH, respectively, may mean that the low-level voltage LV is substantially the same as the first voltage VGL or has a level slightly higher than the first voltage VGL, and the high-level voltage HV is substantially the same as the second voltage VGH or has a level slightly lower than the second voltage VGH. The difference between the low-level voltage LV and the first voltage VGL, and the difference between the high-level voltage HV and the second voltage VGH, may be generated by the threshold voltage of the switching transistor.

[0078] For a local period of time, a charge corresponding to the voltage difference between the high-level voltage HV and the low-level voltage LV is stored in the first capacitor C1, the second capacitor C2, and the third capacitor C3. The voltage difference between the high-level voltage HV and the low-level voltage LV can be maintained between the two electrodes of each of the first capacitor C1, the second capacitor C2, and the third capacitor C3. In this specification, the voltage difference between the high-level voltage HV and the low-level voltage LV is referred to as a reference voltage difference. A voltage that is lower than the low-level voltage LV by the reference voltage difference is referred to as a second low-level voltage LV2, and a voltage that is higher than the high-level voltage HV by the reference voltage difference is referred to as a second high-level voltage.

[0079] The first clock signal CLK1 and the second clock signal CLK2 are both periodic signals having the same period. The first clock signal CLK1 and the second clock signal CLK2 may alternately have a low-level voltage LV. The first clock signal CLK1 and the second clock signal CLK2 may have the same duty cycle. For example, the duty cycle of the first clock signal CLK1 is (P2+P3+P4) / (P1+P2+P3+P4), and the duty cycle of the second clock signal CLK2 is (P1+P2+P4) / (P1+P2+P3+P4).

[0080] According to some example embodiments, Figure 3 As shown in , the first clock signal CLK1 may have a low-level voltage LV in the first period P1 and the fifth period P5, and the second clock signal CLK2 may have a low-level voltage LV in the third period P3 and the seventh period P7. The first clock signal CLK1 may have a high-level voltage HV in the second period P2 to the fourth period P4 and the sixth period P6 to the eighth period P8, and the second clock signal CLK2 may have a high-level voltage HV in the first period P1, the second period P2, the fourth period P4 to the sixth period P6, and the eighth period P8.

[0081] In addition, the first clock signal CLK1 may have a low-level voltage LV in the eleventh period P11, and a high-level voltage HV in the ninth period P9, the tenth period P10, and the twelfth period P12. The second clock signal CLK2 may have a low-level voltage LV in the ninth period P9, and a high-level voltage HV in the tenth period P10 to the twelfth period P12.

[0082] The input signal FLM / CARRY may have a low-level voltage LV in the first to fourth periods P1 to P4, and a high-level voltage HV in the fifth to eighth periods P5 to P8. The input signal FLM / CARRY may have a high-level voltage HV until the ninth period P9, and have a low-level voltage LV from the ninth period P9.

[0083] The emission control signal EM is shifted to a high-level voltage HV in response to the second clock signal CLK2 having a low-level voltage LV while the input signal FLM / CARRY has a high-level voltage HV, and is shifted to a low-level voltage LV in response to the first clock signal CLK1 having a low-level voltage LV while the input signal FLM / CARRY has a low-level voltage LV.

[0084] In the first period P1 , the input signal FLM / CARRY having the low level voltage LV, the first clock signal CLK1 having the low level voltage LV, and the second clock signal CLK2 having the high level voltage HV are input to the stage 100 .

[0085] During a first period P1, the first circuit unit 110 generates a first control signal SC1 having a low-level voltage LV and a second control signal SC2 having a low-level voltage LV. During the first period P1, the first switching transistor T1 is turned on in response to the first clock signal CLK1 having a low-level voltage LV, and the input signal FLM / CARRY having a low-level voltage LV is transmitted to the first node N1. As a result, the voltage of the first node N1 (i.e., the first control signal SC1) has a low-level voltage LV. The first control signal SC1 having a low-level voltage LV is transmitted to the first output node NQ.

[0086] The second switching transistor T2 is turned on in response to the low-level voltage LV at the first node N1, and the first clock signal CLK1 having the low-level voltage LV is transmitted to the second node N2. In addition, the third switching transistor T3 is turned on in response to the first clock signal CLK1 having the low-level voltage LV, and the first voltage VGL is applied to the second node N2. Therefore, the voltage of the second node N2 (i.e., the second control signal SC2) has the low-level voltage LV.

[0087] The fifth switching transistor T5 is turned on in response to the low-level voltage LV of the second node N2 (i.e., the second control signal SC2), and the second voltage VGH is applied to the third node N3. In addition, the fourth switching transistor T4 is turned on in response to the low-level voltage LV of the first output node NQ, and the second clock signal CLK2 of the high-level voltage HV is transmitted to the third node N3.

[0088] The high level voltage HV is applied to the first electrode of the second capacitor C2 connected to the third node N3, and the low level voltage LV is applied to the second electrode connected to the first output node NQ, thus storing the reference voltage difference in the second capacitor C2.

[0089] The sixth switching transistor T6 is turned on in response to the low-level voltage LV (i.e., the second control signal SC2) at the second node N2, and the second clock signal CLK2 of the high-level voltage HV is transmitted to the fourth node N4. The seventh switching transistor T7 is turned off in response to the second clock signal CLK2 of the high-level voltage HV, and the eighth switching transistor T8 is turned on in response to the low-level voltage LV at the first node N1, and the second voltage VGH is applied to the second output node NQB. The high-level voltage HV is applied to both electrodes of the third capacitor C3.

[0090] The first output transistor M1 can be weakly turned on in response to the low-level voltage LV of the first output node NQ, and can output the emission control signal EM of the low-level voltage LV when the first voltage VGL is applied to the stage output node NO. The second output transistor M2 is turned off in response to the high-level voltage HV of the second output node NQB.

[0091] The floating transistor FT is turned off in response to the low-level voltage LV of the first node N1, and the low-level voltage LV of the second node N2 is not transmitted to the fifth node N5. Therefore, no current is charged into or discharged from the first capacitor C1, and thus no power consumption for charging or discharging the first capacitor C1 occurs in the first period P1.

[0092] In the second period P2, the input signal FLM / CARRY having the low level voltage LV, the first clock signal CLK1 having the high level voltage HV, and the second clock signal CLK2 having the high level voltage HV are input to the stage 100. In the second period P2, the first circuit portion 110 generates the first control signal SC1 having the low level voltage LV and the second control signal SC2 having the high level voltage HV.

[0093] During the second period P2, the first switching transistor T1 is turned off in response to the first clock signal CLK1 having a high-level voltage HV, and the input signal FLM / CARRY having a low-level voltage LV is not transmitted to the first node N1. However, the fourth switching transistor T4 is turned on due to the reference voltage difference stored in the second capacitor C2. The second clock signal CLK2 having a high-level voltage HV is applied to the third node N3 through the turned-on fourth switching transistor T4. The first output node NQ and the first node N1 have a low-level voltage LV due to the second capacitor C2 storing the reference voltage difference. The first control signal SC1 of the first node N1 has a low-level voltage LV.

[0094] The third switching transistor T3 is turned off in response to the first clock signal CLK1 of the high level voltage HV, and the second switching transistor T2 is turned on in response to the low level voltage LV of the first node N1. The first clock signal CLK1 of the high level voltage HV is transmitted to the second node N2.

[0095] The high voltage HV at the second node N2 turns off the fifth and sixth switching transistors T5 and T6. Furthermore, the seventh switching transistor T7 turns off in response to the second clock signal CLK2 at the high voltage HV. The eighth switching transistor T8 turns on in response to the low voltage LV at the first node N1, and the second voltage VGH is applied to the second output node NQB. The high voltage HV is applied to both electrodes of the third capacitor C3.

[0096] The first output transistor M1 can be weakly turned on in response to the low-level voltage LV of the first output node NQ, and can output the emission control signal EM of the low-level voltage LV when the first voltage VGL is applied to the stage output node NO. The second output transistor M2 is turned off in response to the high-level voltage HV of the second output node NQB.

[0097] The floating transistor FT is turned off in response to the low-level voltage LV of the first node N1 , and the high-level voltage HV of the second node N2 is not transferred to the fifth node N5 .

[0098] When the floating transistor FT connected to both electrodes of the first capacitor C1 and the sixth and seventh switching transistors T6 and T7 are all turned off, the first capacitor C1 is in a floating state, and no current is charged into or discharged from the first capacitor C1. Therefore, during the second period P2, there is no power consumption for charging or discharging the first capacitor C1.

[0099] In the third period P3, the input signal FLM / CARRY having the low level voltage LV, the first clock signal CLK1 having the high level voltage HV, and the second clock signal CLK2 having the low level voltage LV are input to the stage 100. In the third period P3, the first circuit portion 110 generates the first control signal SC1 having the second low level voltage LV2 and the second control signal SC2 having the high level voltage HV.

[0100] During the third period P3, the first switching transistor T1 is turned off in response to the first clock signal CLK1 having a high-level voltage HV. However, the fourth switching transistor T4 is turned on due to the reference voltage difference stored in the second capacitor C2. The third node N3 is supplied with the second clock signal CLK2 having a low-level voltage LV via the turned-on fourth switching transistor T4. The first output node NQ and the first node N1 have a second low-level voltage LV2 due to the second capacitor C2 storing the reference voltage difference. The second low-level voltage LV2 is a voltage lower than the low-level voltage LV by the reference voltage difference. The first control signal SC1 of the first node N1 has a second low-level voltage LV2.

[0101] The third switching transistor T3 is turned off in response to the first clock signal CLK1 of the high level voltage HV, and the second switching transistor T2 is turned on in response to the second low level voltage LV2 of the first node N1. The first clock signal CLK1 of the high level voltage HV is transmitted to the second node N2.

[0102] The high-level voltage HV at the second node N2 turns off the fifth and sixth switching transistors T5 and T6. The eighth switching transistor T8 is turned on in response to the low-level voltage LV at the first node N1, and the second voltage VGH is applied to the second output node NQB. The high-level voltage HV is applied to both electrodes of the third capacitor C3. The seventh switching transistor T7 is turned on in response to the second clock signal CLK2 with the low-level voltage LV, and the high-level voltage HV at the second output node NQB is transmitted to the fourth node N4.

[0103] The first output transistor M1 is fully turned on in response to the second low-level voltage LV2 of the first output node NQ, and outputs the emission control signal EM of the low-level voltage LV when the first voltage VGL is applied to the stage output node NO. The second output transistor M2 is turned off in response to the high-level voltage HV of the second output node NQB.

[0104] The floating transistor FT is turned off in response to the second low-level voltage LV2 of the first node N1, and the high-level voltage HV of the second node N2 is not applied to the fifth node N5. Therefore, no current is charged into or discharged from the first capacitor C1, and thus no power consumption for charging or discharging the first capacitor C1 occurs in the third period P3.

[0105] In the fourth period P4, the input signal FLM / CARRY having the low level voltage LV, the first clock signal CLK1 having the high level voltage HV, and the second clock signal CLK2 having the high level voltage HV are input to the stage 100. In the fourth period P4, the first circuit portion 110 generates the first control signal SC1 having the low level voltage LV and the second control signal SC2 having the high level voltage HV.

[0106] During the fourth period P4, the first switching transistor T1 is turned off in response to the first clock signal CLK1 having a high-level voltage HV. However, the fourth switching transistor T4 is turned on due to the reference voltage difference stored in the second capacitor C2. The second clock signal CLK2 having a high-level voltage HV is applied to the third node N3 through the turned-on fourth switching transistor T4. The first output node NQ and the first node N1 have a low-level voltage LV due to the second capacitor C2 storing the reference voltage difference. The first control signal SC1 of the first node N1 has a low-level voltage LV.

[0107] The third switching transistor T3 is turned off in response to the first clock signal CLK1 of the high level voltage HV, and the second switching transistor T2 is turned on in response to the low level voltage LV of the first node N1. The first clock signal CLK1 of the high level voltage HV is transmitted to the second node N2.

[0108] The high voltage HV at the second node N2 turns off the fifth and sixth switching transistors T5 and T6. Furthermore, the seventh switching transistor T7 turns off in response to the second clock signal CLK2 at the high voltage HV. The eighth switching transistor T8 turns on in response to the low voltage LV at the first node N1, and the second voltage VGH is applied to the second output node NQB. The high voltage HV is applied to both electrodes of the third capacitor C3.

[0109] The first output transistor M1 is turned on in response to the low-level voltage LV of the first output node NQ, and outputs the emission control signal EM of the low-level voltage LV when the first voltage VGL is applied to the stage output node NO. The second output transistor M2 is turned off in response to the high-level voltage HV of the second output node NQB.

[0110] The floating transistor FT is turned off in response to the low-level voltage LV at the first node N1. When the floating transistor FT, the sixth switching transistor T6, and the seventh switching transistor T7, connected to both electrodes of the first capacitor C1, are turned off, the first capacitor C1 is in a floating state, and no current is charged into or discharged from the first capacitor C1. Therefore, no power is consumed by charging or discharging the first capacitor C1 during the fourth period P4.

[0111] In the fifth period P5, the input signal FLM / CARRY having the high level voltage HV, the first clock signal CLK1 having the low level voltage LV, and the second clock signal CLK2 having the high level voltage HV are input to the stage 100. In the fifth period P5, the first circuit portion 110 generates the first control signal SC1 having the high level voltage HV and the second control signal SC2 having the low level voltage LV.

[0112] The first switching transistor T1 is turned on in response to the first clock signal CLK1 having a low-level voltage LV, and the input signal FLM / CARRY having a high-level voltage HV is transmitted to the first node N1. Therefore, the voltage of the first node N1 (i.e., the first control signal SC1) has a high-level voltage HV. The first control signal SC1 having a high-level voltage HV is transmitted to the first output node NQ.

[0113] The second switching transistor T2 is turned off in response to the high-level voltage HV of the first node N1. The third switching transistor T3 is turned on in response to the first clock signal CLK1 having the low-level voltage LV, and the first voltage VGL is applied to the second node N2. The voltage of the second node N2 (i.e., the second control signal SC2) has the low-level voltage LV.

[0114] The fourth switching transistor T4 is turned off in response to the high-level voltage HV of the first output node NQ. The fifth switching transistor T5 is turned on in response to the low-level voltage LV of the second node N2 (i.e., the second control signal SC2), and the second voltage VGH is applied to the third node N3. When the high-level voltage HV is applied to both electrodes of the second capacitor C2 connected between the third node N3 and the first output node NQ, substantially zero voltage is stored in the second capacitor C2.

[0115] The sixth switching transistor T6 is turned on in response to the low-level voltage LV of the second node N2 (i.e., the second control signal SC2), and the second clock signal CLK2 of the high-level voltage HV is transmitted to the fourth node N4. The floating transistor FT is turned on in response to the high-level voltage HV of the first node N1, and the low-level voltage LV of the second node N2 is transmitted to the fifth node N5. The first capacitor C1 may include a first electrode connected to the fourth node N4 and a second electrode connected to the fifth node N5. The high-level voltage HV of the second clock signal CLK2 is applied to the first electrode, and the low-level voltage LV of the second node N2 is applied to the second electrode. Therefore, the voltage difference between the high-level voltage HV and the low-level voltage LV (i.e., the reference voltage difference) is stored in the first capacitor C1.

[0116] The seventh switching transistor T7 is turned off in response to the second clock signal CLK2 having a high voltage level HV, and the eighth switching transistor T8 is turned off in response to the high voltage level HV at the first node N1. The second voltage VGH is applied to the first electrode of the third capacitor C3, storing a substantially zero voltage in the third capacitor C3. The second output node NQB has a high voltage level HV due to the substantially zero voltage stored in the third capacitor C3.

[0117] The first output transistor M1 is turned off in response to the high-level voltage HV of the first output node NQ, and the second output transistor M2 is turned off in response to the high-level voltage HV of the second output node NQB. Since the control line for outputting the emission control signal EM has parasitic capacitance, the emission control signal EM may maintain the voltage of the previous period (i.e., the low-level voltage LV of the fourth period P4).

[0118] The floating transistor FT is turned on in response to the high voltage HV of the first node N1, and the low voltage LV of the second node N2 is transmitted to the fifth node N5. When the reference voltage difference is stored in the first capacitor C1 in the fourth period P4, there is no power consumption for charging or discharging the first capacitor C1 in the fifth period P5.

[0119] In the sixth period P6, the input signal FLM / CARRY having the high level voltage HV, the first clock signal CLK1 having the high level voltage HV, and the second clock signal CLK2 having the high level voltage HV are input to the stage 100. In the sixth period P6, the first circuit portion 110 generates the first control signal SC1 having the high level voltage HV and the second control signal SC2 having the low level voltage LV.

[0120] The first switching transistor T1 is turned off in response to the first clock signal CLK1 having a high-level voltage HV. However, the sixth switching transistor T6 is turned on due to the reference voltage difference stored in the first capacitor C1. The second clock signal CLK2 having a high-level voltage HV is applied to the fourth node N4 through the turned-on sixth switching transistor T6. The fifth node N5 has a low-level voltage LV due to the first capacitor C1 storing the reference voltage difference. As described below, when the floating transistor FT is turned on in the sixth period P6 and the fifth node N5 and the second node N2 are connected to each other, the second control signal SC2 of the second node N2 has a low-level voltage LV.

[0121] The fifth switching transistor T5 is turned on in response to the low-level voltage LV of the second node N2, and the second voltage VGH is applied to the third node N3. In the fifth period P5, when substantially zero voltage is stored in the second capacitor C2, the first output node NQ and the first node N1 have a high-level voltage HV due to the second capacitor C2 storing substantially zero voltage.

[0122] The second switching transistor T2 is turned off in response to the high voltage HV of the first node N1, and the third switching transistor T3 is turned off in response to the high voltage HV of the first clock signal CLK1. As described above, the floating transistor FT is turned on in response to the high voltage HV of the first node N1.

[0123] The seventh switching transistor T7 is turned off in response to the high voltage HV of the second clock signal CLK2, and the eighth switching transistor T8 is turned off in response to the high voltage HV of the first node N1. The second voltage VGH is applied to the first electrode of the third capacitor C3, and a substantially zero voltage is stored in the third capacitor C3. The second output node NQB has a high voltage HV due to the substantially zero voltage stored in the third capacitor C3.

[0124] The first output transistor M1 is turned off in response to the high-level voltage HV of the first output node NQ, and the second output transistor M2 is turned off in response to the high-level voltage HV of the second output node NQB. Since the control line for outputting the emission control signal EM has parasitic capacitance, the emission control signal EM may maintain the voltage of the previous period (i.e., the low-level voltage LV of the fourth period P4).

[0125] In the sixth period P6 , since the first capacitor C1 maintains the reference voltage difference, there is no power consumption for charging or discharging the first capacitor C1 .

[0126] In the seventh period P7, the input signal FLM / CARRY having the high level voltage HV, the first clock signal CLK1 having the high level voltage HV, and the second clock signal CLK2 having the low level voltage LV are input to the stage 100. In the seventh period P7, the first circuit portion 110 generates the first control signal SC1 having the high level voltage HV and the second control signal SC2 having the second low level voltage LV2.

[0127] The first switching transistor T1 is turned off in response to the first clock signal CLK1 having a high-level voltage HV. However, the sixth switching transistor T6 is turned on due to the reference voltage difference stored in the first capacitor C1. The low-level voltage LV of the second clock signal CLK2 is applied to the fourth node N4 through the turned-on sixth switching transistor T6. The fifth node N5 has a second low-level voltage LV2 due to the first capacitor C1 storing the reference voltage difference. The second low-level voltage LV2 is a voltage lower than the low-level voltage LV by the reference voltage difference. As described below, in the seventh period P7, when the floating transistor FT is turned on and the fifth node N5 and the second node N2 are connected to each other, the second control signal SC2 of the second node N2 has a second low-level voltage LV2.

[0128] The fifth switching transistor T5 is turned on in response to the second low-level voltage LV2 of the second node N2, and the second voltage VGH is applied to the third node N3. In the sixth period P6, when substantially zero voltage is stored in the second capacitor C2, the first output node NQ and the first node N1 have a high-level voltage HV due to the second capacitor C2 storing substantially zero voltage.

[0129] The second switching transistor T2 is turned off in response to the high voltage HV of the first node N1, and the third switching transistor T3 is turned off in response to the high voltage HV of the first clock signal CLK1. As described above, the floating transistor FT is turned on in response to the high voltage HV of the first node N1.

[0130] The seventh switching transistor T7 is turned on in response to the low level voltage LV of the second clock signal CLK2 and connects the fourth node N4 and the second output node NQB to each other. The low level voltage LV of the second clock signal CLK2 is applied not only to the fourth node N4 but also to the second output node NQB.

[0131] The eighth switching transistor T8 is turned off in response to the high voltage HV of the first node N1. When the second voltage VGH is applied to the first electrode of the third capacitor C3 and the low voltage LV is applied to the second electrode connected to the second output node NQB, the reference voltage difference is stored in the third capacitor C3.

[0132] When the second output transistor M2 is turned on in response to the low level voltage LV of the second output node NQB and the second voltage VGH is applied to the stage output node NO, the emission control signal EM of the high level voltage HV is output. The first output transistor M1 is turned off in response to the high level voltage HV of the first output node NQ.

[0133] In the seventh period P7 , since the first capacitor C1 maintains the reference voltage difference, there is no power consumption for charging or discharging the first capacitor C1 .

[0134] In the eighth period P8, the input signal FLM / CARRY having the high level voltage HV, the first clock signal CLK1 having the high level voltage HV, and the second clock signal CLK2 having the high level voltage HV are input to the stage 100. In the eighth period P8, the first circuit portion 110 generates the first control signal SC1 having the high level voltage HV and the second control signal SC2 having the low level voltage LV.

[0135] The first switching transistor T1 is turned off in response to the high-level voltage HV of the first clock signal CLK1. However, the sixth switching transistor T6 is turned on due to the reference voltage difference stored in the first capacitor C1. The high-level voltage HV of the second clock signal CLK2 is applied to the fourth node N4 through the turned-on sixth switching transistor T6. The fifth node N5 has a low-level voltage LV due to the first capacitor C1 storing the reference voltage difference. As described below, in the eighth period P8, when the floating transistor FT is turned on and the fifth node N5 and the second node N2 are connected to each other, the second control signal SC2 of the second node N2 has a low-level voltage LV.

[0136] The fifth switching transistor T5 is turned on in response to the low-level voltage LV of the second node N2, and the second voltage VGH is applied to the third node N3. In the seventh period P7, when substantially zero voltage is stored in the second capacitor C2, the first output node NQ and the first node N1 have a high-level voltage HV due to the second capacitor C2 storing substantially zero voltage.

[0137] The second switching transistor T2 is turned off in response to the high voltage HV of the first node N1, and the third switching transistor T3 is turned off in response to the high voltage HV of the first clock signal CLK1. As described above, the floating transistor FT is turned on in response to the high voltage HV of the first node N1.

[0138] The seventh switching transistor T7 is turned off in response to the high-level voltage HV of the second clock signal CLK2. The eighth switching transistor T8 is turned off in response to the high-level voltage HV of the first node N1. When the reference voltage difference is stored in the third capacitor C3 and the second voltage VGH is applied to the first electrode of the third capacitor C3, the second output node NQB has a low-level voltage LV.

[0139] When the second output transistor M2 is turned on in response to the low level voltage LV of the second output node NQB and the second voltage VGH is applied to the stage output node NO, the emission control signal EM of the high level voltage HV is output. The first output transistor M1 is turned off in response to the high level voltage HV of the first output node NQ.

[0140] In the eighth period P8 , since the first capacitor C1 maintains the reference voltage difference, there is no power consumption for charging or discharging the first capacitor C1 .

[0141] When the input signal FLM / CARRY has a high-level voltage HV, the operations of the fifth period P5 to the eighth period P8 are repeated, and the stage output node NO outputs the emission control signal EM of the high-level voltage HV. Since the reference voltage difference is applied to both electrodes of the first capacitor C1 in the fifth period P5 and the first capacitor C1 maintains the reference voltage difference from the sixth period P6 to the eighth period P8, when the operations of the fifth period P5 to the eighth period P8 are repeated, there is substantially no power consumption for charging or discharging the first capacitor C1.

[0142] In the ninth period P9, the input signal FLM / CARRY is shifted to the low-level voltage LV. In the ninth period P9, the input signal FLM / CARRY having the low-level voltage LV, the first clock signal CLK1 having the high-level voltage HV, and the second clock signal CLK2 having the low-level voltage LV are input to the stage 100. In the ninth period P9, the first circuit unit 110 generates the first control signal SC1 having the high-level voltage HV and the second control signal SC2 having the second low-level voltage LV2.

[0143] Although the ninth period P9 is different from the seventh period P7 in that the input signal FLM / CARRY has a low-level voltage LV, when the first switching transistor T1 is turned off by the high-level voltage HV of the first clock signal CLK1, the low-level voltage LV of the input signal FLM / CARRY is not applied to the first node N1. Therefore, the operation of the ninth period P9 is substantially the same as that of the seventh period P7.

[0144] The first switching transistor T1 is turned off in response to the first clock signal CLK1 having a high-level voltage HV. However, the sixth switching transistor T6 is turned on due to the reference voltage difference stored in the first capacitor C1. The low-level voltage LV of the second clock signal CLK2 is applied to the fourth node N4 through the sixth switching transistor T6. The fifth node N5 has a second low-level voltage LV2 due to the first capacitor C1 storing the reference voltage difference. When the fifth node N5 and the second node N2 are connected to each other through the turned-on floating transistor FT, the second control signal SC2 of the second node N2 has a second low-level voltage LV2.

[0145] The fifth switching transistor T5 is turned on in response to the second low level voltage LV2 of the second node N2, and the second voltage VGH is applied to the third node N3. The first output node NQ and the first node N1 have a high level voltage HV due to the second capacitor C2 storing substantially zero voltage.

[0146] The second switching transistor T2 is turned off in response to the high voltage HV of the first node N1, the third switching transistor T3 is turned off in response to the high voltage HV of the first clock signal CLK1, and the floating transistor FT is turned on in response to the high voltage HV of the first node N1.

[0147] The seventh switching transistor T7 is turned on in response to the low level voltage LV of the second clock signal CLK2 and connects the fourth node N4 and the second output node NQB to each other. The low level voltage LV of the second clock signal CLK2 is applied not only to the fourth node N4 but also to the second output node NQB.

[0148] The eighth switching transistor T8 is turned off in response to the high voltage HV of the first node N1. When the second voltage VGH is applied to the first electrode of the third capacitor C3 and the low voltage LV is applied to the second electrode connected to the second output node NQB, the reference voltage difference is stored in the third capacitor C3.

[0149] When the second output transistor M2 is turned on in response to the low level voltage LV of the second output node NQB and the second voltage VGH is applied to the stage output node NO, the emission control signal EM of the high level voltage HV is output. The first output transistor M1 is turned off in response to the high level voltage HV of the first output node NQ.

[0150] In the ninth period P9 , since the first capacitor C1 maintains the reference voltage difference, there is no power consumption for charging or discharging the first capacitor C1 .

[0151] In the tenth period P10, the input signal FLM / CARRY having the low level voltage LV, the first clock signal CLK1 having the high level voltage HV, and the second clock signal CLK2 having the high level voltage HV are input to the stage 100. In the tenth period P10, the first circuit portion 110 generates the first control signal SC1 having the high level voltage HV and the second control signal SC2 having the low level voltage LV.

[0152] Although the tenth period P10 is different from the eighth period P8 in that the input signal FLM / CARRY has a low-level voltage LV, when the first switching transistor T1 is turned off by the high-level voltage HV of the first clock signal CLK1, the low-level voltage LV of the input signal FLM / CARRY is not applied to the first node N1. Therefore, the operation of the tenth period P10 is substantially the same as that of the eighth period P8.

[0153] The sixth switching transistor T6 is turned on due to the reference voltage difference stored in the first capacitor C1. The high-level voltage HV of the second clock signal CLK2 is applied to the fourth node N4 through the sixth switching transistor T6. The fifth node N5 has a low-level voltage LV due to the first capacitor C1 storing the reference voltage difference. When the fifth node N5 and the second node N2 are connected to each other through the turned-on floating transistor FT, the second control signal SC2 of the second node N2 has a low-level voltage LV.

[0154] The fifth switching transistor T5 is turned on in response to the low voltage LV of the second node N2, and the second voltage VGH is applied to the third node N3. The first output node NQ and the first node N1 have a high voltage HV due to the second capacitor C2 storing substantially zero voltage.

[0155] The second switching transistor T2 is turned off in response to the high voltage HV of the first node N1, the third switching transistor T3 is turned off in response to the high voltage HV of the first clock signal CLK1, and the floating transistor FT is turned on in response to the high voltage HV of the first node N1.

[0156] The seventh switching transistor T7 is turned off in response to the high-level voltage HV of the second clock signal CLK2. The eighth switching transistor T8 is turned off in response to the high-level voltage HV of the first node N1. When the reference voltage difference is stored in the third capacitor C3 and the second voltage VGH is applied to the first electrode of the third capacitor C3, the second output node NQB has a low-level voltage LV.

[0157] When the second output transistor M2 is turned on in response to the low level voltage LV of the second output node NQB and the second voltage VGH is applied to the stage output node NO, the emission control signal EM of the high level voltage HV is output. The first output transistor M1 is turned off in response to the high level voltage HV of the first output node NQ.

[0158] In the tenth period P10 , since the first capacitor C1 maintains the reference voltage difference, there is no power consumption for charging or discharging the first capacitor C1 .

[0159] In the eleventh period P11, the input signal FLM / CARRY having the low level voltage LV, the first clock signal CLK1 having the low level voltage LV, and the second clock signal CLK2 having the high level voltage HV are input to the stage 100. In the eleventh period P11, the first circuit portion 110 generates the first control signal SC1 having the low level voltage LV and the second control signal SC2 having the low level voltage LV.

[0160] The signal input in the eleventh period P11 has the same voltage level as the signal input in the first period P1. The first switching transistor T1 is turned on by the low-level voltage LV of the first clock signal CLK1, and the low-level voltage LV of the input signal FLM / CARRY is applied to the first node N1. Therefore, the operation of the eleventh period P11 is substantially the same as that of the first period P1.

[0161] The first switching transistor T1 is turned on in response to the low level voltage LV of the first clock signal CLK1, the low level voltage LV of the input signal FLM / CARRY is applied to the first node N1, and the voltages of the first node N1 and the first output node NQ have the low level voltage LV.

[0162] The second switching transistor T2 is turned on in response to the low-level voltage LV of the first node N1, and the low-level voltage LV of the first clock signal CLK1 is applied to the second node N2. The third switching transistor T3 is turned on in response to the low-level voltage LV of the first clock signal CLK1, and the first voltage VGL is applied to the second node N2. The voltage of the second node N2 (i.e., the second control signal SC2) has the low-level voltage LV.

[0163] The fifth switching transistor T5 is turned on in response to the low-level voltage LV at the second node N2, and the second voltage VGH is applied to the third node N3. The fourth switching transistor T4 is turned on in response to the low-level voltage LV at the first output node NQ, and the high-level voltage HV of the second clock signal CLK2 is transmitted to the third node N3. When the high-level voltage HV is applied to the first electrode of the second capacitor C2 and the low-level voltage LV is applied to the second electrode connected to the first output node NQ, a reference voltage difference is stored in the second capacitor C2.

[0164] The sixth switching transistor T6 is turned on in response to the low-level voltage LV at the second node N2, and the high-level voltage HV of the second clock signal CLK2 is applied to the fourth node N4. The seventh switching transistor T7 is turned off in response to the high-level voltage HV of the second clock signal CLK2. The eighth switching transistor T8 is turned on in response to the low-level voltage LV at the first node N1, and the second voltage VGH is applied to the second output node NQB. When the high-level voltage HV is applied to both electrodes of the third capacitor C3, the third capacitor C3 stores substantially zero voltage.

[0165] Since the first output transistor M1 can be weakly turned on in response to the low-level voltage LV of the first output node NQ and the first voltage VGL is applied to the stage output node NO, the emission control signal EM of the low-level voltage LV can be output. The second output transistor M2 is turned off in response to the high-level voltage HV of the second output node NQB.

[0166] The floating transistor FT is turned off in response to the low-level voltage LV of the first node N1, and the low-level voltage LV of the second node N2 is not transmitted to the fifth node N5. Therefore, no current is charged into or discharged from the first capacitor C1, and thus there is no power consumption for charging or discharging the first capacitor C1 in the eleventh period P11.

[0167] In the twelfth period P12 , the input signal FLM / CARRY having the low level voltage LV, the first clock signal CLK1 having the high level voltage HV, and the second clock signal CLK2 having the high level voltage HV are input to the stage 100 .

[0168] The signal input in the twelfth period P12 has the same voltage level as the signal input in the second period P2. Therefore, the operation of the twelfth period P12 is substantially the same as the operation of the second period P2. Then, until the input signal FLM / CARRY having a high level voltage HV is input to the stage 100, the operations of the third period P3, the fourth period P4, the first period P1, and the second period P2 are repeated.

[0169] According to the reference Figure 3 With the described operation of the stage 100, the first capacitor C1 can maintain a substantially constant reference voltage difference. Therefore, there is substantially no power consumption in charging or discharging the first capacitor C1.

[0170] Figure 4 is a circuit diagram of the stage 200 included in the emission control driver 1000 according to some example embodiments.

[0171] Reference Figure 4The stage 200 may include a first circuit section 210, a second circuit section 220, a third circuit section 230, a first output transistor M1, and a second output transistor M2. Figure 1 The first stage 1100 , the second stage 1200 and the third stage 1300 correspond to one of the first stage 1100 , the second stage 1200 and the third stage 1300 .

[0172] The first circuit section 210, the second circuit section 220, the third circuit section 230, the first output transistor M1 and the second output transistor M2 are respectively included in Figure 2 The first circuit section 110 , the second circuit section 120 , the third circuit section 130 , the first output transistor M1 , and the second output transistor M2 in the stage 100 substantially correspond to each other.

[0173] The stage 200 may further include a first normally-on transistor AOT1 through which the second control signal SC2 is transmitted between the first circuit portion 210 and the third circuit portion 230. The first normally-on transistor AOT1 may be always on by including a gate having a low-level first voltage VGL applied thereto, and may connect the second node N2 and the floating transistor FT to each other.

[0174] The first normally-on transistor AOT1 can protect the fifth switch transistor T5 from the voltage applied to the gate of the fifth switch transistor T5. For example, because the second node N2 has the second low-level voltage LV2 during the seventh period P7 and the ninth period P9, the second low-level voltage LV2 is applied to the gate of the fifth switch transistor T5. In this case, the on-resistance of the first normally-on transistor AOT1 can protect the fifth switch transistor T5.

[0175] The stage 200 may further include a second normally-on transistor AOT2, through which the first control signal SC1 is transmitted between the first circuit portion 210 and the first output node NQ. The second normally-on transistor AOT2 may be always on by including a gate having a low-level first voltage VGL applied thereto, and may connect the first node N1 and the first output node NQ to each other.

[0176] The second normally-on transistor AOT2 has an on-resistance between the first node N1 and the first output node NQ and can protect the first switch transistor T1 by preventing an excessive voltage from being applied between the drain and the source of the first switch transistor T1.

[0177] The two switching transistors T2-1 and T2-2 of stage 200 are connected in series to perform the same function as the second switching transistor T2 of stage 100. The two switching transistors T2-1 and T2-2 can prevent the charge stored in the first capacitor C1 from leaking. Therefore, the power consumption used to replenish the charge leaked from the first capacitor C1 can be reduced.

[0178] Figure 5 yes Figure 4 The voltage waveforms of the main nodes of the circuit diagram.

[0179] Reference Figure 5 , Figure 5 The voltage waveform and Figure 3 The timing diagrams are basically the same.

[0180] like Figure 5 As shown in FIG, the voltage between the fourth node N4 and the fifth node N5 is always kept substantially constant. In the second period P2, the fourth period P4, and the twelfth period P12 in which the first capacitor C1 is in a floating state, although the potentials of the fourth node N4 and the fifth node N5 increase by substantially the same amount due to the influence of the parasitic capacitance, the first capacitor C1 is not charged or discharged during this period. Therefore, it can be seen that there is substantially no power consumption for charging or discharging the first capacitor C1.

[0181] Figure 6 is a circuit diagram of the stage 300 included in the emission control driver 1000 according to a comparative example.

[0182] Reference Figure 4 and Figure 6 According to the comparative example, stage 300 may include a first circuit portion 310, a second circuit portion 320, a third circuit portion 330, a first output transistor M1, and a second output transistor M2. Stage 300 is identical to stage 200 except that it does not include the floating transistor FT of stage 200.

[0183] Figure 7 yes Figure 6 The voltage waveforms of the main nodes of the circuit diagram.

[0184] Reference Figure 7 As shown in the rectangular box B, although the voltage waveform of the fourth node N4 and the voltage waveform of the fifth node N5 correspond to each other in the period in which the input signal FLM / CARRY has the high level voltage HV, the voltage waveform of the fourth node N4 and the voltage waveform of the fifth node N5 are different from each other in the period in which the input signal FLM / CARRY has the low level voltage LV.

[0185] For example, in the first period P1, when a high-level voltage HV is applied to the fourth node N4 and a low-level voltage LV is applied to the fifth node N5, the first capacitor C1 stores a reference voltage difference. In the third period P3, when the high-level voltage HV is applied to both the fourth node N4 and the fifth node N5, the first capacitor C1 stores a substantially zero voltage. Therefore, during the period in which the input signal FLM / CARRY of the low-level voltage LV is input, the stage 300 repeats the operations corresponding to the first to fourth periods P1 to P4. The first capacitor C1 discharges from the reference voltage difference to substantially zero voltage between the first period P1 and the third period P3, and charges from substantially zero voltage to the reference voltage difference between the third period P3 and the first period P1. In this manner, because the first capacitor C1 unnecessarily repeats charging and discharging, unnecessary power consumption occurs.

[0186] Return to reference Figure 5 , as shown in the rectangular box A, in the period in which the input signal FLM / CARRY has the low level voltage LV, since the difference between the voltage of the fourth node N4 and the voltage of the fifth node N5 is constant, the first capacitor C1 is not unnecessarily repeatedly charged and discharged, thereby preventing unnecessary power consumption.

[0187] Figure 8 is a block diagram of a display device 500 according to an embodiment. Figure 9 is included in Figure 8 5 is a circuit diagram of an example of a pixel circuit of a pixel Px in a display device 500, but the embodiments of the present disclosure are not limited thereto, and the pixel circuit may include additional or fewer electrical components without departing from the spirit and scope of the embodiments of the present disclosure.

[0188] Reference Figure 8 , the display device 500 may include a display panel 510 , a scan driver 520 , a data driver 530 , an emission control driver 540 , and a timing controller 550 .

[0189] The display panel 510 may include a plurality of pixels Px. A plurality of data lines DL and a plurality of scan lines SL may be arranged in the display panel 510, and the plurality of pixels Px may be arranged in regions where the data lines DL and the scan lines SL intersect each other.

[0190] Reference Figure 9, a pixel (or pixel circuit) Px may include a driving transistor TD, a switching transistor TS, a storage capacitor Cst, an emission transistor TE, and an organic light emitting diode EL. The switching transistor TS may be turned on or off in response to a scan signal SCAN supplied via a scan line SL. When the switching transistor TS is turned on in response to the scan signal SCAN, a data signal DATA supplied via a data line DL may be stored in the storage capacitor Cst. The driving transistor TD may generate a driving current based on the data signal DATA. The emission transistor TE may be turned on or off in response to an emission control signal EM supplied via an emission control line EML. When the emission transistor TE is turned on in response to the emission control signal EM, a driving current may be supplied to the organic light emitting diode EL.

[0191] like Figure 9 As shown in FIG, the driving transistor TD, the switching transistor TS, and the emission transistor TE may be implemented by p-type MOSFETs. In this case, the driving transistor TD, the switching transistor TS, and the emission transistor TE may be turned on in response to a signal having a low-level voltage (eg, VGL). Figure 9 The driving transistor TD, the switching transistor TS, and the emission transistor TE are illustrated as being implemented by p-type MOSFETs, but the driving transistor TD, the switching transistor TS, and the emission transistor TE are not limited thereto.

[0192] The scan driver 520 may supply a scan signal SCAN to the pixel Px via the scan line SL. The data driver 530 may supply a data signal DATA to the pixel Px via the data line DL in synchronization with the scan signal SCAN. The timing controller 550 may generate control signals to control the scan driver 520, the data driver 530, and the emission control driver 540.

[0193] The emission control driver 540 can supply an emission control signal EM to the pixel Px via an emission control line EML. The emission control driver 540 can include multiple stages. Each stage connected in cascade can sequentially output the emission control signal EM. Each stage can receive a start signal or a carry signal, a first clock signal, and a second clock signal. Each stage can include a first circuit unit, a second circuit unit, and a third circuit unit.

[0194] The first circuit unit can generate a first control signal at a first node and a second control signal at a second node based on an input signal (such as a start signal or a carry signal) and a first clock signal. The second circuit unit can control the voltage level of the first control signal based on the first control signal and the second clock signal. The third circuit unit can generate a third control signal based on the first control signal, the second control signal and the second clock signal. The first output transistor can output a first voltage as an emission control signal in response to the first control signal, and the second output transistor can output a second voltage as an emission control signal in response to the third control signal.

[0195] The third circuit unit may include a first capacitor configured to maintain a substantially constant voltage between two electrodes while outputting an emission control signal at each stage. Since the substantially constant voltage is maintained between the two electrodes of the first capacitor, the first capacitor is not charged or discharged, and thus, there may be substantially no power consumption for charging or discharging the first capacitor.

[0196] Figure 10 is included Figure 8 1 is a block diagram of an electronic device 600 of a display apparatus 500. Figure 11 Shown Figure 10 The electronic device 600 is implemented as an example of a smart phone 700 .

[0197] Reference Figure 10 and Figure 11 , the electronic device 600 may include a processor 610, a memory device 620, a storage device 630, an input / output device 640, a power supply 650, and a display device 660. In this state, the display device 660 may be connected to Figure 8 In addition, the electronic device 600 may also include several ports that can communicate with a video card, a sound card, a memory card, a USB device or other systems. Figure 11 As shown in FIG, the electronic device 600 may be implemented by a smart phone 700, but the electronic device 600 is not limited thereto.

[0198] The processor 610 may perform specific calculations or tasks. According to some example embodiments, the processor 610 may be a microprocessor or a central processing unit (CPU). The processor 610 may be connected to other components via an address bus, a control bus, and a data bus. In addition, the processor 610 may be connected to an expansion bus such as a peripheral component interconnect (PCI) bus. The memory device 620 may store data required for the operation of the electronic device 600. For example, the memory device 620 may include a non-volatile memory device (such as an electrically programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, a phase change random access memory (PRAM), a resistive random access memory (RRAM), a magnetic random access memory (MRAM), a ferroelectric random access memory (FRAM), etc.) and / or a volatile memory device (such as a dynamic random access memory (DRAM), a static random access memory (SRAM), a mobile DRAM, etc.). The storage device 630 may include a solid-state drive (SSD), a hard disk drive (HDD), a CD-ROM, etc.

[0199] The input / output device 640 may include input devices such as a keyboard, keypad, touchpad, touch screen, mouse, and the like, and output devices such as a speaker, printer, and the like. A display device 660 may be provided within the input / output device 640. A power supply 650 may supply the power required for the operation of the electronic device 600. The display device 660 may be connected to other components via a bus or other communication link. As described above, the display device 660 may include a display panel, a scan driver, a data driver, an emission control driver, and a timing controller. The display panel may include a plurality of pixels. The scan driver may supply scan signals to the pixels. The data driver may supply data signals to the pixels in response to the scan signals. The emission control driver may supply emission control signals to the pixels. The emission control driver may include multiple stages. Each stage may include a first circuit unit, a second circuit unit, and a third circuit unit. The first circuit unit may generate a first control signal and a second control signal based on a start signal or a carry signal and a first clock signal. The second circuit unit may control the voltage level of the first control signal based on the first control signal and the second clock signal. The third circuit unit may generate a third control signal based on the first control signal, the second control signal, and the second clock signal. The first output transistor and the second output transistor can output an emission control signal in response to the first control signal and the third control signal. In this state, the voltage level of the first control signal can be controlled by utilizing a coupling effect while the first output transistor is turned off, and the voltage level of the first control signal can be maintained while the first output transistor is turned on. Therefore, the first output transistor can be stably driven.

[0200] As described above, the electronic device 600 may include a display device 660 including an emission control driver. In this state, since each stage of the emission control driver includes a first circuit section, a second circuit section, and a third circuit section, and the third circuit section includes a first capacitor configured to maintain a substantially constant voltage between two electrodes while outputting an emission control signal, there may be no power consumption for charging or discharging the first capacitor.

[0201] According to various embodiments, since the transistors connected in series to the capacitors included in each stage of the emission control driver are turned off during a period in which the capacitors are unnecessarily charged and discharged, unnecessary power consumption can be prevented. The emission control driver according to some embodiments and the display device and electronic apparatus including the emission control driver can reduce power consumption.

[0202] Although the present disclosure is described primarily with respect to limited embodiments in this specification, various embodiments are possible within the scope of the present disclosure. Moreover, according to some example embodiments, equivalent means may be incorporated into the present disclosure as is. Therefore, the true scope of protection of the present disclosure should be defined by the claims.

[0203] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope as defined in the claims and their equivalents.

Claims

1. An emission control driver, comprising: a plurality of stages, connected in cascade to each other and configured to sequentially output corresponding emission control signals, Wherein, each of the plurality of stages comprises: a first circuit portion configured to generate a first control signal at a first node and a second control signal at a second node based on an input signal and a first clock signal; a second circuit portion configured to control a voltage level of the first control signal based on the first control signal and a second clock signal; a third circuit unit configured to generate a third control signal based on the first control signal, the second control signal, and the second clock signal; a first output transistor configured to output a first voltage as the emission control signal in response to the first control signal; and a second output transistor configured to output a second voltage as the emission control signal in response to the third control signal, and wherein the third circuit section includes a first capacitor configured to maintain a constant voltage between two electrodes while each of the plurality of stages outputs the emission control signal, and The third circuit portion further includes a floating transistor connected between the second node and the first capacitor.

2. The emission control driver according to claim 1, wherein: The floating transistor is configured to be turned off in response to the input signal having a low level voltage and output the first voltage as the emission control signal to separate the second node and the first capacitor from each other, and The floating transistor is configured to be turned on or output the second voltage as the emission control signal in response to the input signal having a high-level voltage to connect the second node and the first capacitor to each other.

3. The emission control driver according to claim 1, wherein: The floating transistor is configured to connect the second node and the first capacitor to each other or to separate them from each other in response to the first control signal, and The floating transistor has a conductivity type opposite to that of the second output transistor.

4. The emission control driver according to claim 1, wherein: The first circuit unit includes: a first switching transistor configured to transmit the input signal to the first node in response to the first clock signal; a second switching transistor configured to transmit the first clock signal to the second node in response to the first control signal; and The third switching transistor is configured to apply the first voltage to the second node in response to the first clock signal.

5. The emission control driver according to claim 1, wherein: The second circuit unit includes: a fourth switching transistor configured to transmit the second clock signal to a third node in response to the first control signal; a fifth switching transistor configured to apply the second voltage to the third node in response to the second control signal; and A second capacitor is connected between the gate of the fourth switch transistor and the third node.

6. The emission control driver according to claim 1, wherein: The third circuit unit includes: a sixth switching transistor configured to transmit the second clock signal to a fourth node in response to the second control signal; The first capacitor is connected between the fourth node and the fifth node; a floating transistor configured to connect the second node and the fifth node to each other in response to the first control signal; a seventh switching transistor configured to connect the fourth node and the gate of the second output transistor to each other in response to the second clock signal; an eighth switching transistor configured to apply the second voltage to the gate of the second output transistor in response to the first control signal; and A third capacitor includes a first electrode configured to receive the second voltage and a second electrode at the gate of the second output transistor. 7 . The emission control driver according to claim 1 , further comprising a first normally-on transistor, wherein the second control signal is transmitted between the first circuit section and the third circuit section through the first normally-on transistor. 8 . The emission control driver according to claim 1 , further comprising a second normally-on transistor, wherein the first control signal is transmitted between the first circuit portion and the first output transistor through the second normally-on transistor.

9. The emission control driver according to claim 1, wherein: The first capacitor includes a first electrode and a second electrode, and After each of the plurality of stages outputs the second voltage as the emission control signal, the potential of the first electrode is maintained to be higher than the potential of the second electrode by a difference between a high-level voltage corresponding to the second voltage and a low-level voltage corresponding to the first voltage, wherein the first electrode and the second electrode are in a floating state in response to the input signal having a low-level voltage, both the first clock signal and the second clock signal have a high-level voltage, and the first voltage is output as the emission control signal, and wherein the third circuit portion further includes a floating transistor configured to connect the second node and the second electrode of the first capacitor to each other or separate them from each other in response to the first control signal.

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