Method for reading a cross-point memory array containing a two-terminal switch material

Abstract

The object of the present invention is to provide a current reading method for analog information processing in a memory array for a synaptic device. To this end, the present invention provides a method for reading a memory array containing a two-terminal switch material, the method comprising the following steps: (a) applying a voltage to the memory array to select one or more cells; and (b) simultaneously measuring the current of the selected one or more cells to obtain the sum of the currents, wherein the voltage applied to the one or more cells selected in step (a) is greater than the voltage applied to the unselected one or more cells, and is within a range that makes the selected one or more cells all non-conductive.

Description

Technical Field

[0001] The present invention relates to a method for reading a memory array including a two-terminal switch material, and more particularly, to a method for reading a memory array for a synaptic device, which can simultaneously read currents flowing in the memory array within a low current range, thereby reading currents differentiated according to cells selected from the memory array and the sum of the currents with low power consumption. Background Art

[0002] The AI ​​semiconductor industry is now in its infancy. In recent years, semiconductor design and manufacturing companies have begun to release prototypes or early products. These prototypes or early products are the first generation of AI semiconductor products based on complementary metal oxide semiconductor (CMOS) technology and are no different from conventional semiconductor products in terms of materials. It is eagerly expected that new materials will be introduced and used in the second generation of AI semiconductor products.

[0003] Artificial synapses with all the key features of biological synapses must be implemented as a single device to manufacture second-generation artificial intelligence semiconductors with an integration level close to that of biological neural networks. In particular, in order to increase the integration level, the device size needs to be small, and the characteristic of gradual change of current (resistance) is very important so that one synapse has various weights. In order to achieve such a goal, various types of artificial synaptic devices have been proposed and manufactured. Most of these devices are based on storage devices such as flash memory, resistive random access memory (RRAM), phase change random access memory (PRAM), and magnetic random access memory (MRAM).

[0004] The technology that has been studied so far in the field of semiconductors for synaptic devices is to use memristors such as RRAM, PRAM, and MRAM to distinguish low resistance states from high resistance states in a memory array and store information in each cell. Research has been conducted in the direction of realizing high resistance changes in a switch-type digital method and reading the logical state of a cell in a memory array based on this change in resistance. However, since the synaptic system has characteristics that appear in a continuously changing analog method rather than a digital method, measuring the change in the logical state of a cell in a digital method cannot adequately process information. Therefore, a synaptic device for neuromorphic applications, etc., needs to be able to read currents from multiple cells at the same time and sense the change in current by the sum of the currents from the corresponding cells.

[0005] In addition, since the device size must be small and it is very important to reduce the process cost in order to manufacture the memory cell for such a synaptic device, it is necessary to manufacture the memory cell based on the cross-point structure. Compared with the generally known 1T1R structure consisting of transistors and memory cells, the cross-point structure can be manufactured in three dimensions with the memory cells stacked vertically without using transistors, thereby increasing the density of the memory cell and reducing the number of manufacturing processes.

[0006] This cross-point structure needs to include the following two-terminal switch material, which allows the memory cell to have a very small amount of current flowing in the low voltage area and show a rapid rise in current at a specific voltage or higher. In a memory array with a cross-point structure, the process of selecting, reading and programming the cell is performed by word lines and bit lines that cross each other. In particular, the sneak current and voltage drop that occur when reading and programming the cell make it difficult to increase the size of the memory array. Switching materials are used to solve this problem.

[0007] Therefore, the present invention relates to a method for reading a memory array for a synaptic device having such a cross-point structure and comprising a two-terminal switch material. Summary of the invention

[0008] Technical issues

[0009] The present invention provides a method for reading current for use in processing analog information in a memory array for a synaptic device.

[0010] Technical Solutions

[0011] According to an embodiment of the present invention, a method for reading a memory array containing a two-terminal switch material is provided, the method comprising the following steps: (a) selecting at least one cell by applying a voltage to the memory array; and (b) simultaneously measuring the sum of currents from the at least one selected cell, wherein the voltage applied to the at least one cell selected in operation (a) is higher than the voltage applied to the at least one unselected cell and is within a range that makes the at least one selected cell non-conductive.

[0012] Beneficial effects

[0013] According to the method according to the present invention, since a plurality of cells can be read simultaneously from a memory array having a cross-point structure and the amount of change in the total current can be sensed by the sum of the currents from the individual cells, the utilization of memory semiconductors as synaptic devices or fully connected layers and convolutional neural networks (CNNs) for neuromorphic applications can be increased. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1is a graph illustrating a conventional method for reading a memory array having a cross point structure.

[0015] Figure 2 is a diagram illustrating a method for selecting a cell from a memory array having a cross point structure according to an embodiment of the present invention.

[0016] Figure 3 is a graph illustrating a method for reading a memory array having a cross point structure according to an embodiment of the present invention.

[0017] Figure 4 is a diagram illustrating a reading method according to a position of a cell selected in a memory array having a cross point structure according to an embodiment of the present invention.

[0018] Figure 5 is a diagram illustrating application of a pulse voltage to a memory array having a cross point structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0019] Hereinafter, the configuration and functions of the embodiments of the present invention will be described with reference to the accompanying drawings. In the following description of the present invention, when a detailed description of known functions and configurations incorporated herein would make the subject matter of the present invention rather unclear, the detailed description will be omitted. In addition, when a component "includes" an element, another element may also be included, rather than excluding another element, unless otherwise specified.

[0020] A method for reading a memory array containing a two-terminal switch material according to an embodiment of the present invention comprises the following steps: (a) selecting at least one cell by applying a voltage to the memory array; and (b) simultaneously measuring the sum of currents from the selected at least one cell. The voltage applied to the at least one cell selected in operation (a) is higher than the voltage applied to the at least one cell not selected, and is within a voltage range that makes all the selected at least one cell non-conductive.

[0021] The memory array includes a two-terminal switch material and has a cross-point structure in which word lines and bit lines as address lines are arranged in a grid, and such a memory cell connects the word lines and the bit lines at the cross-points of the word lines and the bit lines. The memory cell can be manufactured based on a memory device such as a resistive random access memory (RRAM), a phase change random access memory (PRAM), and a magnetic random access memory (MRAM), for example, while including a two-terminal switch material.

[0022] The two-terminal switch material has a characteristic of causing a significant change in resistance when a voltage higher than a certain level is applied. The voltage at which the resistance change occurs in a memory cell containing the two-terminal switch material is represented as a threshold voltage, and the phenomenon of the resistance change occurring is represented as conduction.

[0023] A general read process in a memory array having a cross-point structure is performed by allowing only a very low current to flow in unselected cells that are less than or equal to a threshold voltage and allowing a voltage capable of distinguishing the logic state of a selected cell to be applied to a cell selected by using the characteristics of a two-terminal switch material.

[0024] refer to Figure 1 A conventional method for reading a memory array comprising a two-terminal switch material and having a cross-point structure is described below. inh is applied to the unselected cells and the applied voltage V inh In the region of , cells with high resistance and low resistance are not distinguished, and the flow of current becomes very small. In contrast, the voltage V read1 is applied to the selected cell and can be based on the threshold voltage V th_A With a high resistance threshold voltage V th_B The voltage level between V read1 (V th_A <V read1 <V th_B ) and the current flowing in the selected cell is used to distinguish the logical state. Figure 1 The voltage V read1 Allowable current I target,off Flows in cells with high resistance and allows current I target,on The conventional method can select only one cell from the memory array and read only the digital on and off states, which is difficult to apply to synaptic devices and causes power consumption problems because the flow of current in the on state is very large.

[0025] The present invention provides a method for selecting at least one cell and reading the sum of currents flowing in a memory array through the selected at least one cell. Figure 2 This process is described below. The high voltage difference is used to select the high voltage V sel_BL and V sel_WL The cell at the point where the bit line and word line cross each other is read without selecting it with a low voltage applied to V desel_BL and V desel_WL For example, when the 3V voltage V sel_BL is applied to both bit lines, a -3V voltage V sel_WL is applied to both word lines, 0V voltage V desel_BL and V desel_WLWhen the remaining bit lines and word lines are applied, a voltage of 6V is applied to cells T1 to T6, and a voltage lower than or equal to 3V is applied to the remaining cells. In this case, since very small current flows in the cells to which a voltage lower than or equal to 3V is applied, these cells are not read and selected in the read process, and since a current with a large level flows in the cells T1 to T6 to which a voltage of 6V is applied, the cells T1 to T6 are read and selected in the read process. The two-terminal switch material enables selection.

[0026] Figure 3 The process of reading the current from the selected cell in this manner is illustrated. As in the conventional method, the voltage V inh is applied to the unselected cells. When a voltage V inh In the region of , the flow of current occurs according to the resistance state of the cell. Therefore, the cells are not distinguished, and the flow of current becomes very small.

[0027] However, unlike the method for applying a threshold voltage V with a low resistance to the selected cell, th_A With a high resistance threshold voltage V th_B Unlike conventional methods of applying a voltage at a level between , the method according to an embodiment of the present invention allows a voltage to be applied to at least one selected cell so that the voltage is within a range of a subthreshold region voltage that makes all of the at least one selected cell non-conductive and is greater than Figure 3 The voltage is indicated as "V read2 " is a voltage within a high voltage range of a voltage applied to at least one unselected cell. For example, Figure 3 The voltage V read2 At a voltage V inh High voltage and voltage V th1 Low voltage range between, voltage V th1 is the threshold voltage of the cell with the lowest resistance among the selected cells.

[0028] In addition, a minimum current flowing due to a voltage applied to the selected at least one cell may be in a range higher than a sum of currents flowing due to a voltage applied to the unselected at least one cell.

[0029] like Figure 3 As exemplified in Figure 2 In the case of applying "V read2 "When the selected cells have different resistances and the resistances are T6>T5>T4>T3>T2>T1, the current I T6 The current flows in the cell T6 with the highest resistance, so the current flow becomes smaller. The reason is that when the current I T6 Than the current I flowing through the unselected cellsinh When the sum of the current I is high, the cell can be easily selected. inh When the current I flows through n cells, T6 Can be higher than n×I inh .

[0030] In addition, the minimum current flowing due to the voltage applied to the selected at least one cell can be higher than or equal to n times (here, n is the number of cells in the same column and row) the current of the unit cell flowing due to the bias voltage applied to the unselected at least one cell.

[0031] More specifically, refer to Figure 3 , when the voltage V applied to the selected cell read2 (at a voltage V inh High voltage and voltage V th1 The lowest current I among the currents flowing in the corresponding cells is T6 becomes higher than or equal to the current I flowing in the unselected unit cell inh When the voltage applied to at least one selected cell is n times (here, n is an integer), the cell can be selected more smoothly and the size of the memory array can be increased. As described above, by controlling the difference in the current of the unit cell flowing due to the bias voltage applied to at least one unselected cell, the minimum current flowing due to the voltage applied to at least one selected cell enables the size of the memory array to be adjusted and enables easy selection of the cell.

[0032] In addition, in an embodiment of the present invention, the voltage applied to the selected at least one cell may be applied to the at least one cell to be within a voltage range in which currents flowing in corresponding cells due to the voltage can be distinguished from each other according to resistance characteristics of the cells.

[0033] As described above, the current flowing in the selected cells can be distinguished and measured, thereby increasing the utilization of the memory array as a synaptic device through analog operation. Figure 3 , as the voltage V applied to the cell selected in the read process read2 can be set to a voltage higher than V sep The higher voltage is higher than the voltage V as the minimum threshold voltage th1 The voltage range between low and high is where the voltage V sep At , the IV curves separate according to the resistance characteristics of the selected cell. In this case, due to the applied voltage V read2 And the currents flowing in the cells T1 to T6 having different resistances all have different values.

[0034] In addition, in the embodiment of the present invention, the difference between the maximum current and the minimum current among the currents flowing in the selected at least one cell may exceed a voltage range that makes the current flowing in the corresponding cell measurable.

[0035] For example, as described above, in order to distinguish and measure the current flowing according to the resistance characteristics of the selected cells, the highest value among the values ​​of the current flowing in the selected cells may be set to be greater than or equal to 1.2 times the lowest value. Figure 3 , when the voltage V applied to the selected cell read2 is set to be at a voltage V greater than that at which the IV curves are separated sep A voltage higher than the minimum threshold voltage V th1 The voltage range between low and high is as follows: read2 The current I of the highest current among the currents flowing in the corresponding cells is selected. T6 is set to a current greater than or equal to the minimum current T1 1.2 times of the original speed, the reading process can be performed more smoothly.

[0036] In addition, in the embodiment of the present invention, the two-terminal switch material can be at least one of an ovonic threshold switch material, a transition metal oxide switch material, a mixed ion-electron conductor (MIEC) switch material, a complementary resistance switch material, and doped amorphous silicon. In addition to the above materials, the material is not particularly limited as long as the material can perform the two-terminal switch function defined in the embodiment of the present invention.

[0037] The two-terminal switch material changes from an insulator state to a conductor state by rapidly reducing resistance when a voltage higher than or equal to a threshold voltage is applied. In the present invention, by using this characteristic, a plurality of cells can be selected from a memory array having a cross-point structure. From this point of view, the above-mentioned two-terminal switch material can be applied to the reading method proposed in the present invention.

[0038] As the bidirectional threshold switch material mentioned above, chalcogenide materials are often used, and In-Ge-As-Se alloy, Te-Se alloy, As-Se alloy, Ge-Te alloy, Ge-Se alloy, As-Se-Te alloy, Ge-As-Se alloy, Ge-As-Sb alloy, Ge-Sb-Te alloy, Ge-Sb-Se alloy, Ge-As-Te alloy, Si-Ge-As-Se alloy, Si-Te-As-Ge alloy, In-Sb-Te alloy, In-Sb-Se alloy, In-Ge-As alloy, In-Ge-Te alloy, In-Te alloy, etc. can be used.

[0039] In addition, NbOx It can be used as a transition metal oxide switching material. Compounds containing Cu such as CuGeS or MIEC conductors containing La, Sr, Ce, Ti, Li, Gd, etc. can be used as MIEC switching materials, and SiO doped with W can be used as a MIEC switching material. x , SiO doped with As x and B-doped SiO x Can be used as doped amorphous silicon.

[0040] However, in addition to the materials exemplified above, the material is not particularly limited as long as the material can perform a switching function through a change in resistance.

[0041] In particular, this two-terminal switch material can be a material having a threshold current (that is, a current in the range of 20nA to 5μA at a point in time when a sudden decrease in resistance occurs). In the present invention, in the selected cell, the current in the subthreshold region is measured. Since the current in the subthreshold region is lower than the threshold current, it may be difficult to measure the current if a two-terminal switch material with too low a threshold current is used. On the other hand, if the threshold current is too high, the power consumption may be high, which is not preferred.

[0042] According to an embodiment of the present invention, a method for reading a memory array including a two-terminal switch material is provided, wherein a voltage applied to a memory cell via a metal line (i.e., a word line or a bit line) is controlled so that a voltage drop in an individual cell voltage of a current reaching one or more cells selected in the memory array that occurs according to a current flow distance from a power source to the selected cell is compensated, and the current flow distance is determined by the number of cells through which the current applied to the memory array passes before reaching the selected cell from the power source and the lengths of the word line and the bit line.

[0043] When a cell is selected and a voltage is applied thereto, the current flowing due to the applied voltage passes through the word line and the bit line as metal lines until the current reaches the selected cell, so the current may have a voltage drop due to resistance and also have a voltage drop due to leakage current to the cell connected to the metal line. When such a voltage drop occurs and the current reaches the selected cell, a voltage lower than the target voltage is applied to the selected cell. Therefore, in order to apply the target voltage to the selected cell, compensation should be performed in consideration of this.

[0044] In order to compensate, Figure 4 In the example, the selected unit is W ij+0 To W ij+3 The situation and Figure 4 The unit selected is W ij+10 To W ij+13When W is selected as the unit close to the power supply ij+0 To W ij+3 When the voltage V applied through the word line sel_WL is applied almost intact to the selected cell. However, at a distance from the power supply W ij+10 To W ij+13 In the case of ij+0 To W ij+9 A large voltage drop inevitably occurs due to the leakage current and the resistance caused by passing through the word line. Therefore, the voltage to be applied varies according to the position of the cell to be selected in the memory array. In order to use the selected cell as a single synaptic device, if the applied voltage varies according to the position, accurate information cannot be obtained. Therefore, it is necessary to adjust the voltage to be applied to compensate for the voltage drop.

[0045] The voltage applied to the selected cell is equal to the difference between the voltages applied to the word line and the bit line as described above. Figure 4 In the case of V sel_WL is 3V and V sel_BLs1 is -3V, 6V is applied to the W of the selected cell ij+0 To W ij+3 However, if the selected unit is W ij+10 To W ij+13 , then even if the voltage V applied by the word line sel_WL Initially 3V, it may also become 2.5V after actually reaching the selected cell. Here, when -3V is applied to V sel_BLs2 With V sel_BLs1 At the same time, 5.5V is applied to W as the selected cell. ij+10 To W ij+13 , so there is a problem that a voltage lower than the target voltage is applied. In particular, if W ij+0 To W ij+3 and W ij+10 To W ij+13 If all are selected cells, then the voltage W is applied first. ij+0 To W ij+3 The leakage current is larger, so the voltage drop appears larger.

[0046] In order to solve this voltage drop, when a voltage is applied by selecting a cell at a position where a large voltage drop occurs, the voltage drop can be compensated by making the difference between the voltages applied to the word line and the bit line larger in consideration of the voltage drop according to the position of the selected cell. Figure 4 If applied to W ij+10 To W ij+13The voltage at V becomes 2.5V due to the voltage drop, so to compensate for this, if -3.5V is applied to V sel_BLs2 Rather than applying V sel_BLs1 The same -3V, and no voltage drop occurs in W ij+0 To W ij+3 The same 6V voltage is applied to the W of the selected cell as ij+10 To W ij+13 .

[0047] The voltage drop compensation can be achieved by controlling the voltage applied to the bit line and the word line at the same time, but can be achieved by changing only the voltage on the other side of the bit line or word line without changing the voltage on one side of the bit line or word line for voltage drop compensation. That is, the voltage drop compensation can be achieved by controlling only the bit line voltage for voltage drop compensation without changing the word line voltage. Conversely, the voltage drop compensation can be achieved by changing the word line voltage without changing the bit line voltage. By changing only the voltage on one side of the bit line or word line in this way, the control method can be made simpler.

[0048] In the present invention, the voltage applied to the memory array may be a pulse voltage that varies with time. A pulse voltage that varies according to input information that varies with time is applied to the actual synaptic device, rather than a single voltage. Therefore, when a pulse voltage that varies with time is applied, the method for reading the memory array according to the present invention can be utilized. Figure 5 The application of this pulse type voltage is illustrated, where the word line is constant but the bit line varies with time, resulting in a pulse voltage caused by the voltage difference between the bit lines. This pulse voltage becomes the input signal, and the current flowing from the memory array becomes the final output signal, causing the memory array to operate as a synaptic device.

Claims

1. A method for reading a memory array for a synaptic device, the memory array comprising a plurality of memory cells, the plurality of memory cells comprising a bidirectional threshold switch material as a two-terminal switch material, the method comprising the following steps: (a) selecting a plurality of first cells by applying a voltage to the memory array at one time; as well as (b) measuring the sum of currents flowing through the selected plurality of first cells, wherein a first voltage applied to the selected plurality of first cells is higher than a second voltage applied to one or more second cells that are not selected when the first voltage is applied to the memory array, and is within a range where all of the selected plurality of first cells are not turned on, indicating that the resistance of the two-terminal switch material does not change significantly, and The first voltage is higher than a voltage at a point where IV curves of the selected plurality of first cells are separated according to resistance characteristics of the selected plurality of first cells.

2. The method according to claim 1, in, A minimum current flowing through the plurality of first cells due to the first voltage applied thereto is within a range higher than a sum of currents flowing through the one or more unselected second cells due to the second voltage applied thereto.

3. The method according to claim 1, in, The two-terminal switch material has a threshold current of 20 nA or more and 5 μA or less.

4. The method according to claim 1, in, controlling voltages applied to the memory array through word lines and / or bit lines so that a voltage drop in individual cell voltages of currents reaching one or more cells selected in the memory array, which occurs according to a current flow distance from a power source to the selected cell, is compensated, and The current flow distance is determined by the number of cells through which the current applied to the memory array passes before the current reaches the selected cell from the power supply and the lengths of word lines and bit lines.

5. The method according to claim 4, in, Voltage drop compensation is achieved by controlling a voltage applied to one or both of a bit line and a word line connected to the selected cell.

6. The method according to one of claims 1 to 5, in, The voltage applied to the memory array through the bit lines and / or word lines is a pulse voltage of one or more pulses having the same width and height.

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