Systems and methods for junction termination of wide bandgap superjunction power devices

Abstract

The disclosed superjunction (SJ) device includes a first epitaxial (epi) layer forming a first SJ layer of the SJ device, and includes a second epi layer disposed on the first SJ layer and forming a device layer of the SJ device. The active regions of the first epi layer and the second epi layer include: a first group of SJ columns including a specific doping concentration of a first conductivity type, and a second group of SJ columns including the specific doping concentration of a second conductivity type. The terminal regions of the first epi layer and the second epi layer have a minimum epi doping concentration of the first conductivity type that is less than the specific doping concentration, and the terminal region of the second epi layer includes a plurality of floating regions of the second conductivity type, the plurality of floating regions forming a junction terminal of the SJ device.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Provisional Application No. 62 / 783,683, filed on December 21, 2018, entitled “SYSTEMS AND METHODS FOR JUNCTION TERMINATION IN SEMICONDUCTOR DEVICES,” which is incorporated herein by reference in its entirety for all purposes. Background Art

[0003] The subject matter disclosed herein relates to wide bandgap power devices (eg, silicon carbide (SiC) power devices), and more particularly to termination designs for wide bandgap superjunction (SJ) power devices.

[0004] For semiconductor power devices, terminals (such as junction terminals) can be used to generally prevent electric fields from gathering near the edge of the active area of ​​the device during reverse bias operation. As used herein, the term "junction terminal" is intended to include a terminal structure that uses a floating or electrically attached p / n junction to the main blocking junction as a means of shaping and controlling the electric field around the active area of ​​the device. However, although the terminal improves device reliability and operability, there are also costs associated with using the terminal. For example, the terminal usually occupies a certain amount of die area (referred to herein as the terminal area) of the semiconductor power device. Together with other parts of the device (e.g., gate bus area, gate pad area, etc.), the terminal area has an impact on the overhead area of ​​the device referred to herein. Therefore, although the active area of ​​the device includes device units (e.g., metal oxide semiconductor field effect transistor (MOSFET) units) for power conversion, the overhead area includes features that support the operation of these device units.

[0005] Therefore, it may be desirable to maximize the ratio of active area to overhead area of ​​a device to improve performance. Wide terminations create large termination areas and large overhead areas, and this limits the amount of die area available for the active area of ​​the device. Therefore, by reducing the overhead area, the ratio of active area to overhead area can be increased, which can improve the efficiency and / or operation of the device. Summary of the invention

[0006] In an embodiment, a super junction (SJ) device includes a first epitaxial (epi) layer forming a first SJ layer of the SJ device, and includes a second epi layer disposed on the first SJ layer and forming a device layer of the SJ device. The active regions of the first epi layer and the second epi layer include: a first group of SJ columns including a specific doping concentration of a first conductivity type, and a second group of SJ columns including the specific doping concentration of a second conductivity type. The terminal regions of the first epi layer and the second epi layer have a minimum epi doping concentration of the first conductivity type that is less than the specific doping concentration, and the terminal region of the second epi layer includes a plurality of floating regions of the second conductivity type, the plurality of floating regions forming a junction terminal of the SJ device.

[0007] In another embodiment, a method of manufacturing a superjunction (SJ) device includes forming a first SJ layer by the following steps: forming a first epitaxial (epi) layer on a substrate layer, wherein the first epi layer has a minimum epi doping concentration of a first conductivity type; implanting a first set of SJ pillars into an active region of the first epi layer to produce a specific doping concentration of the first conductivity type, wherein the specific doping concentration is greater than the minimum epi doping concentration; and implanting the active region of the first epi layer to produce a second set of SJ pillars including the specific doping concentration of a second conductivity type. The method also includes forming a device layer by the following steps: forming a second epi layer on the first SJ layer, wherein the second epi layer has a minimum epi doping concentration of the first conductivity type; implanting a first set of device layer pillars into an active region of the second epi layer to produce a second doping concentration of the first conductivity type less than the specific doping concentration; implanting a second set of device layer pillars into an active region of the second epi layer to produce the specific doping concentration of the second conductivity type; and forming a junction termination in the device layer by implanting a plurality of floating regions having the second conductivity type into a termination region of the second epi layer.

[0008] In another embodiment, a silicon carbide (SiC) superjunction (SJ) device includes a first superjunction (SJ) layer formed in a first epitaxial (epi) layer of the SiC-SJ device, wherein a termination region of the first epi layer has a minimum epi doping concentration of a first conductivity type, wherein the minimum epi doping concentration is less than or equal to 1.5×10 15 cm -3 The SiC-SJ device further includes a device layer formed in a second epi layer of the SiC-SJ device, wherein the second epi layer is disposed on the first SJ layer, and wherein a terminal region of the device layer has a minimum epi doping concentration of a first conductivity type, and a plurality of floating regions of a second conductivity type, the plurality of floating regions forming a junction terminal of the SiC-SJ device. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] These and other features, aspects and advantages of the present invention will be better understood when the following detailed description is read with reference to the accompanying drawings, in which like reference numerals refer to like parts throughout, and in which:

[0010] Figure 1 is a schematic diagram illustrating a cross-sectional view of a portion of an embodiment of a multilayer silicon carbide superjunction (SiC-SJ) device having a termination region including a junction termination having a floating doped region according to some aspects of the present technique;

[0011] Figure 2 According to some aspects of this technology Figure 1 Top view of the SiC-SJ device;

[0012] Figure 3 is a graph showing some aspects of the present technology. Figure 1 an achievable breakdown voltage varying with a junction termination extension (JTE) width of an exemplary embodiment of a SiC-SJ device;

[0013] Figure 4 is a schematic diagram showing a terminal region having a first width according to some aspects of the present technology Figure 1 An embodiment of a SiC-SJ device comprising an equal rate line showing an impact ionization rate existing in a reverse bias state;

[0014] Figure 5 is a schematic diagram showing a terminal region having a second width according to some aspects of the present technology Figure 1 Another embodiment of the SiC-SJ device includes iso-rate contours showing the impact ionization rate existing in a reverse bias state;

[0015] Figure 6 is a graph showing some aspects of the present technology. Figure 1 The termination area of ​​the exemplary embodiment of the SiC-SJ device is in units of cubic centimeters (cm -3 )’s breakdown voltage changes with the epi doping concentration;

[0016] Figure 7 is a schematic diagram illustrating a terminal region including a first epi doping concentration according to some aspects of the present technology Figure 1 A cross-sectional view of an embodiment of a SiC-SJ device including iso-rate contours showing impact ionization rates present in a reverse bias state;

[0017] Figure 8 is a schematic diagram illustrating a terminal region including a second epi doping concentration according to some aspects of the present technology Figure 1 A cross-sectional view of another embodiment of a SiC-SJ device including iso-rate contours showing impact ionization rate present in a reverse bias state;

[0018] Fig. 9 is a flow chart of a process for fabricating an embodiment of a wide bandgap SJ device having one or more junction terminations according to aspects of the present technology;

[0019] Fig.10 According to some aspects of the present technology Figure 1 A cross-sectional view of an embodiment of an intermediate structure formed during fabrication of a SiC-SJ device, wherein the intermediate structure has a first epitaxial (epi) layer formed on a substrate layer;

[0020] Fig.11 According to some aspects of the present technology, after forming several SJ layers and device layers Fig.10 A cross-sectional view of an embodiment of an intermediate structure;

[0021] Fig.12 According to some aspects of the present technology, after a junction termination extension (JTE) has been implanted into the termination region of the device layer Fig.11 A cross-sectional view of an embodiment of an intermediate structure;

[0022] Fig.13 is a cross-sectional view of a portion of an embodiment of a SiC-SJ device having a termination region including a JTE according to some aspects of the present technology;

[0023] Fig.14 According to some aspects of this technology Fig.13 An enlarged view of an embodiment of a SiC-SJ device;

[0024] Fig.15 is a graph showing some aspects of the present technology along the Fig.14 The absolute net doping concentration changes with the distance between line A and line B;

[0025] Fig.16 is a graph illustrating a breakdown voltage varying according to a depth of a doping modification of a first conductivity type SJ pillar closest to a termination region according to aspects of the present technology;

[0026] Fig.17A and Fig. 17B The present invention is respectively demonstrated in some aspects of the present technology. Fig.13 Embodiments of SiC-SJ devices of the present invention provide a breakdown rate of the device in the termination region and the active region under reverse bias conditions; and

[0027] Fig.18is a graph illustrating a breakdown voltage varying according to doping concentration in a modified doping modification of a modified SJ pillar according to aspects of the present technology. DETAILED DESCRIPTION

[0028] One or more specific embodiments will be described below. In order to provide a concise description of these embodiments, not all features of the actual implementation are described in the specification. It should be understood that in the development process of any such actual implementation, such as in an engineering or design project, a large number of implementation-specific decisions must be made to achieve the developer's specified goals, such as meeting system-related and business-related constraints, which may change with the implementation. In addition, it should be understood that such development efforts may be complex and time-consuming, but will still be routine design, production and manufacturing tasks for ordinary technicians who benefit from the present disclosure.

[0029] Unless otherwise defined, the technical terms and scientific terms used herein have the same meanings as those of ordinary skill in the art to which the present disclosure belongs. The terms "first", "second", etc. used herein do not represent any order, quantity or importance, but are used to distinguish one element from another element. And when introducing the elements of the various embodiments of the present disclosure, the articles "one", "an" and "the" are intended to indicate that there are one or more elements. The terms "include", "comprise" and "have" are intended to be open and represent that there may be other elements in addition to the listed elements. In addition, it should be understood that the reference to "one embodiment" or "embodiment" of the present disclosure is not intended to be interpreted as excluding the existence of additional embodiments that also include the cited features. If certain ranges are disclosed, the endpoints of all ranges for the same component or attribute are inclusive and independently combinable. The modifier "about" related to quantity includes the stated value and has the meaning specified in the context (for example, including the degree of process variation or error associated with the measured value of a specific number). The modifier “substantially” when used in conjunction with a descriptive term is intended to convey that the descriptive term applies primarily, substantially, or mostly (e.g., applies to greater than 90%, greater than 95%, or greater than 99% of the time) and may be used to account for limited exceptions that may result from process variations and technical limitations that are understood by those skilled in the art.

[0030] As used herein, the term "layer" refers to a material disposed on at least a portion of the lower surface in a continuous or discontinuous manner. In addition, the term "layer" does not necessarily mean that the material disposed has a uniform thickness, but that the material disposed can have a uniform or variable thickness. In addition, unless the context clearly specifies otherwise, the term "layer" used herein refers to a single layer or multiple layers. As used herein, the term "adjacent" refers to two layers or features disposed continuously and in direct contact with each other. In the present disclosure, when a layer / device is described as "on" another layer or substrate, it should be understood that the layer / device can be in direct contact with each other or have one (or more) layers or features between layers and between devices. In addition, the term "on..." describes the relative position of the layer / device relative to each other and does not necessarily mean "at the top of...", because the relative position above or below depends on the orientation of the device relative to the observer. In addition, the use of "top", "bottom", "above", "below", "on", "buried" and variations of these terms is for convenience, and does not require any specific orientation of the component unless otherwise specified. With this in mind, as used herein, the terms "lower," "buried," "middle," or "bottom" refer to features that are relatively closer to the substrate layer (e.g., an epitaxial layer, a termination region), while the terms "top" or "upper" refer to a particular feature that is relatively farthest from the substrate layer (e.g., an epitaxial layer, a termination region).

[0031] The present embodiments relate to designs and methods for fabricating wide bandgap superjunction (SJ) power devices, such as silicon carbide superjunction (SiC-SJ) power devices. The disclosed designs and methods can be used to fabricate SJ devices, such as metal oxide semiconductor field effect transistors (MOSFETs), junction field effect transistors (JFETs), bipolar junction transistors (BJTs), diodes, and other SJ devices that can be used in medium voltage (e.g., 2kV-10kV) and high voltage (e.g., greater than or equal to 10kV) power conversion related applications. As discussed below, the disclosed SJ device design includes a multi-layer termination region implemented using repeated epitaxial growth and dopant implantation steps. As used herein, the term "multi-layer" and references to a specific number of layers (e.g., "two layers," "three layers," "four layers") refer to the number of epitaxial layers (referred to herein as epi layers).

[0032] More specifically, the present embodiments relate to designs and methods for manufacturing power device terminations (such as junction terminations) for wide bandgap SJ devices (e.g., SiC-SJ devices). As described above, a junction termination is a termination structure that uses a p / n junction that is floating or electrically attached to a main blocking junction as a means of shaping and controlling the electric field around the active region of the device. In general, the disclosed termination design satisfies multiple design parameters to provide an effective edge termination for a wide bandgap SJ device. For example, the disclosed termination design provides a breakdown voltage close to or equal to (e.g., 90% or more) the device entitlement while reducing the terminal width. The disclosed termination design is also relatively robust to process variations (e.g., dopant concentration in the implanted region, dopant concentration in the epitaxial layer, doping activation percentage, etc.). Relative to typical junction termination designs, the disclosed termination design consumes a smaller portion of the die area and has a relatively low manufacturing cost. For example, certain disclosed SJ device embodiments can be manufactured using common semiconductor manufacturing equipment (such as a high-volume ion implantation system used in existing Si / SiC device manufacturing) to provide additional cost advantages.

[0033] As discussed in detail below, the disclosed SJ termination design includes one or more n-type and / or p-type doped regions arranged in a specific manner to form a junction termination (such as a junction termination extension (JTE)) to allow the electric field magnitude outside the active region (e.g., conductive region) of the SJ power device to be gradually reduced under reverse bias conditions. In various embodiments, these doped regions can be implemented as blocks, continuous columns, strips, segments, grids, dots, or any other suitable shapes that are not connected to each other. In some embodiments, these doped regions can be described as "floating", meaning that they are not in electrical contact with the device terminals or under an externally applied bias; however, in other embodiments, at least a portion of these regions can be in electrical contact with the device terminals. The location and size of these implanted regions in the termination area of ​​the disclosed SJ device are designed to achieve a high blocking voltage to prevent premature device breakdown caused by electric field crowding effects and allow these devices to operate reliably, especially when subjected to long-term high temperature / high voltage operation. In addition, by using high energy ion implantation to control the doping of the epitaxial (epi) layer within the active region of the SJ device, and, for example, by controlling the epi doping in the terminal region of the device, the disclosed termination design occupies significantly less die area than conventional junction termination designs, which significantly increases the ratio of active area to overhead area without any performance loss in terms of breakdown voltage.

[0034] It is understood that for the present embodiment, the epi layer of the SJ device can be formed at a minimum controllable doping level, for example, without any intentional epi doping (e.g., without any intentionally introduced dopant), or at a minimum doping level that allows the doping type (n or p) to be controlled within a specified low concentration range. However, it should be recognized that due to the presence of impurities (such as nitrogen) in the equipment and / or tools used during the epitaxial growth process, the epi layer may still include a small amount of epi doping (e.g., of the first conductivity type (n-type)), referred to herein as the "minimum epi doping concentration". Therefore, although the epi layer can be formed without an intentional doping concentration, the actual epi doping concentration of the epi layer can generally be 8.0×10 13 cm -3 or higher, depending on the equipment used for epitaxial growth. For example, in some embodiments discussed below, the minimum epi doping concentration of the first conductivity type (e.g., n-type) may be less than 3.0×10 15 cm -3 , less than 2×10 15 cm -3 , less than 1×10 15 cm -3 or in 8×10 13 cm -3 and 2×10 15 cm -3 For example, when the first conductivity type is n-type, nitrogen, phosphorus, arsenic, antimony, etc. may be used as a dopant. Alternatively, when the first conductivity type is p-type, boron, aluminum, etc. may be used as a dopant.

[0035] As discussed below, after forming each epi layer having such a minimum epi doping concentration, a high energy (HE) implantation operation is used to implant dopants of the first conductivity type and the second conductivity type into portions of the active region of the device to form SJ pillars of the SJ layer. Additionally, the top or device epi layer may also be implanted one or more times to form device structures (e.g., well regions, source regions, etc.), and in some embodiments, these implantation operations may be performed using a standard energy implantation process. For example, in a device having a minimum epi doping concentration (e.g., less than or equal to 3×10 15 cm -3 After forming the SJ pillars in the epi layer of the embodiment of the present invention using HE implantation, a portion of the SJ pillars in the active region of the epi layer has a specific doping concentration of the first dopant type (e.g., greater than or equal to 5×10 15 cm -3 ), while the remaining SJ pillars may have a specific doping concentration of the second dopant type (e.g., greater than or equal to 5×10 15 cm -3). Additionally, as discussed below, in certain embodiments, certain SJ pillars may include a modified portion having a relatively reduced doping concentration, wherein the reduced doping concentration and the depth of the modified portion also affect the breakdown characteristics of the SJ device.

[0036] Considering the above, Figure 1 A cross-sectional view of an embodiment of a SiC-SJ device 4 according to an embodiment of the present solution is shown, the device having an active region 6 and an intermediate region 8, and a terminal region 10 having a junction termination (such as a junction termination extension (JTE) 12). It is understood that in order to more clearly illustrate certain components of the SiC-SJ device 4, certain well-known design elements (e.g., top metallization, passivation, etc.) may be omitted. It is also understood that although the device 4 is described herein in the context of a SiC-SJ device, in accordance with the present disclosure, in other embodiments, other wide bandgap materials (e.g., germanium (Ge), aluminum nitride (AlN), gallium nitride (GaN), boron nitride, gallium arsenide (GaAs), diamond (C), etc.) may be used.

[0037] The illustrated embodiment of the SiC-SJ device 4 includes several epitaxial (epi) layers 14. These epi layers include an epi layer 14Z that forms a device layer 16 of the SiC-SJ device 4, and epi layers 14A, 14B, and 14C that form super junction (SJ) layers 18A, 18B, and 18C of the SiC-SJ device 4, respectively. Although the illustrated embodiment includes four epi layers 14, in other embodiments, the SiC-SJ device 4 may include any suitable number of epi layers 14 (e.g., 2, 3, 4, 5, 6, or more) to produce a SiC-SJ device 4 with a particular desired voltage rating. The epi layers 14 may be manufactured using repeated cycles of epitaxial overgrowth. As shown, a first epi layer 14A is formed and disposed directly on a substrate layer 20, and a second epi layer 14B is formed and disposed directly on the first epi layer 14A. Further, the third epi layer 14C is formed and disposed directly on the second epi layer 14B, and the fourth epi layer 14Z (e.g., a device epi layer) is formed and disposed directly on the third epi layer 14C. In other embodiments, the SiC-SJ device 4 may include additional epi layers 14 (e.g., 14D, 14E, 14F, etc.) including any suitable number of SJ layers 18 disposed between the first epi layer 14A and the device epi layer 14Z and / or below the first epi layer 14A.

[0038] for Figure 1In the illustrated embodiment, in the active region 6, the top surface 42 of the device layer 16 includes a well region 40 (e.g., a p-well region 40) having a second conductivity type, which is disposed adjacent to a source region 44 (e.g., an n-type source region 44) having a first conductivity type. A dielectric layer 46 (also referred to as a gate insulating layer or a gate dielectric layer) is disposed adjacent to the device layer 16, and a gate electrode 48 is disposed adjacent to the dielectric layer 46. Further, the SJ layer 18 is disposed on a substrate layer 20 (e.g., a semiconductor substrate layer, a wide bandgap substrate layer), and a drain contact 50 is disposed on a bottom 52 of the SiC-SJ device 4, adjacent to the substrate layer 20. As shown in FIG. Figure 1 As additionally shown in the embodiment of FIG. 1 , source contact 54 is disposed adjacent top surface 42 of device layer 16 and over a portion of both source region 44 and well region 40 of device layer 14Z.

[0039] During the on-state operation of the SiC-SJ device 4 shown, a suitable gate voltage (e.g., equal to or higher than the threshold voltage (V TH )) creates an inversion layer form in the channel region 56, and the conductive path in the junction field effect transistor (JFET) region 58 is enhanced due to the accumulation of carriers, thereby allowing current to flow from the drain contact 50 (e.g., drain electrode, drain terminal) to the source contact 54 (e.g., source electrode, source terminal) within the portion of the active region 6 and / or in the intermediate region 8. The channel region 56 can be generally defined as the upper portion of the well region 40, which is disposed below the gate electrode 48 and the dielectric layer 46.

[0040] To reduce the on-state resistance (Rds(on)) and the resulting on-state conduction losses, the SiC-SJ device 4 includes an SJ region 60, which may have any suitable number of SJ layers 18 formed in the active region 6 and / or the intermediate region 8 of the SiC-SJ device 4. Each SJ layer 18 includes a first group of implanted SJ pillars 62A that are oppositely doped relative to a second group of implanted SJ pillars 62B. In other words, the first group of SJ pillars 62A have a first conductivity type (e.g., n-type SJ pillars 62), while the second group of SJ pillars 62B have a second conductivity type (e.g., p-type SJ pillars 62). In some embodiments, the first group of SJ pillars 62A may be doped with nitrogen, phosphorus, or other suitable n-type dopants, while the second group of SJ pillars 62B are doped with boron, aluminum, or other suitable p-type dopants, or vice versa.

[0041] Further, the dopant concentrations in the first group of SJ pillars 62A and the second group of SJ pillars 62B of the SJ region 60 are substantially the same (e.g., ±3%, ±2%, ±1%). For example, in some embodiments, each of the first group of SJ pillars 62A and each of the second group of SJ pillars 62B may have a dopant concentration greater than 5×10 15 cm-3 and / or less than 1×10 17 cm -3 In some embodiments, the first set of SJ pillars 62A and the second set of SJ pillars 62B are each generally designed to be substantially depleted and provide a similar amount (e.g., substantially equal amount) of effective charge (e.g., per square centimeter (cm2)) from ionized dopants under reverse bias. -2 ), normalized to the device active region 6). Therefore, since both the p-type semiconductor portion and the n-type semiconductor portion are substantially (e.g., completely) depleted in the nominal blocking state, the illustrated superjunction structure allows the SiC-SJ device 4 to achieve a high breakdown voltage and a low on-state resistance.

[0042] In some embodiments, the respective thicknesses 65A, 65B, 65C, and 65Z of the first epi layer 14A, the second epi layer 14B, the third epi layer 14C, and the device epi layer 14Z may be the same or different. For example, in some embodiments, the thickness 65 (e.g., 65A, 65B, 65C, and 65Z) of the epi layer 14 may be between 2 microns (μm) and 15 μm (e.g., 10 μm or 12 μm). Additionally, the SJ column 62 in the SJ region 60 of the SiC-SJ device 4 shown has a specific depth (e.g., extending along the Y axis). It should be understood that in some embodiments, the depth of the SJ column 62 may be the same between the first group of SJ columns 62A and the second group of SJ columns 62B. In some embodiments, for example, each SJ column 62 may extend through the entire thickness 65A of the epi layer 14A and may contact (e.g., be electrically connected to) the substrate layer 20. Alternatively, each SJ pillar 62 may not extend through the entire thickness 65A of the first epi layer 14A, thereby leaving a gap (e.g., an epi doped region) between the SJ pillar 62 and the substrate layer 20. In addition, in some embodiments, each of the first group of SJ pillars 62A may contact (e.g., electrically connect to) at least one of the first group of device layer pillars 64A (e.g., n-type device layer pillars) having a similar conductivity type, and each of the second group of SJ pillars 62B may contact (e.g., electrically connect to) at least one of the second group of device layer pillars 64B (e.g., p-type device layer pillars) having a similar conductivity type, as described in more detail below. It will be understood that because the first group of device layer pillars 64A and the second group of device layer pillars 64B are not charge balanced due to other structures in the device layer, these device layer pillars are not technically SJ structures themselves. However, for convenience, for some embodiments, the device layer pillars 64A and 64B may be described herein as part of the SJ pillars 62A and 62B, respectively.

[0043] Furthermore, the depth of the SJ pillar 62 may be different in different SJ layers 18 of the SJ region 60. Figure 1As shown, each of the first group of SJ pillars 62A and the second group of SJ pillars 62B in the first SJ layer 18A has a depth 67, while each of the first group of SJ pillars 62A and the second group of SJ pillars 62B in the second SJ layer 18B has a depth 69. The first group of SJ pillars 62A and the second group of SJ pillars 62B in the second SJ layer 18B extend through the entire thickness 65B of the epi layer 14B. By extending through the thickness 65B of the epi layer 14B, a continuous vertical SJ pillar 62 can be formed from each SJ layer 18 in the SJ region 60. The continuous vertical SJ pillars 62 can then provide low conduction losses and high blocking voltage. It should be understood that for the illustrated embodiment, the total depth of the first group of SJ pillars 62A is equal to the sum of the respective depths (e.g., 67, 69, and 71) of the first group of SJ pillars 62A in the first SJ layer 18A, the second SJ layer 18B, and the third SJ layer 18C. Similarly, the total depth of the second group of SJ pillars 62B is equal to the sum of the respective depths (eg, 67, 69, and 71) of the second group of SJ pillars 62B in the first SJ layer 18A, the second SJ layer 18B, and the third SJ layer 18C.

[0044] With respect to size, each SJ column 62 may have a specific width 73. In some embodiments, the size (e.g., width 73) of the SJ column 62 may vary along the Y-axis. In addition, the size of the first group of SJ columns 62A may vary relative to the size of the second group of SJ columns 62B. Further, the SJ columns 62 may have different cross-sectional shapes (e.g., defined by a mask set used during implantation). However, the size of the first group of SJ columns 62A in the first SJ layer 18A generally matches the size of the corresponding first group of SJ columns 62A in other SJ layers 18 (e.g., SJ layer 18B). Similarly, the size of the second group of SJ columns 62B in the first SJ layer 18A may match the size of the corresponding second group of SJ columns 62B in other SJ layers 18 (e.g., SJ layer 18B), so that the corresponding first group of SJ columns 62A and the corresponding second group of SJ columns 62B of each SJ layer 18 are aligned with each other.

[0045] Further, it should be understood that for different embodiments, the doping of the epi layer 14, the doping of the SJ pillar 62, the thickness 65 of the epi layer 14, the depth of the SJ pillar 62 (e.g., 67, 69, 71), and the width 73 of the SJ pillar 62 can be varied to achieve desired electrical performance (e.g., desired breakdown voltage) of the SiC-SJ device 4. For example, in some embodiments, certain device parameters (e.g., the thickness 65 and doping of the epi layer 14) can be selected to provide a breakdown voltage of the SiC-SJ device 4 between approximately 1 kilovolt (kV) and 10 kV, between 1 kV and 5 kV, or any other suitable range. Further, in some embodiments, the dopant concentration of the SJ pillar 62 can be between approximately 5×10 15 cm-3 and approximately 1×10 17 cm -3 Furthermore, in some embodiments, for example, the SiC-SJ device 4 may include fewer or additional SJ layers 18 (eg, two SJ layers 18 , three SJ layers 18 , four SJ layers 18 , etc.) to obtain a desired voltage rating.

[0046] For certain semiconductor materials with low dopant diffusion coefficients, it may be difficult to fabricate a continuous vertical superjunction column extending through the thickness 65 of one or more epi layers 14. For example, for embodiments in which the epi layer 14 is made of SiC (which has a lower dopant diffusion coefficient than silicon (Si)), it may be difficult to fabricate such an SJ column 62. For example, in order to form an SJ column 62 (and device column 64) that extends through the entire thickness 65 of one or more epi layers 14 as present in a full SJ device, at least in some cases, a number (e.g., 10+) of thin epitaxial growth / shallow ion implantation steps may be performed. In addition, a combination of low energy implants (e.g., implant acceleration energies less than 0.5 megaelectronvolts (MeV)) and high energy implants (e.g., implant acceleration energies greater than 0.5 MeV) may be used to implant the SJ column 62. For example, an implant acceleration energy greater than 0.1 MeV and / or less than 50 MeV may be used. For example, in some embodiments, an implant acceleration energy between 0.1 MeV and 30 MeV may be employed. Therefore, the penetration range (e.g., penetration depth) of most commonly used SiC dopants (e.g., boron, nitrogen, phosphorus, aluminum) is approximately between 2 micrometers (μm) and 15 μm, which is at least suitable for implanting SJ pillars 62 through epi layers 14 having a thickness between 2 μm and 15 μm. Further, in some embodiments, suitable high-energy mask materials (e.g., silicon on insulator (SOI), polysilicon, thick silicon oxide, and high-Z metal) can be employed during the implantation of SJ pillars 62 and device pillars 64, as described in more detail below.

[0047] Additionally, for Figure 1In the illustrated embodiment, the device layer 16 includes a first group of device layer columns 64A and a second group of device layer columns 64B injected into the active region 6 and the intermediate region 8. The first group of device layer columns 64A has the same conductivity as the first group of SJ columns 62A, while the second group of device layer columns 64B has the same conductivity as the second group of SJ columns 62B. Therefore, the first group of device layer columns 64A are oppositely doped relative to the second group of device layer columns 64B. In other words, the first group of device layer columns 64A has a first conductivity type (e.g., n-type device layer columns 64), while the second group of device layer columns 64B has a second conductivity type (e.g., p-type device layer columns 64). In addition, as shown in the figure, the first group of device layer columns 64A is in contact with and electrically connected to the first group of SJ columns 62A in the third epi layer 14C (e.g., SJ layer 18C). Further, the second group of device layer pillars 64B is in contact with and electrically connected to the second group of SJ pillars 62B in the third epi layer 14C (e.g., SJ layer 18C), the well region 40 has the same conductivity type as the second group of device layer pillars 64B, and / or the well region 66 in the intermediate region 8 has the same conductivity type as the second group of device layer pillars 64B. Therefore, in some embodiments, as described above with reference to a group of SJ pillars 62, the first group of device layer pillars 64A and / or the second group of device layer pillars 64B can be implanted according to any suitable means, such as using high energy implantation, low energy implantation, or a combination thereof.

[0048] In some embodiments, the dopant concentrations in the first set of device layer pillars 64A and the second set of device layer pillars 64B of the device layer 16 are substantially the same (e.g., ±3%, ±2%, ±1%). For example, in some embodiments, the first set of SJ pillars 62A and the second set of SJ pillars 62B are each generally designed to be substantially depleted and provide a similar amount (e.g., substantially the same amount) of effective charge (e.g., per square centimeter (cm2)) from ionized dopants under reverse bias. -2 ), normalized to the device active region 6). Further, in some embodiments, the dopant concentration in the first group of device layer pillars 64A and the second group of device layer pillars 64B of the device layer 16 is approximately the same as the dopant concentration in the first group of SJ pillars 62A and the second group of SJ pillars 62B (e.g., ±3%, ±2%, ±1%). In such embodiments, the first group of device layer pillars 64A and the second group of device layer pillars 64B may be included in the first group of SJ pillars 62A and the second group of SJ pillars 62B, respectively, and the SJ layer 18Z or a portion of the SJ layer may be formed in the device layer 16.

[0049] In other embodiments, the dopant concentration in the first group of device layer pillars 64A is different from the dopant concentration in the second group of device layer pillars 64B of the device layer 16. For example, the dopant concentration in the second group of device layer pillars 64B can be approximately the same as the dopant concentration in the second group of SJ pillars 62B (e.g., ±3%, ±2%, ±1%), while the dopant concentration in at least one of the first group of device layer pillars 64A can be lower than the dopant concentration in the second group of device layer pillars 64B and / or the dopant concentration in the first group of SJ pillars 62A, as described below with respect to Figures 13 to 18 In such an embodiment, when the specific on-state resistance of the SiC-SJ device 4 can be greater than the on-state resistance of the SiC-SJ device 4 having substantially equal dopant concentrations in the first group of device layer pillars 64A and the second group of device layer pillars 64B, premature avalanche breakdown at the junction of the terminal region 10 and the intermediate region 8 and / or the active region 6 can be reduced. Therefore, as discussed below, the maximum breakdown voltage of the SiC-SJ device 4 can be increased compared to other device designs.

[0050] As described above, the termination region 24 disposed in the termination region 10 of the SiC-SJ device 4 may have a doping concentration of the first conductivity type corresponding to the minimum epi doping concentration. Further, as discussed in more detail below, within the active region 6 and / or the intermediate region 8, the doping concentrations of the first group of SJ pillars 62A and the second group of SJ pillars 62B are significantly greater (e.g., 2 times, 3 times, 5 times, 10 times, or more) than the minimum epi doping concentration of the termination region 24. For example, in some embodiments, the doping concentration of the first conductivity type in the first group of SJ pillars 62A and the doping concentration of the second conductivity type in the second group of SJ pillars may be greater than or equal to 5×10 15 Per cubic centimeter (cm -3 ) and / or less than 1×10 17 cm -3 , for example 1.0×10 16 cm -3 . In addition, within a device region (e.g., the terminal region 10, the intermediate region 8 and / or the active region 6), the doping concentration of the first conductivity type in some portions of the epi layer (e.g., the terminal region 24, the first group of SJ pillars 62A and / or the second group of SJ pillars 62B, respectively) may be the same or different.

[0051] for Figure 1In the embodiment shown, the termination region 10 includes a junction termination (i.e., JTE 12) in the termination region 24Z of the device layer 16. In some embodiments, the JTE 12 includes a plurality of implanted regions having a dopant of a second conductivity type (e.g., p-type), which extend from the intermediate region 8 over a width 11 and are used to reconstruct the electric field at least in the termination region 10 of the SiC-SJ device 4. In some embodiments, the implanted regions include floating regions 68, which are located at the bottom of the device layer 16. Figure 1 The SiC-SJ device 4 is implemented in the form of unconnected, dopant-implanted blocks. When the floating regions 68 are arranged as disclosed, they gradually reduce the strength of the electric field outside the active region 6 of the SiC-SJ device 4 during the high voltage blocking operation. Additionally, the SiC-SJ device 4 may further include several passivation layers 70 disposed on the device layer 16 in the termination region 10, which may be formed of one or more dielectric materials that help reduce the electric field above the device layer 16.

[0052] As described above, the floating regions 68 of the illustrated SiC-SJ device 4 are regions of opposite conductivity type relative to the minimum epi doping of the epi layer 14Z (eg, the termination region 24Z) in which they are located. Figure 1 When the embodiment of the SiC-SJ device 4 shown in FIG. 4 is in the off state under reverse bias, the floating regions 68 are depleted to provide ionized dopants (immobilized charges) that, when appropriately sized, shaped, and positioned relative to the X-axis and the Z-axis, allow the electric field to be reconstructed within the perimeter of the SiC-SJ device 4 (e.g., within the termination region 10). More specifically, when the floating regions 68 are depleted under reverse bias, they prevent electric field peaks and provide an electric field distribution whose amplitude gradually decreases with increasing distance from the active region 6 of the SiC-SJ device 4. Under reverse bias, the specific electric field distribution in the termination region 10 of the SiC-SJ device 4 depends on, for example, the distribution of dopants (e.g., dopant concentration, size and position of the floating regions 68).

[0053] for Figure 1 In the embodiment of the SiC-SJ device 4 shown, the floating region 68 has a specific depth 72. In other embodiments, the floating region 68 may extend through the entire thickness of the device epitaxial layer 14Z (e.g., thickness 65Z). Figure 1In the illustrated embodiment, the width 74 of the floating region 68 and the spacing 76 between the floating regions 68 in the termination region 10 vary (e.g., decrease or increase) as the distance from the active region 6 of the SiC-SJ device 4 increases to provide a gradual decrease in the effective sheet doping concentration in the termination region 10. It will be appreciated that in other embodiments, the width 74 of the floating region 68 decreases significantly as the distance from the active region 6 increases, while the spacing 76 between the floating regions 68 remains substantially constant. In still other embodiments, the spacing 76 between the floating regions 68 increases significantly as the distance from the active region 6 increases, while the width 74 of the floating region 68 remains substantially constant. Further, in some embodiments, the SiC-SJ device 4 may include at least one additional JTE 12 in at least one buried epi layer 14 (e.g., SJ layer 18). That is, for example, while the illustrated embodiment includes a single JTE 12, it is understood that in some embodiments, the SiC-SJ device 4 may include a corresponding JTE 12 (e.g., 12B, 12C, 12D, etc.) in each epi layer 14. Alternatively, the SiC-SJ device 4 may include a JTE 12 for each epi layer in a set of epi layers 14, such that the JTE 12 is adjacent to every other epi layer 14, every third epi layer 14, and so on. Thus, in some embodiments, the floating region 68 of each epi layer 14 may have a different depth 72, width 74, and spacing 76. For such embodiments, one or more masking / lithography steps may be used to fabricate the JTE 12 of each epi layer 14.

[0054] Furthermore, in some embodiments, the disclosed floating regions 68 may have one or more characteristics (e.g., doping, width, depth, spacing, etc.) as described for floating regions in co-pending U.S. Patent Application No. 16 / 060,549, filed on June 8, 2018, entitled “EDGE TERMINATION DESIGNS FOR SILICON CARBIDE SUPER-JUNCTION POWER DEVICES,” the disclosure of which is incorporated herein by reference in its entirety for all purposes. For example, in some embodiments, the width 74 of each floating region 68 may be between 0.8 micrometers (μm) and approximately 5 μm, while the spacing 76 between the floating regions 68 may generally be less than the thickness of the corresponding epi layer 14 in which the floating region 68 is disposed (e.g., the thickness 65Z of the device epi layer 14Z). Further, the depth 72 of each floating region 68 may be approximately 1 μm. In addition, the overall charge (e.g., dose) of the JTE 12 can be within 6×1012 cm -2 and 3×10 13 cm -2 For example, in some embodiments, the overall charge of JTE 12 may be 1.6×10 13 cm -2 .

[0055] The JTE 12 described herein provides an illustrative example of a junction termination, and more specifically, the JTE 12 described herein depicts an illustrative example of a graded region JTE. However, in some embodiments, an implant region (such as a floating region 68) having a second conductivity type (e.g., p-type) may be additionally or alternatively implemented to have one or more characteristics corresponding to another termination and / or junction termination structure. For example, the implant region may be implemented as a single region JTE (which may include a single implant region in contact with the intermediate well region 66), and / or as a multi-region JTE (which may include two or more interconnected implant regions). In some embodiments, the two or more interconnected implant regions may have the same or different characteristics, and at least one of the two or more interconnected implant regions may contact the intermediate well region 66. Additionally, in some embodiments, the implant region may be implemented to form a multi-floating region JTE. In such an embodiment, a first implant region may contact the intermediate well region 66, and a set of additional implant regions (such as a floating region 68) having different spacings and / or widths may be implanted separately from the first implant region and separately from each other. Furthermore, in some embodiments, implant regions (e.g., floating regions 68) may be implemented to form floating field ring (FFR) terminations. In such embodiments, floating regions 68 may be implanted unconnected to each other and unconnected to the intermediate well region 66. Additionally or alternatively, implant regions may be implemented to form a spatially modulated JTE, which may include a first implant region in contact with the intermediate well region and unconnected to a set of additional implant regions that are implanted to form the FFR. Thus, it will be appreciated that the techniques described herein may be applied to any suitable junction termination (e.g., single-region JTE, multi-region JTE, graded JTE, multi-floating region JTE, FFR, spatially modulated JTE, etc.), and that the embodiments described herein are intended to be illustrative rather than limiting.

[0056] Figure 2 A top view (vertical to the direction of the SiC-SJ device 4) according to an embodiment of the present invention is shown. Figure 1 More specifically, Figure 2 A top view of an embodiment of a SiC-SJ device 4 having a termination region 10 including a floating region 68 implemented as an unconnected doped block is shown. In particular, Figure 2A top view of the JTE 12 and a cross section 100 revealing the SJ layer 18C is shown. In other words, the JTE 12 and the SJ layer 18C are shown in the same top view. However, it is understood that the SJ layer 18C can be disposed at a different depth (e.g., along the Y axis) than the JTE 12, as indicated by the cross section.

[0057] for Figure 2 In the illustrated embodiment, each floating region 68 has a specific length 78 along the Z axis and an additional spacing 80. In some embodiments, the length 78 of each floating region 68 can be between 0.8 μm and approximately 5 μm, and the additional spacing 80 between the floating regions 68 can generally be less than the thickness 65 of the corresponding epi layer 14 in which the floating region 68 is disposed (e.g., the thickness 65Z of the device epi layer 14Z). Although the floating regions 68 are shown as blocks that are not connected to each other, the floating regions 68 can be implemented as blocks that are not connected to each other, continuous columns, strips, segments, grids, dots, or any other suitable shape. Therefore, the length 78 and the additional spacing 80 between the floating regions 68 can vary between certain embodiments. In addition, as described above, the floating regions 68 can be implemented to have characteristics (e.g., length 78, additional spacing 80, etc.) for forming alternative terminal and / or junction terminal structures. Therefore, the embodiments disclosed herein are intended to be illustrative rather than restrictive.

[0058] In some embodiments, reconfiguring the electric field of the SiC-SJ device 4 may include forming the JTE 12 so that avalanche breakdown (the result of impact ionization) occurs outside the termination region 10 (e.g., within the active region 6 and / or the intermediate region 8) at the nominal rated voltage. That is, for example, in some embodiments, avalanche breakdown may occur in isolation in the active region 6 and / or the intermediate region 8, which may maximize the breakdown voltage of the SiC-SJ device 4, thereby achieving a breakdown voltage close to or equal to that of the device. Briefly review Figure 1 It can be understood that in a conventional SiC device (for example, having 5.0×10 15 cm -3 In order to confine the avalanche breakdown to the active region 6 and / or the intermediate region 8 in a SiC device having an epi doping concentration of 100 or higher, the width 11 of the JTE 12 may be greater than or equal to five times (5x) the one-dimensional (1-D) depletion width of the device, where the 1-D depletion width may be approximately equal to the epi thickness of the active region 6 (e.g., the sum of the thickness 65 of the epi layer 14). That is, for example, in a conventional device, the ratio of the width 11 of the JTE 12 to the 1-D depletion width of the device may be 5:1. However, as Figure 3As shown in the graph 120, in order to achieve a peak (e.g., maximum) breakdown voltage in a SiC-SJ device 4 having one or more SJ layers 18 and a termination region 24 with a minimum epi doping concentration, the ratio of the width 11 of the JTE 12 to the 1-D depletion width of the SiC-SJ device 4 can be significantly reduced. For example, as described in more detail below, the graph 120 shows that for a SiC-SJ device design having a JTE 12 with a width 11 greater than or equal to 2.75x (e.g., between 2.75x and 5x, between 2.75x and 4x, between 2.75x and 3x) of the 1-D depletion width of the SiC-SJ device 4, avalanche breakdown can be limited to only within the active region 6 and / or the intermediate region 8. Thus, by using the disclosed JTE design, it is presently recognized that for a SiC-SJ device 4, the ratio of the active region 6 to the overhead region (e.g., including the termination region 10) of the SiC-SJ device 4 can be increased. Therefore, the die area available for the active region 6 can be increased. It can be noted that, as discussed below, in certain embodiments, it may be desirable for breakdown to occur at the JTE 12 in the termination region 10 of the SiC-SJ device 4. For such embodiments, the disclosed junction termination design can also enable a breakdown voltage close to or equal to the device's intended breakdown voltage with a reduced termination width 11.

[0059] More specifically, graph 120 depicts an example of a breakdown voltage that can be achieved by a SiC-SJ device 4 as a function of the width 11 of the JTE 12 (eg, the width of the termination region 10 ). Figure 3 In the illustrated example of the SiC-SJ device 4 in FIG. 1 , the 1-D depletion width is 40 μm. Therefore, the ratio of the width 11 of the JTE 12 (e.g., the width of the termination region 10) to the 1-D depletion width of the SiC-SJ device 4 can be determined by dividing the width 11 by 40 μm. However, it is understood that the ratio of the width 11 of the JTE 12 (e.g., the width of the termination region 10) to the 1-D depletion width of the SiC-SJ device 4 described herein can be extended to SiC-SJ device designs having any suitable 1-D depletion width. Therefore, the embodiments described herein are intended to be illustrative rather than limiting.

[0060] To the left of line 122 (e.g., for a ratio of the width 11 of JTE 12 to the 1-D depletion width of the device below about 2.75), avalanche breakdown occurs at JTE 12 (e.g., termination region 10) and / or at the junction of JTE 12 and intermediate well region 66. To help illustrate, Figure 4, a cross-sectional view of a portion of an embodiment of a SiC-SJ device 4 having a JTE 12 having a width 11 of 100 μm (eg, a ratio of the width 11 of the JTE 12 to the 1-D depletion width of the device is approximately 2.5). Additionally, Figure 4 The isokinetic lines 140 indicating the collision generation rate (e.g., collision ionization rate) present in different regions of the SiC-SJ device 4 under the reverse bias state are included. It can be noted that when the isokinetic lines 140 are close to each other, the collision generation rate is indicated as being higher (e.g., larger), and when there is a larger spacing between the isokinetic lines 140, the collision generation rate is indicated as being lower. Therefore, because avalanche breakdown occurs at the JTE 12 (e.g., the termination region 10), the collision generation rate is highest at the JTE 12 and the termination region 10 and decreases outward from these regions.

[0061] Simply review Figure 3 , to the right of line 122 (e.g., for a ratio of the width 11 of the JTE 12 to the 1-D depletion width of the device greater than or equal to about 2.75), avalanche breakdown desirably occurs in the active region 6 and / or the intermediate region 8, rather than in the termination region 10 of the SiC-SJ device 4. To help illustrate, Figure 5 , a cross-sectional view of a portion of an embodiment of a SiC-SJ device 4 having a JTE 12 having a width 11 of 160 μm (eg, a ratio of the width 11 of the JTE 12 to the 1-D depletion width of the device of approximately 4). For comparison, Figure 4 All other device parameters (e.g., minimum epi doping, thickness 65, etc.) included in the illustrated embodiment are Figure 5 The embodiment shown remains unchanged. Additionally, Figure 5 The isokinetic lines 160 are included to indicate the collision generation rate (e.g., collision ionization rate) present in different regions of the SiC-SJ device 4 under the reverse bias state. It can be noted that when the isokinetic lines 160 are close to each other, the collision generation rate is represented as higher (e.g., larger), while when there is a larger spacing between the isokinetic lines 140, the collision generation rate is represented as lower. Therefore, because avalanche breakdown occurs at the active region 6 and / or the intermediate region 8, the collision generation rate is highest at the SJ region 60 and the well region 66 in the intermediate region 8 and decreases outward from these regions. Therefore, for the illustrated embodiment, the collision generation rate within the termination region 10 is minimized and can gradually decrease with increasing distance from the intermediate region 8 and / or the active region 6. Therefore, embodiments of the SiC-SJ device 4 in which the ratio of the width 11 of the JTE 12 to the 1-D depletion width of the device is greater than or equal to about 2.75 can achieve the maximum breakdown voltage of the SiC-SJ device 4.

[0062] As described above, the termination regions 24 (e.g., 24A, 24Z) generally have a minimum epi doping concentration that is significantly lower than the doping concentration of the first conductivity type in the first set of SJ pillars 62A and / or the second set of SJ pillars 62B of the device. In some embodiments, together with the width of the JTE 12, the minimum epi doping concentration of the termination regions 24 may affect the maximum breakdown voltage of the SiC-SJ device 4 and / or the location of avalanche breakdown within the SiC-SJ device 4. To demonstrate this relationship, Figure 6 The graph 180 shown in FIG. 1 shows the epi doping concentration (cm -3 ) is an example of the breakdown voltage of the SiC-SJ device 4 changed by .

[0063] Curve 182 on graph 180 plots the change in epi doping concentration in termination region 24. Figure 1 10. The breakdown voltage of an embodiment of a SiC-SJ device 4 of FIG. 10. More specifically, curve 182 illustrates an example of a relationship between a breakdown voltage of a SiC-SJ device 4 having a single device JTE 12 and an epi doping concentration of the termination region 24. The graph 180 additionally includes a first line 184 indicating a threshold breakdown voltage that permits the device to receive a 4.5 kilovolt (kV) device rating. Further, the graph 180 includes a second line 186 representing a breakdown voltage level below which avalanche breakdown of the SiC-SJ device 4 occurs outside the termination region 10 (e.g., avalanche breakdown occurs within the active region 6 and / or the intermediate region 8).

[0064] Therefore, as shown in the graph 180, in order to design a SiC-SJ device 4 with a specific device rating (e.g., 4.5 kV) and to confine avalanche breakdown to the active region 6 and / or the intermediate region 8 (e.g., to increase the maximum breakdown voltage of the device), the termination region 24 may be less than or equal to 1.5×10 15 cm -3 (For example, 8.0×10 13 cm -3 , 1.0×10 15 cm -3 ) is achieved, which is referred to herein as the minimum epi-doping concentration 188 of this exemplary SiC-SJ device 4. For example, for less than or equal to 1.5×10 15 cm -3 On the other hand, for an epi doping concentration greater than 1.5×10 15 cm -3The avalanche breakdown occurs at the termination region 10 (e.g., the device JTE 12) and / or at the junction of the device JTE 12 and the intermediate well region 66. As a result, for an epi doping concentration greater than 1.5×10 15 cm -3 As the epi doping concentration of the termination region 24 increases (e.g., the minimum epi doping concentration 188 for the present embodiment), the maximum breakdown voltage of the SiC-SJ device 4 decreases. Moreover, in some cases, the maximum breakdown voltage of the SiC-SJ device 4 may be reduced to below a threshold breakdown voltage (e.g., the first line 184) for classifying the voltage rating of the SiC-SJ device 4. Further, while the minimum epi doping concentration 188 described herein is associated with an embodiment of a SiC-SJ device 4 having a single JTE 12, it is presently recognized that the range of the minimum epi doping concentration 188 of the termination region 24 may have a greater tolerance to increase the epi doping concentration for device designs having a greater number of JTEs 12. Accordingly, the embodiments described herein are intended to be illustrative and not limiting.

[0065] To help illustrate the effect of the epi doping concentration of the termination region 24 on the maximum breakdown voltage of the SiC-SJ device 4 and / or the location of avalanche breakdown within the SiC-SJ device 4, Figure 7 and Figure 8 Each shows a cross-sectional view of a portion of a respective embodiment of a SiC-SJ device 4 having a termination region 24 of a respective different epi doping concentration. Figure 7 In the example of the SiC-SJ device 4 shown, the epi doping concentration of the termination region 24 is 8.0×10 13 cm -3 Additionally, Figure 7 The isokinetic lines 200 are included, which indicate the collision generation rate (e.g., collision ionization rate) present in different regions of the SiC-SJ device 4 under the reverse bias state. It can be noted that when the isokinetic lines 200 are close to each other, the collision generation rate is represented as higher (e.g., larger), and when there is a larger spacing between the isokinetic lines 200, the collision generation rate is represented as lower. Therefore, because avalanche breakdown occurs at the active region 6 and / or the intermediate region 8 (e.g., SJ region 60), the collision generation rate is highest at the active region 6 and / or the intermediate region 8 and decreases from these regions outward. In addition, for an embodiment in which avalanche breakdown occurs at the active region 6 and / or the intermediate region 8, the maximum breakdown voltage of the representative SiC-SJ device 4 is about 6300 kV.

[0066] For comparison, Figure 8In the illustrated portion of the embodiment of the SiC-SJ device 4, the epi doping concentration of the termination region 24 is 1.4×10 15 cm -3 ,and Figure 7 All other device parameters included in the illustrated embodiment (eg, width 11, thickness 65, etc.) remain unchanged. Additionally, Figure 8 The iso-rate lines 220 are included, which indicate the collision generation rates (e.g., collision ionization rates) present in different regions of the SiC-SJ device 4 under the reverse bias state. It can be noted that when the rate lines 220 are close to each other, the collision generation rate is represented as higher (e.g., larger), and when there is a larger spacing between the rate lines 220, the collision generation rate is represented as lower. Since the avalanche breakdown of the illustrated embodiment mainly occurs at the active region 6 and / or the intermediate region 8 (e.g., the SJ region 60), the collision generation rate at the JTE 12 is higher than that at the JTE 12. Figure 7 The collision rate at JTE 12 is shown. As a result, Figure 8 The maximum breakdown voltage of the embodiment of the portion of the SiC-SJ device 4 shown is lower than Figure 7 The maximum breakdown voltage of the embodiment of the portion of the SiC-SJ device 4 shown. That is, Figure 8 The maximum breakdown voltage of the illustrated embodiment of the portion of the SiC-SJ device 4 is approximately 5600 kV. Therefore, it can be understood that the maximum breakdown voltage of the SiC-SJ device 4 decreases as the epi doping concentration of the termination region 24 increases.

[0067] Fig. 9 2 is a flow chart of a process 240 for fabricating an embodiment of a SiC-SJ device 4 having one or more junction terminations (such as one or more JTEs 12) according to embodiments described herein. Although the following contents of process 240 are described in a particular order representative of a particular embodiment, it should be noted that process 240 may be performed in any suitable order. Further, certain steps may be repeated or skipped entirely, and in other embodiments, additional steps may be included in process 240. Reference Figure 1 The embodiment of the SiC-SJ device 4 shown and referring to Figures 10 to 12 The following contents of process 240 are described below.

[0068] The process shown begins by forming (process block 242) an epi layer having a minimum epi doping concentration of a first conductivity type on a base layer, such as Fig.10 As shown. In some embodiments, the base layer may include a semiconductor substrate layer 20. As described above, the substrate layer 20 may be made of silicon, silicon carbide (SiC), gallium nitride, diamond, aluminum nitride, boron nitride, or any other suitable wide bandgap substrate. Alternatively, the epi layer may be formed on another epi layer 14 and / or SJ layer 18, as described in more detail below.

[0069] To form the first epi layer 14A on the base layer, chemical vapor deposition (CVD) may be used to grow the epi layer 14A. However, in some embodiments, the epi layer 14A may be grown onto the base layer using any suitable technique. The epi layer 14A may be formed of one or more wide bandgap semiconductor materials such as silicon carbide, gallium nitride, diamond, aluminum nitride, and / or boron nitride. Further, as discussed above, the epi layer 14A may have a first conductivity type (e.g., n-type) and a low dopant concentration relative to other regions of the SiC-SJ device 4 (e.g., SJ pillars 62, JTE 12, etc.). More specifically, in some embodiments, the first epi layer 14A may be formed without any intentional epi doping such that the first epi layer 14A has a dopant concentration less than or equal to 1.5×10 15 cm -3 (For example, at 8.0×10 13 cm -3 and 1.0×10 15 cm -3 The minimum epi doping concentration between ) is formed.

[0070] Back to Fig. 9 After forming the first epi layer 14A on the base layer, the process continues to implant (process block 244) pillars of the first conductivity type into the first epi layer 14A. More specifically, to form the SJ layer 18A, a first set of SJ pillars 62A having the first conductivity type may be implanted into the active region 6 and the intermediate region 8 within the first epi layer 14A. Fig.11 As shown, the implanted region of the first conductivity type (e.g., n-type) can extend through the thickness 65A of the first epi layer 14A. Therefore, in some embodiments, a suitable high-energy ion implantation technique can be used to implant the region of the first conductivity type. Therefore, each of the one or more regions can be implanted into the epi layer 14A to a depth greater than 1 μm (e.g., implanted to a depth of 2 μm to 15 μm). In addition, an implantation energy greater than 500 keV and / or less than 50 MeV can be used to implant each of the one or more regions. Therefore, a high-energy implantation mask (e.g., silicon on insulator (SOI), polysilicon, thick silicon oxide, such as high-Z metals such as platinum, molybdenum, gold, etc.) can be used in combination with high-energy ion implantation. In addition, any suitable means can be used to form the mask. That is, for example, the mask can be directly deposited, grown, and / or coated onto a portion of the epi layer 14A. Furthermore, once the mask material has been deposited on the surface of epi layer 14A, a mask may be formed by patterning the mask material (eg, photolithographic patterning) to expose or uncover a portion of epi layer 14A. The set of SJ pillars 62A may then be selectively implanted through the exposed portions of epi layer 14A.

[0071] Additionally, to form the SJ layer 18A, a second set of SJ pillars 62B of a second conductivity type (e.g., p-type) are implanted (process block 246) into the active region 6 and / or the intermediate region 8. In some embodiments, the SJ layer 18A may be formed using a self-aligned method and a set of masks, as described in co-pending U.S. Provisional Patent Application No. 62 / 738,961, filed on September 28, 2018, entitled “SUPER-JUNCTION SEMICONDUCTOR DEVICE FABRICATION,” the disclosure of which is incorporated herein by reference in its entirety for all purposes. For example, after the first set of SJ pillars 62A are implanted into the first portion of the epi layer 14A using a first mask covering the second portion of the epi layer as described above, a second mask self-aligned with respect to the first mask may be formed on the first portion of the epi layer 14A. In some embodiments, the second mask may be formed to have different physical and / or chemical properties relative to the first mask. For example, the second mask can be formed of a different material, can undergo different chemical and / or physical changes, and / or can be formed to have different optical properties and / or wavelength absorption properties relative to the first mask. Therefore, the first mask can then be removed by a suitable process (e.g., dissolution, stripping, and / or degradation) that leaves the second mask intact. By removing the first mask, the second portion of the epi layer 14A is exposed, while the first portion of the epi layer 14A remains masked by the second mask. Therefore, the second group of SJ columns 62B can be selectively injected into the second portion of the epi layer 14A, and then the second mask can be removed. More specifically, in some embodiments, the second group of SJ columns 62B can be injected into a position adjacent to the first group of SJ columns 62A and arranged in an interlaced manner with the first group of SJ columns. For embodiments in which the first mask and the second mask are self-aligned, misalignment (e.g., overlap and / or gap) between the first group of SJ pillars 62A and the second group of SJ pillars 62B can be reduced or avoided, which may destroy the uniformity of the electric field and reduce the maximum blocking voltage of the SiC-SJ device 4.

[0072] Further, the group of SJ pillars 62 can be implanted using any suitable means (e.g., high energy implantation, low energy implantation), as discussed below. For example, in some embodiments, the group of SJ pillars 62 can be implanted using standard low energy implantation techniques. For example, the group of SJ pillars 62 can be implanted to a depth less than or equal to 1 μm. Therefore, each SJ pillar 62 can be implanted using an implantation energy of less than 500 keV. However, in some embodiments, the group of SJ pillars 62 can be implanted using suitable high energy ion implantation techniques. Therefore, each SJ pillar 62 can be implanted using an implantation energy greater than 500 keV and / or less than 50 MeV. In addition, the above-mentioned mask can be a high energy implantation mask (e.g., silicon on insulator (SOI), polysilicon, thick silicon oxide, high Z metal) used in combination with high energy ion implantation.

[0073] In order to form a suitable number of SJ layers 18 in the SiC-SJ device 4, a portion of the process 240 (e.g., process block 242, process block 244, and / or process block 246) may be repeated one or more times. Thus, after forming the SJ layer 18A, the process 240 may continue to determine (decision block 248) whether to add an additional SJ layer 18B to the SiC-SJ device 4. For example, in an embodiment having one or more additional SJ layers 18, a second epi layer 14B may be formed on the previously implanted SJ layer 18A (process block 242) and a second SJ layer 18B may be formed (e.g., process block 244, process block 246). For example, for Fig.11 As shown in the embodiment of the SiC-SJ device intermediate product 280 , portions of the process 240 (eg, process block 242 , process block 244 , and / or process block 246 ) may also be repeated to form the third SJ layer 18C.

[0074] After the fabrication of one or more SJ layers 18 is completed, Fig. 9 The process 240 shown continues to form (process box 250) a device epi layer 14Z having a minimum epi doping concentration of the first conductivity type. As discussed in the formation of one or more epi layers 14 with reference to the SJ layer 18 (process box 242), the device epi layer 14Z can be grown using CVD. Alternatively, the device epi layer 14Z can be formed on one or more underlying SJ layers 18 using any suitable technique. The device epi layer 14Z can also be formed of one or more wide bandgap semiconductor materials (such as silicon carbide, gallium nitride, diamond, aluminum nitride, and / or boron nitride). More specifically, for a SiC-SJ device 4 having a single junction termination (e.g., a single JTE 12), the device epi layer 14Z can be less than or equal to 1.5×10 15 cm -3 (For example, at 8.0×10 13 cm-3 and 1.0×10 15 cm -3 The minimum epi doping concentration between ) is formed.

[0075] Fig. 9 The process 240 shown then continues to form (process box 254) certain device features within the active region 6 and / or the intermediate region 8 within the device epi layer 14Z to define the device layer 16. That is, for example, the first group of device layer pillars 64A and the second group of device layer pillars 64B can be implanted into the active region 6 and / or the intermediate region 8 within the device epi layer 14Z. More specifically, in some embodiments, a high-energy ion implantation technique can be used to implant each of the first group of device layer pillars 64A and the second group of device layer pillars 64B so that the first group of device layer pillars 64A contact and are electrically connected to the first group of SJ pillars 62A, and so that the second group of device layer pillars 64B contact and are electrically connected to the second group of SJ pillars 62B, such as Fig.11 As shown. Further, in some embodiments, the first group of device layer pillars 64A and the second group of device layer pillars 64B can be implanted using a self-aligned method and a mask set, as described above with reference to the group of SJ pillars 62. In addition, as described below, the doping concentration of at least one of the first group of device layer pillars 64A can be less than the doping concentration of the second group of device layer pillars 64B. Further, the well region 40, the source region 44, the intermediate well region 66, etc. can be formed (e.g., implanted) in the active region 6 and / or the intermediate region 8 within the device epi layer 14Z to define the device layer 16, as shown. Fig.12 Therefore, although process block 252 is described herein as a single step, it is understood that forming device features (e.g., first set of device layer pillars 64A, second set of device layer pillars 64B, well region 40, intermediate well region 66, source region 44, etc.) may include multiple steps, such as a separate implantation step for each corresponding feature and / or multiple implantation steps for each feature.

[0076] further, Fig. 9 The process 240 shown involves implanting (process block 254) a floating region having a second conductivity type into the termination region 24Z of the device epi layer 14Z to define a junction termination (such as JTE 12) in the device layer 16, as shown in FIG. Fig.12As shown. The floating region 68 can be implanted according to any suitable means (e.g., high energy implantation, low energy implantation). Therefore, in some embodiments, the floating region 68 can be selectively implanted through a portion of the terminal region 24Z exposed by a mask formed on the terminal region 24Z, and then the mask can be removed. Further, in some embodiments, the floating region 68 can be implanted to a depth less than or equal to 1 μm. Therefore, an implantation energy of less than 500 keV can be used to implant each floating region 68. However, in some embodiments, the floating region 68 can be implanted according to a suitable high energy ion implantation technique. Therefore, for such an embodiment, each floating region 68 can be implanted into the device epi layer 14Z to a depth greater than about 2 μm and / or less than about 15 μm. In addition, each floating region 68 can generally be implanted using an implantation energy greater than 500 keV and / or less than 50 MeV. Subsequently, other processing steps may be performed to form other features of SiC-SJ device 4 (eg, gate electrode 48 , dielectric layer 46 , source contact 54 , drain contact 50 , etc.) to form a functional power conversion device in accordance with the present disclosure.

[0077] In some embodiments, different implantation operations may be used to implant features of the second conductivity type in the device epi layer 14Z, such as the well region 40 and the floating region 68. Alternatively, in some embodiments, the floating region 68 may be implanted simultaneously with other features of the device epi layer 14Z (e.g., the well region 40, the intermediate well region 66). For example, during the same ion implantation step used to implant these features with the second conductivity type, the floating region 68 of the JTE 12 may be implanted with the same dopant type (e.g., p-type or n-type dopant) and / or using the same material (e.g., Al, B, N, P, etc.), which may reduce manufacturing time and cost.

[0078] As described above, in some embodiments, the doping of the SJ pillar 62A of the first conductivity type (e.g., n-type) closest to the termination region 10 may be modified relative to the other SJ pillars 62A to further adjust the BV (breakdown voltage) of the device and control the portion of the device that experiences breakdown when the BV is reached (e.g., the active region 6 or the termination region 10). To illustrate this, Fig.13 is a cross-sectional view of a portion of an embodiment of a SiC-SJ device 300 having a termination region 10 including a JTE 12 according to aspects of the present technique. For the illustrated embodiment of the SiC-SJ device 300, the first conductivity type is n-type, which corresponds to the conductivity type of the SJ pillar 62A, the minimum epi-doped epi layer 14 in the termination region 10, and the SiC substrate 20. Additionally, for the illustrated embodiment, the second conductivity type is p-type, which corresponds to the conductivity type of the SJ pillar 62B, the intermediate well region 66, and the JTE 12.

[0079] The SiC-SJ device 300 shown is modeled to determine how a change in doping of the last SJ pillar 64A of the first conductivity type closest to the termination region 10 (hereinafter referred to as the modified SJ pillar 302) affects the breakdown characteristics of the device 300. With this in mind, Fig.14 yes Fig.13 00. An enlarged view of an embodiment of a SiC-SJ device 300. As shown, the modified SJ column 302 includes a modified portion 304 having a lower n-type doping concentration relative to the remainder of the column 302 and relative to other n-type SJ columns 62A in the active region 6 of the device 300 (not shown). The modified portion 304 of the SJ column 302 can be described as having a depth 306 extending to one or more epi layers 14 below the intermediate well region 66. For example, in the illustrated embodiment, the depth 306 of the modified portion 304 is approximately 12 μm. As discussed below, by controlling both the depth 306 and the doping concentration within the modified portion 304 of the modified SJ column 302, the breakdown properties of the device 300 can be controlled. It will be appreciated that although Fig.13 and Fig.14 Only the middle region 8 and the terminal region 10 of one portion of the device 300 are shown, but the n-type SJ pillar 64A closest to the terminal region 10 in other portions of the device 300 may also be a modified SJ pillar 302 as discussed herein.

[0080] For the model discussed below, the embodiment of the SiC-SJ device 300 has a 1×10 15 cm -3 The minimum epi doping concentration and a combined or total epi layer thickness of 40 μm. The intermediate well region 66 has a depth of 1 μm and a 3×10 17 cm -3 JTE12 has a doping concentration of 3×10 13 cm -2 The p-type SJ pillar 62B of the device 300 has a width 73 of 5 μm and a width of 160 μm (eg, slightly greater than four times the 1-D depletion width). 16 cm -3 The n-type SJ pillar 62A has a width 73 of 5 μm and has a thickness of 1.7×10 16 cm -3 Additionally, it may be noted that for these examples, device layer pillars 64A and 64B are generally described as being part of SJ pillars 62A and 62B, respectively.

[0081] Fig.15 is a graph 310 showing the Fig.143 shows an embodiment of a SiC-SJ device 300 as a function of the absolute net doping concentration along line A and line B (μm). More specifically, curve 312 corresponds to line A, while curve 314 corresponds to line B. As shown, when moving along line B, the net doping concentrations within the unmodified portion of the modified SJ column 302 and within the p-type SJ column 64B are approximately the same until a significantly lower minimum epi doping concentration is reached in the termination region 10. When moving along line A, the net doping concentration within the modified portion 304 of the modified SJ column 302 is significantly less (e.g., about 40% less) than the net doping concentration of the p-type SJ column 64B until a significantly lower minimum epi concentration is again reached in the termination region 10.

[0082] Fig.16 3 is a graph 320 showing the breakdown voltage as a function of the depth 306 of the modified portion 304 of the modified SJ pillar 302 for an embodiment of a SiC-SJ device. In addition to the model parameters discussed above, for the embodiment represented in the graph 320, the doping concentration of the modified portion 304 is 1.02×10 16 cm -3 Graph 320 includes a line 322 representing the desired BV of SiC-SJ device 300, which for these examples is 6092 V. Graph 320 also includes a curve 324 corresponding to the data of Table 1, which represents the breakdown voltage of embodiments of Si-SJ device 300 having modified portions 304 of modified SJ pillars 302 with different depths 306.

[0083]

[0084]

[0085] Table 1. Corresponding to Fig.16 The data of curve 324.

[0086] As shown in the graph 320, for the modeled embodiment of the SiC-SJ device 300, when the modified portion 304 of the modified SJ pillar 302 has a depth 306 of about 11 μm or more, the breakdown voltage approaches the desired breakdown voltage of the device. In certain embodiments, this depth 306 may correspond to about 30% or more (e.g., about 1 / 3) of the total depth of the modified SJ pillar 302. Thus, an embodiment of the SiC-SJ device 300 may be fabricated based on the above modeled parameters, and the depth 306 of the modified portion 304 may be about 7.1 μm, which yields a breakdown voltage of about 5483 V or about 90% of the desired breakdown voltage of the device. As also shown in the graph 320 , for the modeled SiC-SJ device 300 , when the modified portion 304 of the modified SJ pillar 302 has a depth 306 less than about 12 μm, the breakdown occurs at the top of the n-type SJ pillar 62A in the active region 6 and the intermediate region 8 of the device 300 , and when the modified portion 304 has a depth 306 greater than about 12 μm, the breakdown occurs at the JTE 12 in the terminal region 10 of the device 300 .

[0087] It is also currently recognized that in certain embodiments, it may be advantageous for the depth 306 of the modified portion 304 of the modified SJ pillar 302 to correspond to the thickness of the device epi layer 14Z. For example, briefly reviewing Fig.13 , in an embodiment where the device epi layer 14Z has a thickness 65Z of about 14 μm and the intermediate well region 66 occupies approximately the top 1 μm of the device epi layer 14Z, the depth 306 of the modified portion 304 of the modified SJ pillar 302 will be about 13 μm. In other words, in some embodiments, the modified portion 304 can be confined to that device layer pillar 64B in the intermediate region 8 of the device epi layer 14Z that is closest to the terminal region 10 of the device. For such embodiments, the modified portion 304 of the modified SJ pillar 302 is completely contained within the device epi layer 14Z, and only the doping of that portion of the modified SJ pillar 302 in the device epi layer 14Z is reduced relative to the remainder of the modified SJ pillar 302 or other n-type SJ pillars 62A in the active region 6, which simplifies the manufacture of the device 300. In certain embodiments, the thickness 65Z of the device epi layer 14Z may be between 2 μm and 15 μm, such as between 2 μm and 10 μm or between 10 μm and 15 μm.

[0088] It is understood that, generally, it is desirable that the breakdown occur uniformly over a relatively large device area / volume. Fig.16 Based on the data presented in , it is now recognized that a device designer can use the depth 306 of the modified portion 304 of the modified SJ pillar 302 as a method of controlling where breakdown occurs within the device 300 . Fig.17A and Fig. 17B It is a display Fig.16 . More specifically, Fig.17A 3 is a graph 330 showing the collision occurrence rate of an embodiment of the SiC-SJ device 300 in which the depth 306 of the modified portion 304 of the modified SJ pillar 302 is 13.5 μm, and therefore, breakdown occurs at the JTE 12 in the termination region 10. In contrast, Fig. 17B is a graph 340 showing the collision occurrence rate of the SiC-SJ device 300 where the depth 306 of the modified portion 304 of the modified SJ pillar 302 is 12 μm, and therefore, breakdown occurs at the top of the n-type SJ pillar 62A in the active region 6 and the intermediate region 8 of the device.

[0089] In addition to the depth 306 of the modified portion 304 , it is currently recognized that the doping of the modified portion 304 of the modified SJ pillar 302 also affects the breakdown characteristics of the SiC-SJ device 300 . Fig.18 3 is a graph 350 showing the breakdown voltage according to the doping concentration in the modified portion 304 of the modified SJ pillar 302. The data of the graph 350 is modeled based on the above model parameters, except that the depth 306 of the modified portion 304 is kept at a constant value of 13.5 μm. The graph 350 also includes a curve 352 corresponding to the data of Table 2, which represents the breakdown voltage of the embodiment of the SiC-SJ device 300 with different doping concentrations in the modified portion 304 of the modified SJ pillar 302.

[0090]

[0091] Table 2. Corresponding to Fig.18 The data of curve 352.

[0092] like Fig.18 As shown in the graph 350, for the modified SJ pillar 302, the doping concentration in the modified portion 304 is greater than about 1.05×10 16 cm -3 In the embodiment of the SiC-SJ device 300, the breakdown occurs at the top of the n-type SJ pillar 34A in the active region 6 and the middle region 8 of the device. In contrast, the doping concentration in the modified portion 304 of the modified SJ pillar 302 is less than or equal to about 1.05×10 16 cm -3 In the embodiment of the present invention, the breakdown occurs at the JTE 12 in the terminal region 10 of the device. Additionally, the doping concentration in the modified portion 304 of the modified SJ pillar 302 is less than or equal to about 1.05×10 16 cm -3The embodiment of the SiC-SJ device 300 exhibits a breakdown voltage equal to that of the device 300. Therefore, in one example, the embodiment of the SiC-SJ device 300 can be manufactured such that the doping concentration in the modified portion 304 of the modified SJ pillar 302 is approximately 1.26×10 16 cm -3 The breakdown voltage of the SiC-SJ device 300 is about 90% of what it should be.

[0093] The technical effects of the present solution include effective termination of the SJ device. Additionally, the disclosed termination design consumes a relatively small portion of the die area relative to the common junction termination design and has a relatively low manufacturing cost. For example, the disclosed junction termination design can be designed to have a certain width so that the ratio of the terminal width to the one-dimensional (1-D) depletion width is minimized (e.g., less than 5, such as between 2.75 and 5, between 2.75 and 4, between 2.75 and 3), which increases the die area available for the active area of ​​the device while also providing a breakdown voltage close to or equal to the breakdown voltage that the device should have. Additionally, certain SJ columns (e.g., device columns) near the termination area may include an upper portion having a reduced doping concentration relative to other SJ columns of the device, which may increase the breakdown voltage of the device 300. In addition, the depth and doping concentration of this modified portion of these SJ columns may be changed to adjust the breakdown voltage of the SJ device and the location where the breakdown occurs.

[0094] This description is written to use examples to disclose the invention and also to enable any person skilled in the art to practice the invention, including making and using any device or system and performing any combined method. The patentable scope of the invention is defined by the claims and may include other examples that occur to one of ordinary skill in the art. Such other examples are intended to fall within the scope of the claims if they have structural elements that do not differ from the literal language of the claims, or if they include equivalent structural elements that do not differ substantially from the literal language of the claims.

[0095] The technology presented and claimed herein is cited and applied to material objects and specific examples of a practical nature that clearly advance the art and are therefore not abstract, intangible, or purely theoretical. Further, if any claim appended to the end of this specification contains one or more elements designated as "means for performing [function] ..." or "steps for performing [function] ...", it is intended that such elements will be interpreted under 35 USC 112(f). However, for any claim containing elements designated in any other manner, such elements should not be interpreted under 35 USC 112(f).

Claims

1. A super junction SJ device, comprising: a first epitaxial epi layer, the first epi layer forming a first SJ layer of the SJ device; and a second epi layer, the second epi layer being disposed on the first SJ layer and forming a device layer of the SJ device, wherein active regions of the first epi layer and the second epi layer include a first group of SJ columns and a second group of SJ columns, the first group of SJ columns including a first doping concentration of a first conductivity type, the second group of SJ columns including the first doping concentration of a second conductivity type, wherein a middle region of the first epi layer contains SJ columns including the first doping concentration of the first conductivity type, and a middle region of the second epi layer contains modified columns, the modified columns including a modified portion at an upper portion of the second epi layer and an unmodified portion at a lower portion of the second epi layer, the modified portion having a first conductivity type The modified column is arranged to be closer to the terminal region of the second epi layer than the first group of SJ columns of the second epi layer, and wherein the terminal region of the second epi layer includes a plurality of floating regions of the second conductive type, the plurality of floating regions forming junction terminals of the SJ device, and the width of the floating region and / or the spacing between the floating regions varies with increasing distance from the active region.

2. The SJ device according to claim 1, wherein: The SJ device is a silicon carbide SiC SJ device, and the minimum epi doping concentration is less than or equal to 1.5×10 15 cm -3 .

3. The SJ device according to claim 1, wherein: The minimum epi doping concentration is at least 50% less than the first doping concentration.

4. The SJ device according to claim 1, wherein: The first epi layer has a thickness between 2 micrometers (μm) and 15 μm.

5. The SJ device according to claim 1, wherein: The first epi layer is disposed on a base wide bandgap substrate layer.

6. The SJ device according to claim 1, wherein: The first epi layer is arranged on a third epi layer, and the third epi layer forms a second SJ layer of the SJ device, wherein the active area of ​​the third epi layer includes the first group of SJ pillars and the second group of SJ pillars, the first group of SJ pillars includes the first doping concentration of the first conductivity type, the second group of SJ pillars includes the first doping concentration of the second conductivity type, and wherein the terminal area of ​​the third epi layer includes the minimum epi doping concentration of the first conductivity type.

7. The SJ device according to claim 1, wherein: The intermediate region of the second epi layer includes an intermediate well region of the second conductivity type, the intermediate well region being disposed adjacent to a surface of the second epi layer, and wherein the modified pillars are disposed directly below the intermediate well region and extend through a remainder of the thickness of the second epi layer.

8. The SJ device according to claim 7, wherein: The active region of the second epi layer includes a well region of the second conductivity type, the well region being disposed adjacent to the intermediate well region.

9. The SJ device according to claim 8, wherein: The well region extends vertically from the surface of the second epi layer to contact at least one of the second group of SJ pillars of the second epi layer.

10. The SJ device according to claim 8, wherein The well region, the intermediate well region, and the plurality of floating regions each extend vertically from the surface of the second epi layer to a same depth within the second epi layer.

11. The SJ device according to claim 7, wherein: The middle well region includes a width extending from a first edge of a middle region of the second epi layer adjacent to the active region of the second epi layer to a second edge of the middle region of the second epi layer adjacent to the termination region.

12. The SJ device according to claim 1, wherein: The intermediate regions of the first epi layer and the second epi layer each include a second SJ pillar having the first doping concentration of the second conductivity type and disposed adjacent to the terminal region.

13. The SJ device according to claim 12, wherein: The middle region of the second epi layer includes an intermediate well region of the second conductivity type, the intermediate well region is arranged adjacent to the surface of the second epi layer, and the second SJ column in the middle region of the first epi layer and the second epi layer is vertically aligned with the edge of the intermediate well region adjacent to the terminal region.

14. The SJ device according to claim 1, wherein: The SJ pillars in the middle region of the first epi layer are vertically aligned with the modified pillars in the second epi layer.

15. The SJ device according to claim 1, wherein: The minimum epi doping concentration is less than or equal to 3×10 15 cm -3 And the second doping concentration is greater than 1.05×10 16 cm -3 .

16. A method for manufacturing a super junction SJ device, comprising: The first SJ layer is formed by the following steps: forming a first epitaxial epi layer on the base layer, wherein the first epi layer comprises a minimum epi doping concentration of a first conductivity type; implanting a first set of SJ pillars into an active region of the first epi layer to produce a specific doping concentration of the first conductivity type, wherein the specific doping concentration is greater than the minimum epi doping concentration; as well as implanting an active region of the first epi layer to produce a second set of SJ pillars including the specific doping concentration of a second conductivity type; The device layer is formed by the following steps: forming a second epi layer on the first SJ layer, wherein the second epi layer comprises the minimum epi doping concentration of the first conductivity type; implanting a first set of device layer pillars into an active region of the second epi layer to produce the specific doping concentration of the first conductivity type; as well as implanting a second set of device layer pillars into an active region of the second epi layer to produce the specific doping concentration of the second conductivity type; implanting a middle region of the first epi layer to produce an SJ pillar including the specific doping concentration of the first conductivity type; implanting a middle region of the second epi layer to produce a modified column, the modified column comprising a modified portion at an upper portion of the second epi layer and an unmodified portion at a lower portion of the second epi layer, the modified portion having a second doping concentration of the first conductivity type less than the specific doping concentration, and the unmodified portion having the specific doping concentration of the first conductivity type; as well as A junction termination is formed in the device layer by implanting a plurality of floating regions having the second conductivity type into a termination region of the second epi layer, wherein the width of the floating regions and / or the spacing between the floating regions varies with increasing distance from the active region.

17. The method of claim 16, wherein: The SJ device is a silicon carbide SiC SJ device, and the minimum epi doping concentration is less than or equal to 1.5×10 15 cm -3 .

18. The method of claim 16, wherein: Implanting the first set of SJ pillars into the active area of ​​the first epi layer and implanting the second set of SJ pillars into the active area of ​​the first epi layer comprises: forming a first mask over first and second portions of an active area of ​​the first epi layer, and then patterning the first mask to selectively expose the second portion of the active area of ​​the first epi layer; selectively implanting the first set of SJ pillars into exposed second portions of the active area of ​​the first epi layer; forming a second mask on a second portion of the active area of ​​the first epi layer to expose the first portion of the active area of ​​the first epi layer without exposing the second portion of the active area of ​​the first epi layer; selectively implanting the second set of SJ pillars into exposed first portions of the active area of ​​the first epi layer; and The second mask is removed to produce the first SJ layer.

19. The method of claim 18, wherein: The first mask, the second mask, or a combination thereof includes a high energy implantation mask including silicon on insulator (SOI), polysilicon, thick silicon oxide, a metal layer, a resist layer, or a combination thereof.

20. The method of claim 16, wherein: Implanting the first set of SJ pillars into the active region of the first epi layer or implanting the first set of device layer pillars into the active region of the second epi layer includes implanting at an implant energy greater than or equal to 500 kiloelectronvolts (keV) and less than or equal to 50 megaelectronvolts (MeV).

21. The method of claim 16, wherein: The junction termination comprises a junction termination extension (JTE), wherein the JTE comprises a width that is five times less than a combined thickness of the first epi layer and the second epi layer.

22. The method of claim 16, wherein: Forming the device layer comprises: implanting a well region having the second conductivity type in an active region of the second epi layer so that the well region extends from at least one of the second group of device layer pillars to a surface of the device layer; and A source region having the first conductivity type is implanted adjacent to the well region in the active area of ​​the second epi layer such that the source region extends to the surface of the device layer.

23. A silicon carbide super junction SiC-SJ device, comprising: A first superjunction SJ layer, the first superjunction layer is formed in a first epitaxial epi layer of the SiC-SJ device, wherein a terminal region of the first epi layer comprises a minimum epi doping concentration of a first conductivity type, and wherein the minimum epi doping concentration is less than or equal to 1.5×10 15 cm -3 ; and a device layer formed in a second epi layer of the SiC-SJ device, wherein the second epi layer is disposed on the first SJ layer, and wherein a terminal region of the device layer includes the minimum epi doping concentration of the first conductivity type and a plurality of floating regions of a second conductivity type, the plurality of floating regions forming a junction termination of the SiC-SJ device; wherein the active regions of the first epi layer and the second epi layer include a first group of SJ columns and a second group of SJ columns, the first group of SJ columns including a first doping concentration of the first conductive type, the second group of SJ columns including the first doping concentration of the second conductive type, wherein the middle region of the first epi layer contains SJ columns including the first doping concentration of the first conductive type, and the middle region of the second epi layer contains modified columns, the modified columns include a modified portion at the upper portion of the second epi layer and an unmodified portion at the lower portion of the second epi layer, the modified portion having a second doping concentration of the first conductive type that is less than the first doping concentration, and the unmodified portion having the first doping concentration of the first conductive type, wherein the modified columns are arranged to be closer to the terminal region of the device layer than the first group of SJ columns of the second epi layer, and wherein the minimum epi doping concentration is less than the first doping concentration and the second doping concentration.

24. The SiC-SJ device according to claim 23, wherein: The first doping concentration of the first conductivity type is less than or equal to 1×10 17 cm -3 and greater than or equal to 5×10 15 cm -3 .

25. The SiC-SJ device according to claim 23, wherein: Each of the plurality of floating regions has a respective width, and wherein the respective width of each of the plurality of floating regions is between 0.8 micrometers (μm) and 5 μm.

26. The SiC-SJ device according to claim 23, wherein: The junction termination comprises a junction termination extension, JTE, wherein the JTE comprises a width between 2.75 and 5 times the combined thickness of the first epi layer and the second epi layer.

27. The SiC-SJ device according to claim 26, wherein: The overall charge of the JTE is greater than or equal to 6×10 12 cm -2 and less than or equal to 3×10 13 cm -2 .

28. The SiC-SJ device according to claim 23, wherein: The SiC-SJ device includes a metal oxide semiconductor field effect transistor (MOSFET), a junction field effect transistor (JFET), a bipolar junction transistor (BJT) or a diode.

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