A scanning test switching network and scanning test method
By designing a scanning test switching network based on multi-level Internet networks, the problem of limited number of external ports and lack of flexibility in the prior art is solved, and free gated of external ports and scan test channels is realized, which meets the changes in later testing requirements and reduces design costs.
Patent Information
- Application Number
- CN202111067489.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2021-09-13
- Publication Date
- 2025-04-04
- Estimated Expiration
- 2041-09-13
AI Technical Summary
In the existing scanning and testing technology, the number of external ports is limited, which requires pre-dividing the test mode and port allocation in the early stage, which lacks flexibility and cannot meet the changes in later stage testing requirements.
A scanning test switching network based on multi-level Internet network is designed, and free gates of external ports and scan test channels are realized through configuration units and switching units, allowing dynamic division of test modes and port allocations according to test needs in the later stage.
It realizes the flexibility and adaptability of the scan test switch network, and can arbitrarily specify I/O ports and scan test channels in the later stage, meeting different test needs and reducing design costs.
Smart Images
Figure CN113655376B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor digital integrated circuit design and testing, and in particular to a scan test switching network and a scan test method. Background Art
[0002] With the rapid development of large-scale digital chips, design for testability (DFT) is becoming more and more important in the design and testing of large-scale digital chips. With the continuous growth of chip scale, in the scan test (SCAN), the number of scan test channels is increasing, and the number of external ports required is also increasing. Since the number of external ports is limited, the number of ports required for each test module cannot exceed the number of available external ports. Therefore, it is necessary to divide it into multiple tests, each time testing different modules. In order to solve the problem of the limited number of external ports, the commonly used method is to use a multiplexer (MUX) for port multiplexing. In each test mode, a fixed corresponding relationship is established between the mapping of the module scan test channel and the external port. However, the above MUX multiplexing method lacks flexibility. If the early design is unreasonable and there is a lack of corresponding test modes, when some modules need to be tested in the later stage, they cannot be tested. Or if the port division is unreasonable, it needs to be re-divided and the design structure needs to be re-modified, which will seriously affect the progress of design testing. Summary of the invention
[0003] In view of this, the present invention provides a scan test switching network and a corresponding scan test method, which does not require pre-division in the early stage, but can be directly divided according to test requirements in the later stage, while ensuring free selection of external ports and scan test channels.
[0004] In a first aspect, the present invention provides a scan test switching network, comprising:
[0005] An I / O input unit, used for providing input data, wherein the input data is used for testing a scan test channel of a module to be tested;
[0006] a configuration unit for controlling the port input / output state of the I / O input unit and generating a configuration signal for scanning the switching network; and
[0007] A scan switching network, composed of a plurality of switching units, for determining a mapping switching path of the input data between the plurality of switching units according to the configuration signal, so as to gate the I / O input unit with a scan test channel of a module to be tested;
[0008] The I / O output unit is used to receive the test result data of the scan test channel.
[0009] Preferably, the multiple switching units form a multi-level interconnection network according to a predefined topological relationship.
[0010] Preferably, the configuration unit is connected to a plurality of switching units in the scanning switching network, and the plurality of switching units receive the configuration signal to determine a mapping switching path of the input data between the plurality of switching units.
[0011] Preferably, the multi-stage interconnection network is a non-blocking switching network.
[0012] Preferably, the scan switching network is arranged between the I / O output unit and the scan output channel of the module to be tested.
[0013] Preferably, the scanning switching network includes a first scanning switching network and a second scanning switching network;
[0014] The first scan switching network is used to select the scan input channel of the I / O input unit and the module to be tested;
[0015] The second scan switching network is used to select the scan output channel of the module to be tested and the I / O output unit.
[0016] Another aspect of the present invention provides a scan test method for a scan test switching network based on the above aspects, comprising:
[0017] Determining a configuration signal of the scanning switching network according to the module to be tested;
[0018] Inputting the determined configuration signal into the scan switching network to generate a gating path of the scan test channel, wherein the gating path is composed of a combination of mapping switching paths;
[0019] According to the generated strobe path, the module to be tested is scanned and tested through the I / O input unit.
[0020] Preferably, after the strobe path of the scan test channel is generated, an input / output state control signal is provided to the I / O input unit through the configuration unit.
[0021] Preferably, before determining the configuration signal of the scan switching network, the method further comprises: specifying an I / O input port of the I / O input unit and a scan input channel of the module to be tested.
[0022] Preferably, scanning and testing the module to be tested through the I / O input unit further includes: sending the input data from the external I / O port of the I / O input unit to the scan test channel that needs to be tested through the corresponding mapping switching paths of multiple switching units.
[0023] It can be seen that the freely selectable scan test switching network and scan test method of the present invention can arbitrarily specify I / O ports and scan test channels in the later stage, and routing selection can be realized through configuration, which is convenient and flexible and can meet different test requirements. At the same time, the relationship between the test mode and the pin allocation does not need to be determined in the early stage of design, thereby reducing the design cost. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0025] Figure 1 FIG. 1 is a schematic diagram of the structure of a scan test switching network according to the present invention.
[0026] Figure 2 FIG. 1 is a schematic diagram of the internal structure of the scan exchange unit according to the present invention.
[0027] Figure 3 FIG. 1 is a schematic diagram of the structure of an extended scan test switching network according to the present invention.
[0028] Figure 4 According to the present invention, Figure 1 A flow chart of a method for performing a scan test on a switching network structure.
[0029] Figure 5 According to the present invention, Figure 3 A flow chart of a method for performing a scan test on a switching network structure. DETAILED DESCRIPTION
[0030] In order to better understand the above technical solution, the above technical solution will be described in detail below in conjunction with the accompanying drawings and specific implementation methods.
[0031] It should be clear that the described embodiments are only some embodiments of the present invention, rather than all embodiments. In order to more clearly illustrate the present invention, many technical details are described in the following specific embodiments. Those skilled in the art should understand that the present invention can also be implemented without some of the details. In addition, in order to highlight the main purpose of the present invention, some methods, means, components and their applications well known to those skilled in the art are not described in detail, but this does not affect the implementation of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work belong to the scope of protection of the present invention.
[0032] The inventors have found in long-term research that the scan test switching network can draw on the networking ideas of the multistage interconnection network (MIN) in the communication field. The multistage interconnection network is composed of a large number of basic switching units interconnected according to a specific topological structure. By establishing channels in the switching network, cell exchange can be realized. A variety of multistage interconnection networks can realize free gating from the input end to the output end, and can change the state of node switches at each level in real time according to the requirements of full channel sorting through specific path-finding routing algorithms. In view of this, by freely gating the external port and the test channel, specifying the external I / O port and the scan test channel (scan_channel) to be tested, the corresponding mapping switching path can also be obtained, which can also meet the needs of the scan test switching network without the need for preliminary mode division. Based on this, the present invention proposes a hardware-implementable scan test switching network based on a multistage interconnection network structure.
[0033] The scan test switching network proposed by the present invention constructs a scan test switching network based on a multi-level interconnection network by constructing a scan switching unit, and obtains configuration data of the scan test switching network through a network routing algorithm according to the positions of the external I / O port and the scan channel to be tested in the scan test switching network. When performing a scan test, the free routing gating of the test mode can be realized by configuring the scan test switching network accordingly.
[0034] Embodiment 1
[0035] The scan test switching network structure provided by the present invention for free gating of scan test input channels is as follows: Figure 1 As shown, it includes an I / O unit, a configuration unit (CONFIG), and a scan switching network (MAPPING). The I / O unit further includes an I / O input unit and an I / O output unit. The output end of the I / O input unit is connected to the scan switching network through a data bus, and the output end of the configuration unit is connected to the scan switching network. The I / O output unit is used to receive the test result data of the scan test channel.
[0036] The output end of the scan switching network is connected to a plurality of scan input channel modules module_1 to module_n to be tested (hereinafter referred to as modules to be tested). The scan input channel modules to be tested may be functional modules of a chip.
[0037] The I / O input unit is used to provide input data (channel_in[n-1:0]) of the scan test channel, and the input data is used to test the scan test channel in the scan input channel module to be tested. Specifically, the input data can be input from the outside by the user or the host computer, and can be used to specify one or more modules module_1 to module_n that need to be tested. When the user needs to test module_x, that is, the xth channel channel_x, the following command can be used as input data:
[0038] CHANNELTEST x testdata.
[0039] testdata may be actual test data for scanning the test channel. It should be understood by those skilled in the art that the above commands are only for illustrative purposes and are not intended to limit the command format of the present invention.
[0040] To explain the principle of the present invention, Figure 1 Each module to be tested shown corresponds to one scan test channel. Those skilled in the art should understand that each module to be tested may correspond to multiple scan test channels.
[0041] The configuration unit (CONFIG) is used to control the input / output state of the I / O port of the I / O unit, and generate a configuration signal (swap[m:0]) for the scan switching network, where m is the number of configuration signals. The scan switching network determines the mapping switching path of the input data between the multiple switching units according to the configuration signal to select the scan test channel of the I / O input unit and the module to be tested. In other words, the scan switching network uses the configuration signal to determine how the data signal is mapped step by step in the switching network, that is, to determine the final data path. Specifically, Figure 1 As shown, the configuration unit is connected to a plurality of switching units, so that the plurality of switching units can receive the configuration signal.
[0042] The scanning switching network (MAPPING) is a non-blocking, freely selectable multi-level interconnection network MIN composed of multiple switching units according to a certain topological relationship. Figure 1 The multi-stage interconnected network shown in the example is a benes network.
[0043] The internal structure of each switching unit is as follows Figure 2 As shown. The configuration signal is swap, the input is i_0, i_1, and the output is o_0, o_1. The configuration signal can control whether the switching unit is in parallel connection or cross connection. The connection relationship between different switching units is controlled by the connection function. According to the connection function, the structural form of the entire scanning switching network, that is, the topological relationship, can be determined.
[0044] See again Figure 1 , N / 2 2×2 switching units are set on both sides of the benes network, and two N / 2×N / 2 benes sub-networks are set in the middle. Each switching unit is connected to each sub-network by a link; the intermediate sub-network is further decomposed according to the above method until the intermediate sub-network is decomposed into 2×2 switching units. N is a parameter representing the scale of the benes network. There are 2n-1 different paths between any pair of input and output ends, which can avoid the occurrence of blocking.
[0045] Through the scan switching network, the I / O input unit can be connected to the scan test channel (channel_mapping_in) of the module to be tested, and multiple scan input channel modules module_1 to module_n are connected through channel_mapping_in, where n represents the total number of scan input channel modules to be tested. Since the scan switching network is a benes network, it can be freely selected. When any I / O port and scan input channel are specified, there is at least one selection path. In this way, different modules to be tested can be tested jointly as needed.
[0046] Embodiment 2
[0047] In an extended embodiment, the scan test channel of the module to be tested includes a scan input channel (channel_mapping_in) and a scan output channel (channel_mapping_out). In addition to setting a switching network between the I / O port and the scan input channel, the above-mentioned scan test switching network also sets a switching network between the scan output channel and the I / O port. In addition, the number of scan switching networks can be one or more. When the number of scan channels is large and the number of I / O ports is insufficient, multiple scan switching networks can also be set. Figure 3 The scanning switching network MAPPING corresponding to the scanning input channel and the scanning output channel is a schematic diagram of a free non-blocking multi-stage interconnection network. Figure 1 Based on the scan output channel and the I / O port switching network is added. Figure 1 The same components will not be described again.
[0048] See also Figure 3, multiple scan switching networks MAPPING can be set in the scan test switching network, which can be divided into a first scan switching network MAPPING_IN* and a second scan switching network MAPPING_OUT* according to their functions. The first scan switching network MAPPING_IN* connects the I / O input unit with the scan input channel, and the second scan switching network MAPPING_OUT* connects the scan output channel with the I / O output unit. The scan input channel modules of module_1~module_i are connected to the I / O input unit through MIN_1 in the first scan switching network MAPPING_IN*, and the scan output channel is connected to the I / O output unit through MIN_2 in the second scan switching network MAPPING_OUT*. In one embodiment, the first scan switching network MAPPING_IN* and the second scan switching network MAPPING_OUT* are both benes networks constructed by the aforementioned scheme. Since there are many scan test channels, the same network is constructed in the scan input channel modules of module_j~module_t, that is, its scan input channel is connected to the I / O input unit through MIN_3 in the first scan switching network MAPPING_IN*, and its scan output channel is connected to the I / O output unit through MIN_4 in the second scan switching network MAPPING_OUT*. In this way, the structural complexity of a single interconnection network can be reduced, making the network construction process more flexible.
[0049] When the number of scan switching networks is more than one, the configuration unit (CONFIG) not only has the function of configuring the scan switching network, but also has the function of selecting and outputting the test result data from the multiple scan switching networks. Specifically, the configuration unit (CONFIG) outputs a selection signal sel to the multiplexer MUX, outputs the test result of the module to be tested to the MUX through channel_map_out, and selects and outputs it to the designated external output I / O port in a multiplexing manner.
[0050] Embodiment 3
[0051] According to another aspect of the present invention, based on Figure 1 The freely selectable scan test switching network structure shown in FIG. 1 is a first exemplary scan test method provided by the present invention. Figure 4 The specific process includes:
[0052] Step S101: determining a configuration signal for scanning a switching network according to a module to be tested (module to be tested).
[0053] The user can divide the test mode according to the needs. When it is determined that one or more specific modules need to be tested, the input I / O port and the scan input channel of the module to be tested are first specified, and the configuration parameters required for the switching network are calculated according to the connection function used to construct the scanning switching network, that is, the input / output of each switching unit of the given switching network is calculated. Preferably, the scanning switching network can be a benes multi-stage interconnection network or other types of non-blocking, freely selectable multi-stage interconnection networks. The configuration parameters are stored in the configuration unit (CONFIG).
[0054] Step S102: input the determined configuration signal into the scan switching network to generate a gating path of the scan test channel, wherein the gating path is composed of a combination of mapping switching paths.
[0055] At the beginning of the scan test, the corresponding configuration signal is input into the scan switching network through the configuration signal port (swap[m:0]) of the configuration unit (CONFIG) to realize routing gating. Since the scan switching network is a non-blocking, freely gating multi-level interconnected network, it can ensure that the gating path of any pair of I / O ports and scan input channels can be controlled and generated according to the configuration signal. Since the scan switching network includes multiple switching units, the gating path from the I / O input port to the scan input channel can be obtained by combining the mapping switching paths between the switching units. In addition, after generating the gating path of the scan test channel, the configuration unit provides a control signal to the I / O input unit for controlling the input / output state of the I / O input unit.
[0056] Step S103 : Scanning and testing the module to be tested through the I / O input unit according to the generated selection path.
[0057] Since the scan switching network has realized the free selection of the external I / O port and the test channel of the I / O input unit, the input data for testing can be sent from the external I / O port to the scan test channel scan_channel that needs to be tested through the corresponding mapping switching path, thereby realizing the scan test of the module to be tested.
[0058] Embodiment 4
[0059] According to another aspect of the present invention, based on Figure 3 The freely selectable scan test switching network structure shown in FIG. 1 is used. The present invention provides the following exemplary second scan test method, see Figure 5 The specific process includes:
[0060] Step S201: determining configuration signals of a first scanning switching network and a second scanning switching network according to a module to be tested (ie, a module to be tested).
[0061] When it is determined that one or more specific modules need to be tested, the input I / O port, the scan input channel of the module to be tested, the scan output channel of the module to be tested, and the output I / O port are first specified, and the configuration parameters required for the first and second scan switching networks are calculated according to the connection function used to construct the scan switching network, that is, the input / output of each switching unit of the given switching network is calculated. Among them, the first scan switching network is the scan switching network between the input I / O port and the scan input channel of the module to be tested, and the second scan switching network is the scan switching network between the scan output channel of the module to be tested and the output I / O port. The scan switching network can be a benes multi-level interconnection network. The configuration parameters are stored in the configuration unit (CONFIG).
[0062] Step S202, inputting the determined configuration signal into the first scan switching network and the second scan switching network to generate a first gating path of the scan input channel and a second gating path of the scan output channel, wherein the gating paths are composed of mapping switching paths.
[0063] At the beginning of the scan test, the corresponding configuration signal is independently input into the first and second scan switching networks through the configuration signal port (swap) of the configuration unit (CONFIG) to realize routing gating. Since the scan switching network is a non-blocking, freely gating multi-stage interconnected network, it can ensure that the gating path of any pair of input I / O ports and scan input channels, and the gating path of any pair of scan output channels and output I / O ports are generated according to the configuration signal. Since the first and second scan switching networks respectively include a plurality of switching units, by combining the mapping switching paths between the switching units in the first and second scan switching networks, the gating path from the I / O input port to the scan input channel and the gating path from the scan output channel to the I / O output port can be obtained. In addition, after generating the gating path of the scan test channel, the configuration unit provides control signals to the I / O input unit and the I / O output unit for controlling the input / output states of the I / O input unit and the I / O output unit.
[0064] Step S203, according to the generated first selection path and second selection path, the module to be tested is scanned and tested through the input I / O port (I / O input unit), and the test result data of the module to be tested is output through the output I / O port (I / O output unit).
[0065] Since the first and second scan switching networks have realized the free selection of external input and output I / O ports and test channels, the test instructions can be sent from the designated external input I / O port to the scan test channel scan_channel to be tested through the corresponding mapping switching path, and the input data channel_in for testing is input into the module to be tested to realize the scan test of the module to be tested, and the test result data of the module to be tested is output to the multiplexer MUX through one of the channel_map_outs, and is selected and output to the designated external output I / O port in a multiplexing manner.
[0066] Although the above multi-stage interconnection network is described as a benes network, in actual implementation, the benes network can be replaced by other non-blocking and freely selectable multi-stage interconnection networks, such as BATCHER-BANYAN network, extended BANYAN network, etc., according to the chip size and requirements. As long as non-blocking free selection can be achieved, it can be applied to the multi-stage interconnection network of the present invention.
[0067] In addition, those skilled in the art should understand that the present invention includes but is not limited to the structure shown in the above figure. When the number of scan test channels is too large, more scan switching networks can be built. On the premise that various Internet networks can realize non-blocking free selection functions by hardware, different types of multi-level Internet networks can also be used in combination.
[0068] Meanwhile, the structure of the switching unit also includes but is not limited to the above structure, as long as it can constitute a unit suitable for the above scanning switching network. The switching unit can also be optimized according to actual needs.
[0069] It can be seen that the above technical solution of the present invention provides a scan test switching network that can be freely selected. Compared with the traditional scan test structure, after arbitrarily specifying the I / O port and the scan test channel, the routing selection can be realized by configuration, which is convenient and flexible and can meet different test requirements. At the same time, since there is no need to determine the test mode and pin allocation relationship at the initial stage of design, the design cost can be significantly reduced.
[0070] The above describes multiple implementation schemes provided by the embodiments of the present invention. The various optional methods introduced in the implementation schemes can be combined and cross-referenced with each other without conflict, thereby extending a variety of possible implementation schemes, which can all be considered as implementation schemes disclosed and open in the embodiments of the present invention.
[0071] Although the embodiments of the present invention are disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.
Claims
1. A scan test switching network, characterized in that: include: An I / O input unit, used for providing input data, wherein the input data is used for testing a scan test channel of a module to be tested; A configuration unit, used to control the port input / output state of the I / O input unit and generate a configuration signal for scanning the switching network; as well as A scan switching network, composed of a plurality of switching units, for determining a mapping switching path of the input data between the plurality of switching units according to the configuration signal, so as to gate the I / O input unit with a scan test channel of a module to be tested; The connection relationship of the multiple switching units is controlled by a connection function; the scanning switching network is a benes multi-level interconnected network, with multiple switching units arranged on both sides, two benes sub-networks in the middle, and each switching unit is connected to each benes sub-network by a link; The I / O output unit is used to receive the test result data of the scan test channel.
2. The scan test switching network according to claim 1, characterized in that: The configuration unit is connected to a plurality of switching units in the scanning switching network, and the plurality of switching units receive the configuration signal to determine a mapping switching path of the input data between the plurality of switching units.
3. The scan test switching network according to claim 2, characterized in that: The multi-stage internetwork is a non-blocking switching network.
4. The scan test switching network according to claim 1, characterized in that: The scan switching network is arranged between the I / O output unit and the scan output channel of the module to be tested.
5. The scan test switching network according to claim 1, characterized in that: The scanning switching network includes a first scanning switching network and a second scanning switching network; The first scan switching network is used to select the scan input channel of the I / O input unit and the module to be tested; The second scan switching network is used to select the scan output channel of the module to be tested and the I / O output unit.
6. A scan test method for a scan test switching network based on any one of claims 1 to 5, characterized in that: include: Determining a configuration signal of the scanning switching network according to the module to be tested; Inputting the determined configuration signal into the scan switching network to generate a gating path of the scan test channel, wherein the gating path is composed of a combination of mapping switching paths; According to the generated strobe path, the module to be tested is scanned and tested through the I / O input unit.
7. The scanning test method according to claim 6, characterized in that: After the strobe path of the scan test channel is generated, an input / output state control signal is provided to the I / O input unit through the configuration unit.
8. The scanning test method according to claim 6, characterized in that: Before determining the configuration signal of the scan switching network, the method further includes: specifying an I / O input port of the I / O input unit and a scan input channel of the module to be tested.
9. The scanning test method according to claim 6, characterized in that: The scanning and testing of the module to be tested through the I / O input unit further includes: sending the input data from the external I / O port of the I / O input unit to the scan test channel that needs to be tested through the corresponding mapping switching paths of multiple switching units.
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