Silicon-based solar cell unit and its manufacturing method

Abstract

Embodiments of this disclosure provide a silicon-based solar cell unit and a method for manufacturing the same. The silicon-based solar cell unit includes: a first-type silicon substrate having a first surface and a second surface opposite to the first surface; a plurality of first doped portions, separated from each other and doped with first-type dopant particles, located on the first surface of the silicon substrate; a plurality of first doped source portions, each disposed on a surface of the plurality of first doped portions facing away from the silicon substrate and doped with first-type dopant particles; and a first passivation layer covering the first surface of the silicon substrate and the surfaces of the plurality of first doped source portions facing away from the silicon substrate. By omitting the step of removing the first doped source portions, the manufacturing process of the cell unit is simplified, and the manufacturing cost is reduced.

Description

Technical Field

[0001] Embodiments of this disclosure relate to silicon-based solar cell units and methods for manufacturing the same. Background Technology

[0002] Human survival and development are inseparable from energy. Solar energy is one of the most renewable, abundant, and clean energy sources. Silicon-based solar cells are a type of semiconductor device that directly converts light energy into electrical energy. PERC (Passivated Emitter and Rear Cell) structures have become the mainstream direction in the development of silicon-based solar cell technology due to their high photoelectric conversion efficiency. Compared to conventional aluminum back-field cell structures, PERC cell structures also have a back passivation layer, thereby reducing minority carrier recombination. For example, a silicon-based solar cell with a PERC structure has been proposed, which places the pn junction on the back of the cell, thus greatly reducing the absorption of light by the amorphous silicon thin film and effectively improving the photoelectric conversion efficiency. However, the manufacturing process of such silicon-based solar cells is complex and costly. There is a desire to further improve the photoelectric conversion efficiency of cells and to have simplified manufacturing processes and lower costs for silicon-based solar cell units. Summary of the Invention

[0003] Embodiments of this disclosure provide a silicon-based solar cell unit, comprising: a first-type silicon substrate having a first surface and a second surface opposite to the first surface; a plurality of first doped portions in the first surface of the silicon substrate, the plurality of first doped portions being separated from each other and doped with first-type doped particles; a plurality of first doped source portions, the plurality of first doped portions being respectively disposed on the surfaces of the plurality of first doped portions facing away from the silicon substrate and doped with first-type doped particles; and a first passivation layer covering the first surface of the silicon substrate and the surfaces of the plurality of first doped source portions facing away from the silicon substrate.

[0004] By directly passivating the undoped regions of the silicon substrate, minority carrier recombination on the first surface can be significantly reduced compared to a fully doped surface. Since the cell uses localized doping on its first surface, the first doping source portion used to form the first doped portion only locally covers the silicon substrate at the location of the first contact electrode, without significantly obstructing the silicon substrate and thus reducing the cell's light conversion efficiency. Therefore, the first doping source portion is retained between the first contact electrode and the first doped portion in the silicon substrate. During cell fabrication, the first doping source portion can be used as a doping source to dope the silicon substrate to form the first doped portion, but it is not necessary to remove this first doping source portion. By omitting the step of removing the first doping source portion, the cell manufacturing process is simplified, and manufacturing costs are reduced.

[0005] For example, in some embodiments, the plurality of first doped portions are formed by activating first-type doped particles in the plurality of first doped source portions to dope the first-type doped particles into the first surface of the silicon substrate.

[0006] For example, in some embodiments, the battery cell further includes a plurality of first contact electrodes that penetrate the first passivation layer and make ohmic contact with the first doped source portion.

[0007] For example, in some embodiments, the projection of the first contact electrode onto the silicon substrate along the thickness direction of the silicon substrate falls within the projection of the first doped source portion onto the silicon substrate along the thickness direction of the silicon substrate.

[0008] For example, in some embodiments, the silicon substrate and the first doped portion are monocrystalline silicon or polycrystalline silicon. The first doped source portion includes one or more of microcrystalline silicon, amorphous silicon, or polycrystalline silicon.

[0009] For example, in some embodiments, the first passivation layer includes one or more single layers or stacks of silicon oxide, aluminum oxide, gallium oxide, titanium oxide, silicon oxynitride, aluminum oxynitride, silicon, and silicon carbide.

[0010] For example, in some embodiments, the battery cell further includes: a passivation dielectric layer on a second surface of the silicon substrate; a selective carrier transport layer on the surface of the passivation dielectric layer opposite to the silicon substrate, the selective carrier transport layer being doped with type II doped particles; and a second passivation layer on the surface of the selective carrier transport layer opposite to the silicon substrate.

[0011] For example, in some embodiments, the battery cell further includes a plurality of second contact electrodes that penetrate the second passivation layer and make ohmic contact with the selective carrier transport layer.

[0012] For example, in some embodiments, the first type is n-type and the second type is p-type.

[0013] For example, in some embodiments, the first type is p-type and the second type is n-type.

[0014] For example, in some embodiments, the selective carrier transport layer comprises one or more of microcrystalline silicon, amorphous silicon, and polycrystalline silicon.

[0015] For example, in some embodiments, the second passivation layer includes one or more single layers or stacks of silicon oxide, aluminum oxide, gallium oxide, titanium oxide, silicon oxynitride, aluminum oxynitride, silicon, and silicon carbide.

[0016] For example, in some embodiments, the passivation dielectric layer comprises one or more single layers or stacks of non-metallic oxide layers and metal oxide layers.

[0017] For example, in some embodiments, the passivation dielectric layer includes one or more single layers or stacks of silicon oxide, aluminum oxide, gallium oxide, titanium oxide, silicon oxynitride, aluminum oxynitride, and silicon nitride.

[0018] For example, in some embodiments, the thickness of the passivation dielectric layer is in the range of 0.1 nm to 10.0 nm.

[0019] Embodiments of this disclosure provide a method for manufacturing a battery cell, comprising: providing a first type of silicon substrate, the silicon substrate including a first surface and a second surface opposite to the first surface; forming a plurality of first doped source portions on the first surface of the silicon substrate, the plurality of first doped source portions being separated from each other and doped with first type doped particles; activating the first type doped particles in the plurality of first doped source portions by a high-temperature annealing process to form a plurality of first doped portions in the first surface of the silicon substrate respectively; and forming a first passivation layer, the first passivation layer covering the first surface of the silicon substrate and the surfaces of the plurality of first doped source portions facing away from the silicon substrate.

[0020] For example, in some embodiments, the manufacturing method further includes: forming a plurality of first contact electrodes such that the plurality of first contact electrodes penetrate the first passivation layer and make ohmic contact with the plurality of first doped source portions.

[0021] For example, in some embodiments, the manufacturing method further includes: forming a passivation dielectric layer on a second surface of the silicon substrate; forming a selective carrier transport layer on the surface of the passivation dielectric layer opposite to the silicon substrate, the selective carrier transport layer being doped with type II doped particles; forming a second passivation layer on the surface of the selective carrier transport layer opposite to the silicon substrate; and forming a plurality of second contact electrodes that penetrate the second passivation layer and make ohmic contact with the selective carrier transport layer. Attached Figure Description

[0022] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of this disclosure and should not be regarded as a limitation on the scope of protection. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1This is a cross-sectional schematic diagram of a battery cell according to the first embodiment of the present disclosure;

[0024] Figure 2 This is a schematic flowchart of a method for manufacturing a battery cell according to the first embodiment of the present disclosure;

[0025] Figure 3A-3G These are schematic diagrams showing the different steps of the battery cell manufacturing method according to the first embodiment of this disclosure.

[0026] Figure 4 This is a schematic flowchart of a method for manufacturing a battery cell according to a second embodiment of the present disclosure;

[0027] Figure 5 This is a schematic diagram of the structure after forming a plurality of first doped source portions on a first surface of a silicon substrate, and forming a passivation dielectric layer, a first selective carrier transport front layer and a second selective carrier transport front layer on a second surface of a silicon substrate, according to the second embodiment of the present disclosure.

[0028] Figure 6 This is a schematic flowchart of a method for manufacturing a battery cell according to a third embodiment of the present disclosure;

[0029] Figure 7 This is a schematic diagram of the structure after forming a plurality of first doped source portions and a plurality of pre-doped portions on a first surface of a silicon substrate, and forming a passivation dielectric layer and a first selective carrier transport front layer on a second surface of the silicon substrate, according to the third embodiment of the present disclosure.

[0030] Figure 8 This is a schematic flowchart of a method for manufacturing a battery cell according to the fifth embodiment of the present disclosure. Detailed Implementation

[0031] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0032] It should be noted that, unless otherwise defined, the technical or scientific terms used in this disclosure should have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms "first," "second," and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects.

[0033] In this document, the front and light-receiving surfaces of the battery cell shown as the upper side of the battery cell in the accompanying drawings are interchangeable, as are the back or backlighting surfaces of the battery cell shown as the lower side of the battery cell in the accompanying drawings. In this document, "intrinsic" refers to a battery cell that is not doped with any doped particles.

[0034] The silicon substrate in a silicon-based solar cell unit is typically plate-shaped or sheet-shaped, extending substantially in a plane and having a certain thickness. For ease of and clarity in describing the cell unit according to this disclosure, the direction perpendicular to the plane in which the silicon substrate of the cell extends is defined as the "thickness direction" of the silicon substrate.

[0035] Overview

[0036] Embodiments of this disclosure provide a silicon-based solar cell unit, comprising: a first-type silicon substrate having a first surface and a second surface opposite to the first surface; a plurality of first doped portions in the first surface of the silicon substrate, the plurality of first doped portions being separated from each other and doped with first-type doped particles; a plurality of first doped source portions, the plurality of first doped portions being respectively disposed on the surfaces of the plurality of first doped portions facing away from the silicon substrate and doped with first-type doped particles; and a first passivation layer covering the first surface of the silicon substrate and the surfaces of the plurality of first doped source portions facing away from the silicon substrate.

[0037] By locally passivating the undoped regions of the silicon substrate, minority carrier recombination on the first surface can be significantly reduced compared to a fully doped surface. Since the cell uses localized doping on its first surface, the first doping source portion used to form the first doped portion only partially covers the silicon substrate at the location of the first contact electrode, without significantly obstructing the silicon substrate and thus reducing the cell's light conversion efficiency. Therefore, the first doping source portion is retained between the first contact electrode and the first doped portion in the silicon substrate. During cell fabrication, the first doping source portion can be used as a doping source to dope the silicon substrate to form the first doped portion, but it is not necessary to remove this first doping source portion. By omitting the step of removing the first doping source portion, the cell manufacturing process is simplified, and manufacturing costs are reduced.

[0038] Embodiments of this disclosure provide a method for manufacturing a battery cell, which can be used, for example, to manufacture the battery cell described above. The method includes: providing a first-type substrate, the substrate including a first surface and a second surface opposite to the first surface; forming a plurality of first doped source portions on the first surface of the substrate, the plurality of first doped source portions being separated from each other and doped with first-type doped particles; activating the first-type doped particles in the plurality of first doped source portions by a high-temperature annealing process to form a plurality of first doped portions respectively in the first surface of the substrate; and forming a first passivation layer covering the first surface of the silicon substrate and the surfaces of the plurality of first doped source portions facing away from the silicon substrate.

[0039] In this manufacturing method, multiple first doped portions are locally formed using multiple first doped source portions that are separated from each other. After forming the first doped portions, a first passivation layer is formed on a first surface of a silicon substrate while retaining the first doped source portions, without removing the first doped source portions. Because the step of removing the first doped source portions is omitted, the manufacturing process of the battery cell is simplified, and the manufacturing cost is reduced.

[0040] The foregoing and other aspects of this disclosure will be illustrated below by way of example.

[0041] It should be noted that the steps in the method described herein do not necessarily have to be performed in the order described. They may be performed in other orders, at least one step may be omitted, or at least one additional step may be added. This disclosure is not limited thereto. Without departing from the scope of the claims of this disclosure, those skilled in the art can combine or modify the steps, features, processes, and parameters of the embodiments given herein to obtain other embodiments.

[0042] First Embodiment

[0043] Figure 1 This is a cross-sectional schematic diagram of a battery cell according to a first embodiment of the present disclosure. Figure 2 This is a schematic flowchart of a method for manufacturing a battery cell according to the first embodiment. Figure 3A-3G These are schematic diagrams showing the different steps of the battery cell manufacturing method according to the first embodiment of this disclosure.

[0044] like Figure 1As shown, the battery cell includes a first-type silicon substrate 111, a first doped layer including multiple first doped portions 116, a first doped source layer including multiple first doped source portions 1151, multiple first contact electrodes 1191, a first passivation layer 117, a passivation dielectric layer 112, a selective carrier transport layer 113, multiple second contact electrodes 1192, and a second passivation layer 118. The multiple first doped portions 116 are formed separately on a first surface of the silicon substrate 111 and are doped with first-type doped particles. The multiple first doped source portions 1151 are respectively formed on the surface of each of the multiple first doped portions 116 facing away from the silicon substrate 111 and are doped with first-type doped particles. The first passivation layer 117 is formed on the first surface of the silicon substrate 111 and the surface of the first doped source portions 1151 facing away from the silicon substrate 111. The multiple first contact electrodes 1191 penetrate the first passivation layer 117 and make ohmic contact with the multiple first doped source portions 1151 of the first doped source layer. The projection of the first contact electrode 1191 onto the silicon substrate 111 along its thickness direction falls within the projection of the first doped source portion 1151 onto the silicon substrate 111 along its thickness direction. The passivation dielectric layer 112 is formed on the second surface of the silicon substrate 111. The selective carrier transport layer 113 is formed on the surface of the passivation dielectric layer 112 facing away from the silicon substrate and is doped with type II doped particles. The second passivation layer 118 is formed on the surface of the selective carrier transport layer 113 facing away from the silicon substrate 111. The plurality of second contact electrodes 1192 penetrate the second passivation layer 118 and make ohmic contact with the selective carrier transport layer 113. The first surface of the silicon substrate 111 can face the front of the battery cell, and the second surface of the silicon substrate 111 can face the back of the battery cell.

[0045] The passivation dielectric layer 112 and the selective carrier transport layer 113 form a passivated contact structure. Because the selective carrier transport layer 113 and the silicon substrate 111 have different types of doped particles, the emitter is formed on the back side of the battery cell. This passivation structure reduces metal-to-metal recombination. The selective carrier transport layer 113 can selectively transport carriers, helping to reduce back-side recombination and achieve high on-voltage performance.

[0046] Furthermore, on the front side of the battery cell, the first surface of the silicon substrate 111 is locally doped, which significantly reduces surface recombination on the front side of the battery cell compared to full-surface doping. Thus, through the combined use of the front and back passivation structures of the battery cell, minority carrier recombination on both the front and back sides is effectively reduced, resulting in better passivation and a higher open-circuit voltage.

[0047] Furthermore, since the battery cell employs localized doping on the first surface of the silicon substrate 111, the first doped source layer, including multiple first doped source portions 1151, only partially covers the silicon substrate 111, thus avoiding significant obstruction of the silicon substrate 111 and preventing a decrease in the light conversion efficiency of the battery cell. Therefore, the first doped source portion 1151 between the first contact electrode 1191 and the first doped portion 116 in the silicon substrate 111 is retained. During the fabrication of the battery cell, the first doped source portion 1151 can be used as a doping source to dope the silicon substrate 111 to form the first doped portion 116, but it is not necessary to remove the first doped source portion 1151. By omitting the step of removing the first doped source portion 1151, the manufacturing process of the battery cell is simplified, and the manufacturing cost is reduced.

[0048] The first type can be p-type, and the second type can be n-type. Alternatively, the first type can be n-type, and the second type can be p-type. When the silicon substrate 111 is a p-type silicon substrate 111, the cost of the silicon substrate 111 is reduced, thereby reducing the cost of the battery cell. When the silicon substrate 111 is an n-type silicon substrate 111, the substrate life of the silicon substrate 111 of the battery cell is high. Therefore, the lifespan of the battery cell is improved.

[0049] When the first type is p-type and the second type is n-type, the dopant particles of the first type can be group III element particles such as boron (B), and the dopant particles of the second type can be group V element particles such as phosphorus (P).

[0050] The silicon substrate 111 can be monocrystalline silicon or polycrystalline silicon. For example, the resistivity of the silicon substrate 111 is in the range of 0.1-20 Ω·cm, such as 0.1 Ω·cm, 1 Ω·cm, 5 Ω·cm, 10 Ω·cm, or 15 Ω·cm or 20 Ω·cm, etc., and its thickness is in the range of 50-300 nm, such as 80-300 nm, 50-100 nm, 50-80 nm, 100-300 nm, 100-200 nm, 100-150 nm, and 120-150 nm, etc.

[0051] The second surface of the silicon substrate 111 can be a flat or rough surface, such as a polished surface, a wet-etched surface, or a textured surface.

[0052] The first doped portion 116 of the first doped layer is formed by doping the silicon substrate 111 with first-type doped particles by activating the first doped source portion 1151. Similar to the silicon substrate 111, the first doped layer can be monocrystalline silicon or polycrystalline silicon.

[0053] The first doped source layer comprises one or more of microcrystalline silicon, amorphous silicon, or polycrystalline silicon. For example, the thickness of the first doped source layer is in the range of 10-300 nm, such as 20-100 nm, 40-80 nm, 40 nm, 50 nm, etc.

[0054] The passivation dielectric layer 112 can also be called a tunneling passivation layer, which may include metal oxides or non-metal oxides, such as silicon oxide (SiO2). x ) layer, silicon oxynitride (SiO) x N 1-x ) layer, aluminum oxide (AlO) x ) layer, titanium oxide (TiO) x ( ) layer and gallium oxide (GaOx) layer, silicon carbide (SiC) layer x The passivation dielectric layer 112 may be a single layer or a stack of one or more of the following: a passivation dielectric layer and an aluminum oxynitride layer. For example, the thickness of the passivation dielectric layer 112 may be in the range of 0.1-10 nm, such as 0.1-5 nm, 0.5-2 nm, 1.5 nm, 1.8 nm, etc.

[0055] The selective carrier transport layer 113 may include one or more of a microcrystalline silicon layer, an amorphous silicon layer, and a polycrystalline silicon layer. For example, the thickness of the selective carrier transport layer 113 is in the range of 1-300 nm, such as 10-300 nm, 10-100 nm, 30-100 nm, 50-100 nm, 70 nm, etc.

[0056] The first passivation layer 117 may include one or more single layers or stacks of silicon oxide, aluminum oxide, gallium oxide, titanium oxide, silicon oxynitride, aluminum oxynitride, silicon carbide, and silicon layers (polycrystalline silicon, amorphous silicon, or microcrystalline silicon). For example, the thickness of the first passivation layer 117 can be 1-300 nm, such as 10-300 nm, 10-100 nm, 30-100 nm, 50-100 nm, 70 nm, etc. For example, the first passivation layer 117 can be designed to provide anti-reflection. When the materials of each layer in the multilayer stack are different, the passivation effect and anti-reflection effect of each layer are different. Through multilayer combination, the first passivation layer 117 can be endowed with good passivation effect and anti-reflection effect.

[0057] Similarly, the second passivation layer 118 may comprise one or more single layers or stacks of silicon oxide, aluminum oxide, gallium oxide, titanium oxide, silicon oxynitride, aluminum oxynitride, silicon carbide, and silicon layers (polycrystalline silicon, amorphous silicon, or microcrystalline silicon). For example, the thickness of the second passivation layer 118 can be 1-300 nm, such as 10-300 nm, 10-100 nm, 30-100 nm, 50-100 nm, 70 nm, etc. When the materials of each layer in a multilayer stack are different, the passivation effect and antireflection effect of each layer are different. Through multilayer combination, the second passivation layer 118 can be endowed with good passivation effect and antireflection effect.

[0058] like Figures 1 to 3G As shown, in this embodiment, the method for manufacturing the battery cell may include:

[0059] Step S11: Provide a first-type silicon substrate 111 and perform surface treatment on the first and second surfaces of the silicon substrate 111, such as... Figure 3A As shown. For example, the surface treatment includes texturing the first and second surfaces of the silicon substrate 111 in a texturing bath using sodium hydroxide (NaOH) or potassium hydroxide (KOH) solution to form a textured structure comprising multiple pyramidal substructures, smoothing the pyramidal substructures with a mixed solution of nitric acid (HNO3) and hydrofluoric acid (HF), and polishing the second surface with a tetramethylammonium hydroxide (TMAH) solution. In other embodiments, for example, a mixed solution of ozone (O3) and HF can be used to smooth the pyramids of the textured surface; for example, a mixed solution of HNO3 and HF, or NaOH solution, or KOH solution can be used to wet-etch or polish the second surface. Specifically, in this embodiment, the silicon substrate 111 is p-type single-crystal silicon with a resistivity of 2 Ω·cm.

[0060] Step S12, a passivation dielectric layer 112 is formed on the second surface of the silicon substrate 111, such as... Figure 3BAs shown. Specifically, in this embodiment, a silicon dioxide layer with a thickness of 1.8 nm is formed as the passivation dielectric layer 112 by plasma-enhanced chemical vapor deposition (PECVD). Furthermore, the passivation dielectric layer 112 can be formed, for example, by low-temperature furnace tube oxidation, nitric acid oxidation, ozone oxidation, atomic layer deposition (ALD) processes (e.g., including plasma-enhanced atomic layer deposition (PEALD), chemical vapor deposition (CVD) processes (e.g., including PECVD, low-pressure chemical vapor deposition (LPCVD), atmospheric pressure chemical vapor deposition (APCVD), physical vapor deposition (PVD) processes (such as sputtering or evaporation), rapid plasma deposition (RPD), etc.).

[0061] Step S13: A first selective carrier transport front layer 113' with type II doped particles is formed on the surface of the passivation dielectric layer 112 facing away from the silicon substrate, as shown below. Figure 3C As shown. Specifically, in this embodiment, a phosphorus-doped amorphous silicon layer with a thickness of 70 nm is formed by PVD as the first selective carrier transport front layer 113'. In this embodiment, the first selective carrier transport front layer 113' is in-situ doped, that is, it is a selective carrier transport front layer 113' that has been doped with type II doped particles. The first selective carrier transport front layer 113' is not crystallized. In this document, "selective carrier transport front layer" is used to distinguish it from the selective carrier transport layer 113 that has been crystallized.

[0062] Step S14: A first doped source layer comprising a plurality of first doped source portions 1151 doped with type I doped particles is formed in a local region on the first surface of the silicon substrate 111, such as... Figure 3D As shown. Specifically, in this embodiment, multiple boron-containing amorphous silicon portions with a thickness of 40 nm are formed using a PVD process with a mask, serving as multiple first dopant source portions 1151.

[0063] Step S15 involves performing a high-temperature annealing process on the structure formed in step S14 to activate the first type of doped particles in the first doped source portion 1151 to form a plurality of first doped portions 116 on the first surface of the silicon substrate 111, and to activate the second type of doped particles in the first selective carrier transport front layer 113' and to crystallize the first selective carrier transport front layer 113' to form a selective carrier transport layer 113, as shown. Figure 3E As shown. Furthermore, during the high-temperature annealing process, a first oxide layer 1152 is formed on the first surface of the first doped source layer and the silicon substrate 111, and a second oxide layer 1131 is formed on the surface of the selective carrier transport layer 113 facing away from the silicon substrate 111. Specifically, in this embodiment, the high-temperature annealing process includes high-temperature heat treatment at 950°C in an annealing furnace tube.

[0064] Step S16, remove the first oxide layer 1152 and the second oxide layer 1131, as follows Figure 3F As shown. Specifically, in this embodiment, the first oxide layer 1152 and the second oxide layer 1131 generated by the high-temperature annealing treatment are removed by using an HF solution.

[0065] Step S17: A first passivation layer 117 is formed on the first surface of the silicon substrate 111 and the surface of the first doped source layer facing away from the silicon substrate, and a second passivation layer 118 is formed on the surface of the selective carrier transport layer 113 facing away from the silicon substrate, as shown below. Figure 3G As shown. Specifically, in this embodiment, a first passivation layer 117 is formed on the first surface of the silicon substrate 111 and the surface of the first doped source layer facing away from the silicon substrate 111 by tubular PECVD, and a second passivation layer 118 is formed on the surface of the selective carrier transport layer 113 facing away from the silicon substrate 111. For example, alternatively or additionally, ALD, PEALD, etc. can be used to form the first passivation layer 117 and the second passivation layer 118. For example, the first passivation layer 117 and the second passivation layer 118 can be a stack of an aluminum oxide layer and a silicon nitride layer, respectively.

[0066] Step S18, forming the first contact electrode 1191 and the second contact electrode 1192, as follows: Figure 1 As shown. Specifically, in this embodiment, a metal contact paste, such as silver paste, aluminum paste, or silver-aluminum paste, is printed on the surfaces of the first passivation layer 117 and the second passivation layer 118 by screen printing, and then solidified first contact electrode 1191 and second contact electrode 1192 are obtained by sintering. Alternatively, the first contact electrode 1191 and the second contact electrode 1192 can also be formed by electroplating or the like.

[0067] In this embodiment, the step of removing the first doped source layer is omitted, thereby simplifying the manufacturing process and reducing manufacturing costs.

[0068] Furthermore, in this embodiment, a single high-temperature annealing step (step S15) is used to simultaneously heat-treat the front and back sides of the semiconductor structure. Specifically, on the front side, type I doped particles are activated to form a plurality of first doped portions 116; on the back side, type II doped particles are activated and the first selective carrier transport front layer 113' is crystallized to form a selective carrier transport layer 113. This simplifies the manufacturing process, reduces manufacturing costs, and is suitable for mass production.

[0069] Furthermore, in this embodiment, a PVD process is used to form the first selective carrier transport front layer 113' and the first doped source portion 1151. Compared to processes such as CVD, the PVD process can form a single-sided film layer only on the target surface, without forming a film layer on the surface or side surface opposite to the target surface, thus avoiding wrap-around plating. This eliminates the need for additional manufacturing steps to remove unwanted films generated by wrap-around plating, improving production efficiency.

[0070] In addition, in this embodiment, since both the first selective carrier transport front layer 113' and the first doped source portion 1151 are formed using PVD technology, by performing the steps of forming the first selective carrier transport front layer 113' and the first doped source portion 1151 in consecutive steps, the first selective carrier transport front layer 113' and the first doped source portion 1151 can be formed in the same PVD equipment, which further simplifies the manufacturing steps and improves production efficiency.

[0071] It should be noted that the steps in the method described herein do not necessarily have to be performed in the order described above. They may be performed in other orders, at least one step may be omitted, or at least one additional step may be added. This disclosure is not limited thereto. Without departing from the scope of the claims of this disclosure, those skilled in the art can combine or modify the steps, features, processes, and parameters of the embodiments given herein to obtain other embodiments. For example, the following describes a method for manufacturing a battery cell according to other embodiments of this disclosure.

[0072] Second Embodiment -

[0073] Figure 4 This is a schematic flowchart of a method for manufacturing a battery cell according to a second embodiment of the present disclosure. Figure 5 This is a schematic diagram of the structure after forming a plurality of first doped source portions 1151 on the first surface of a silicon substrate 111, and forming a passivation dielectric layer 112, a first selective carrier transport front layer 113' and a second selective carrier transport front layer 113" on the second surface of the silicon substrate 111, according to the second embodiment of the present disclosure.

[0074] The structure of the battery cell manufactured using the manufacturing method according to the second embodiment is similar to that of... Figure 1 The structure of the battery cell manufactured using the manufacturing method according to the first embodiment is basically the same, and will not be described again here.

[0075] A method for manufacturing a battery cell according to a second embodiment of the present disclosure includes:

[0076] Step S21 involves providing a first-type silicon substrate 111 and performing surface treatment on the first and second surfaces of the silicon substrate 111. Specifically, in this embodiment, the silicon substrate 111 is p-type single-crystal silicon with a resistivity of 1 Ω·cm. For example, the surface treatment includes texturing the first and second surfaces of the silicon substrate 111 in a texturing bath using a sodium hydroxide (NaOH) or potassium hydroxide (KOH) solution to form a textured structure comprising multiple pyramidal substructures, smoothing the pyramidal substructures with a mixed solution of O3 and HF, and finally polishing the second surface with a solution of HNO3 and HF.

[0077] Step S22: A first doped source layer comprising a plurality of first doped source portions 1151 having doped particles of the first type is formed on a first surface of the silicon substrate 111. Specifically, in this embodiment, a plurality of boron-containing amorphous silicon portions with a thickness of 30 nm are formed using a PVD process with a mask as the plurality of first doped source portions 1151.

[0078] Step S23: A passivation dielectric layer 112 is formed on the second surface of the silicon substrate 111. Specifically, in this embodiment, a silicon dioxide layer with a thickness of 1.5 nm is formed by ALD as the passivation dielectric layer 112.

[0079] Step S24: A stack of a first selective carrier transport front layer 113' having type II doped particles and an intrinsic second selective carrier transport front layer 113" is formed on the surface of the passivation dielectric layer 112 facing away from the silicon substrate 111, as shown below. Figure 5 As shown. For example, a phosphorus-doped amorphous silicon thin film layer with a thickness of 40 nm is formed by PVD as a first selective carrier transport front layer 113', and an undoped amorphous silicon thin film layer with a thickness of 30 nm is formed as a second selective carrier transport front layer 113'". In other embodiments, the positions of the first selective carrier transport front layer 113' and the second selective carrier transport front layer 113' can be interchanged.

[0080] Unlike the single-layer in-situ doped first selective carrier transport front layer 113' of the first embodiment, the structure formed during manufacturing in the second embodiment includes a stack of a first selective carrier transport front layer 113' having second-type doped particles and an intrinsic second selective carrier transport front layer 113". The first selective carrier transport layer 113' is subsequently provided with second-type doped particles for the formation of the selective carrier transport layer 113 in a high-temperature annealing process and is crystallized to form a portion of the selective carrier transport layer 113. The second selective carrier transport front layer 113" receives second-type doped particles from the first selective carrier transport layer 113' in a subsequent high-temperature annealing process and is also crystallized to form a portion of the selective carrier transport layer 113.

[0081] The advantage of forming a first selective carrier transport front layer 113' of a single layer of in-situ doped type II doped particles in the first embodiment is that it requires only one step and is simpler to operate.

[0082] The advantage of forming the stack of the first selective carrier transport front layer 113' and the intrinsic second selective carrier transport front layer 113" in the second embodiment is that it improves production efficiency, because forming the in-situ doped first selective carrier transport front layer 113' takes longer, while here the intrinsic second selective carrier transport front layer 113" replaces part of the in-situ doped first selective carrier transport front layer 113'.

[0083] Furthermore, the manufacturing method according to the second embodiment also includes the following steps that are the same as or similar to those in the manufacturing method of the first embodiment:

[0084] Step S25 involves performing a high-temperature annealing process on the semiconductor structure formed in step S24. This activates the first type of doped particles in the first doped source portion 1151 to form a plurality of first doped portions 116 on the first surface of the silicon substrate 111. Simultaneously, it activates the second type of doped particles in the first selective carrier transport front layer 113' and crystallizes the first selective carrier transport front layer 113' and the second selective carrier transport front layer 113' to form a doped selective carrier transport layer 113. Furthermore, during the high-temperature annealing process, a first oxide layer 1152 is formed on the surface of the first doped source portion 1151 facing away from the silicon substrate 111 and on the first surface of the silicon substrate 111, and a second oxide layer 1131 is formed on the surface of the selective carrier transport layer 113 facing away from the silicon substrate 111. Specifically, in this embodiment, the high-temperature annealing process includes high-temperature heat treatment at 920°C in an annealing furnace tube.

[0085] Step S26: Remove the first oxide layer 1152 and the second oxide layer 1131. For example, use an HF solution.

[0086] In step S27, a first passivation layer 117 is formed on the first surface of the silicon substrate 111 and the surface of the first doped source layer facing away from the silicon substrate 111, and a second passivation layer 118 is formed on the surface of the selective carrier transport layer 113 facing away from the silicon substrate 111. For example, the first passivation layer 117 and the second passivation layer 118 can be a stack of a titanium oxide layer and a silicon oxynitride layer, respectively.

[0087] Step S28: Form the first contact electrode 1191 and the second contact electrode 1192.

[0088] Further descriptions of the manufacturing methods according to the second embodiment and the following third and fourth embodiments can be found in the corresponding description of the first embodiment.

[0089] Third Embodiment

[0090] Figure 6 This is a schematic flowchart of a method for manufacturing a battery cell according to a third embodiment of the present disclosure. Figure 7 This is a schematic diagram of the structure after forming a plurality of first doped source portions 1151 and a plurality of pre-doped portions 116' on the first surface of a silicon substrate 111, and forming a passivation dielectric layer 112 and a first selective carrier transport front layer 113' on the second surface of the silicon substrate 111, according to the third embodiment of the present disclosure.

[0091] The structure of the battery cell manufactured using the manufacturing method according to the third embodiment is similar to that of... Figure 1 The structure of the battery cell manufactured using the manufacturing method according to the first embodiment is basically the same, and will not be described again here.

[0092] The method for manufacturing a battery cell according to the third embodiment of this disclosure includes:

[0093] Step S31 involves providing a first-type silicon substrate 111 and performing surface treatment on the first and second surfaces of the silicon substrate 111. Specifically, in this embodiment, the silicon substrate 111 is p-type single-crystal silicon with a resistivity of 4 Ω·cm. For example, the surface treatment includes texturing the first and second surfaces of the silicon substrate 111 in a texturing bath using a sodium hydroxide (NaOH) or potassium hydroxide (KOH) solution to form a textured surface structure comprising multiple pyramidal substructures, smoothing the pyramidal substructures with a mixed solution of O3 and HF, and finally polishing the second surface with a solution of HNO3 and HF.

[0094] In step S32, a passivation dielectric layer 112 is formed on the second surface of the silicon substrate 111. Specifically, in this embodiment, a silicon dioxide layer with a thickness of 1.8 nm is formed as the passivation dielectric layer 112 by ion-enhanced chemical vapor deposition (PECVD).

[0095] In step S33, a first doped layer comprising a plurality of first doped source portions 1151 having doped particles of the first type and a pre-doped layer comprising a plurality of intrinsic pre-doped portions 116' are sequentially formed on the first surface of the silicon substrate 111. Specifically, in this embodiment, a boron-containing microcrystalline silicon portion with a thickness of 20 nm is formed using a PVD process with a mask as a plurality of first doped source portions 1151 and a plurality of intrinsic amorphous silicon thin film portions with a thickness of 20 nm are formed as pre-doped portions 116'. Since the growth rate of the intrinsic pre-doped layer is faster than that of the in-situ doped first doped layer, replacing a portion of the first doped layer with the pre-doped layer can shorten the manufacturing time and improve the manufacturing efficiency.

[0096] Step S34: A first selective carrier transport front layer 113' is formed on the surface of the passivation dielectric layer 112 facing away from the silicon substrate 111, as shown below. Figure 7 As shown. Specifically, in this embodiment, an 80 nm thick phosphorus-doped amorphous silicon layer is formed by PVD as the first selective carrier transport front layer 113'.

[0097] Step S35 involves performing a high-temperature annealing process on the structure formed in step S34. This activates the first type of doped particles in the first doped source portion 1151 to form a plurality of first doped portions 116 on the first surface of the silicon substrate 111. Simultaneously, it activates the second type of doped particles in the first selective carrier transport front layer 113' and crystallizes the first selective carrier transport front layer 113' to form a selective carrier transport layer 113. Furthermore, during the high-temperature annealing process, a first oxide layer 1152 is formed on the surface of the first doped source portion 1151 facing away from the silicon substrate 111 and on the first surface of the silicon substrate 111. A second oxide layer 1131 is also formed on the surface of the selective carrier transport layer 113 facing away from the silicon substrate 111. Specifically, in this embodiment, the high-temperature annealing process includes performing a high-temperature heat treatment of the intermediate semiconductor structure at 900°C in an annealing furnace.

[0098] Step S36: Remove the first oxide layer 1152 and the second oxide layer 1131. For example, use an HF solution to wash away the first oxide layer 1152 and the second oxide layer 1131 generated by the high-temperature annealing treatment.

[0099] In step S37, a first passivation layer 117 is formed on the first surface of the silicon substrate 111 and the first doped source layer, and a second passivation layer 118 is formed on the selective carrier transport layer 113. For example, the first passivation layer 117 and the second passivation layer 118 can be a stack of gallium oxide and silicon oxynitride layers, respectively.

[0100] Step S38: Form the first contact electrode 1191 and the second contact electrode 1192.

[0101] Fourth embodiment

[0102] The structure of the battery cell manufactured using the manufacturing method according to the fourth embodiment is similar to that of... Figure 1 The main difference in the structure of the battery cell manufactured using the manufacturing method according to the first embodiment is that, in the first embodiment, the first type is p-type and the second type is n-type; in the fourth embodiment, the first type is n-type and the second type is p-type.

[0103] The method for manufacturing a battery cell according to the fourth embodiment of this disclosure includes:

[0104] Step S41: Provide a silicon substrate 111 of n-type single crystal silicon with a resistivity of 3 Ω·cm and perform surface treatment on the first and second surfaces of the silicon substrate 111.

[0105] In step S42, a stack of aluminum oxide and titanium oxide with a thickness of 2.0 nm is formed on the second surface of the silicon substrate 111 as a passivation dielectric layer 112.

[0106] Step S43: A boron-containing amorphous silicon layer with a thickness of 80 nm is formed on the passivation dielectric layer 112 by PVD as a first selective carrier transport front layer 113'.

[0107] Step S44: Using a PVD process, multiple phosphorus-containing amorphous silicon portions with a thickness of 40 nm are locally formed on the second surface of the front side of the silicon substrate 111 as multiple first doping source portions 1151.

[0108] In step S45, the structure formed in step S44 is subjected to high-temperature annealing to activate the n-type dopant particles in the first dopant source portion 1151 to form a plurality of first dopant portions 116 in the second surface of the silicon substrate 111, activate the p-type dopant particles in the first selective carrier transport front layer 113', and crystallize the first selective carrier transport front layer 113' to form a selective carrier transport layer 113. Furthermore, during the high-temperature annealing process, a first oxide layer 1152 is formed on the surface of the first dopant source portion 1151 facing away from the silicon substrate 111 and on the first surface of the silicon substrate 111, and a second oxide layer 1131 is formed on the surface of the selective carrier transport layer 113 facing away from the silicon substrate 111. For example, the high-temperature annealing process includes high-temperature heat treatment of the intermediate semiconductor structure at 970°C in an annealing furnace tube.

[0109] Step S46: Remove the first oxide layer 1152 and the second oxide layer 1131. For example, use an HF solution.

[0110] In step S47, a first passivation layer 117 is formed on the first surface of the silicon substrate 111 and the surface of the first doped source layer facing away from the silicon substrate 111, and a second passivation layer 118 is formed on the surface of the selective carrier transport layer 113 facing away from the silicon substrate 111. For example, the first passivation layer 117 and the second passivation layer 118 may be a stack of aluminum oxide, gallium oxide and silicon oxynitride layers, respectively.

[0111] Step S48, forming the first contact electrode 1191 and the second contact electrode 1192.

[0112] In the first to fourth embodiments described above, a single high-temperature annealing step is used to simultaneously heat-treat the front and back sides of the semiconductor structure to be formed into a battery cell, but this disclosure is not limited to this. Alternatively, the front and back sides of the semiconductor structure to be formed into a battery cell can be heat-treated separately.

[0113] Furthermore, the aforementioned selective carrier transport front layers 113' and 113" are not limited to being formed by PVD, but can also be formed by other methods, such as CVD such as PECVD.

[0114] For example, the fifth embodiment below provides an exemplary description.

[0115] Fifth embodiment

[0116] Figure 8 This is a schematic flowchart of a method for manufacturing a battery cell according to the fifth embodiment of the present disclosure.

[0117] The structure of the battery cell manufactured using the manufacturing method according to the fifth embodiment is similar to that of... Figure 1The structure of the battery cell manufactured using the manufacturing method according to the first embodiment is basically the same, and will not be described again here.

[0118] The method for manufacturing a battery cell according to the fifth embodiment of this disclosure includes:

[0119] Step S51: Provide a first type of silicon substrate 111 and perform surface treatment on the first and second surfaces of the silicon substrate 111.

[0120] Step S52: A first doped source layer comprising a plurality of first doped source portions 1151 having first type doped particles is locally formed on the first surface of the silicon substrate 111.

[0121] Step S53: Perform high-temperature annealing on the structure formed in step S52 to activate the first type of doped particles in the first doped source portion 1151 to form a plurality of first doped portions 116 that are separated from each other in the first surface of the silicon substrate 111.

[0122] Step S54: A passivation dielectric layer 112 is formed on the second surface of the silicon substrate 111.

[0123] In step S55, a first selective carrier transport front layer 113' having type II doped particles is formed on the surface of the passivation dielectric layer 112 facing away from the silicon substrate 111. The type II doped particles in the first selective carrier transport front layer 113' are activated by a high-temperature annealing process, and the first selective carrier transport front layer 113' is crystallized to form a selective carrier transport layer 113. Furthermore, during the high-temperature annealing process, a first oxide layer 1152 is formed on the surface of the first doped portion 116 facing away from the silicon substrate 111 and on the first surface of the silicon substrate 111, and a second oxide layer 1131 is formed on the surface of the selective carrier transport layer 113 facing away from the silicon substrate 111. For example, the high-temperature annealing process includes high-temperature heat treatment at 850°C in an annealing furnace tube.

[0124] Step S56: Remove the first oxide layer 1152 and the second oxide layer 1131.

[0125] Step S57: A first passivation layer 117 is formed on the first surface of the silicon substrate 111 and the surface of the first doped source layer facing away from the silicon substrate 111, and a second passivation layer 118 is formed on the surface of the selective carrier transport layer 113 facing away from the silicon substrate 111.

[0126] Step S58: Form the first contact electrode 1191 and the second contact electrode 1192.

[0127] In addition, the order of steps S52 and S54 in the fifth embodiment can also be interchanged.

[0128] The embodiments disclosed herein also include the following technical solutions:

[0129] Technical Solution 1: A silicon-based solar cell unit, comprising:

[0130] A first type of silicon substrate having a first surface and a second surface opposite to the first surface;

[0131] A plurality of first doped portions are located on a first surface of the silicon substrate, the plurality of first doped portions being separated from each other and doped with doped particles of type 1;

[0132] A plurality of first doped source portions, each of which is disposed on a surface of the plurality of first doped portions facing away from the silicon substrate and is doped with doped particles of the first type; and

[0133] A first passivation layer covers a first surface of the silicon substrate and the surfaces of the plurality of first doped source portions facing away from the silicon substrate.

[0134] Technical Solution 2: The battery cell according to Technical Solution 1, wherein,

[0135] The plurality of first doped portions are formed by activating first-type doped particles in the plurality of first doped source portions, thereby doping the first-type doped particles into the first surface of the silicon substrate.

[0136] Technical solution 3: The battery cell according to technical solution 1 further includes:

[0137] Multiple first contact electrodes, wherein the first contact electrodes penetrate the first passivation layer and make ohmic contact with the first doped source portion.

[0138] Technical solution 4: The battery cell according to technical solution 1, wherein,

[0139] The projection of the first contact electrode onto the silicon substrate along the thickness direction falls within the projection of the first doped source portion onto the silicon substrate along the thickness direction.

[0140] Technical solution 5: The battery cell according to technical solution 1, wherein,

[0141] The silicon substrate and the first doped portion are monocrystalline silicon or polycrystalline silicon.

[0142] The first doping source portion includes one or more of microcrystalline silicon, amorphous silicon, or polycrystalline silicon.

[0143] Technical Solution 6: The battery cell according to Technical Solution 1, wherein,

[0144] The first passivation layer includes one or more single layers or stacks of silicon oxide, aluminum oxide, gallium oxide, titanium oxide, silicon oxynitride, aluminum oxynitride, silicon, and silicon carbide.

[0145] Technical Solution 7: The battery cell according to any one of Technical Solutions 1-6 further includes:

[0146] A passivation dielectric layer is disposed on the second surface of the silicon substrate;

[0147] A selective carrier transport layer, on the surface of the passivation dielectric layer facing away from the silicon substrate, wherein the selective carrier transport layer is doped with type II doped particles; and

[0148] A second passivation layer is located on the surface of the selective carrier transport layer opposite to the silicon substrate.

[0149] Technical solution 8: The battery cell according to technical solution 7 further includes:

[0150] A plurality of second contact electrodes penetrate the second passivation layer and make ohmic contact with the selective carrier transport layer.

[0151] Technical Solution 9: The battery cell according to Technical Solution 7, wherein,

[0152] The first type is n-type, and the second type is p-type.

[0153] Technical solution 10: The battery cell according to technical solution 7, wherein,

[0154] The first type is p-type, and the second type is n-type.

[0155] Technical Solution 11: The battery cell according to Technical Solution 7, wherein,

[0156] The selective carrier transport layer comprises one or more of microcrystalline silicon, amorphous silicon, and polycrystalline silicon.

[0157] Technical Solution 12: The battery cell according to Technical Solution 7, wherein,

[0158] The second passivation layer includes one or more single layers or stacks of silicon oxide, aluminum oxide, gallium oxide, titanium oxide, silicon oxynitride, aluminum oxynitride, silicon, and silicon carbide.

[0159] Technical Solution 13: The battery cell according to Technical Solution 7, wherein,

[0160] The passivation medium layer includes one or more single layers or stacks of non-metallic oxide layers and metallic oxide layers.

[0161] Technical Solution 14: The battery cell according to Technical Solution 7, wherein,

[0162] The passivation dielectric layer includes one or more single layers or stacks of silicon oxide, aluminum oxide, gallium oxide, titanium oxide, silicon oxynitride, aluminum oxynitride, and silicon nitride.

[0163] Technical solution 15: The battery cell according to technical solution 7, wherein,

[0164] The thickness of the passivation dielectric layer is in the range of 0.1 nm to 10.0 nm.

[0165] Technical Solution 16: A method for manufacturing a battery cell, comprising:

[0166] A first type of silicon substrate is provided, the silicon substrate including a first surface and a second surface opposite to the first surface;

[0167] A plurality of first doped source portions are formed on a first surface of the silicon substrate, the plurality of first doped source portions being separated from each other and doped with type I doped particles;

[0168] High-temperature annealing activates the first-type doped particles in the plurality of first doped source portions to form a plurality of first doped portions on the first surface of the silicon substrate; and

[0169] A first passivation layer is formed, which covers the first surface of the silicon substrate and the surfaces of the plurality of first doped sources facing away from the silicon substrate.

[0170] Technical Solution 17: The method for manufacturing a battery cell according to Technical Solution 16 further includes:

[0171] Multiple first contact electrodes are formed, such that the multiple first contact electrodes penetrate the first passivation layer and make partial ohmic contact with the multiple first doped source portions.

[0172] Technical solution 18, the method for manufacturing a battery cell according to technical solution 16, further includes:

[0173] A passivation dielectric layer is formed on the second surface of the silicon substrate;

[0174] A selective carrier transport layer is formed on the surface of the passivation dielectric layer opposite to the silicon substrate, and the selective carrier transport layer is doped with type II doped particles;

[0175] A second passivation layer is formed on the surface of the selective carrier transport layer opposite to the silicon substrate; and

[0176] Multiple second contact electrodes are formed, and the multiple second contact electrodes penetrate the second passivation layer and make ohmic contact with the selective carrier transport layer.

[0177] The scope of this disclosure is not limited by the embodiments described above, but by the appended claims and their equivalents.

Claims

1. A silicon-based solar cell unit, comprising: A first type of silicon substrate having a first surface and a second surface opposite to the first surface; A plurality of first doped portions are located on a first surface of the silicon substrate, the plurality of first doped portions being separated from each other and doped with doped particles of type 1; A plurality of first doping source portions are respectively disposed on the surface of the plurality of first doping portions facing away from the silicon substrate and doped with doping particles of the first type, and the first doping source portions are in contact with the first doping portions; as well as A first passivation layer covers and contacts the undoped portion of a first surface of the silicon substrate, and the first passivation layer covers and contacts the surface of the plurality of first doped source portions facing away from the silicon substrate.

2. The battery cell according to claim 1, wherein, The plurality of first doped portions are formed by activating first-type doped particles in the plurality of first doped source portions, thereby doping the first-type doped particles into the first surface of the silicon substrate.

3. The battery cell according to claim 1, further comprising: Multiple first contact electrodes, wherein the first contact electrodes penetrate the first passivation layer and make ohmic contact with the first doped source portion.

4. The battery cell according to claim 3, wherein, The projection of the first contact electrode onto the silicon substrate along the thickness direction falls within the projection of the first doped source portion onto the silicon substrate along the thickness direction.

5. The battery cell according to claim 1, wherein, The silicon substrate and the first doped portion are monocrystalline silicon or polycrystalline silicon. The first doping source portion includes one or more of microcrystalline silicon, amorphous silicon, or polycrystalline silicon.

6. The battery cell according to claim 1, wherein, The first passivation layer includes one or more single layers or stacks of silicon oxide, aluminum oxide, gallium oxide, titanium oxide, silicon oxynitride, aluminum oxynitride, silicon, and silicon carbide.

7. The battery cell according to any one of claims 1-6, further comprising: A passivation dielectric layer is disposed on the second surface of the silicon substrate; A selective carrier transport layer is provided on the surface of the passivation dielectric layer facing away from the silicon substrate, and the selective carrier transport layer is doped with type II doped particles. as well as A second passivation layer is located on the surface of the selective carrier transport layer opposite to the silicon substrate.

8. The battery cell according to claim 7, further comprising: A plurality of second contact electrodes penetrate the second passivation layer and make ohmic contact with the selective carrier transport layer.

9. The battery cell according to claim 7, wherein, The first type is n-type, and the second type is p-type.

10. The battery cell according to claim 7, wherein, The first type is p-type, and the second type is n-type.

11. The battery cell according to claim 7, wherein, The selective carrier transport layer comprises one or more of microcrystalline silicon, amorphous silicon, and polycrystalline silicon.

12. The battery cell according to claim 7, wherein, The second passivation layer includes one or more single layers or stacks of silicon oxide, aluminum oxide, gallium oxide, titanium oxide, silicon oxynitride, aluminum oxynitride, silicon, and silicon carbide.

13. The battery cell according to claim 7, wherein, The passivation medium layer includes one or more single layers or stacks of non-metallic oxide layers and metallic oxide layers.

14. The battery cell according to claim 7, wherein, The passivation dielectric layer includes one or more single layers or stacks of silicon oxide, aluminum oxide, gallium oxide, titanium oxide, silicon oxynitride, aluminum oxynitride, and silicon nitride.

15. The battery cell according to claim 7, wherein, The thickness of the passivation dielectric layer is in the range of 0.1 nm to 10.0 nm.

16. A method for manufacturing a battery cell, comprising: A first type of silicon substrate is provided, the silicon substrate including a first surface and a second surface opposite to the first surface; A plurality of first doped source portions are formed on a first surface of the silicon substrate, the plurality of first doped source portions being separated from each other and doped with type I doped particles; The first type of doped particles in the plurality of first doped source portions are activated by high-temperature annealing to form a plurality of first doped portions in the first surface of the silicon substrate, and the first doped source portions are in contact with the first doped portions. as well as A first passivation layer is formed, which covers and contacts the undoped portion of the first surface of the silicon substrate, and the first passivation layer covers and contacts the surface of the plurality of first doped source portions facing away from the silicon substrate.

17. The method for manufacturing a battery cell according to claim 16, further comprising: Multiple first contact electrodes are formed, such that the multiple first contact electrodes penetrate the first passivation layer and make partial ohmic contact with the multiple first doped source portions.

18. The method for manufacturing a battery cell according to claim 16, further comprising: A passivation dielectric layer is formed on the second surface of the silicon substrate; A selective carrier transport layer is formed on the surface of the passivation dielectric layer opposite to the silicon substrate, and the selective carrier transport layer is doped with type II doped particles; A second passivation layer is formed on the surface of the selective carrier transport layer opposite to the silicon substrate; as well as Multiple second contact electrodes are formed, and the multiple second contact electrodes penetrate the second passivation layer and make ohmic contact with the selective carrier transport layer.

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