Light detection device and image processing method

Abstract

The present invention relates to a light detection device and an image processing method. The light detection device includes: a pixel circuit including a reset transistor and configured to output a pixel signal; a differential comparator including a pixel input, a reference input and a comparator output; a first signal line connected to the pixel circuit and connected to the differential comparator; and a second signal line connected to the source or drain of the reset transistor and connected to the comparator output. The image processing method includes outputting a pixel signal from a pixel circuit including a reset transistor via the first signal line; and outputting a differential signal from a differential comparator including a pixel input, a reference input and a comparator output, wherein the source or drain of the reset transistor is connected to the comparator output via the second signal line.

Description

[0001] This application is a divisional application of a patent application with application number 201780038975.5 and application date of June 29, 2017, invention name of “Image sensor and image processing method”. Technical Field

[0002] The present application generally relates to image sensors and image processing methods. More specifically, the present application relates to reducing reset spread in image sensors. Background Art

[0003] Image sensing devices typically include: an image sensor (generally an array of pixel circuits); as well as signal processing circuits and any associated control or timing circuits. Within the image sensor itself, charges are collected in the photoelectric conversion devices of the pixel circuits due to the illumination of light. Modern image sensors typically include tens of millions of pixels (tens of times megapixels or MP).

[0004] The accumulated charge is then converted to a digital value. This conversion typically requires several circuit components, such as a sample-and-hold (S / H) circuit, an analog-to-digital converter (ADC), and timing and control circuits, each of which plays a role in the above conversion. For example, the role of the S / H circuit can be to sample analog signals from different time phases of the operation of the photoelectric conversion device, after which these analog signals can be converted to digital form by the ADC. In order to effectively convert analog signals to digital form in an array with a large number of pixel circuits, a group of ADCs work in parallel, where multiple pixels share one ADC. The specific sharing arrangement depends on the architecture of the image sensor. For example, the arrangement can be: a column-based arrangement, in which all pixel circuits in a column of the array share one ADC; a shared column arrangement, in which several columns of pixel circuits share one ADC; a block-based arrangement, in which rectangular pixel circuit blocks share one ADC; and so on.

[0005] In order to reduce the noise in the image sensor, the correlated double sampling (CDS) method is often used. In CDS, each pixel circuit in the image sensor is sampled twice. In the first measurement, the pixel circuit is reset and the reset voltage from the pixel circuit is measured. This is called the reset signal or "P-phase" signal. After the first measurement, the pixel circuit is exposed to light so that the photoelectric conversion device collects charges according to the level of the incident light. These charges are measured in the second measurement, which gives an analog signal equal to the exposure value (light-exposed value) plus the reset value. This is called the data signal or "D-phase" signal. The difference between the two measurements is equivalent to the exposure signal of the pixel circuit.

[0006] However, in order for the CDS method to work effectively, it is helpful to minimize the variation of the reset signal. In practical CMOS image sensor circuits, especially when operating the sensor at high analog gain, the total variation of the reset value for all pixels in the image sensor must be accommodated by both the gain amplifier and the ADC function.

[0007] For example, in the case where the input voltage range of the ADC is 1V and the change of the reset voltage signal is 100mV, because the ADC must reproduce the data signal including both the reset change and the photodiode change, the voltage range allocated to the photodiode signal is 900mV. As the gain of the amplifier increases, both the reset voltage value and the data voltage value are amplified so that: a gain of 8 times (or 18dB) results in a voltage change of 800mV for the reset signal at the ADC input, and therefore the photodiode signal change is only 200mV. However, in this example, because the reset plus photodiode signal change will not be allowed within the allowed ADC input voltage range, a gain level such as 16 times (24dB) is not possible.

[0008] This allowable photodiode signal range is called "dynamic range" and is an important parameter in image sensor design. In order to achieve higher dynamic range at any gain level, and to increase the maximum usable dynamic range of the image sensor, it is necessary to reduce the reset signal variation in the ADC circuit. Summary of the invention

[0009] Various aspects of the present disclosure relate to an image sensor and an image processing method capable of implementing an active reset method using a single-slope ADC.

[0010] In one aspect of the present disclosure, an image sensor includes: a pixel circuit, which includes a reset transistor and is configured to output a pixel signal; and a differential comparator, which includes a pixel input, a reference input, and a comparator output, wherein the source or drain of the reset transistor is connected to the comparator output.

[0011] In another aspect of the present disclosure, an image processing method includes: outputting a pixel signal from a pixel circuit including a reset transistor; and outputting a differential signal from a differential comparator including a pixel input, a reference input and a comparator output, wherein the source or drain of the reset transistor is connected to the comparator output.

[0012] In the above aspects of the present disclosure, a digital-to-analog converter configured to output a reference signal having a ramp waveform is also provided. The digital-to-analog converter may be configured to be initialized to an initial signal level and then output the ramp waveform, at which time the differential comparator is configured to perform a P-phase measurement corresponding to a reset level of the pixel circuit; and the digital-to-analog converter may be configured to subsequently reinitialize to the initial signal level and then output the ramp waveform, at which time the differential comparator is configured to perform a D-phase measurement corresponding to a data level of the pixel circuit.

[0013] The present disclosure can be embodied in various forms, including: hardware or circuits controlled by computer-implemented methods, computer program products, computer systems and networks, user interfaces, and application programming interfaces; as well as methods implemented by hardware, signal processing circuits, image sensor circuits, application-specific integrated circuits, and field programmable gate arrays, etc. The foregoing summary is intended only to give a general idea of ​​the various aspects of the present disclosure and is not intended to limit the scope of the present disclosure in any way. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] These and other more detailed and specific features of various embodiments will be more fully disclosed in the following description in conjunction with the accompanying drawings. In the accompanying drawings:

[0015] Figure 1 An exemplary image sensor according to various aspects of the present disclosure is shown;

[0016] Figure 2A An exemplary pixel circuit according to various aspects of the present disclosure is shown;

[0017] Figure 2B Another exemplary pixel circuit according to various aspects of the present disclosure is shown;

[0018] Figure 3 Another exemplary pixel circuit according to various aspects of the present disclosure is shown;

[0019] Figure 4A An exemplary processing chain in an image sensor according to various aspects of the present disclosure utilizing analog CDS operation is shown;

[0020] Figure 4B An exemplary processing chain in an image sensor according to various aspects of the present disclosure utilizing a digital CDS operation is shown;

[0021] Figure 5 An exemplary pixel circuit with a matched comparator circuit according to various aspects of the present disclosure is shown;

[0022] Figure 6 An exemplary pixel circuit with a single slope ADC according to various aspects of the present disclosure is shown;

[0023] Fig. 7A Shown according to Figure 6 An exemplary signal waveform diagram of an exemplary pixel circuit;

[0024] Figure 7B Shown according to Figure 6 An exemplary signal waveform diagram of an exemplary pixel circuit of FIG. 1 , which includes a signal drift;

[0025] Figure 8 An exemplary active reset circuit for a single slope ADC according to various aspects of the present disclosure is shown; and

[0026] Fig. 9 Shown according to Figure 8 An exemplary signal waveform diagram of an exemplary active reset circuit. DETAILED DESCRIPTION

[0027] In the following description, many details are described, such as flow charts, data tables, and system configurations. It is obvious to those skilled in the art that these specific details are merely exemplary and are not intended to limit the scope of the present application.

[0028] In addition, although the present disclosure focuses on the example of using the ADC circuit in an image sensor, it should be understood that this is only one example of an implementation. It should also be understood that the disclosed S / H circuit can be used in any device that needs to convert a signal from analog to digital and / or needs to compare two voltages; for example, it can be used in audio signal processing circuits, industrial measurement and control circuits, etc.

[0029] In this manner, the present disclosure provides improvements in the art of signal processing and in the related art of image sensing and image processing.

[0030] [Image sensor]

[0031] Figure 1 An exemplary image sensor 100 is shown that implements mode switching in a column-sharing architecture in which each column of pixel circuits shares a CDS circuit. The image sensor 100 includes an array 110 of pixel circuits 111. The pixel circuits 111 will be described in more detail below. The pixel circuits 111 are located at the intersections where horizontal signal lines 112 and vertical signal lines 113 cross each other. The horizontal signal lines 112 are operably connected to a vertical drive circuit 120 (which is also referred to as a "row scanning circuit") somewhere outside the pixel array, and transmit signals from the vertical drive circuit 120 to a specific row of pixel circuits 111. The pixel circuits 111 in a specific column output analog signals corresponding to the amount of incident light to the vertical signal lines 113. For purposes of illustration, Figure 1 Only a small number of pixel circuits 111 are actually shown; however, in practice, image sensor 100 may have up to tens of millions of pixel circuits (tens of times "megapixels" or MP) or more.

[0032] The vertical signal line 113 transmits the analog signal of a specific column to the column circuit 130. Figure 1 One vertical signal line 113 is shown for each column in the pixel array 110, but the present disclosure is not limited thereto. For example, more than one vertical signal line 113 may be provided for each column, or each vertical signal line 113 may correspond to more than one column. In either case, the column circuit 130 preferably includes a plurality of CDS circuits 131. Individual CDS circuits 131 will be described in more detail below. For clarity, Figure 1 Other possible circuit components of the column circuit 130, such as an S / H circuit, a voltage-to-current (V2I) circuit, and a counter, are omitted in the illustration.

[0033] The column circuits 130 are controlled by the horizontal drive circuits 140, which are also referred to as "column scanning circuits". The vertical drive circuits 120, the column circuits 130, and the horizontal drive circuits 140 each receive one or more clock signals from the controller 150. The controller 150 controls the timing and operation of the various image sensor components so that analog signals from the pixel array 110 (which have been converted to digital signals in the column circuits 130) are output via the output circuits 160, thereby being used for signal processing, storage, transmission, etc.

[0034] During the readout process, the pixel circuits 111 in each row are read together, and the pixel circuits 111 in different rows are read in sequence row by row. At the beginning of the processing period, a row of pixel circuits 111 is connected to the CDS circuit 131 through the vertical signal line 113. The CDS circuit 131 samples a row of pixel circuits 111 and converts it into digital form. After processing a row of pixel circuits 111, the image sensor 100 turns to the next row of pixel circuits 111 and repeats the process. This continues until the entire frame is read out.

[0035] like Figure 2A and Figure 2B As shown, two examples of the pixel circuit 111 are pixel circuits 210a and 210b, which are so-called 3T-type pixel circuits. Figure 2A As shown, the pixel circuit 210a includes a photoelectric conversion device 201a (e.g., a photodiode), a floating diffusion portion FD, a reset transistor 202a, a source follower transistor 203a (sometimes referred to as an "amplifier transistor"), a selection transistor 204a, and a vertical signal line 205a. The gate electrode of the reset transistor 202a and the gate electrode of the selection transistor 204a receive signals RST and SEL, respectively. These signals can be provided, for example, by a control or timing circuit (e.g., the vertical drive circuit 120 described above). The pixel circuit 210a operates by first applying a value of the signal RST, which causes the photodiode 201a to be cleared of charge and continuously reset. However, when the signal RST returns to ground, several effects may cause the value at the gate terminal of the source follower transistor 203a to have a value different from the reset voltage Vrst. The main sources of changes in the reset voltage level measured by the vertical signal line 205a include changes from within the pixel 210a and changes from outside the pixel 210a.

[0036] Variations from within pixel 210a include: kTC noise, which is caused by random variations in the channel resistance of reset transistor 202a combined with the capacitance at the gate terminal of source follower transistor 203a; reset charge injection, which is caused by high-to-low transitions of signal RST coupled through parasitic capacitance Cgs between the gate and source terminals of reset transistor 202a; process variations of transistors, which include the threshold voltage Vt of source follower transistor 203a and the drain-source voltage Vds of reset transistor 202a; and additional parasitic capacitance coupling effects, such as parasitic capacitance coupling effects between the RST signal line and the photodiode 201a or metal wiring associated with the sensing node connected to the source follower transistor 204. Variations from outside pixel 210a include: power and signal distribution effects, such as IR drops associated with pixel voltages and control signals across a large array of pixels; and offsets and random noise that occur in the readout circuits used to process the output of vertical signal line 205a.

[0037] Figure 2B Another configuration of the 3T type is shown as the pixel circuit 210b. In this circuit, the respective power supply voltages to the source follower transistor 204b and the reset transistor 203b are different. Figure 2A The select transistor 204a is used, and the transfer transistor 202b is set between the photodiode 201b and the floating diffusion FD. In operation, the photodiode 201b is reset by applying a high voltage at the reset transistor 203b and the transfer transistor 202b. Then, the transfer transistor 202b is turned off, after which the floating diffusion FD is reset, and the reset voltage is measured at this time. After the pixel is exposed to light, the transfer transistor 202b is turned on to move the charge from the photodiode 201b to the floating diffusion FD. Then, the reset plus exposure value from the photodiode 201b is measured.

[0038] Although FIG. 2A to FIG. 2B A pixel circuit having three transistors in a specific configuration is shown, but the present disclosure is not limited thereto and can be applied to pixel circuits having fewer or more transistors and other elements such as capacitors, resistors, etc. In addition, the present disclosure can be extended to a configuration in which one or more transistors are shared between multiple photoelectric conversion devices.

[0039] Another example of a pixel circuit 111 having a different number of transistors is as follows Figure 3 The pixel circuit 310 is shown. Figure 3As shown, the so-called 4T-type pixel circuit 310 includes a photoelectric conversion device 301 (e.g., a photodiode), a floating diffusion FD, a transfer transistor 302, a reset transistor 303, a source follower transistor 304 (sometimes referred to as an "amplification transistor"), a selection transistor 305, and a vertical signal line 306. The gate electrode of the transfer transistor 302, the gate electrode of the reset transistor 303, and the gate electrode of the selection transistor 305 receive signals TRG, RST, and SEL, respectively. For example, these signals can be provided by a control or timing circuit (e.g., the vertical drive circuit 120 described above).

[0040] In operation, the floating diffusion FD is reset by asserting and de-asserting the signal RST at the gate of the reset transistor 303. After the reset, a first measurement is performed to obtain the reset signal change by asserting the signal SEL and storing the reset signal change outside the pixel. Next, the signal TRG is asserted, allowing the signal collected on the photodiode to be added to the reset signal. Then, a second measurement is performed to obtain the reset plus photodiode signal change by asserting the signal SEL. Finally, the previously obtained reset signal is subtracted from the second measurement using a subtraction method in an analog or digital circuit.

[0041] Figure 4A and Figure 4B Exemplary processing chains 400a and 400b are shown for implementing the subtraction method in analog or digital circuits, respectively. Figure 4A As shown, processing chain 400a includes: pixel 410, which can be pixel 210a / b, pixel 310 or another pixel; switch 420; analog amplifier 430, which is configured to provide gain to the analog signal; analog CDS subtraction circuit 440a, which is configured to provide a differential signal; and ADC 450, which is configured to generate an output pixel value. Therefore, CDS subtraction can be performed in the analog domain.

[0042] like Figure 4B As shown, the processing chain 400b includes: a pixel 410, which can be a pixel 210a / b, a pixel 310, or another pixel; a switch 420; an analog amplifier 430, which is configured to provide gain to the analog signal; an ADC 450, which is configured to convert from an analog value to a digital value; and a digital CDS subtraction circuit 440b, which is configured to provide a differential signal as an output signal. Therefore, the CDS subtraction can be performed in the digital domain.

[0043] In a practical circuit implementation, both processing chains 400a and 400b may be controlled by a sequential circuit (e.g., controller 150 described above), and may be provided with memory and / or registers to store any necessary intermediate values. Depending on the specific implementation, the memory and / or registers may be provided for a single pixel, a row of pixels, an entire image, etc. In either implementation, the pixel output undergoes an analog gain process before being converted to digital in ADC 450.

[0044] [Matched comparator active reset circuit]

[0045] Figure 5 An exemplary matched comparator configuration including an active reset circuit 500 and a pixel circuit 510 is shown. Although the pixel circuit 510 is illustrated as having its own matched comparator, other configurations are possible. For example, there may be one active reset circuit 500 per column, wherein the individual pixel circuits 510 in a given column share the active reset circuit 500 for that column. The pixel circuit 510 is illustrated as a 4T-type circuit, which includes a photodiode 501, a transfer transistor 502, a reset transistor 503, a source follower transistor 504, a select transistor 505, and a holding capacitor 508. As shown, the active reset circuit 500 shares the source follower transistor 504 and the select transistor 505 with the pixel circuit 510. The active reset circuit 500 additionally includes transistors 521 to 525 provided separately from the pixel circuit 510.

[0046] The transistor 522, the source follower transistor 504 and the select transistor 505 are set at the power supply voltage V dd2 The transistors 523 to 525 are set at the power supply voltage V dd2 and the column signal line 506. As described above, in the case where a plurality of pixel circuits 510 are connected or connectable to a single active reset circuit 500, a plurality of “first current paths” and one “second current path” may exist.

[0047] As shown, the gates of transistors 522 to 523 are connected to each other, and transistor 523 is arranged in a diode configuration. Transistor 525 is controlled by an active reset signal RST2 at its gate. The gate of transistor 524 receives an FD voltage reset signal RST3. Transistor 521 is set at a reset voltage V r With the power line V ddIn operation, transistors 521 and 525 are controlled to have opposite conductive states during operation of the associated image sensor. As shown, active / passive reset selection is achieved by having transistors 521 and 525 have opposite channel times and providing the same control signal RST2 to both of them at the same time. Therefore, when RST2 is high, transistor 521 is in the off state and transistor 525 is in the on state, and when RST2 is low, transistor 521 is in the on state and transistor 525 is in the off state. Alternatively, transistors 521 and 525 can have the same channel time and alternatively have opposite control signals provided to them.

[0048] Transistors 521 and 525 are used to control whether the pixel circuit 510 will perform a passive reset operation or an active reset operation. When RST2 is low, the pixel power supply voltage V dd Connect to reset voltage V r , while the second current path through transistors 523 to 525 is cut off by transistor 525. This allows a passive reset operation to be performed by controlling the reset signal RST. On the other hand, when RST2 is high, the pixel power supply voltage V dd The transistor 521 is reset from the voltage V r cut off, and when the selection signal SEL is also high, the first current path through transistors 504 to 505 and 522 and the second current path through transistors 523 to 525 are enabled to perform an active reset operation, thereby stabilizing the charge in the floating diffusion capacitor and resulting in a reset voltage with less variation.

[0049] [Single slope ADC]

[0050] A single slope ADC uses a ramp signal generated by a digital-to-analog converter (DAC) and measures the analog signal from the sensor by counting the time it takes for the ramp signal to cross the analog signal from the photodiode, providing a digital representation of the analog signal. Like all other types of ADCs, single slope ADCs are also affected by circuit noise. In sensor operation, high levels of analog gain can be used to amplify the photodiode signal above the circuit noise level of the amplifier and ADC circuits, allowing the image sensor to produce useful images at low light levels and low read noise. Therefore, the read noise level is an important parameter for image sensor implementations.

[0051] Figure 6 An exemplary pixel circuit and a single slope ADC are shown. Figure 6As shown, the 4T pixel circuit 610 is connected to the differential comparator 620 at one input of the differential comparator 620 through a signal line 606, and the other input of the differential comparator 620 receives a ramp signal from a DAC 630. The DAC 630 and the pixel circuit 610 provide their respective signals to the differential comparator 620 through a first coupling capacitor 641 and a second coupling capacitor 642, respectively.

[0052] As shown, pixel circuit 610 includes photodiode 601, transfer transistor 602, reset transistor 603, source follower transistor 604, select transistor 605, current source 607 and holding capacitor 608. Other pixel circuit designs (such as 3T or 5T+ configurations) can be used in similar arrangements. Differential comparator 620 includes transistors 621 to 629.

[0053] When sampling the analog signal from the pixel circuit 610 , the DAC 630 is operated to issue a ramp signal. Fig. 7A An exemplary set of signals is shown, where the analog signal from the pixel circuit 610 is shown as a solid line and the ramp signal generated by the DAC 630 is shown as a dotted line. Because CDS is performed, the ramp signal is operated for two measurement periods. In the first measurement period, the pixel circuit 610 is reset. Immediately before the first measurement period, the DAC 630 is reset to an initial level, and then the ramp signal decreases under the control of the DAC 630. When the ramp signal crosses the pixel signal, the digital comparator 620 changes state. Counting the time when this state change occurs in the DAC 630 provides a measurement of the P-phase signal.

[0054] Thereafter, the pixel circuit 610 is exposed to light and the DAC 630 restarts from the initial level and then ramps the signal down again. Counting the time when this subsequent state change occurs provides a measurement of the D-phase signal. The difference between the D-phase signal and the P-phase signal gives the output value of the pixel circuit 630.

[0055] In order to improve the accuracy of measurement, an automatic zero adjustment (AZ) function can be performed. AZ is performed by turning on transistors 622 and 626, thereby causing the two inputs of the differential comparator 620 to become equal. As a result, capacitors 641 and 642 are charged so that any DC imbalance on both sides of the differential comparator 620 causes capacitors 641 and 642 to be charged to an appropriate level. Even when transistors 622 and 626 are turned off, the charge in capacitors 641 and 642 can also be maintained. Therefore, the two inputs of the differential comparator 620 only sense the difference caused by the change of the pixel signal or the change of the ramp signal.

[0056] The AZ process can be interpreted as a process that stores variations due to circuit noise or other parameter differences in capacitors 641 and 642. When these variation signals are stored and taken into account, the AZ circuit effectively performs measurements without noise components (e.g., thermal noise in the pixel circuit, pass-through dispersion from the pixel circuit, offset errors in the source follower transistor, non-zero offsets in the two input terminals of the differential comparator, etc.). However, in a configuration where the image sensor utilizes a shared ADC structure in which multiple columns of pixels share one ADC, the AZ method cannot eliminate variations caused by pixel readout in different columns. This is because, even though each column may have different variations, columns that share a single ADC must use a single AZ setting; that is, a single stored value for each variation.

[0057] There may be additional sources of inaccuracy that are not eliminated by the AZ circuit. For example, the signal line from the pixel circuit 610 may drift by a non-zero amount ΔP during the P-phase measurement, such as Figure 7B This drift may be due to factors such as thermal noise in the AZ switches (transistors 622 and 626), switching noise due to non-zero on-resistance, parameter differences between comparators within the image sensor, different delays in the ramp signal, etc.

[0058] [Active reset using single slope ADC]

[0059] In order to further improve the measurement accuracy, an active reset method for a single slope ADC is preferably used. Figure 8 An exemplary active reset circuit 800 is shown using a 4T pixel circuit 810 and a single slope ADC that includes a differential comparator 820 and a DAC 830. As shown, the pixel circuit 810 includes a photodiode 801, a transfer transistor 802, a reset transistor 803, a source follower transistor 804, a select transistor 805, a current source 807, and a holding capacitor 808 (sometimes referred to as a "charge-to-voltage conversion capacitor" or a "floating diffusion capacitor"). The pixel circuit 810 is connected to the differential comparator 820 via a signal line 806. As described above, other pixel circuit designs (such as 3T or 5T+ configurations) can be used in a similar arrangement. The differential comparator 820 includes transistors 821, 823 to 825, and 827 to 829. That is, compared to the differential comparator 620, two transistors and two capacitors are omitted. In addition, compared to Figure 6In contrast, active reset circuit 800 has a connection from the comparator output line to the source of reset transistor 803. Because there is no capacitor between DAC 830 and the input of differential comparator 820, it may be preferable to rescale the reset level of DAC 830 to match the DC operating range of differential comparator 820.

[0060] To measure a pixel signal using the active reset circuit 800, the DAC 830 is initialized to a reset level; for example, the initial level described above. Thereafter, the reset signal RST is asserted to turn on the reset transistor 803. At this point, current flows from the output of the differential comparator 820 through the reset transistor 803, thereby charging the holding capacitor 808. This continues until the holding capacitor 808 is charged to a level that reaches an equilibrium state at the differential comparator 820. When this occurs, the differential comparator 820 has reached a neutral start-up state that takes into account all noise sources of the circuit, including resistance differences and capacitance differences of circuit elements, differences in parasitic resistance and capacitance, offsets such as comparator offsets, and timing differences. In particular, two potentially large noise sources are eliminated, namely, voltage variations in the source follower transistor 804 and mismatch variations in the differential comparator 820. After this step, the reset signal RST is deasserted to turn off the reset transistor 803, and the circuit is now ready to measure the photodiode signal.

[0061] Alternatively, a two-step reset transistor turn-off control may be applied. Fig. 9 803 is a two-step reset transistor turn-off control waveform diagram. In this configuration, the steps of resetting the DAC 830 and turning on the reset transistor 803 are the same as described above. At this time, the reset transistor 803 is in the on state, and the gate voltage of the reset transistor 803 is at a high level, as shown in FIG. Fig. 9 As shown in the first part of . Subsequently, the gate voltage of reset transistor 803 is reduced from a high level to an intermediate level. The intermediate level is slightly lower than the gate voltage threshold of reset transistor 803, so that reset transistor 803 is in a "weakly on" state. Finally, the gate voltage of reset transistor 803 is reduced to a low level. The low level is higher than the gate voltage threshold, so that reset transistor 803 is in an off state. Because reset transistor 803 is still conductive in the weakly on state, a more gradual method of transitioning reset transistor 803 to an off state allows capacitor 808 to be kept charged to a level that more accurately represents the changes in the circuit elements. In other words, the two-step reset transistor off control reduces through variation because it reduces the swing of reset transistor 803.

[0062] After performing the two-step reset transistor turn-off control, the same method as above can be used. Fig. 7A The P-phase and D-phase signals from the photodiode 801 are measured in the manner shown (i.e., by turning on a ramp signal from the DAC 830 and measuring the time required for the ramp signal to cross the pixel output signal). Because the noise variations of each specific ADC circuit are stored in the corresponding holding capacitor 808, a more accurate measurement of the P-phase and D-phase signals is obtained.

[0063] The active reset circuit 800 has many effects. For example, because active reset is performed when connected to a specific pixel circuit 810, the active reset circuit 800 is efficient in a column sharing scheme where multiple columns of pixels share a single ADC. In this case, when a measurement is made, the reset potential of each column is stored in the holding capacitor 803, thus overcoming the limitation of the conventional AZ method (whereby only one set of noise changes can be stored for each ADC).

[0064] In addition, active reset circuit 800 allows for more efficient use of silicon in image sensors. Figure 6 Compared to the circuit of FIG. 8 , two transistors and two capacitors are removed from each ADC. In image sensor implementations where thousands of ADCs operate in parallel, active reset circuit 800 results in a more efficient design that occupies a smaller area due to the reduced circuit elements.

[0065] In addition, the active reset circuit 800 controls the reset level of the floating diffusion in the pixel circuit 810 by feeding the output level of the differential comparator 820 and storing it in the holding capacitor 803. This allows the reset level of the circuit to be controlled by adjusting the reset level of the DAC 830. In this way, the dark current in the pixel circuit 810 can be minimized by resetting the pixel circuit 810 to the lowest voltage level required when supporting the dynamic range used at any given system gain (that is, at any analog gain of the circuit).

[0066] Furthermore, active reset circuit 800 allows analog-to-digital conversion of analog pixel signals at substantially the same speed as a single slope ADC that does not incorporate active reset, while still achieving full CDS and allowing high analog gain levels to be used.

[0067] [in conclusion]

[0068] With respect to the processes, systems, methods, heuristics, etc. described herein, it should be understood that although the steps of these processes, etc. have been described as occurring according to a certain ordered sequence, these processes may also be practiced using the described steps performed in an order other than the order described herein. It should also be understood that certain steps may be performed simultaneously, other steps may be added, or certain steps described herein may be omitted. In other words, the descriptions of the processes herein are provided for the purpose of illustrating certain embodiments and should in no way be construed as limiting the scope of the claims of the present invention.

[0069] Therefore, it should be understood that the above description is intended to be illustrative and not restrictive. After reading the above description, many embodiments and applications other than the examples provided will be understood. The scope of the present invention should not be determined with reference to the above description, but should be determined with reference to the full scope of the equivalents given by the appended claims and these claims. It is expected and anticipated that future developments will occur in the technology discussed herein, and the disclosed systems and methods will be incorporated into such future embodiments. In short, it should be understood that the present invention is capable of modification and variation.

[0070] As understood by those skilled in the art described herein, all terms used in the claims of the present invention are intended to be given their broadest reasonable constructions and their ordinary meanings unless otherwise expressly indicated herein. In particular, the use of singular articles such as "a", "an", "the", "said", etc. should be understood to describe one or more of the indicated elements unless a claim records an explicit limitation to the contrary.

[0071] The abstract of the present invention is provided to allow the reader to quickly determine the essence of the present technical disclosure. It should be understood that the submitted abstract will not be used to interpret or limit the scope or meaning of the claims. In addition, in the foregoing detailed description, it can be seen that in order to simplify the present disclosure, various features are combined together in various embodiments. The method of the present disclosure should not be interpreted as reflecting the intention that the claimed embodiments require more features than the features explicitly stated in each claim. The fact is that, as reflected in the attached claims, the subject matter of the present invention lies in less than all the features of a single disclosed embodiment. Therefore, the attached claims are also incorporated into the detailed description, wherein each claim is independently the subject matter of a separate claim.

Claims

1. A light detection device, comprising: a pixel circuit including a reset transistor and configured to output a pixel signal; a differential comparator including a pixel input, a reference input, and a comparator output; a first signal line connected to the pixel circuit and to the differential comparator; as well as A second signal line is connected to the source or drain of the reset transistor and to the comparator output, wherein when the reset transistor is turned on, current flows from the comparator output through the reset transistor until a balanced state is reached at the differential comparator.

2. The light detection device according to claim 1, further comprising: A digital-to-analog converter is configured to output a reference signal having a ramp waveform.

3. The light detection device according to claim 2, wherein: The differential comparator is configured to receive the pixel signal at the pixel input and the reference signal at the reference input and to output a representation of a digital signal.

4. The light detection device according to claim 2, wherein: The digital-to-analog converter is configured to be initialized to an initial signal level and then output the ramp waveform, at which time the differential comparator is configured to perform a P-phase measurement corresponding to a reset level of the pixel circuit, and The digital-to-analog converter is configured to subsequently reinitialize to the initial signal level and then output the ramp waveform, at which time the differential comparator is configured to perform a D-phase measurement corresponding to the data level of the pixel circuit.

5. The light detection device according to claim 4, wherein: The initial signal level is based on a system gain of the light detection device.

6. The light detection device according to claim 1, wherein: The gate of the reset transistor is configured to sequentially receive a high reset level, an intermediate reset level, and a low reset level.

7. The light detection device according to claim 6, wherein: The high reset level and the intermediate reset level are higher than a gate threshold of the reset transistor, and the low reset level is lower than a gate threshold of the reset transistor.

8. The light detection device according to claim 1, wherein The pixel circuit also includes a photodiode, a transfer transistor, a source follower transistor, and a holding capacitor.

9. The light detection device according to claim 8, wherein: The pixel circuit also includes a selection transistor.

10. The light detection device according to claim 1, wherein The pixel circuit is one of a plurality of pixel circuits arranged in a matrix, and The differential comparators correspond to a plurality of columns of the matrix.

11. An image processing method, comprising: outputting a pixel signal from a pixel circuit including a reset transistor via a first signal line; as well as outputting a differential signal from a differential comparator including a pixel input, a reference input, and a comparator output, The source or drain of the reset transistor is connected to the comparator output via a second signal line, wherein when the reset transistor is turned on, current flows from the comparator output through the reset transistor until a balanced state is reached at the differential comparator.

12. The image processing method according to claim 11, further comprising: A reference signal having a ramp waveform is output from the digital-to-analog converter.

13. The image processing method according to claim 12, further comprising: receiving the reference signal at the reference input of the differential comparator; and The pixel signal is received at the pixel input of the differential comparator.

14. The image processing method according to claim 12, further comprising: Initializing the digital-to-analog converter to an initial signal level and then outputting the ramp waveform; Then, performing a P-phase measurement corresponding to a reset level of the pixel circuit; Then, reinitializing the digital-to-analog converter to the initial signal level, and then outputting the ramp waveform; and Then, a D-phase measurement corresponding to the data level of the pixel circuit is performed.

15. The image processing method according to claim 14, wherein: The initial signal level is based on the system gain of the light detection device.

16. The image processing method according to claim 11, further comprising: At the gate of the reset transistor, a high reset level, an intermediate reset level and a low reset level are received in sequence.

17. The image processing method according to claim 16, wherein: The high reset level and the intermediate reset level are higher than a gate threshold of the reset transistor, and the low reset level is lower than a gate threshold of the reset transistor.

18. The image processing method according to claim 11, wherein: The pixel circuit also includes a photodiode, a transfer transistor, a source follower transistor, and a holding capacitor.

19. The image processing method according to claim 18, wherein: The pixel circuit also includes a selection transistor.

20. The image processing method according to claim 11, wherein: The pixel circuit is one of a plurality of pixel circuits arranged in a matrix, and The differential comparators correspond to a plurality of columns of the matrix.

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