RF semiconductor device and method of manufacturing the same

Abstract

The present disclosure relates to a radio frequency device including a transfer device die and a multi-layer redistribution structure located under the transfer device die. The transfer device die includes a device region and a transfer substrate, the device region having a back end of line (BEOL) portion and a front end of line (FEOL) portion located above the BEOL portion. The FEOL portion includes an isolation section and an active layer, the active layer being surrounded by the isolation section. A top surface of the device region is planarized. The transfer substrate including a porous silicon (PSi) region is located on the top surface of the device region. Herein, a porosity of the PSi region is 1% to 80%. The multi-layer redistribution structure includes a plurality of bump structures, the plurality of bump structures being located at a bottom of the multi-layer redistribution structure and electrically coupled to the FEOL portion of the transfer device die.

Description

Technical Field

[0001] This disclosure relates to a radio frequency (RF) device and its manufacturing process, and more specifically to an RF device having enhanced thermal and electrical properties, and a wafer-level manufacturing and packaging process for providing the RF device with enhanced properties. Background Technology

[0002] The widespread use of cellular and wireless devices has driven the rapid development of radio frequency (RF) technology. The substrate on which RF devices are fabricated plays a crucial role in achieving high levels of performance in RF technology. Fabricating RF devices on conventional silicon substrates benefits from low-cost silicon materials, large-scale wafer fabrication capabilities, well-developed semiconductor design tools, and advanced semiconductor manufacturing technologies. While conventional silicon substrates offer advantages for RF device fabrication, it is well-known in the industry that they can possess two undesirable properties for RF devices: harmonic distortion and low resistivity values. Harmonic distortion is a key obstacle to achieving high levels of linearity in RF devices built on silicon substrates.

[0003] Furthermore, high-speed and high-performance transistors are more densely integrated into RF devices. Therefore, due to the large number of transistors integrated on the RF device, a significant amount of power passes through the transistors, and / or the high operating speed of the transistors, the heat generated by the RF device will increase significantly. Therefore, it is desirable to package the RF device in a configuration that allows for better heat dissipation.

[0004] Wafer-level fan-out (WLFO) and embedded wafer-level ball grid array (eWLB) technologies are currently attracting widespread attention in portable RF applications. WLFO and eWLB technologies are designed to provide high-density input / output (I / O) ports without increasing package size. This capability allows for the dense packaging of RF devices within a single wafer.

[0005] To improve the operating speed and performance of RF devices, accommodate the increasing heat generation of RF devices, reduce harmful harmonic distortion of RF devices, and leverage the advantages of WLFO / eWLB technology, the object of this disclosure is to provide an improved wafer-level manufacturing and packaging process for RF devices with enhanced performance. Furthermore, there is a need to enhance the performance of RF devices without increasing device size. Summary of the Invention

[0006] This disclosure relates to a radio frequency (RF) device with enhanced performance and its manufacturing process. The disclosed RF device includes a transfer device die and a multilayer redistribution structure. The transfer device die includes a device region and a transfer substrate, the device region having a front-end-of-line (FEOL) portion and a back-end-of-line (BEOL) portion. Hereinafter, the FEOL portion is located above the BEOL portion and includes an isolation segment and an active layer surrounded by the isolation segment and not extending vertically beyond the isolation segment. The device region has a planarized top surface. The transfer substrate, including porous silicon (PSi) regions, is located above the top surface of the device region. Hereinafter, the porosity of the PSi regions is between 1% and 80%. The multilayer redistribution structure, including a plurality of protrusions, is formed beneath the BEOL portion of the transfer device die. The protrusions are located on the bottom surface of the multilayer redistribution structure and are electrically coupled to the FEOL portion of the transfer device die.

[0007] In one embodiment of the RF device, there is no silicon crystal without germanium, nitrogen, or oxygen content between the PSi region of the transfer substrate and the active layer within the device region.

[0008] In one embodiment of the RF device, the thermal conductivity of the PSi region is greater than 2 W / m·K and the resistivity is greater than 100 Ohm-cm.

[0009] In one embodiment of the RF device, the thickness of the PSi region is between 20 μm and 1000 μm.

[0010] In one embodiment of the RF device, the transfer substrate further includes a silicon processing region situated above the PSi region.

[0011] In one embodiment of the RF device, the thickness of the PSi region is between 20 μm and 1000 μm, and the thickness of the silicon-processed region is between [missing information]. Between 100μm and 100μm.

[0012] In one embodiment of the RF device, the active layer is formed of a strained silicon epitaxial layer, wherein the silicon in the strained silicon epitaxial layer has a lattice constant greater than 5.461 at a temperature of 300K.

[0013] In one embodiment of the RF device, the BEOL portion includes a connection layer, the FEOL portion further includes a contact layer, and the multilayer redistribution structure further includes redistributed interconnects. Herein, the active layer and the isolation section are located above the contact layer, and the BEOL portion is located below the contact layer. The protrusion structure is electrically coupled to the FEOL portion of the delivery device die via the redistributed interconnects within the multilayer redistribution structure and the connection layer within the BEOL portion.

[0014] In one embodiment of the RF device, the device region further includes a passivation layer situated above the active layer and surrounded by the isolation segments. Hereinafter, the passivation layer is formed of silicon dioxide. The top surface of each isolation segment is coplanar with the top surface of the passivation layer and forms the top surface of the device region.

[0015] In one embodiment of the RF device, the top surface of each isolation segment and the top surface of the active layer are coplanar and form the top surface of the device region.

[0016] In one embodiment of the RF device, the delivery device die further includes a barrier layer formed of silicon nitride, the barrier layer being coupled between the top surface of the device region and the PSi region of the delivery substrate.

[0017] According to another embodiment, an alternative RF device includes a delivery device die and a multilayer redistribution structure. The delivery device die includes a device region and a delivery substrate, the device region having a FEOL portion and a BEOL portion. Herein, the FEOL portion is situated above the BEOL portion and includes an isolation segment and an active layer surrounded by the isolation segment and not extending vertically beyond the isolation segment. The device region has a planarized top surface. The delivery substrate, including a PSi region, is situated above the top surface of the device region. The porosity of the PSi region is between 1% and 80%. The multilayer redistribution structure, formed beneath the BEOL portion of the delivery device die, extends horizontally beyond the delivery device die. The multilayer redistribution structure includes a plurality of protrusions situated on the bottom surface of the multilayer redistribution structure and electrically coupled to the FEOL portion of the delivery device die. The alternative RF device further includes a molding compound situated above the multilayer redistribution structure to encapsulate the delivery device die.

[0018] In one embodiment of the alternative RF device, there is no silicon crystal without germanium, nitrogen, or oxygen content between the PSi region of the transfer substrate and the active layer within the device region.

[0019] In one embodiment of the alternative RF device, the PSi region has a thermal conductivity greater than 2 W / m·K and a resistivity greater than 100 Ohm-cm.

[0020] In one embodiment of the alternative RF device, the thickness of the PSi region is between 20 μm and 1000 μm.

[0021] In one embodiment of the alternative RF device, the delivery substrate further includes a silicon processing region situated above the PSi region.

[0022] In one embodiment of the alternative RF device, the thickness of the PSi region is between 20 μm and 1000 μm, and the thickness of the silicon-processed region is between [missing information]. Between 100μm and 100μm.

[0023] In one embodiment of the alternative RF device, the active layer is formed of a strained silicon epitaxial layer, wherein the silicon in the strained silicon epitaxial layer has a lattice constant greater than 5.461 at a temperature of 300 K.

[0024] In one embodiment of the alternative RF device, the BEOL portion includes a connection layer, the FEOL portion further includes a contact layer, and the multilayer redistribution structure further includes redistributed interconnects. Herein, the active layer and the isolation section are located above the contact layer, and the BEOL portion is located below the contact layer. The protrusion structure is electrically coupled to the FEOL portion of the delivery device die via the redistributed interconnects within the multilayer redistribution structure and the connection layer within the BEOL portion.

[0025] In one embodiment of the alternative RF device, the device region further includes a passivation layer situated above the active layer and surrounded by the isolation segments. Herein, the passivation layer is formed of silicon dioxide. The top surface of each isolation segment is coplanar with the top surface of the passivation layer and forms the top surface of the device region.

[0026] In one embodiment of the alternative RF device, the top surface of each isolation segment and the top surface of the active layer are coplanar and form the top surface of the device region.

[0027] In one embodiment of the alternative RF device, the delivery device die further includes a barrier layer formed of silicon nitride, the barrier layer being coupled between the top surface of the device region and the PSi region of the delivery substrate.

[0028] According to an exemplary process, a precursor wafer is first provided, comprising multiple complete device regions, multiple individual interface layers, and a sacrificial silicon processing substrate. Each complete device region comprises a BEOL portion and a complete FEOL portion situated above the BEOL portion. The complete FEOL portion has an active layer and a complete isolation segment extending vertically beyond and surrounding the active layer. Herein, each individual interface layer is situated above an active layer and surrounded by the complete isolation segment of the corresponding complete device region. Each individual interface layer is formed of SiGe. The sacrificial silicon processing substrate is situated above each complete isolation segment and each individual interface layer. Next, the sacrificial silicon processing substrate is completely removed. The complete isolation segments are then thinned to provide a thinned wafer with a planarized top surface. The thinned wafer comprises multiple device regions, and the combination of the top surfaces of each device region forms the planarized top surface of the thinned wafer. Each device region comprises the BEOL portion and the FEOL portion situated above the BEOL portion. The FEOL portion has the active layer and the thinned isolation segment surrounding the active layer. A transfer substrate is attached to the top surface of the thinned wafer to provide a transfer device wafer comprising a plurality of transfer device dies. Herein, the transfer substrate comprises a porous silicon (PSi) region with a porosity between 1% and 80%. Each transfer device die includes a corresponding device region and a portion of the PSi region located above the corresponding device region.

[0029] In one embodiment of the exemplary process, there is no silicon crystal without germanium, nitrogen, or oxygen content between the PSi region of the transfer substrate and the active layer in the device region.

[0030] In one embodiment of the exemplary process, the thickness of the PSi region is between 20 μm and 1000 μm.

[0031] In one embodiment of the exemplary process, the transfer substrate further includes a silicon processing region situated above the PSi region. In this document, each transfer device die in the transfer device die further includes a portion of the silicon processing region situated above the portion of the PSi region.

[0032] In one embodiment of the exemplary process, the thickness of the PSi region is between 20 μm and 1000 μm, and the thickness of the silicon-processed region is between [missing information]. Between 100μm and 100μm.

[0033] According to another embodiment, the exemplary process further includes bonding the precursor wafer to a temporary carrier via a bonding layer before removing the sacrificial silicon processing substrate; and debonding the temporary carrier from the transfer device wafer and removing the bonding layer from the transfer device wafer after attaching the transfer substrate.

[0034] According to another embodiment, the exemplary process further includes forming a multilayer redistribution structure beneath the transfer device wafer. Herein, the multilayer redistribution structure includes a plurality of protrusions on the bottom surface of the multilayer redistribution structure and redistributed interconnects within the multilayer redistribution structure. Each protrusion is electrically coupled to an active layer of the corresponding transfer device die via the redistributed interconnects within the multilayer redistribution structure and a connection layer within the BEOL portion of the corresponding transfer device die.

[0035] According to another embodiment, the exemplary process further includes dicing the transfer device wafer into a plurality of individual transfer device dies. A molding compound is then applied around and over each individual transfer device die to provide a molded device wafer. Herein, the molding compound encapsulates the top and side surfaces of each individual transfer device die, while the bottom surface of each individual transfer device die is exposed. The bottom surface of the molded device wafer is a combination of the bottom surface of each individual transfer device die and the bottom surface of the molding compound. Next, a multilayer redistribution structure is formed beneath the molded device wafer. The multilayer redistribution structure includes a plurality of protrusions on the bottom surface of the multilayer redistribution structure and redistributed interconnects within the multilayer redistribution structure. Each protrusion is electrically coupled to an active layer of the corresponding individual transfer device die via the redistributed interconnects within the multilayer redistribution structure and a connection layer within the BEOL portion of the corresponding individual transfer device die.

[0036] According to another embodiment, the exemplary process further includes removing each individual interface layer after removing the sacrificial silicon processing substrate and before thinning the complete isolation segment. Thus, after the thinning step, the planarized top surface of each device region is formed by the top surface of the corresponding active layer and the top surface of the corresponding thinned isolation segment.

[0037] According to another embodiment, the exemplary process further includes removing each individual interface layer and applying a passivation layer over the corresponding active layer after removing the sacrificial silicon substrate and before thinning the complete isolation segment. Thus, after the thinning step, the planarized top surface of each device region is formed by the top surface of the corresponding passivation layer and the top surface of the corresponding thinned isolation segment.

[0038] In one embodiment of the exemplary process, the passivation layer is applied using one of a plasma-enhanced deposition process, an anodizing process, and an ozone-based oxidation process.

[0039] According to another embodiment, the exemplary process further includes applying a barrier layer over the top surface of the thinned wafer before attaching the transfer substrate to the thinned wafer. Hereinafter, the barrier layer is formed of silicon nitride.

[0040] In one embodiment of the exemplary process, providing the precursor wafer begins with providing a starter wafer comprising a common silicon epitaxial layer, a common interface layer over the common silicon epitaxial layer, and a sacrificial silicon processing substrate over the common interface layer. A complementary metal-oxide-semiconductor (CMOS) process is then performed to provide the precursor wafer. Herein, the complete isolation segment extends through the common silicon epitaxial layer and the common interface layer and into the sacrificial silicon processing substrate, such that the common interface layer is separated into the individual interface layers, and the common silicon epitaxial layer is separated into a plurality of individual silicon epitaxial layers. Each active layer is formed by a corresponding individual silicon epitaxial layer.

[0041] In one embodiment of the exemplary process, the sacrificial silicon substrate is removed by a mechanical polishing process followed by an etching process.

[0042] In one embodiment of the exemplary process, the sacrificial silicon substrate is removed by an etching process using an etchant chemical, which is at least one of tetramethylammonium hydroxide (TMAH), potassium hydroxide (KOH), sodium hydroxide (NaOH), acetylcholine (ACH), and xenon difluoride (XeF2).

[0043] In one embodiment of the exemplary process, the sacrificial silicon substrate is removed by a reactive ion etching system containing chlorine-based gas chemicals.

[0044] In one embodiment of the exemplary process, the transfer substrate is attached to the top surface of the thinned wafer by one of the following: anodic bonding, plasma bonding, and polymer adhesive bonding.

[0045] Those skilled in the art will understand the scope of this disclosure and recognize other aspects of it after reading the following detailed description of preferred embodiments in conjunction with the accompanying drawings. Attached Figure Description

[0046] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate several aspects of this disclosure and, together with the specification, serve to explain the principles of this disclosure.

[0047] Figure 1 An exemplary radio frequency (RF) device with enhanced performance is shown according to one embodiment of the present disclosure.

[0048] Figure 2 An alternative RF device with enhanced thermal and electrical performance according to one embodiment of the present disclosure is shown.

[0049] Figure 3A-16 The image shows the provided Figure 1 The exemplary wafer-level manufacturing and packaging process of the steps of the exemplary RF device shown.

[0050] Figure 17-22 The image shows the provided Figure 2 Alternative wafer-level manufacturing and packaging processes for the steps of the alternative RF device shown.

[0051] It should be understood that, for the sake of clarity, Figure 1-22 It is not necessary to draw it to scale. Detailed Implementation

[0052] The embodiments described below illustrate the necessary information to enable those skilled in the art to practice the embodiments and demonstrate the best manner in which the embodiments are practiced. Those skilled in the art will understand the concepts of this disclosure and recognize the application of these concepts not specifically set forth herein when reading the following description in conjunction with the accompanying drawings. It should be understood that these concepts and applications fall within the scope of this disclosure and the appended claims.

[0053] It should be understood that although the terms first, second, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. As used herein, the term "and / or" includes any and all combinations of one or more of the associated enumerations.

[0054] It should be understood that when an element such as a layer, region, or substrate is referred to as "on another element" or extends "to another element," it may be directly on or directly extended onto the other element, or intermediate elements may also exist. In contrast, when an element is referred to as "directly on another element" or "directly extended onto another element," no intermediate elements exist. Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as "on top of another element" or "extends over another element," it may be directly on or directly extended over the other element, or intermediate elements may also exist. In contrast, when an element is referred to as "directly on top of another element" or "extends directly over another element," no intermediate elements exist. It should also be understood that when an element is referred to as "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or intermediate elements may exist. In contrast, when an element is referred to as "directly connected" or "directly coupled" to another element, no intermediate elements exist.

[0055] In this document, relative terms such as “below,” “above,” “upper,” “lower,” “horizontal,” “vertical,” “over,” or “under” may be used to describe the relationship between one element, layer, or region and another, as shown in the figures. It should be understood that, in addition to the orientations depicted in the figures, these terms and those discussed above are intended to cover different orientations of the device.

[0056] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should be further understood that, when used herein, the terms “comprises,” “comprising,” “includes,” and / or “including” specify the presence of stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or combinations thereof.

[0057] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should be further understood that the terms used herein shall be interpreted as having the same meaning as they have in the context of this specification and the relevant field, and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0058] With anticipated shortages of conventional radio frequency silicon-on-insulator (RFSOI) wafers in the coming years, alternative technologies are being designed to utilize silicon wafers, trap-rich layer formation, and smart dicing SOI wafer processes to meet high resistivity requirements. One alternative technology is based on using a silicon-germanium (SiGe) interface layer between the silicon substrate and the silicon epitaxial layer instead of a buried oxide layer (BOX). However, this technology will still suffer from detrimental distortion effects caused by the silicon substrate, similar to those observed in RFSOI technology. This disclosure relates to a radio frequency (RF) device with enhanced performance, and a wafer-level fabrication and packaging process for manufacturing said device, which utilizes a SiGe interface layer without the detrimental distortion effects from the silicon substrate.

[0059] Figure 1 An exemplary RF device 10 with enhanced performance according to one embodiment of the present disclosure is shown. For the purposes of this illustration, the exemplary RF device 10 includes a delivery device die 12 having a device region 14 and a delivery substrate 15, and a multilayer redistribution structure 18 formed beneath the device region 14 of the delivery device die 12.

[0060] Specifically, device region 14 includes a front-end process (FEOL) portion 20 and a back-end process (BEOL) portion 22 located below the FEOL portion 20. In one embodiment, the FEOL portion 20 may be configured to provide a switching field-effect transistor (FET) and includes an active layer 24 and a contact layer 26. The active layer 24 may be formed of a relaxable silicon epitaxial layer or a strained silicon epitaxial layer and includes a source 28, a drain 30, and a channel 32 between the source 28 and the drain 30. Hereinafter, a relaxable silicon epitaxial layer refers to a silicon epitaxial layer in which the lattice constant of silicon is 5.431 at a temperature of 300 K. A strained silicon epitaxial layer refers to a silicon epitaxial layer in which the lattice constant of silicon is greater than that of the relaxable silicon epitaxial layer, such as greater than 5.461, or greater than 5.482, or greater than 5.493, or greater than 5.515. Thus, the electron mobility in strained silicon epitaxial layers can be enhanced compared to relaxed silicon epitaxial layers. Therefore, FETs formed from strained silicon epitaxial layers can switch at faster speeds compared to FETs formed from relaxed silicon epitaxial layers.

[0061] A contact layer 26 is formed beneath the active layer 24 and includes a gate structure 34, a source contact 36, a drain contact 38, and a gate contact 40. The gate structure 34 may be formed of silicon oxide and extends horizontally beneath a channel 32 (e.g., from beneath the source 28 to beneath the drain 30). The source contact 36 is connected to and beneath the source 28, the drain contact 38 is connected to and beneath the drain 30, and the gate contact 40 is connected to and beneath the gate structure 34. An insulating material 42 may be formed around the source contact 36, drain contact 38, gate structure 34, and gate contact 40 to electrically isolate the source 28, drain 30, and gate structure 34. In different applications, the FEOL section 20 may have different FET configurations or provide different device components, such as diodes, capacitors, resistors, and / or inductors.

[0062] Additionally, the FEOL portion 20 also includes an isolation section 44 situated above the insulating material 42 of the contact layer 26 and surrounding the active layer 24. The isolation section 44 is configured to electrically isolate the RF device 10, particularly the active layer 24, from other devices (not shown) formed in a common wafer. The isolation section 44 may be formed of silicon dioxide, which is resistant to etching chemicals such as tetramethylammonium hydroxide (TMAH), xenon difluoride (XeF2), potassium hydroxide (KOH), sodium hydroxide (NaOH), or acetylcholine (ACH), and is resistant to dry etching systems such as reactive ion etching (RIE) systems with chlorine-based gas chemicals.

[0063] In some applications, device region 14 further includes a passivation layer 48, which may be formed of silicon dioxide, to passivate the active layer 24. The passivation layer 48 is deposited over the top surface of the active layer 24 and is surrounded by an isolation section 44. In one embodiment, the top surface of the passivation layer 48 and the top surface of the isolation section 44 are coplanar. The passivation layer 48 is configured to terminate surface bonding of the active layer 24, which can be a cause of unwanted leakage.

[0064] In some applications, device region 14 further includes an interface layer and / or buffer structure (not shown) formed of SiGe, located above the top surface of active layer 24 and surrounded by isolation segment 44 (described in the following paragraphs, not shown herein). If passivation layer 48, buffer structure, and interface layer are present, the interface layer and buffer structure are vertically positioned between active layer 24 and passivation layer 48. Hereinafter, the top surface of passivation layer 48 and the top surface of isolation segment 44 are coplanar. If passivation layer 48 is omitted, and interface layer and / or buffer structure are present, the top surface of interface layer (or the top surface of buffer structure) and the top surface of isolation segment 44 are coplanar (not shown). If passivation layer 48, buffer structure, and interface layer are omitted, the top surface of active layer 24 and the top surface of isolation segment 44 are coplanar (not shown). It should be noted that regardless of the presence of the passivation layer 48, the buffer structure, and / or the interface layer, the top surface of the device region 14 (the combination of the top surface of the isolation section 44 and the top surface of the passivation layer 48, the combination of the top surface of the isolation section 44 and the top surface of the interface layer, the combination of the top surface of the isolation section 44 and the top surface of the buffer structure, or the combination of the top surface of the isolation section 44 and the top surface of the active layer 24) is always planarized.

[0065] A transfer substrate 15 comprising a porous silicon (PSi) region 16 and a silicon processing region 17 is located above the top surface of a device region 14. The PSi region 16 is coupled between the device region 14 and the silicon processing region 17. Herein, the silicon processing region 17 can be composed of conventional, low-cost, low-resistivity, and high-dielectric-constant silicon. The resistivity of the silicon processing region 17 can be between 0.02 Ohm-cm and 50 Ohm-cm. The PSi region 16 is formed of porous silicon, which is silicon in the form of silicon with nanopores introduced into its microstructure. The resistivity of the PSi region 16 is sensitive to the porosity within the PSi region 16. As the porosity of the PSi region 16 increases from 31% to 73%, the resistivity of the PSi region 16 can increase from 4565.8 Ohm-cm to 32133.7 Ohm-cm. Typically, the resistivity of the PSi region 16 is much higher than that of the silicon processing region 17. Furthermore, the thermal conductivity of the PSi region 16 is also related to its porosity. In one embodiment, the porosity of the PSi region 16 can be between 1% and 80%, with the pore size between 1 nm and 10000 nm. The resistivity of the PSi region 16 can be between 100 Ohm-cm and 1E12 Ohm-cm, and the thermal conductivity of the PSi region 16 can be between 2 W / m·K and 120 W / m·K.

[0066] The thickness of the PSi region 16 is based on the porosity of the PSi region 16, the resistance required to transfer the substrate 15, and the thermal performance required by the RF device 10. The thickness of the silicon processing region 17 is based on the device layout, the distance from the multilayer redistribution structure 18, and the details of the package and assembly. The thickness of the PSi region 16 can be between 2 μm and 1000 μm, while the thickness of the silicon processing region 17 can be between [missing information - likely a range or value]. Between 100μm and 100μm. Sometimes the silicon processing region 17 can be omitted.

[0067] In some applications, the delivery device die 12 may further include a barrier layer coupled between the top surface of the device region 14 and the PSi region 16 of the delivery substrate 15 (not shown). This barrier layer may be made of a material with a thickness between and Silicon nitride is formed between the active layer 14 and the passivation layer 48. The barrier layer is configured to provide excellent protection against moisture and impurities that may diffuse into the channel 32 of the active layer 24 and cause device reliability issues. Additionally, the barrier layer may be configured to enhance adhesion between the device region 14 and the PSi region 16 of the transfer substrate 15. It should be noted that regardless of the presence of the barrier layer, passivation layer 48, buffer structure, and / or interface layer, there is no silicon crystal without germanium, nitrogen, or oxygen content between the PSi region 16 and the top surface of the active layer 24. Each of the barrier layer, passivation layer 48, buffer structure, and interface layer is formed of a silicon composite.

[0068] The BEOL portion 22 is located below the FEOL portion 20 and includes a plurality of interconnect layers 50 formed within a dielectric layer 52. Some of the interconnect layers 50 (for internal connections) are encapsulated by the dielectric layer 52 (not shown), while some of the interconnect layers 50 have bottom portions not covered by the dielectric layer 52. Some of the interconnect layers 50 are electrically connected to the FEOL portion 20. For the purposes of this illustration, one of the interconnect layers 50 is connected to the source contact 36, and another interconnect layer 50 is connected to the drain contact 38.

[0069] The multilayer redistribution structure 18 formed beneath the BEOL portion 22 of the delivery device die 12 includes a plurality of redistributed interconnects 54, dielectric patterns 56, and a plurality of protrusions 58. Herein, each redistributed interconnect 54 is connected to a corresponding interconnect layer 50 within the BEOL portion 22 and extends above the bottom surface of the BEOL portion 22. The connection between the redistributed interconnects 54 and the interconnect layer 50 is solderless. Dielectric patterns 56 are formed around and beneath each redistributed interconnect 54. Some of the redistributed interconnects 54 (connecting the delivery device die 12 to other device components formed from the same wafer) may be encapsulated by the dielectric patterns 56 (not shown), while some of the redistributed interconnects 54 have bottom portions exposed through the dielectric patterns 56. Each protrusion 58 is formed at the bottom surface of the multilayer redistribution structure 18 and is electrically coupled to a corresponding redistributed interconnect 54 via the dielectric patterns 56. Thus, the redistributed interconnect 54 is configured to electrically connect the protrusion structure 58 to certain interconnect layers in the FEOL portion 20 of the connection layer 50 in the BEOL portion 22. Therefore, the protrusion structure 58 is electrically connected to the FEOL portion 20 via the corresponding redistributed interconnect 54 and the corresponding connection layer 50. Furthermore, the protrusion structures 58 are separated from each other and protrude from the dielectric pattern 56.

[0070] In some applications, additional redistributed interconnects (not shown) electrically coupled to the redistributed interconnects 54 via dielectric pattern 56, and additional dielectric patterns (not shown) formed beneath dielectric pattern 56, can expose the bottom portions of some of the additional redistributed interconnects. Thus, each bump structure 58 is coupled to a corresponding additional redistributed interconnect via an additional dielectric pattern (not shown). Regardless of the number of layers of redistributed interconnects and / or dielectric patterns, the multilayer redistributed structure 18 may be glass fiber-free or glass-free. Herein, glass fiber refers to individual glass filaments twisted into larger groups. These glass filaments can then be woven into a fabric. The redistributed interconnects 54 can be formed of copper or other suitable metals. The dielectric pattern 56 can be formed of benzocyclobutene (BCB), polyimide, or other dielectric materials. The bump structure 58 can be solder balls or copper pillars. The thickness of the multilayer redistributed structure 18 is between 2 μm and 300 μm.

[0071] Figure 2 It shows the same as Figure 1Compared to the RF device 10 shown, an alternative RF device 10A further includes a molding compound 60. In this document, the multilayer redistribution structure 18 may extend horizontally beyond the delivery device die 12, and the molding compound 60 is located on the multilayer redistribution structure 18 to encapsulate the delivery device die 12. In this embodiment, the redistribution interconnects 54 of the multilayer redistribution structure 18 may extend horizontally beyond the delivery device die 12, and the protrusions 58 of the multilayer redistribution structure 18 may not be confined to the periphery of the delivery device die 12. The molding compound 60 may be an organic epoxy resin system, etc.

[0072] Figure 3A-16 Provided demonstration of manufacturing Figure 1 The exemplary wafer-level fabrication and packaging process of the exemplary RF device 10 shown is illustrated. Although the exemplary steps are shown as a series, the exemplary steps are not necessarily dependent on the order. Some steps may be performed in a different order than presented. Furthermore, the process within the scope of this disclosure may include more than Figure 3A-16 The steps shown are fewer or more.

[0073] First, such as Figure 3A and 3B The diagram shows a starting wafer 62. The starting wafer 62 includes a common silicon epitaxial layer 64, a common interface layer 66 over the common silicon epitaxial layer 64, and a sacrificial silicon processing substrate 68 over the common interface layer 66. Hereinafter, the common silicon epitaxial layer 64 is formed of device-grade silicon material having the silicon epitaxial properties desired for forming an electronic device. The sacrificial silicon processing substrate 68 may be composed of conventional low-cost, low-resistivity, and high-dielectric-constant silicon with a lattice constant of approximately 5.431 at a temperature of 300 K. The common interface layer 66 is formed of SiGe, which separates the common silicon epitaxial layer 64 from the sacrificial silicon processing substrate 68.

[0074] At a fixed temperature, such as 300 K, the lattice constant of relaxor silicon is... And relaxation Si 1-x Ge x The lattice constant depends on the germanium concentration, such as The lattice constant of relaxed SiGe is greater than that of relaxed silicon. If the common interface layer 66 is grown directly beneath the sacrificial silicon substrate 68, the lattice constant in the common interface layer 66 will be strained (reduced) by the sacrificial silicon substrate 68. If the common silicon epitaxial layer 64 is grown directly beneath the common interface layer 66, the lattice constant in the common silicon epitaxial layer 64 can remain in its original relaxed form (approximately the same as the lattice constant in the silicon substrate). Therefore, the common silicon epitaxial layer 64 may not enhance electron mobility.

[0075] In one embodiment, a common buffer structure 70 may be formed between the sacrificial silicon substrate 68 and the common interface layer 66, such as Figure 3A As shown, the common buffer structure 70 allows the lattice constant to transition from the sacrificial silicon processed substrate 68 to the common interface layer 66. The common buffer structure 70 may comprise multiple layers and may be formed of SiGe with vertically graded germanium concentrations. The germanium concentration within the common buffer structure 70 can increase from 0% at the top side (near the sacrificial silicon processed substrate 68) to X% at the bottom side (near the common interface layer 66). X% may depend on the germanium concentration within the common interface layer 66, such as 15%, 25%, 30%, or 40%. In this paper, the common interface layer 66 grown beneath the common buffer structure 70 can maintain its lattice constant in a relaxed manner and can be strain-free (reduced) to match the lattice constant of the sacrificial silicon processed substrate 68. The germanium concentration can be uniform throughout the common interface layer 66 and greater than 15%, 25%, 30% or 40%, such that at a temperature of 300 K, the lattice constant of the relaxed SiGe in the common interface layer 66 is greater than 5.461, or greater than 5.482, or greater than 5.493 or greater than 5.515.

[0076] In this paper, the common silicon epitaxial layer 64 is grown directly beneath the relaxed common interface layer 66, such that the lattice constant of the common silicon epitaxial layer 64 matches (stretched to) the lattice constant in the relaxed common interface layer 66. Therefore, at a temperature of 300 K, the lattice constant in the strained common silicon epitaxial layer 64 can be greater than 5.461, or greater than 5.482, or greater than 5.493, or greater than 5.515, and thus greater than the lattice constant in the relaxed silicon epitaxial layer (e.g., 5.431 at 300 K). The electron mobility of the strained common silicon epitaxial layer 64 can be higher than that of the relaxed silicon epitaxial layer. The thickness of the common silicon epitaxial layer 64 can be between 700 nm and 2000 nm, and the thickness of the common interface layer 66 can be between [missing information - likely a specific value]. and The thickness of the common buffer structure 70 can be between 100 nm and 1000 nm, and the thickness of the sacrificial silicon substrate 68 can be between 200 μm and 700 μm.

[0077] In another embodiment, the common interface layer 66 can be formed directly beneath the sacrificial silicon substrate 68, and the common buffer structure 70 can be formed between the common interface layer 66 and the common silicon epitaxial layer 64, such as... Figure 3BAs shown. In this paper, the lattice constant of the common interface layer 66 can be strained (reduced) due to the sacrificial silicon-processed substrate 68. The common buffer structure 70 can still be formed of SiGe with vertically graded germanium concentrations. The germanium concentration within the common buffer structure 70 can be increased from 0% at the top side (near the common interface layer 66) to X% at the bottom side (near the common silicon epitaxial layer 64). X% can be 15%, 25%, 30%, or 40%. The lattice constant at the bottom side of the common buffer structure 70 is greater than the lattice constant at the top side of the common buffer structure 70. In this paper, the lattice constant of the common silicon epitaxial layer 64 grown beneath the common buffer structure 70 matches (stretched to) the lattice constant at the bottom side of the common buffer structure 70. Therefore, the lattice constant in the strained common silicon epitaxial layer 64 is greater than the lattice constant in the relaxed silicon epitaxial layer (e.g., 5.431 at 300 K).

[0078] In some applications, the common buffer structure 70 (not shown) is omitted. The common interface layer 66 is grown directly beneath the sacrificial silicon substrate 68, and the common silicon epitaxial layer 64 is grown directly beneath the common interface layer 66. Thus, the lattice constant in the common interface layer 66 is strained (reduced) to match the lattice constant in the sacrificial silicon substrate 68, while the lattice constant in the common silicon epitaxial layer 64 remains in its original relaxed form (approximately the same as the lattice constant in the silicon substrate).

[0079] Next, for the starting wafer 62 (in Figure 3A (in the middle) perform complementary metal-oxide-semiconductor (CMOS) process to provide a precursor wafer 72 with multiple complete device regions 14', such as Figure 4 As shown, each complete device region 14' comprises a complete FEOL portion 20' and a BEOL portion 22 located beneath the complete FEOL portion 20', the complete FEOL portion having an active layer 24, a contact layer 26, and a complete isolation segment 44'. For illustrative purposes, the complete FEOL portion 20' is configured to provide a switching FET. In different applications, the complete FEOL portion 20' may have different FET configurations or provide different device components such as diodes, capacitors, resistors, and / or inductors.

[0080] In one embodiment, a complete isolation segment 44' of each complete device region 14' extends through a common silicon epitaxial layer 64, a common interface layer 66, and a common buffer structure 70, and extends into a sacrificial silicon processing substrate 68. Thus, the common buffer structure 70 is split into multiple individual buffer structures 70I, the common interface layer 66 is split into multiple individual interface layers 66I, and the common silicon epitaxial layer 64 is split into multiple individual silicon epitaxial layers 64I. Each individual silicon epitaxial layer 64I is used to form a corresponding active layer 24 within a complete device region 14'. The complete isolation segment 44' can be formed using shallow trench isolation (STI). If the active layer 24 is formed from a single silicon epitaxial layer 64I with a strained (increased) lattice constant, a FET based on the active layer 24 can have a faster switching speed (lower on-resistance) than a FET formed from a relaxed silicon epitaxial layer with a relaxed lattice constant.

[0081] The top surface of the active layer 24 contacts the corresponding interface layer 66I located beneath the corresponding buffer structure 70I. A sacrificial silicon processing substrate 68 lies on each individual buffer structure 70I, and a portion of the sacrificial silicon processing substrate 68 may lie on the entire isolation segment 44'. The BEOL portion 22 of the complete device region 14', comprising at least the plurality of interconnect layers 50 and dielectric layer 52, is formed beneath the contact layer 26 of the complete FEOL portion 20'. Bottom portions of some interconnect layers 50 are exposed through the dielectric layer 52 located at the bottom surface of the BEOL portion 22.

[0082] After the precursor wafer 72 is completed, the precursor wafer 72 is then bonded to the temporary carrier 74, as follows: Figure 5 As shown, the precursor wafer 72 can be bonded to the temporary carrier 74 via a bonding layer 76 that provides a planarized surface for the temporary carrier 74. From a cost and thermal expansion perspective, the temporary carrier 74 can be a thick silicon wafer, but it can also be constructed from glass, sapphire, or any other suitable carrier material. The bonding layer 76 can be a span-on polymeric adhesive film, such as Brewer Science's WaferBOND temporary adhesive series.

[0083] The sacrificial silicon substrate 68 is then selectively removed to provide the etched wafer 78, as... Figure 6As shown, selective removal stops at each individual buffer structure 70I or each interface layer 66I. The removal of the sacrificial silicon substrate 68 can be achieved by providing an opening 79 above each active layer 24 and within the complete isolation segment 44'. The removal of the sacrificial silicon substrate 68 can be achieved through a mechanical polishing process and an etching process, or by the etching process itself. As an example, the sacrificial silicon substrate 68 can be polished to a thinner thickness to reduce subsequent etching time. The etching process is then performed to at least completely remove the remaining sacrificial silicon substrate 68. Because the sacrificial silicon substrate 68, the individual buffer structures 70I, and the individual interface layers 66I have different germanium concentrations, they may react differently to the same etching technique (e.g., different etching rates under the same etchant). Therefore, the etching system can be able to identify the presence of the individual buffer structures 70I or the individual interface layers 66I (the presence of germanium) and can indicate when to stop the etching process. Generally, the higher the germanium concentration, the better the etch selectivity between the sacrificial silicon substrate 68 and the individual buffer structures 70I (or between the sacrificial silicon substrate 68 and the individual interface layers 66I). The etching process can be provided by a wet etching system with etching chemicals, which are at least one of TMAH, KOH, NaOH, ACH and XeF2, or by a dry etching system such as a reactive ion etching system with chlorine-based gaseous chemicals.

[0084] During the removal process, the complete isolation segment 44' is not removed and the sides of each active layer 24 are protected. The bonding layer 76 and the temporary carrier 74 protect the bottom surface of each BEOL portion 22. In this document, after the removal step, the top surface of each complete isolation segment 44' and the top surface of each individual buffer structure 70I (or each individual interface layer 66I) are exposed. Due to the narrow gap nature of the SiGe material, the individual buffer structure 70I and / or the individual interface layer 66I may be conductive (for some types of devices). The individual buffer structure 70I and / or the individual interface layer 66I may cause significant leakage between the source 28 and drain 30 of the active layer 24. Therefore, in some applications such as FET switching applications, it is also desirable to remove the individual buffer structure 70I and the individual interface layer 66I, such as... Figure 7As shown, each active layer 24 is exposed at the bottom of the corresponding opening 79. The individual buffer structure 70I and the individual interface layer 66I can be removed using the same etching process used to remove the sacrificial silicon processing substrate 68, or by an alternative etching process such as a chlorine-based dry etching system. In this context, if each individual interface layer 66I is thin enough, it may not cause any noticeable leakage between the source 28 and drain 30 of the FEOL portion 20. In this case, the individual interface layer 66I (not shown) can be left intact. Similarly, if both the individual interface layer 66I and the individual buffer structure 70I are thin enough, they may not cause any noticeable leakage between the source 28 and drain 30 of the FEOL portion 20, allowing the individual interface layer 66I and the individual buffer structure 70I (not shown) to be left intact.

[0085] In some applications, after removing the sacrificial silicon processing substrate 68, the separate buffer structure 70I, and the separate interface layer 66I, each active layer 24 can be passivated to achieve a suitable low level of current leakage in the device. A passivation layer 48 can be formed over each active layer 24 and within the opening 79 of each complete FEOL portion 20', as shown below. Figure 8 As shown, the passivation layer 48 can be formed from silicon dioxide using plasma-enhanced deposition, anodic oxidation, ozone-based oxidation, and a variety of other suitable techniques. The passivation layer 48 is configured to terminate surface bonding at the top surface of the active layer 24, which could be a cause of unwanted leakage.

[0086] Next, the complete isolation segment 44' is thinned to become isolation segment 44, to provide a thinned wafer 80 with a planarized top surface, as shown. Figure 9 As shown, the thinned wafer 80 includes a plurality of device regions 14, and the combination of the top surfaces of each device region 14 forms the planarized top surface of the thinned wafer 80. Hereinafter, if a passivation layer 48 is applied, the top surface of each passivation layer 48 is coplanar with the top surface of each isolation segment 44. If the passivation layer 48 is omitted, and a separate interface layer 66I and / or a separate buffer structure 70I are present, the top surface of each separate interface layer 66I (or the top surface of each separate buffer structure 70I) is coplanar with the top surface of each isolation segment 44 (not shown). If the passivation layer 48, the separate buffer structure 70I, and the separate interface layer 66I are omitted, the top surface of each active layer 24 is coplanar with the top surface of each isolation segment 44 (not shown). Regardless of the presence of the passivation layer 48, the separate buffer structure 70I, and / or the separate interface layer 66I, the top surface of each device region 14 is always planarized. The planarization step can be accomplished using a chemical mechanical polishing (CMP) process with appropriate slurry and polishing wheel, etc.

[0087] Figure 10A and 10C An exemplary process for manufacturing the transfer substrate 15 is shown. Figure 10A In this process, a precursor silicon processing substrate 82 is provided, which can be composed of conventional, low-cost, low-resistivity, and high-dielectric-constant silicon. The resistivity of the precursor silicon processing substrate 82 can be between 0.02 Ohm-cm and 50 Ohm-cm. Next, a low-dose high-energy ion (such as boron) is implanted into the precursor silicon processing substrate 82 to provide an intermediate substrate 84, such as... Figure 10B As shown, the lower portion of the precursor silicon processing substrate 82 forms a buried region 86 in the intermediate substrate 84, while the upper portion of the precursor silicon processing substrate 82 remains unchanged as the silicon processing region 17 in the intermediate substrate 84. When the intermediate substrate 84 is annealed in nitrogen at a temperature between 600°C and 1200°C, the silicon lattice properties in the buried region 86 are restored. Ions (such as boron) in the buried region 86 are essentially fully activated. An electrochemical etching process is then performed to provide a transfer substrate 15 containing the PSi region 16 formed by the buried region 86, as shown. Figure 10C As shown, the silicon-treated region 17 remains unchanged. The electrochemical etching process requires applying a bias voltage across the intermediate substrate 84 and immersing the intermediate substrate 84 in a suitable wet chemical solution. For example, a bias of 0.4V-1V for a duration of several minutes (5-15 minutes) and a chemical solution of hydrofluoric acid:isopropanol (HF:IPA) in a 4:1 ratio can be used to transform the boron-doped buried region 86 into a high-quality p-type PSi portion 16 while keeping the silicon-treated region 17 unchanged.

[0088] The resistivity of PSi region 16 is significantly higher than that of silicon-processed region 17 (the upper portion of the precursor silicon-processed substrate 82). In one embodiment, the porosity of PSi region 16 can be between 1% and 80%, with pore sizes between 1 nm and 10,000 nm. The resistivity of PSi region 16 can be between 100 Ohm-cm and 1E12 Ohm-cm, and the thermal conductivity of PSi region 16 can be between 2 W / m·K and 120 W / m·K. The thickness of PSi region 16 can be between 20 μm and 1000 μm, while the thickness of silicon-processed region 17 is between [missing information - likely a specific thickness]. Between 100 μm and 100 μm. Sometimes, the precursor silicon processing substrate 82 can be fully transferred to the PSi region 16 (not shown).

[0089] Then, the transfer substrate 15 is bonded to the top surface of the thinned wafer 80 to provide the transfer device wafer 88, as shown. Figure 11As shown, the PSi region 16 is located above the top surface of the thinned wafer 80, and the silicon processing region 17 is located above the PSi region 16. Thus, the PSi region, which has excellent resistivity and thermal conductivity, is close to each active layer 24. In addition, since the top surface of the thinned wafer 80 is planarized, the transfer device wafer 88 has no voids or defects at the bonding region.

[0090] The transfer device wafer 88 includes a plurality of transfer device dies 12, each of which includes at least a device region 14, a portion of a PSi region 16, and a portion of a silicon processing region 17. Various suitable low-temperature bonding processes can be employed in this step, such as anodic bonding, plasma bonding, polymer adhesive bonding, etc. During the bonding process of the transfer substrate 15, a temporary carrier 74 provides mechanical strength and rigidity to the thinned wafer 80.

[0091] In some applications, a barrier layer (not shown) may be formed on the top surface of the thinned wafer 80 prior to bonding the transfer substrate 15. This barrier layer may be made of a material with a thickness between [missing information - likely a thickness range] and Silicon nitride is formed between the layers. The barrier layer is configured to provide excellent protection against moisture and impurities that may diffuse into the channels 32 of each active layer 24. Additionally, the barrier layer can be configured to enhance adhesion between the thinned wafer 80 and the transfer substrate 15. It should be noted that regardless of the presence of the barrier layer, passivation layer 48, or the individual interface layer 66I, there is no silicon crystal without germanium, nitrogen, or oxygen content between the PSi region 16 and the top surface of each active layer 24. Each of the barrier layer, passivation layer 48, and the individual interface layer 66I is formed of a silicon composite.

[0092] Then, the temporary carrier 74 is decoupled from the transfer device wafer 88, and the bonding layer 76 is removed from the transfer device wafer 88, as follows: Figure 12As shown. Depending on the properties of the temporary carrier 74 and bonding layer 76 selected in the previous steps, various debonding and removal processes can be applied. For example, the temporary carrier 74 can be mechanically debonded using a lateral blade process while the stack is heated to a suitable temperature. If the temporary carrier 74 is formed of a transparent material, other suitable processes involve UV light irradiation through the temporary carrier or chemical debonding using a suitable solvent. The bonding layer 76 can be removed by wet etching or dry etching processes such as proprietary solvents and plasma cleaning. After the debonding and removal processes, the bottom portions of certain bonding layers in the bonding layer 50 that can serve as input / output (I / O) ports for each transfer device die 12 are exposed through the dielectric layer 52 at the bottom surface of each BEOL portion 22. Thus, each transfer device die 12 in each transfer device wafer 88 can then be electrically verified to determine that the transfer device die is functioning correctly.

[0093] refer to Figures 13 to 15 According to one embodiment of this disclosure, a multilayer redistribution structure 18 is formed under the transfer device wafer 88. Although the redistribution steps are shown in series, the redistribution steps are not necessarily dependent on the order. Some steps may be performed in a different order than presented. Furthermore, the redistribution steps within the scope of this disclosure may include more than Figure 13-15 The steps shown are fewer or more.

[0094] First, multiple redistributed interconnects 54 are formed under each BEOL section 22, such as Figure 13 As shown, each redistributed interconnect 54 is electrically coupled to the exposed bottom portion of the corresponding interconnect layer 50 within the BEOL portion 22 and can extend above the bottom surface of the BEOL portion 22. The connection between the redistributed interconnect 54 and the interconnect layer 50 is solderless. A dielectric pattern 56 is then formed under each BEOL portion 22 to partially encapsulate each redistributed interconnect 54, as shown. Figure 14 As shown. Thus, the bottom portion of each redistributed interconnect 54 is exposed by the dielectric pattern 56. In different applications, there may be additional redistributed interconnects (not shown) electrically coupled to the redistributed interconnects 54 by the dielectric pattern 56, as well as additional dielectric patterns (not shown) formed under the dielectric pattern 56, such that the bottom portion of each additional redistributed interconnect is exposed.

[0095] Next, multiple bump structures 58 are formed to complete the multilayer redistribution structure 18, and a wafer-level fan-out (WLFO) type package 90 is provided, such as Figure 15As shown, each protrusion 58 is formed at the bottom of the multilayer redistribution structure 18 and is electrically coupled to the exposed bottom portion of the corresponding redistribution interconnect 54 via the dielectric pattern 56. Therefore, the redistribution interconnect 54 is configured to electrically connect the protrusion 58 to certain interconnect layers in the FEOL portion 20 of the connection layer 50 in the BEOL portion 22. Thus, the protrusion 58 is electrically connected to the FEOL portion 20 via the corresponding redistribution interconnect 54 and the corresponding connection layer 50. Furthermore, the protrusions 58 are separate from each other and protrude vertically from the dielectric pattern 56.

[0096] The multilayer redistribution structure 18 may be glass fiber-free or glass-free. Herein, glass fiber refers to individual glass filaments twisted into larger groups. These glass filaments can then be woven into a fabric. The redistribution interconnects 54 can be formed of copper or other suitable metals, the dielectric pattern 56 can be formed of BCB, polyimide, or other dielectric materials, and the protrusions 58 can be solder balls or copper pillars. The thickness of the multilayer redistribution structure 18 is between 2 μm and 300 μm. Figure 16 The final step of dicing the WLFO package 90 into individual RF devices 10 is shown. This dicing step can be achieved through a probe and dicing process at certain isolation sections 44.

[0097] In another embodiment, Figure 17-22 Provided demonstration of manufacturing Figure 2 Alternative processes to the steps of the alternative RF device 10A shown. Although exemplary steps are shown in series, the exemplary steps are not necessarily dependent on the order. Some steps may be performed in a different order than presented. Furthermore, processes within the scope of this disclosure may include more than Figure 17-22 The steps shown are fewer or more.

[0098] like Figure 12 As shown, after the debonding and cleaning processes to provide a clean transfer device wafer 88, a dicing step is performed to dice the transfer device wafer 88 into individual transfer device dies 12, as follows: Figure 17 As shown, this single-cut step can be provided by probing and dicing processes at certain isolation sections 44. In this document, each transfer device die 12 may have the same height and at least include a device region 14 with FEOL portion 20 and BEOL portion 22, and a transfer substrate 15.

[0099] Next, a molding compound 60 is applied around and over the delivery device die 12 to provide a molding device wafer 92, such as Figure 18As shown, molding compound 60 encapsulates the top and side surfaces of each transfer device die 12, while the bottom surface of each transfer device die 12, i.e., the bottom surface of the BEOL portion 22, is exposed. The bottom surface of the molding device wafer 92 is a combination of the bottom surface of each transfer device die 12 and the bottom surface of molding compound 60. Herein, the bottom portions of certain interconnect layers in interconnect layer 50 remain exposed at the bottom surface of each transfer device die 12. Molding compound 60 can be applied through various processes, such as sheet molding, overmolding, compression molding, transfer molding, dike filling encapsulation, or screen printing encapsulation. Unlike the transfer substrate 15, molding compound 60 has no thermal conductivity or resistivity requirements. Molding compound 60 can be an organic epoxy resin system, etc. A curing process (not shown) is then used to harden molding compound 60. The curing temperature is between 100°C and 320°C, depending on the material used as molding compound 60. A grinding process (not shown) can be performed to provide a planarized top surface of the molding compound 60.

[0100] refer to Figures 19 to 21 A multi-layer redistribution structure 18 is formed according to one embodiment of this disclosure. Although the redistribution steps are shown in series, the redistribution steps are not necessarily dependent on the order. Some steps may be performed in a different order than presented. Furthermore, the redistribution steps within the scope of this disclosure may include more than Figure 19-21 The steps shown are fewer or more.

[0101] First, multiple redistributed interconnects 54 are formed under the molding device wafer 92, such as... Figure 19 As shown. Each redistributed interconnect 54 is electrically coupled to a corresponding interconnect layer 50 within the BEOL portion 22 and can extend horizontally beyond the corresponding delivery device die 12 and extend horizontally under the molding compound 60. The connection between the redistributed interconnect 54 and the interconnect layer 50 is solderless. A dielectric pattern 56 is then formed under the molding device wafer 92 to partially encapsulate each redistributed interconnect 54, as shown. Figure 20 As shown. Thus, the bottom portion of each redistributed interconnect 54 is exposed by the dielectric pattern 56. In different applications, there may be additional redistributed interconnects (not shown) electrically coupled to the redistributed interconnects 54 by the dielectric pattern 56, as well as additional dielectric patterns (not shown) formed under the dielectric pattern 56, such that the bottom portion of each additional redistributed interconnect is exposed.

[0102] Next, multiple raised structures 58 are formed to complete the multilayer redistribution structure 18, and an alternative WLFO package 90A is provided, such as Figure 21As shown, each protrusion 58 is formed at the bottom of the multilayer redistribution structure 18 and is electrically coupled to the exposed bottom portion of the corresponding redistribution interconnect 54 via the dielectric pattern 56. Therefore, the redistribution interconnect 54 is configured to electrically connect the protrusion 58 to certain interconnect layers in the FEOL portion 20 of the connection layer 50 in the BEOL portion 22. Thus, the protrusion 58 is electrically connected to the FEOL portion 20 via the corresponding redistribution interconnect 54 and the corresponding connection layer 50. In this document, the protrusion 58 may not be limited to the periphery of the corresponding delivery device die 12. Furthermore, the protrusions 58 are separate from each other and protrude vertically from the dielectric pattern 56.

[0103] Figure 22 The final step of slicing the alternative WLFO package 90A into individual alternative RF devices 10A is shown. The slicing step can be provided by probing and cutting a portion of the molding compound 60, which is horizontally located between adjacent delivery device dies 12.

[0104] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of this disclosure. All such improvements and modifications are considered to be within the scope of the concepts disclosed herein and the following claims.

Claims

1. A radio frequency device, comprising: The transfer device die includes a device region and a transfer substrate, wherein: The device region includes a front-end process portion and a back-end process portion located below the front-end process portion, wherein the front-end process portion includes an isolation section and an active layer; The bottom surface of the active layer is substantially coplanar with the bottom surface of each isolation segment, the active layer does not extend vertically beyond the top surface of each isolation segment, and the active layer is surrounded by the isolation segment; The top surface of the device region, including the top surface of the isolation section, is planarized; and The transfer substrate, including porous silicon PSi regions, is situated above the top surface of the device region, wherein the porosity of the PSi regions is 1% to 80%, and the PSi regions are in contact with the top surface of each isolation segment; and A multi-layer redistribution structure is formed beneath the back-end process portion of the transfer device die, wherein the multi-layer redistribution structure includes a plurality of protrusions located on the bottom surface of the multi-layer redistribution structure and electrically coupled to the front-end process portion of the transfer device die.

2. The radio frequency device of claim 1, wherein there is no silicon crystal without germanium, nitrogen, or oxygen content between the PSi region of the transfer substrate and the active layer in the device region.

3. The radio frequency device according to claim 1, wherein the thermal conductivity of the PSi region is greater than 2 W / m·K and the resistivity is greater than 100 Ohm-cm.

4. The radio frequency device according to claim 1, wherein the thickness of the PSi region is from 20 µm to 1000 µm.

5. The radio frequency device of claim 1, wherein the transfer substrate further includes a silicon processing region located above the PSi region.

6. The radio frequency device of claim 5, wherein the thickness of the PSi region is from 20 µm to 1000 µm, and the thickness of the silicon-processed region is from 100 Å to 100 µm.

7. The radio frequency device of claim 1, wherein the active layer is formed of a strained silicon epitaxial layer, and the silicon in the strained silicon epitaxial layer has a lattice constant greater than 5.461 Å at a temperature of 300 K.

8. The radio frequency device according to claim 1, wherein: The back-end process includes a connection layer; The front-end process portion further includes a contact layer, wherein the active layer and the isolation section are located above the contact layer, and the back-end process portion is located below the contact layer; and The multilayer redistribution structure further includes a redistribution interconnect, wherein the plurality of protrusion structures are electrically coupled to the front-end process portion of the delivery device die through the redistribution interconnect within the multilayer redistribution structure and the connection layer within the back-end process portion.

9. The radio frequency device of claim 1, wherein the device region further comprises a passivation layer, the passivation layer being situated above the active layer and surrounded by the isolation segment, wherein: The passivation layer is formed of silicon dioxide; and The top surface of each isolation section and the top surface of the passivation layer are coplanar and form the top surface of the device region.

10. The radio frequency device of claim 1, wherein the top surface of each isolation segment and the top surface of the active layer are coplanar and form the top surface of the device region.

11. The radio frequency device of claim 1, wherein the delivery device die further comprises a barrier layer formed of silicon nitride, the barrier layer being coupled between the top surface of the device region and the PSi region of the delivery substrate.

12. The radio frequency device of claim 1, wherein the isolation section is formed of silicon dioxide.

13. A radio frequency device comprising: The transfer device die includes a device region and a transfer substrate, wherein: The device region includes a front-end process portion and a back-end process portion located below the front-end process portion, wherein the front-end process portion includes an isolation section and an active layer; The bottom surface of the active layer is substantially coplanar with the bottom surface of each isolation segment, the active layer does not extend vertically beyond the top surface of each isolation segment, and the active layer is surrounded by the isolation segment; The top surface of the device region, including the top surface of the isolation section, is planarized; and The transfer substrate, including a porous silicon PSi region, is located above the top surface of the device region, wherein the porosity of the PSi region is 1% to 80%, and the PSi region is in contact with the top surface of each isolation segment; A multi-layer redistribution structure is formed beneath the back-end process portion of the delivery device die, wherein: The multi-layered redistribution structure extends horizontally beyond the core of the delivery device; and The multilayer redistribution structure includes a plurality of protrusions located on the bottom surface of the multilayer redistribution structure and electrically coupled to the front-end process portion of the delivery device die; and A molding compound, which is situated on the multilayer redistribution structure to encapsulate the delivery device die.

14. The radio frequency device of claim 13, wherein there is no silicon crystal without germanium, nitrogen, or oxygen content between the PSi region of the transfer substrate and the active layer in the device region.

15. The radio frequency device of claim 13, wherein the thermal conductivity of the PSi region is greater than 2 W / m·K and the resistivity is greater than 100 Ohm-cm.

16. The radio frequency device of claim 13, wherein the thickness of the PSi region is from 20 µm to 1000 µm.

17. The radio frequency device of claim 13, wherein the transfer substrate further includes a silicon processing region located above the PSi region.

18. The radio frequency device of claim 17, wherein the thickness of the PSi region is from 20 µm to 1000 µm, and the thickness of the silicon-processed region is from 100 Å to 100 µm.

19. The radio frequency device of claim 13, wherein the active layer is formed of a strained silicon epitaxial layer, wherein the lattice constant of silicon in the strained silicon epitaxial layer is greater than 5.461 Å at a temperature of 300 K.

20. The radio frequency device according to claim 13, wherein: The back-end process includes a connection layer; The front-end process portion further includes a contact layer, wherein the active layer and the isolation section are located above the contact layer, and the back-end process portion is located below the contact layer; and The multilayer redistribution structure further includes a redistribution interconnect, wherein the plurality of protrusion structures are electrically coupled to the front-end process portion of the delivery device die through the redistribution interconnect within the multilayer redistribution structure and the connection layer within the back-end process portion.

21. The radio frequency device of claim 13, wherein the device region further comprises a passivation layer, the passivation layer being situated above the active layer and surrounded by the isolation segment, wherein: The passivation layer is formed of silicon dioxide; and The top surface of each isolation section and the top surface of the passivation layer are coplanar and form the top surface of the device region.

22. The radio frequency device of claim 13, wherein the top surface of each isolation segment and the top surface of the active layer are coplanar and form the top surface of the device region.

23. The radio frequency device of claim 13, wherein the delivery device die further comprises a barrier layer formed of silicon nitride, the barrier layer being coupled between the top surface of the device region and the PSi region of the delivery substrate.

24. The radio frequency device of claim 13, wherein the isolation section is formed of silicon dioxide.

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