Transistor device and method of forming the same

Abstract

This application relates to a transistor device and a method of forming a transistor device. A LDMOS transistor device can be provided, including a substrate having a conductive region therein, a first isolation structure disposed within the substrate, a source region and a drain region disposed within the conductive region, a second isolation (local isolation) structure disposed between the source region and the drain region, and a gate structure disposed at least partially within the second isolation structure. The first isolation structure can extend along at least a portion of the boundary of the conductive region, and the depth of the second isolation structure can be less than the depth of the first isolation structure. During use, a channel for an electron flow can be formed along at least a portion of the side surface of the gate structure disposed within the second isolation (local isolation) structure.

Description

Technical Field

[0001] This application generally relates to transistor devices and methods of forming such transistor devices. Background Art

[0002] Transistor devices are widely used in many applications to amplify or switch electrical signals. One type of transistor device is a laterally-diffused metal-oxide semiconductor (LDMOS) device, which is often used in radio frequency (RF) power amplifiers for mobile networks. An LDMOS device typically includes a source, a drain, and a gate therebetween, where the source and the drain are disposed in respective wells having different conductivity types. When a sufficiently large gate voltage is applied to the gate of the LDMOS device, a channel can be formed in the well where the source is disposed, thereby allowing current flow between the source and the drain.

[0003] Conventional LDMOS devices often suffer from problems such as high on-resistance, low breakdown voltage, and high switching losses. So far, several techniques have been developed to solve these problems. For example, an electrically insulating structure can be included in the well where the drain is disposed to increase the breakdown voltage of the device. However, the increase in the breakdown voltage may not be sufficient, and the on-resistance and switching losses of such LDMOS devices are still high. Additionally, the fabrication of conventional LDMOS devices often involves several etching processes. These processes are very time-consuming and tend to introduce errors, which may affect the performance of the resulting LDMOS devices. Summary of the Invention

[0004] According to various non-limiting embodiments, a transistor device can be provided. The transistor device can include: a substrate in which a conductive region is provided; a first isolation structure disposed in the substrate, where the first isolation structure can extend along at least a portion of a boundary of the conductive region; a source region and a drain region disposed in the conductive region; a second isolation structure disposed between the source region and the drain region, where a depth of the second isolation structure can be less than a depth of the first isolation structure; and a gate structure disposed at least partially in the second isolation structure.

[0005] According to various non - limiting embodiments, a method of forming a transistor device can be provided. The method can include: providing a substrate; forming a conductive region in the substrate; forming a first isolation structure in the substrate, wherein the first isolation structure can extend along at least a portion of a boundary of the conductive region; forming a second isolation structure in the conductive region, wherein a depth of the second isolation structure can be less than a depth of the first isolation structure; forming a gate structure at least partially within the second isolation structure; and forming source and drain regions in the conductive region such that the second isolation structure can be disposed between the source region and the drain region. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] In these drawings, like reference numerals generally represent the same components in different views. Additionally, these drawings are not necessarily drawn to scale, but generally emphasize the principles of the present invention. Now, non - limiting embodiments of the present invention will be described by way of example only with reference to the following drawings, in which:

[0007] Figure 1A and 1B respectively show a simplified top view and a simplified cross - sectional view of a transistor device according to various non - limiting embodiments;

[0008] Figures 2A through 2L show a method of forming a transistor device according to various non - limiting embodiments Figure 1A and 1B in a simplified cross - sectional view;

[0009] Figure 3 show Figure 1A and 1B of the transistor device in a simplified cross - sectional view during use of the transistor device;

[0010] Figure 4 show Figure 1A and 1B of the transistor device and a graph of the drain current versus gate voltage relationship of another transistor device;

[0011] Figure 5 show a simplified cross - sectional view of a transistor device according to an alternative non - limiting embodiment;

[0012] Figure 6 show a simplified cross - sectional view of a transistor device according to an alternative non - limiting embodiment; and

[0013] Figure 7 show an example transmission electron microscopy (TEM) cross - sectional image of an isolation structure that can be used in a transistor device for Figure 1A and 1B 5 or 6. Detailed Embodiments

[0014] Embodiments generally relate to semiconductor devices. In particular, some embodiments relate to transistor devices. For example, some embodiments may relate to LDMOS transistor devices. For example, such transistor devices may be included in power amplifiers and switches.

[0015] The embodiments of the present invention and their specific features, advantages, and details will be more fully explained below with reference to the non - limiting examples shown in the accompanying drawings. Descriptions of known materials, manufacturing tools, processing techniques, etc. are omitted so as not to obscure the present invention unnecessarily in details. However, it should be understood that although the detailed description and specific examples indicate embodiments of the present invention, they are for illustrative purposes only and not restrictive. Those skilled in the art will appreciate from this application various alternatives, modifications, additions, and / or arrangements within the spirit and / or scope of the basic inventive concept.

[0016] Approximating language, as used herein in the specification and claims, may be applied to modify any quantitative representation that allows for change without resulting in a change in the relevant basic function. Thus, a value modified by one or more terms such as "about" or "approximately" is not limited to the specified exact value. In some cases, such approximating language may correspond to the precision of the instrument used to measure the value. Additionally, a direction modified by one or more terms such as "substantially" refers to a direction that will be within the ordinary tolerances of the semiconductor industry. For example, "substantially parallel" means extending generally in the same direction within the ordinary tolerances of the semiconductor industry, and "substantially perpendicular" means at an angle of ninety degrees plus or minus the ordinary tolerances of the semiconductor industry.

[0017] The terms used herein are for the purpose of describing particular embodiments only and are not intended to limit the present invention. Unless otherwise expressly stated in the context, the singular forms "a", "an", and "the" as used herein are also intended to include the plural forms. It should also be understood that the terms "comprise" (and any form of comprise, such as "comprises" and "comprising"), "have" (and any form of have, such as "has" and "having"), "include" (and any form of include, such as "includes" and "including"), and "contain" (and any form of contain, such as "contains" and "containing") are open-ended linking verbs. Thus, a method or apparatus that "comprises", "has", "includes", or "contains" one or more steps or elements has those one or more steps or elements, but is not limited to only those one or more steps or elements. Similarly, a method step or apparatus element that "comprises", "has", "includes", or "contains" one or more features has those one or more features, but is not limited to only those one or more features. Moreover, an apparatus or structure configured in a particular manner is configured at least in that manner, but may also be configured in ways not listed.

[0018] As used herein, the term "connect" when referring to two physical elements means a direct connection between the two physical elements. However, the term "couple" may mean a direct connection or a connection through one or more intermediate elements.

[0019] As used herein, the terms "can" and "may" indicate that something can occur within a set of circumstances; has a specified property, characteristic, or function; and / or modifies another verb (by expressing one or more abilities, functions, or possibilities associated with the restricted verb). Thus, the use of "can" and "may" indicates that the modified term is clearly suitable, able, or adapted to the indicated performance, function, or use, while allowing for the possibility that in some cases, the modified term may not be suitable, able, or applicable. For example, in some cases, an event or performance may be expected, while in other cases, the event or performance may not occur, and the terms "can" and "may" are used to reflect this distinction.

[0020] Figure 1A Shows a simplified top view of a transistor device 100 according to various non-limiting embodiments. Figure 1B Shows a simplified cross-sectional view of the transistor device 100 along Figure 1A line A-A' of the transistor device 100. The transistor device 100 may be an LDMOS transistor device.

[0021] The transistor device 100 may include a substrate 102. The substrate 102 may be a semiconductor substrate. For example, the substrate 102 may include a semiconductor material such as, but not limited to, silicon (Si), germanium (Ge), silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), or a combination thereof.

[0022] The substrate 102 may include a conductive region 104 disposed therein. The conductive region 104 may be a high-voltage well region. A body region 106 and a drift region 108 may also be disposed within the substrate 102, particularly within the conductive region 104. As Figure 1B shown, the drift region 108 may be adjacent to the body region 106. The drift region 108 and the body region 106 may be disposed along the top surface 102t of the substrate 102. In addition, the depth D 106 of the body region 106 may be less than the depth D 108 of the drift region 108. The depth D 108 of the drift region 108 may be configured based on the voltage (Vdd) to be supplied to the transistor device 100.

[0023] The transistor device 100 may further include a source region 110 and a drain region 112. The source region 110 may be disposed within the conductive region 104 (particularly, the body region 106), and the drain region 112 may be disposed within the conductive region 104 (particularly, the drift region 108). In addition, the transistor device 100 may include a body contact 114 disposed within the body region 106, wherein the body contact 114 may be adjacent to the source region 110. The source region 110, the drain region 112, and the body contact 114 may be disposed along the top surface 102t of the substrate 102.

[0024] The transistor device 100 may be a positive-channel metal-oxide semiconductor (PMOS) device. In particular, the substrate 102, the drift region 108, the source region 110, and the drain region 112 may have a first conductivity type, or in other words, may include dopants having a first conductivity type. The conductive region 104, the body region 106, and the body contact 114 may have a second conductivity type different from the first conductivity type, or in other words, may include dopants having a second conductivity type. For example, the substrate 102, the drift region 108, the source region 110, and the drain region 112 may have p-type conductivity, while the conductive region 104, the body region 106, and the body contact 114 may have n-type conductivity. P-type dopants may include boron (B), indium (In), or a combination thereof; while n-type dopants may include phosphorus (P), arsenic (As), antimony (Sb), or a combination thereof.

[0025] The transistor device 100 may further include a first isolation structure 116 disposed within the substrate 102. The first isolation structure 116 may extend along at least a portion of the boundary of the conductive region 104. As used herein, "border" refers to the surface of the conductive region 104 facing the first isolation structure 116. In Figure 1A the "border" is represented by a dashed line. For example, as Figure 1A shown, the first isolation structure 116 may surround the conductive region 104. In other words, the first isolation structure 116 may extend along the entire boundary of the conductive region 104. However, the first isolation structure 116 may alternatively extend only along a portion of the boundary of the conductive region 104. For example, the first isolation structure 116 may be disposed along at least 50% of the boundary of the conductive region 104; or, the first isolation structure 116 may be disposed along at least 70% of the boundary of the conductive region 104, or even may be disposed along at least 90% of the boundary of the conductive region 104.

[0026] As Figure 1B more clearly shown, the first isolation structure 116 may be partially disposed within the conductive region 104. However, the first isolation structure 116 may alternatively be completely disposed outside the conductive region 104 but adjacent to the boundary of the conductive region 104, for example, contacting the surface of the conductive region 104 facing the first isolation structure 116. Additionally, as Figure 1B shown, the first isolation structure 116 may be adjacent to the body region 106 and the drift region 108. Although in Figure 1B it is shown that the transistor device 100 has a portion of the body region 106 located between the body contact 114 and the first isolation structure 116 and has a portion of the drift region 108 located between the drain region 112 and the first isolation structure 116, the first isolation structure 116 may alternatively be adjacent to one or both of the drain region 112 and the body contact 114. The first isolation structure 116 may be a shallow trench isolation (STI) structure and may include an isolation material. The isolation material may be a dielectric material or a gap-fill oxide, such as but not limited to silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. The depth D 116 of the first isolation structure 116 may be approximately equal to the depth of the isolation structure of a typical isolation device and may be equal to or greater than 300 nanometers when the transistor device 100 is fabricated using an 180 nanometer (nm) to 130 nanometer technology node. For example, the depth D 116 of the first isolation structure 116 may be about 320 nanometers. However, if other technology nodes are used to fabricate the transistor device 100, the depth D 116 of the first isolation structure 116 may be different.

[0027] The transistor device 100 may further include a second isolation structure 120 disposed within the substrate 102. The second isolation structure 120 may be entirely disposed within the conductive region 104, particularly within the drift region 108. In other words, the second isolation structure 120 may be a local isolation structure. As Figure 1B shown, the second isolation structure 120 may be disposed between the source region 110 and the drain region 112. The second isolation structure 120 may be laterally spaced from the drain region 112, or in other words, a portion of the drift region 108 may be disposed between the second isolation structure 120 and the drain region 112. In particular, the second isolation structure 120 may be an ultra-shallow trench isolation (USTI) structure and may similarly include an isolation material, such as a dielectric material or a gap-fill oxide (e.g., but not limited to silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof). Additionally, the top surface 120t of the second isolation structure 120 may be substantially laterally aligned with the top surface 116t of the first isolation structure 116 and the top surface 102t of the substrate 102. The depth D of the second isolation structure 120 120 is less than the depth D of the first isolation structure 116 116 . For example, the depth D of the second isolation structure 120 120 may range from one-third of the depth D of the first isolation structure 116 116 to two-thirds of the depth D of the first isolation structure 116 116 . In particular, when the transistor device 100 is fabricated using a 180-nanometer to 130-nanometer technology node, the depth D of the second isolation structure 120 120 may be equal to or less than 120 nanometers. For example, the depth D of the second isolation structure 120 120 may be approximately 120 nanometers. However, if other technology nodes are used to fabricate the transistor device 100, the depth D of the second isolation structure 120 120 may be different.

[0028] The transistor device 100 may further include a gate structure 122 disposed at least partially within the second isolation structure 120. The gate structure 122 may be a vertical gate structure. In particular, as Figure 1B shown, a first portion 1221 of the gate structure 122 may be disposed within the second isolation structure 120, and a second portion 1222 of the gate structure 122 may be disposed above the substrate 102. In Figure 1B , it is shown that the second portion 1222 of the gate structure 122 has a trench 1222R located above the first portion 1221 of the gate structure 122, but in an alternative non-limiting embodiment, this trench 1222R may be absent.

[0029] Please refer to Figure 1B, one side surface 122a of the gate structure 122 facing the source region 110 can be vertically aligned with one side surface 120a of the second isolation structure 120, and a part 1201 of the second isolation structure 120 can extend from the gate structure 122 towards the drain region 112. As Figure 1B shown, a part 1201 of the second isolation structure 120 can extend beyond the gate structure 122. The body region 106 can be disposed between the first isolation structure 116 and the gate structure 122. The gate structure 122 can be adjacent to the body region 106 along the side surface 122a of the gate structure 122, and the second isolation structure 120 can be adjacent to the body region 106 along the side surface 120a of the second isolation structure 120. As Figure 1B shown, the source region 110 can be disposed within the body region 106 and can be spaced apart from the gate structure 122. In other words, a part of the body region 106 can be disposed between the source region 110 and the gate structure 122. As will be described in detail below with reference to Figure 3 , a vertical channel region can be formed in the body region 106 along at least a part of the side surface 122a of the gate structure 122. Additionally, the depth D 106 of the body region 106 can be 120 between the depth D 1221 of the second isolation structure 120 and the depth D 1221 of the gate structure 122 disposed within the second isolation structure 120 (in other words, the depth D 106 of the first part 1221 of the gate structure 122). In particular, the depth D 106 can be less than the depth D 120 but greater than the depth D 1221 .

[0030] Please refer to Figure 1B , the gate structure 122 can include a gate oxide layer 124 and a gate element 126. The gate oxide layer 124 can extend along the top surface 102t of the substrate 102 above the body region 106, along the body region 106 and the second isolation structure 120, and further along the top surface 102t of the substrate 102 above the second isolation structure 120. The gate element 126 can be disposed above the gate oxide layer 124. The gate oxide layer 124 can include a gate oxide material, such as but not limited to silicon dioxide; however, the gate element 126 can include a conductive material, such as but not limited to polysilicon or a metal (e.g., titanium nitride, tantalum nitride, tungsten, its alloy, or its combination).

[0031] The transistor device 100 can further include spacer walls 127a, 127b, 127c, 127d disposed along the side surfaces of the gate element 126. The spacer walls 127a, 127b, 127c, 127d can include a dielectric material, such as but not limited to silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. For clarity of illustration, Figure 1AThe spacer walls 127a, 127b, 127c, and 127d are not shown.

[0032] The transistor device 100 may further include a silicide blocking layer 128 that extends from above the second portion 1222 of the gate structure 122 to the top surface 102t of the substrate 102. As Figure 1B shown, the silicide blocking layer 128 may also extend along the top surface 102t of the substrate 102 between the gate structure 122 and the drain region 112. Additionally, the silicide blocking layer 128 may overlap with the drain region 112. The silicide blocking layer 128 may be a silicon alignment block (SAB) oxide layer and may include a blocking material such as, but not limited to, silicon oxide, silicon nitride, or a combination thereof.

[0033] As Figure 1B shown, the transistor device 100 may further include an insulating layer 130 disposed above the substrate 102. The second portion 1222 of the gate structure 122 and the silicide blocking layer 128 may be disposed within the insulating layer 130. The insulating layer 130 may be an inter-layer dielectric (ILD) layer and may include an insulating material such as, but not limited to, silicon oxide, silicon dioxide, silicon nitride, or a combination thereof.

[0034] As Figure 1A shown, the transistor device 100 may further include a plurality of first contacts 150 disposed above and in contact with the body region 114 and the source region 110, a plurality of second contacts 152 disposed above and in contact with the gate structure 122, a plurality of third contacts 154 disposed above and in contact with the drain region 112, and a plurality of fourth contacts 156 (which may be ground region contacts) disposed above and in contact with the substrate 102. The first, second, third, and fourth contacts 150, 152, 154, 156 may be conductive contacts including a conductive material such as, but not limited to, aluminum, copper, tungsten, their alloys, or a combination thereof.

[0035] Figures 2A through 2L A simplified cross-sectional view showing a method of forming the transistor device 100 according to various non-limiting embodiments is shown. For clarity of illustration, certain reference numerals are omitted from Figures 2A through 2L the figure.

[0036] Please refer to Figure 2A and 2B, the method may include providing a substrate 102 and forming a first isolation structure 116 and a second isolation structure 120 within the substrate 102. To form the first isolation structure 116, the substrate 102 may be etched to form an opening, and the opening may be filled with an isolation material. Subsequently, the second isolation structure 120 may be formed similarly by etching the substrate 102 to form an opening and filling the opening with an isolation material. Alternatively, the openings of both the first and second isolation structures 116, 120 may be filled with an isolation material simultaneously. Additionally, after filling the opening with the isolation material, a planarization process (e.g., a chemical mechanical polishing (CMP) process) may be performed to remove the isolation material outside the substrate 102, so that the top surfaces 116t, 120t of the isolation structures 116, 120 may be aligned with each other and with the top surface 102t of the substrate 102.

[0037] Please refer to Figure 2C , the method may further include forming a conductive region 104 within the substrate 102 and forming a drift region 108 within the conductive region 104. The conductive region 104 and the drift region 108 may be formed by depositing dopants in corresponding regions of the substrate 102.

[0038] Please refer to Figures 2D - 2H , the method may further include forming a gate structure 122 at least partially within the second isolation structure 120. As Figure 2D shown, a mask 202 having an opening 202a may be formed above the substrate 102. As Figure 2E shown, the substrate 102 may be etched through the opening 202a of the mask 202 to form a trench 204 extending into the second isolation structure 120. As Figure 2F shown, a gate oxide material layer 206 may be formed above the substrate 102, with a portion thereof formed within the trench 204. The gate oxide material layer 206 may be a thermal oxide formed by oxidizing the surface of the substrate 102. As Figure 2G shown, a conductive material layer 208 may then be formed above the gate oxide material 206, and similarly, a portion thereof is formed within the trench 204. As Figure 2H shown, a portion of the gate oxide material 206 and a portion of the conductive material 208 may be removed (e.g., by a single etching process using another mask) to form the gate structure 122. In particular, the remaining gate oxide material 206 may form a gate oxide layer 124, and the remaining conductive material 208 may form a gate element 126.

[0039] Please refer to Figure 2I, the method may further include forming a body region 106 within the conductive region 104. To form the body region 106, another mask 210 having an opening 210a may be formed over the substrate 102 and over the gate structure 122. Next, dopants may be deposited into the substrate 102 through the opening 210a of the another mask 210. As shown by arrow 250, the dopants may be deposited into the substrate 102 at an angle substantially perpendicular to the top surface 102t of the substrate 102.

[0040] Please refer to Figure 2J , the method may further include forming spacer walls 127a, 127b, 127c, 127d along the sides of the gate element 126. The spacer walls 127a, 127b, 127c, 127d may be formed by depositing a dielectric material over the substrate 102 and the gate element 126 and etching the dielectric material.

[0041] Please refer to Figure 2K , the method may further include forming a source region 110, a drain region 112, and a body contact 114. The source region 110, the drain region 112, and the body contact 114 may be formed by implanting dopants into the respective regions 106, 108 using, for example, ion implantation. Alternatively, the source region 110, the drain region 112, and the body contact 114 may be formed by forming a mask over the substrate 102 and doping the respective regions of the substrate 102 through the openings of these masks.

[0042] Please refer to Figure 2L , the method may further include forming a silicide blocking layer 128. To form the silicide blocking layer 128, a blocking material may be deposited over the gate structure 122 and the substrate 102, and the blocking material may be etched. The method may further include forming an insulating layer 130 by depositing an insulating material over the substrate 102.

[0043] The above sequence for the method is for illustrative purposes only, and unless otherwise specifically stated, the method is not limited to the order specifically described above.

[0044] Figure 3 Showing the transistor device 100 during use, the substrate 102, the drift region 108, the source region 110, and the drain region 112 have p-type conductivity, while the conductive region 104, the body region 106, and the body contact 114 have n-type conductivity. Also, for clarity of illustration, certain reference numerals are omitted from Figure 3 the drawings.

[0045] As Figure 3 shown in, when the transistor device 100 is in use, a gate voltage (VG) large enough may be applied to the gate structure 122 to form a vertical channel region C within a portion of the body region 106 below the gate structure 122 and along the side 122a of the gate structure 122106 As shown in Figure 3 the vertical channel region C 106 has a length L C106 which can be approximately equal to the depth D of the first part 1221 of the gate structure 122. 1221 By further applying a voltage difference (drain voltage (VD) - source voltage (VS)) between the source region 110 and the drain region 112, electrons can flow from the source region 110 to the drain region 112 (as shown by the arrow 302). As shown in Figure 3 the electrons can flow through the vertical channel region C 106 and through the drift region 108 located below the second isolation structure 120. The source voltage VS, the gate voltage VG, and the drain voltage VD can be applied using the first, second, and third contacts 150, 152, and 154 provided above the source region 110, the gate structure 122, and the drain region 112, respectively. Since the first contact 150 can be provided above both the body contact 114 and the source region 110, the body contact 114 and the source region 110 can be connected to the same voltage VS. It should be understood that if the first conduction type and the second conduction type are n-type and p-type, respectively, the flow of electrons can be in the opposite direction, in particular, from the drain region 112 to the source region 110.

[0046] Compared with the transistor devices of the prior art, the transistor device 100 can have a higher breakdown voltage (BV), a lower on-resistance (Ron), and improved switching performance, such as lower switching losses. In other words, the transistor device 100 can have improved performance parameters, such as an improved figure-of-merit (FOM = Ron × BV), an improved Baliga figure-of-merit (BFOM = BV 2 / Ron), and an improved Ron × Qgg parameter, where Qgg represents the gate charge of the transistor device 100.

[0047] For example, by using the second isolation structure 120 with a smaller depth D 120 the doped region of the drift region 108 can be larger and the electric field in the drift region 108 can be reduced. Therefore, the second isolation structure 120 can help reduce the on-resistance of the device 100. Figure 4Display plots 402, 404, which respectively illustrate the drain current-gate voltage (ID-VG) relationships of the transistor device 100 and a transistor device similar to the transistor device 100 but with the second isolation structure 120 replaced by an isolation structure similar to the first isolation structure 116. The plots 402, 404 are obtained with the drain voltage (VD) set to 0.05V. As Figure 4 shown, in the case where the second isolation structure 120 is present in the drift region 108 of the drain region 112 that can be set, the on-resistance of the transistor device 100 can be reduced and the linear drain current ID can be improved Lin .

[0048] Moreover, partially extending the gate structure 122 into the second isolation structure 120 allows for the formation of a vertical (instead of horizontal) channel region C when a sufficiently large gate voltage is applied to the gate structure 122. 106 . This can help reduce the length of the channel region C 106 and, correspondingly, can reduce the on-resistance of the transistor device 100. Additionally, the silicide blocking layer 128 can help reduce the overvoltage stress in the transistor device 100 in high-current situations. Furthermore, the body region 106 can help reduce the on-resistance of the device 100. Additionally, since the portion 1201 of the second isolation structure 120 extends from the gate structure 122 towards the drain region 112, a thicker gate-to-drain oxide layer can be provided in the transistor device 100 compared to prior art devices. This can help reduce the gate-to-drain capacitance (Cgd) of the transistor device 100.

[0049] The fabrication of the transistor device 100 can also involve fewer etching processes. For example, the formation of the body region 106 of the transistor device 100 can be a self-aligned / self-controlled process (thus, the body region 106 can be referred to as a self-aligned body implant). In particular, as referred to above Figures 2A through 2L , the body region 106 can be formed after the gate structure 122 is formed. Since the gate structure 122 can partially extend into the second isolation structure 120, dopants can be deposited in the substrate 102 guided by the gate structure 122 to achieve an overlap between the body region 106 and the gate structure 122 along the side surface 122a. Therefore, after depositing the gate oxide material 206 and the conductive material 208, a single etch of these materials 206, 208 (instead of two separate etching processes) can be sufficient to form the gate structure 122 and expose a portion of the substrate 102 to form the body region 106.

[0050] Figure 5Figure 500 of a transistor device according to an alternative non - limiting embodiment is shown. The transistor device 500 is similar to the transistor device 100. Therefore, common features are denoted by the same reference numerals and will not be discussed.

[0051] Compared with the transistor device 100, in the transistor device 500, the transistor device 500 may include another conductive region 502 disposed within the substrate 102 (especially within the conductive region 104). The other conductive region 502 may be a high - voltage well region. The body region 106 and the drift region 108 may be disposed within the other conductive region 502. In other words, the source region 110, the drain region 112, and the body contact 114 may be disposed within the other conductive region 502. The transistor device 500 may be a negative channel metal - oxide - semiconductor (NMOS) device. In particular, the substrate 102, the other conductive region 502, the body region 106, and the body contact 114 may have a first conductivity type; while the conductive region 104, the drift region 108, the source region 110, and the drain region 112 may have a second conductivity type. For example, the substrate 102, the other conductive region 502, the body region 106, and the body contact 114 may have p - type conductivity, while the conductive region 104, the drift region 108, the source region 110, and the drain region 112 may have n - type conductivity.

[0052] Figure 6 Figure 600 of a transistor device according to an alternative non - limiting embodiment is shown. The transistor device 600 is similar to the transistor device 100. Therefore, common features are denoted by the same reference numerals and will not be discussed.

[0053] Compared with the transistor device 100, in the transistor device 600, the gate structure 122 may be entirely disposed within the second isolation structure 120. The top surface 122t of the gate structure 122 may be substantially aligned with the top surface 102t of the substrate 102, and the depth D of the gate structure 122 within the second isolation structure 120 122 may be approximately equal to the depth D in the transistor device 100 1221 . Additionally, there may be no silicide blocking layer 128 in the transistor device 600. To form the gate structure 122 of the transistor device 600, instead of the etching process described above with reference to Figure 2H a planarization process (e.g., a CMP process) may be performed to remove the conductive material 208 and the gate oxide material 206 located above the substrate 102. A deoxidation process (e.g., a poly - deoxidation process) may also be performed to more thoroughly remove the conductive material 208 located above the substrate 102.

[0054] In FIGS. 1, 5, and 6, the first isolation structure 116 and the second isolation structure 120 are shown to have side surfaces that are substantially perpendicular to their respective top surfaces 116t, 120t. However, alternatively, the side surfaces of these isolation structures 116, 120 can be inclined at an angle with respect to their top surfaces 116t, 120t. When the transistor device 100 includes such isolation structures 116, 120, the side surface 122a of the gate structure 122 facing the source region 110 can also be inclined at an angle such that it can be aligned with the inclined side surface of the second isolation structure 120 to abut the body region 106. Additionally, although the first and second isolation structures 116, 120 are shown in FIGS. 1, 5, and 6 as being entirely disposed within the substrate 102, these isolation structures 116, 120 can alternatively extend beyond the top surface 102t of the substrate 102. For example, Figure 7 FIG. shows a transmission electron microscope (TEM) cross-sectional image showing exemplary first and second isolation structures 116, 120 that can be used in the transistor device 100, where these isolation structures 116, 120 can have inclined side surfaces and can extend beyond the top surface 102t of the substrate 102. As Figure 7 shown, the top surface 116t of the first isolation structure 116 and the top surface 120t of the second isolation structure 120 can be substantially laterally aligned with each other above the top surface 102t of the substrate 102. The depth D 120 (from its top surface 120t) of the second isolation structure 120 can be less than the depth D 116 (from its top surface 116t) of the first isolation structure 116.

[0055] The present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. Accordingly, the above-described embodiments are to be considered in all respects as illustrative rather than restrictive of the invention described herein. The scope of the invention is, therefore, indicated by the appended claims rather than by the foregoing description, and is intended to include all modifications within the meaning and range of equivalents of the claims.

Claims

1. A transistor device, comprising: a substrate in which a conductive region is provided; a first isolation structure disposed in the substrate, wherein the first isolation structure extends along at least a part of the boundary of the conductive region; a source region and a drain region disposed in the conductive region; a second isolation structure disposed between the source region and the drain region, wherein the depth of the second isolation structure is less than the depth of the first isolation structure; a gate structure disposed at least partially in the second isolation structure; and a drift region disposed in the conductive region, wherein a side surface of the gate structure facing the source region is vertically aligned with a side surface of the second isolation structure and a side surface of the drift region.

2. The transistor device according to claim 1, wherein, Each of the first isolation structure and the second isolation structure includes a dielectric material.

3. The transistor device according to claim 1 further includes a body region disposed between the first isolation structure and the gate structure, wherein, The source region is disposed in the body region.

4. The transistor device according to claim 3, wherein, The gate structure abuts the body region along a side surface of the gate structure.

5. The transistor device according to claim 3, wherein, The depth of the body region is between the depth of the second isolation structure and the depth of the gate structure disposed in the second isolation structure.

6. The transistor device as claimed in claim 3, further comprising a body contact disposed in the body region, wherein, The body contact abuts the source region.

7. The transistor device according to claim 1, wherein, The drain region and the second isolation structure are disposed in the drift region.

8. The transistor device according to claim 1, wherein, The first isolation structure is partially disposed in the conductive region.

9. The transistor device according to claim 1, wherein, The depth of the second isolation structure is less than or equal to 120 nanometers.

10. The transistor device according to claim 1, wherein, The depth of the second isolation structure ranges from one-third to two-thirds of the depth of the first isolation structure.

11. The transistor device according to claim 1, wherein, The second isolation structure is a shallow trench isolation structure.

12. The transistor device according to claim 1, wherein, A side surface of the gate structure facing the source region is aligned with a side surface of the second isolation structure.

13. The transistor device according to claim 1, wherein, A part of the second isolation structure extends from the gate structure toward the drain region.

14. The transistor device according to claim 1, wherein, A first part of the gate structure is disposed in the second isolation structure and a second part of the gate structure is disposed above the substrate.

15. The transistor device according to claim 14, further comprising a silicide blocking layer extending from above the second part of the gate structure to the top surface of the substrate.

16. The transistor device according to claim 1, wherein, The gate structure is completely disposed in the second isolation structure.

17. A method of forming a transistor device, the method comprising: providing a substrate; forming a conductive region in the substrate; forming a first isolation structure in the substrate, wherein the first isolation structure extends along at least a part of the boundary of the conductive region; forming a second isolation structure in the conductive region, wherein the depth of the second isolation structure is less than the depth of the first isolation structure; forming a gate structure disposed at least partially in the second isolation structure; forming a source region and a drain region in the conductive region such that the second isolation structure is disposed between the source region and the drain region; and forming a drift region disposed in the conductive region, wherein a side surface of the gate structure facing the source region is vertically aligned with a side surface of the second isolation structure and a side surface of the drift region.

18. The method according to claim 17, further comprising forming a body region between the first isolation structure and the gate structure.

19. The method according to claim 18, wherein, The body region is formed after the gate structure is formed.

20. The method according to claim 18, wherein Forming the body region includes depositing dopants in the substrate at an angle substantially perpendicular to the top surface of the substrate.

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