Peripheral circuit with recessed gate transistor and method of forming the same

Abstract

In certain aspects, a method for forming a three-dimensional (3D) memory device is disclosed. A first semiconductor structure including an array of NAND memory strings is formed on a first substrate. A second semiconductor structure including a recessed gate transistor is formed on a second substrate. The recessed gate transistor includes a recessed gate structure extending deep into the second substrate. The first semiconductor structure and the second semiconductor structure are bonded in a face-to-face manner such that the array of NAND memory strings is coupled to the recessed gate transistor across a bonding interface.

Description

Technical Field

[0001] The present disclosure relates to a memory device and a method of manufacturing the same. Background Art

[0002] Planar memory cells have been shrunk to smaller sizes by improving process technology, circuit design, program algorithms, and manufacturing processes. However, as the feature size of the memory cell approaches a lower limit, planar processes and manufacturing techniques become more challenging and expensive. As a result, the storage density of planar memory cells approaches an upper limit.

[0003] Three-dimensional (3D) memory architectures can address density limitations in planar memory cells. 3D memory architectures include a memory array and peripheral circuits for facilitating operation of the memory array. Summary of the invention

[0004] In one aspect, a method for forming a 3D memory device is disclosed. A first semiconductor structure including an array of NAND memory strings is formed on a first substrate. A second semiconductor structure including a recessed gate transistor is formed on a second substrate. The recessed gate transistor includes a recessed gate structure extending deep into the second substrate. The first semiconductor structure and the second semiconductor structure are bonded in a face-to-face manner such that the array of NAND memory strings is coupled to the recessed gate transistor across a bonding interface.

[0005] In another aspect, a method for forming a semiconductor device is disclosed. A recess is formed in a substrate. A first gate dielectric is formed on the sidewalls and bottom surface of the recess and a second gate dielectric is formed on the substrate. A first gate electrode is formed on the first gate dielectric and a second gate electrode is formed on the second gate dielectric. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate various aspects of the disclosure and together with the description further serve to explain the principles of the disclosure and to enable one skilled in the relevant art to make and use the disclosure.

[0007] Figure 1A Schematic diagram showing a cross section of an exemplary 3D memory device according to some aspects of the present disclosure.

[0008] Figure 1B A schematic diagram illustrating a cross section of another exemplary 3D memory device according to some aspects of the present disclosure.

[0009] Figure 2 A schematic circuit diagram of an exemplary memory device including a peripheral circuit with a page buffer according to some aspects of the present disclosure is shown.

[0010] Figure 3 A block diagram of an exemplary memory device including a memory cell array and peripheral circuits according to some aspects of the present disclosure is shown.

[0011] Figure 4 A schematic plan view of an exemplary memory device having multiple planes and a page buffer according to some aspects of the present disclosure is shown.

[0012] Figure 5 A schematic plan view of an exemplary memory device having a memory cell array and peripheral circuits including a page buffer according to some aspects of the present disclosure is shown.

[0013] Fig. 6A A plan view and a cross-sectional side view of an exemplary flat gate transistor according to some aspects of the present disclosure are shown.

[0014] Figure 6B A plan view and a cross-sectional side view of an exemplary recessed gate transistor according to some aspects of the present disclosure are shown.

[0015] Figure 7 A side view of a cross section of an exemplary semiconductor device having a recessed gate transistor and a planar gate transistor according to some aspects of the present disclosure is shown.

[0016] Fig. 8A A side view of a cross section of an exemplary 3D memory device is shown in accordance with some embodiments.

[0017] Figure 8B A side view of a cross section of another exemplary 3D memory device is shown in accordance with some embodiments.

[0018] Figure 8C A side view of a cross section of yet another exemplary 3D memory device is shown in accordance with some embodiments.

[0019] Fig.8D A side view of a cross section of yet another exemplary 3D memory device is shown in accordance with some embodiments.

[0020] Fig.9A -9J illustrates a fabrication process for forming an exemplary semiconductor device having a recessed gate transistor and a planar gate transistor according to some aspects of the present disclosure.

[0021] Fig.10 A flow chart of a method for forming an exemplary 3D memory device according to some aspects of the present disclosure is shown.

[0022] Fig.11A flow chart of a method for forming an exemplary semiconductor device having a recessed gate transistor and a planar gate transistor according to some aspects of the present disclosure is shown.

[0023] Fig.12 A block diagram of an exemplary system having a memory device according to some aspects of the present disclosure is shown.

[0024] Fig.13A A diagram of an exemplary memory card having a memory device according to some aspects of the present disclosure is shown.

[0025] Fig. 13B A diagram of an exemplary solid-state drive (SSD) having a memory device according to some aspects of the present disclosure is shown.

[0026] The present disclosure will be described with reference to the accompanying drawings. DETAILED DESCRIPTION

[0027] Although specific configurations and arrangements are discussed, it should be understood that the discussion is for illustrative purposes only. Therefore, other configurations and arrangements may be used without departing from the scope of the present disclosure. Moreover, the present disclosure may also be employed in a variety of other applications. The functions and structural features described in the present disclosure may be combined, adjusted, and modified with each other in a manner not specifically shown in the accompanying drawings, so that these combinations, adjustments, and modifications are within the scope of the present disclosure.

[0028] In general, terms may be understood, at least in part, by the context in which they are used. For example, the term "one or more" as used herein may be used to describe any feature, structure, or characteristic in a singular sense, or may be used to describe a combination of features, structures, or characteristics in a plural sense, at least in part depending on the context. Similarly, terms such as "one," "an," or "the" may also be understood to convey singular usage or to convey plural usage, which may depend, at least in part, on the context. In addition, the term "based on" may be understood to not necessarily be intended to convey an exclusive set of factors, but may allow for the presence of other factors that may not be explicitly stated, which again may depend, at least in part, on the context.

[0029] It should be easily understood that the terms “on,” “over,” and “over” in this disclosure should be interpreted in the broadest manner, such that “on” means not only being directly on something, but also includes being on something with intervening features or layers therebetween, and such that “on” or “over” includes not only the meaning of being on or over something, but also includes the meaning of being on or over something with no intervening features or layers therebetween (i.e., directly on something).

[0030] In addition, spatially relative terms, such as "below," "below," "beneath," "above," "above," etc., may be used herein for ease of description to describe the relationship of one element or feature to other elements or features as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may have other orientations (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0031] As used herein, the term "substrate" refers to the material on which subsequent material layers are added. The substrate itself can be patterned. The material added on top of the substrate can be patterned, or it can remain unpatterned. In addition, the substrate can include a wide range of semiconductor materials, for example, silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of non-conductive materials such as glass, plastic, or sapphire wafers.

[0032] As used herein, the term "layer" refers to a portion of a material including an area having a certain thickness. A layer may extend over the entire underlying structure or overlying structure, or may have a range smaller than the range of the underlying structure or overlying structure. In addition, a layer may be an area of ​​a homogeneous or inhomogeneous continuous structure, the thickness of which is less than the thickness of the continuous structure. For example, a layer may be located between any paired horizontal planes between the top surface and the bottom surface of the continuous structure, or at the top surface and the bottom surface. A layer may extend horizontally, vertically and / or along a tapered surface. A substrate may be a layer, may include one or more layers therein, and / or may have one or more layers located thereon, above it and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductors and contact layers (interconnect lines and / or via contacts are formed therein) and one or more dielectric layers.

[0033] With the development of 3D memory devices (e.g., 3D NAND flash memory devices), more stacked layers (e.g., word lines) require more peripheral circuits to operate the 3D memory device. Specifically, the number and / or size of page buffers must be increased to match the increased number of memory cells. In some cases, in 3D NAND flash memory, the chip area occupied by page buffers may be dominant, for example, exceeding 50% of the total chip area. In addition, in some 3D memory devices where the memory cell array and peripheral circuits are fabricated on different substrates and bonded together, the continued increase in peripheral circuit area (especially page buffer area) has become a bottleneck for reducing the total chip size.

[0034] One way to reduce the size of peripheral circuits is to reduce the transistor area by reducing gate width and length, however doing so may lead to degradation of channel leakage, thus limiting the percentage of device area reduction. Therefore, it has become increasingly challenging to reduce the peripheral circuits in 3D memory devices without sacrificing too much performance.

[0035] To address the aforementioned problems, the present disclosure introduces a solution in which recessed gate transistors are used instead of flat gate transistors when forming some of the peripheral circuits in a memory device (e.g., a 3D NAND flash memory device). That is, the peripheral circuits can have mixed-type transistors (both recessed gate transistors and flat gate transistors), which can balance device size reduction and performance degradation. According to the scope of the present disclosure, in some embodiments, the page buffer (the dominant factor in chip size) has recessed gate transistors instead of flat gate transistors, thereby reducing the device size while maintaining comparable or even better device leakage performance. Peripheral circuits other than page buffers can still use flat gate transistors, which can reduce manufacturing complexity and device structure and performance variations compared to using recessed gate transistors.

[0036] Figure 1A A schematic diagram of a cross section of an exemplary 3D memory device 100 according to some aspects of the present disclosure is shown. The 3D memory device 100 represents an example of a bonded chip. The components of the 3D memory device 100 (e.g., a memory cell array and peripheral circuits) can be formed separately on different substrates and then bonded to form a bonded chip. The 3D memory device 100 may include a first semiconductor structure 102 having an array of memory cells (memory cell array). In some embodiments, the memory cell array includes an array of NAND flash memory cells. For ease of description, a NAND flash memory cell array may be used as an example to describe the memory cell array in the present disclosure. However, it should be understood that the memory cell array is not limited to a NAND flash memory cell array, and may include any other suitable type of memory cell array, such as a NOR flash memory cell array, a phase change memory (PCM) cell array, a resistive memory cell array, a magnetic memory cell array, a spin transfer torque (STT) memory cell array, and only some examples are pointed out here.

[0037] The first semiconductor structure 102 may be a NAND flash memory device, wherein the memory cells are provided in the form of an array of 3D NAND memory strings and / or an array of two-dimensional (2D) NAND memory cells. The NAND memory cells may be organized into pages, which in turn are organized into blocks, wherein each NAND memory cell is electrically connected to a separate line referred to as a bit line (BL). All cells having the same vertical position among the NAND memory cells may be electrically connected by a word line (WL) via a control gate. In some embodiments, a plane contains a certain number of blocks electrically connected by the same bit line. The first semiconductor structure 102 may include one or more planes, and the peripheral circuits required to perform all read / write / erase operations may be included in the second semiconductor structure 104.

[0038] In some embodiments, the array of NAND memory cells is an array of 2D NAND memory cells, each of which includes a floating gate transistor. According to some embodiments, the array of 2D NAND memory cells includes a plurality of 2D NAND memory strings, each of which includes a plurality of memory cells (e.g., 32 to 128 memory cells) connected in series (similar to NAND gates) and two selection transistors. According to some embodiments, each 2D NAND memory string is arranged in the same plane on the substrate (in 2D). In some embodiments, the array of NAND memory cells is an array of 3D NAND memory strings, each of which extends vertically through the memory stack above the substrate (in 3D). Depending on the 3D NAND technology (e.g., the number of layers / levels in the memory stack), the 3D NAND memory string typically includes 32 to 256 NAND memory cells, each of which includes a floating gate transistor or a charge trapping transistor.

[0039] like Figure 1AAs shown in , the 3D memory device 100 may also include a second semiconductor structure 104, which includes peripheral circuits of the memory cell array of the first semiconductor structure 102. The peripheral circuits (also referred to as control and sensing circuits) may include any appropriate digital, analog and / or mixed signal circuits for facilitating the operation of the memory cell array. For example, the peripheral circuits may include one or more of a page buffer, a decoder (e.g., a row decoder or a column decoder), a sense amplifier, a driver (e.g., a word line driver), a charge pump, a current or voltage reference, or any active or passive component of the circuit (e.g., a transistor, a diode, a resistor, or a capacitor). In some embodiments, the peripheral circuits in the second semiconductor structure 104 use metal-oxide-semiconductor (MOS) technology, for example, the technology may be implemented using advanced logic processes (e.g., 90nm, 65nm, 45nm, 32nm, 28nm, 20nm, 16nm, 14nm, 10nm, 7nm, 5nm, 3nm, 2nm, etc. technology nodes) to achieve high speed. It should be understood that in some examples, other processing units (also referred to as "logic circuits") other than peripheral circuits, such as a memory controller or a processor, may also be formed in the second semiconductor structure 104. It should also be understood that the second semiconductor structure 104 may also include other memory devices compatible with the manufacturing process of the logic circuit (e.g., using MOS technology), such as static random access memory (SRAM) and dynamic random access memory (DRAM).

[0040] like Figure 1AAs shown in , the 3D memory device 100 also includes a bonding interface 106 located between the first semiconductor structure 102 and the second semiconductor structure 104 in the vertical direction. As described in detail below, the first semiconductor structure 102 and the second semiconductor structure 104 can be manufactured separately (and in some embodiments, in parallel), so that the thermal budget of manufacturing one of the first semiconductor structure 102 and the second semiconductor structure 104 does not impose a limitation on the process of manufacturing the other of the first semiconductor structure 102 and the second semiconductor structure 104. In addition, a large number of interconnects (e.g., bonding contacts) can be formed through the bonding interface 106, thereby forming a direct short-distance (e.g., micrometer-level) electrical connection between the first semiconductor structure 102 and the second semiconductor structure 104, which is in contrast to the long-distance (e.g., millimeter or centimeter-level) chip-to-chip data bus on a circuit board (e.g., a printed circuit board (PCB)), thereby eliminating chip interface delays and achieving high-speed input / output (I / O) throughput with reduced power consumption. Data transfer between the memory cell array in the first semiconductor structure 102 and the peripheral circuit in the second semiconductor structure 104 can be performed through interconnections (e.g., bonding contacts) across the bonding interface 106. By vertically integrating the first semiconductor structure 102 and the second semiconductor structure 104, the chip size can be reduced and the memory cell density can be increased. In addition, by integrating multiple discrete chips (e.g., various processors, controllers, and memories) into a single bonded chip (e.g., 3D memory device 100) as a "unified chip", faster system speeds and smaller PCB sizes can also be achieved.

[0041] It should be understood that the relative positions of the stacked first semiconductor structure 102 and the second semiconductor structure 104 are not limited. Figure 1B FIG. 1 is a schematic diagram showing a cross section of another exemplary 3D memory device 101 according to some embodiments. Figure 1A In the 3D memory device 100 in the embodiment, the second semiconductor structure 104 including the peripheral circuit is located on the first semiconductor structure 102 including the memory cell array. Figure 1B In the 3D memory device 101, the first semiconductor structure 102 including the memory cell array is located above the second semiconductor structure 104 including the peripheral circuit. Nevertheless, according to some embodiments, the bonding interface 106 is still formed between the first semiconductor structure 102 and the second semiconductor structure 104 in the 3D memory device 101 in the vertical direction, and the first semiconductor structure 102 and the second semiconductor structure 104 are vertically joined by bonding (e.g., hybrid bonding). Data transfer between the memory cell array in the first semiconductor structure 102 and the peripheral circuit in the second semiconductor structure 104 can be performed through an interconnection (e.g., a bonding contact) across the bonding interface 106.

[0042] Figure 2 A schematic circuit diagram of an exemplary memory device 200 including a peripheral circuit with a page buffer according to some aspects of the present disclosure is shown. The memory device 200 may include a memory cell array 201 and a peripheral circuit 202 coupled to the memory cell array 201. The 3D memory devices 100 and 101 may be examples of the memory device 200, wherein the memory cell array 201 and the peripheral circuit 202 may be included in the first semiconductor structure 102 and the second semiconductor structure 104, respectively. The memory cell array 201 may be a NAND flash memory cell array, wherein the memory cells 206 are provided in the form of an array of NAND memory strings 208, each NAND memory string 208 extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 208 includes a plurality of memory cells 206 coupled in series and stacked vertically. Each memory cell 206 is capable of holding a continuous analog value, such as a voltage or charge, which depends on the number of electrons trapped in the area of ​​the memory cell 206. Each memory cell 206 may be a “floating gate” type memory cell including a floating gate transistor, or may be a “charge trapping” type memory cell including a charge trapping transistor.

[0043] In some embodiments, each memory cell 206 is a single-level cell (SLC) having two possible memory states and thus capable of storing one bit of data. For example, a first memory state "0" may correspond to a first range of voltages, and a second memory state "1" may correspond to a second range of voltages. In some embodiments, each memory cell 206 is a multi-level cell (MLC) capable of storing more than one bit of data in four or more memory states. For example, an MLC is capable of storing two bits per cell, three bits per cell (also known as a three-level cell (TLC)), or four bits per cell (also known as a quad-level cell (QLC)). Each MLC can be programmed to present a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed from an erased state to present one of three possible programming levels by writing one of the three possible nominal storage values ​​to the cell. A fourth nominal storage value can be used as an erased state.

[0044] like Figure 2As shown in , each NAND memory string 208 may include a source select gate (SSG) 210 at its source end and a drain select gate (DSG) 212 at its drain end. The SSG 210 and the DSG 212 may be configured to activate a selected NAND memory string 208 (column of the array) during read and program operations. In some embodiments, each SSG 210 of each NAND memory string 208 within the same block 204 is coupled to, for example, ground via a same source line (SL) 214 (e.g., a common SL). According to some embodiments, the DSG 212 of each NAND memory string 208 is coupled to a corresponding bit line 216, from which data can be read via an output bus (not shown). In some embodiments, each NAND memory string 208 is configured to be selected or deselected by applying a selection voltage (e.g., exceeding the threshold voltage of a transistor having DSG 212) or a deselection voltage (e.g., 0 V) ​​to a corresponding DSG 212 via one or more DSG lines 213 and / or by applying a selection voltage (e.g., exceeding the threshold voltage of a transistor having SSG 210) or a deselection voltage (e.g., 0 V) ​​to a corresponding SSG 210 via one or more SSG lines 215.

[0045] like Figure 2 As shown in , the NAND memory strings 208 can be organized into a plurality of blocks 204, each of which can have a common source line 214. In some embodiments, each block 204 is a basic data unit for an erase operation, i.e., all memory cells 206 on the same block 204 are erased at the same time. The memory cells 206 of adjacent NAND memory strings 208 can be coupled by word lines 218, which select which row of memory cells 206 are affected by read and program operations. In some embodiments, each word line 218 is coupled to the memory cells 206 of a page 220, which is the basic data unit of a programming operation. The size of a page 220 measured in bits can correspond to the number of NAND memory strings 208 coupled by word lines 218 in a block 204. Each word line 218 can include a plurality of control gates (gate electrodes) located at each memory cell 206 within a corresponding page 220 and a gate line coupling each control gate.

[0046] The peripheral circuit 202 may be coupled to the memory cell array 201 through the bit line 216, the word line 218, the source line 214, the SSG line 215, and the DSG line 213. As described above, the peripheral circuit 202 may include any suitable circuits for facilitating the operation of the memory cell array 201 by applying a voltage signal and / or a current signal to each target memory cell 206 via the bit line 216 through the word line 218, the source line 214, the SSG line 215, and the DSG line 213, and sensing a voltage signal and / or a current signal from each target memory cell 206, thereby facilitating the operation. The peripheral circuit 202 may include various types of peripheral circuits formed using MOS technology. For example, Figure 3 Some exemplary peripheral circuits 202 are shown, including page buffers 304, column decoders / bit line drivers 306, row decoders / word line drivers 308, voltage generators 310, control logic 312, registers 314, interfaces (I / Fs) 316, and data buses 318. It should be understood that in some examples, other peripheral circuits 202 may also be included.

[0047] The page buffer 304 may be configured to read data from the memory cell array 201 and program data to the memory cell array 201 according to the control of the control logic 312. In one example, the page buffer 304 may store a page of programming data (write data) to be programmed into one page 220 of the memory cell array 201. In another example, the page buffer 304 also performs a program verification operation to ensure that the data has been correctly programmed into the memory cell 206 coupled to the selected word line 218. Figure 2 In some embodiments shown, the page buffer 304 includes a plurality of page buffer circuits 222, each of which is coupled to one NAND memory string 208 via a corresponding bit line 216. That is, the memory device 200 may include respective bit lines 216 coupled to respective NAND memory strings 208, and the page buffer 304 may include respective page buffer circuits 222 coupled to respective bit lines 216 and NAND memory strings 208. Each page buffer circuit 222 may include one or more latches, switches, power supplies, nodes (e.g., data nodes and I / O nodes), current mirrors, verification logic, sensing circuits, etc. In some embodiments, each page buffer circuit 222 is configured to store sensing data corresponding to read data received from the corresponding bit line 216 and output the stored sensing data during a read operation; each page buffer circuit 222 is also configured to store programming data and output the stored programming data to the corresponding bit line 216 during a programming operation.

[0048] The row decoder / word line driver 308 may be configured to be controlled by the control logic 312 and select the block 204 of the memory cell array 201 and the word line 218 of the selected block 204. The row decoder / word line driver 308 may be further configured to drive the selected word line 218 using the word line voltage generated by the voltage generator 310. The voltage generator 310 may be configured to be controlled by the control logic 312 and generate the word line voltages (e.g., read voltage, program voltage, pass voltage, local voltage, and verification voltage) to be provided to the memory cell array 201. The column decoder / bit line driver 306 may be configured to be controlled by the control logic 312 and select one or more NAND memory strings 208 by applying the bit line voltage generated by the voltage generator 310. For example, the column decoder / bit line driver 306 may apply a column signal to select a group of N-bit data to be output in a read operation from the page buffer 304.

[0049] The control logic 312 may be coupled to each peripheral circuit 202 and configured to control the operation of the peripheral circuit 202. The register 314 may be coupled to the control logic 312 and include a status register, a command register, and an address register to store status information, a command operation code (OP code), and a command address for controlling the operation of each peripheral circuit 202.

[0050] The interface 316 can be coupled to the control logic 312 and act as a control buffer to buffer control commands received from a host (not shown) and forward them to the control logic 312, and to buffer status information received from the control logic 312 and forward them to the host. The interface 316 can also be coupled to the page buffer 304 and the column decoder / bit line driver 306 via the data bus 318, and act as an I / O interface and data buffer to buffer programming data received from the host (not shown) and forward it to the page buffer 304, and to buffer read data from the page buffer 304 and forward it to the host. In some embodiments, the interface 316 and the data bus 318 are part of the I / O circuitry of the peripheral circuit 202.

[0051] like Figure 4 As shown in , in some embodiments, the memory cell array 201 is arranged in a plurality of planes 402, each of which has a plurality of blocks 204 and a page buffer 304 of the plane. That is, the memory device 200 may include a plurality of planes 402 composed of memory cells 206 and a plurality of page buffers 304 respectively coupled to the plurality of planes 402. Figure 43, but it should be understood that in some examples, each plane 402 may have its own set of page buffers 304, row decoders / word line drivers 308, and column decoders / bit line drivers 306, so that the control logic 312 can control the operation of multiple planes 402 in parallel in a synchronous or asynchronous manner to increase the operating speed of the memory device 200. As described above in connection with Figure 2-4 As described above, it should be understood that as the number of memory cells increases due to an increase in the number of planes 402, blocks 204, NAND memory strings 208, and / or pages 220, the number of page buffers 304 and the number of page buffer circuits 222 within each page buffer may also increase. Thus, if the device size of each transistor forming the page buffer circuit 222 does not decrease, the total area of ​​the page buffer 304 will continue to increase.

[0052] In addition, in a 3D memory device 100 or 101 in which peripheral circuits and memory cell arrays are stacked one on top of another in a bonded chip, the size of the 3D memory device 100 or 101 depends on the larger size of the first semiconductor structure 102 or the second semiconductor structure 104. Figure 5 As shown in , as the area of ​​the page buffer 304 continues to increase, the size of the second semiconductor structure 104 having the peripheral circuit may eventually become larger than the size of the first semiconductor structure 102 having the memory cell array, and thus dominate the size of the 3D memory device 100 or 101. As a result, in order to compensate for the increase in size of the memory device 200 (especially the 3D memory device 100 or 101), the device size of each transistor forming the page buffer circuit 222 must be reduced without sacrificing performance (e.g., device leakage performance) too much, as described above.

[0053] According to the scope of the present disclosure, in some embodiments, each page buffer 304 (the dominant factor in chip size) has a recessed gate transistor instead of a flat gate transistor, thereby reducing the device size while maintaining comparable or even better device leakage performance. Peripheral circuits 202 other than page buffers 304 (e.g., row decoder / word line driver 308, column decoder / bit line driver 306, voltage generator 310, control logic 312, register 314, data bus 318 and / or interface 316) can still use flat gate transistors, which can reduce manufacturing complexity and device structure and performance variations compared to using recessed gate transistors. In some embodiments, I / O circuits (including interface 316 and data bus 318) use flat gate transistors because flat gate transistors can provide higher operating speeds than recessed gate transistors, which is a desirable feature for I / O circuits that must frequently communicate with external devices. For example, Fig. 6Ashows a plan view and a cross-sectional side view of an exemplary flat gate transistor according to some aspects of the present disclosure, and Figure 6B A plan view and a cross-sectional side view of an exemplary recessed gate transistor according to some aspects of the present disclosure are shown.

[0054] like Fig. 6A As shown in FIG, for a flat gate transistor, the effective channel length Leff is the same as the gate length L, while Figure 6B In, for a recessed gate transistor, the effective channel length Leff = Lb + 2Ld - 2xj, where Lb represents the gate length at the bottom position of the gate structure extending into the substrate, Ld represents the depth of the gate structure extending into the substrate (if the slope is not 90 degrees, the slope should be taken into account to obtain higher accuracy), and xj represents the junction depth of the source / drain. For a flat gate transistor, a reduction in device area can be achieved by reducing the gate length L (and in some cases by reducing the gate width W), and the reduction in gate length will shorten the effective channel length. As a result, channel leakage may be degraded. In contrast, for a recessed gate transistor, due to the increase in Ld, a reduction in device area (for example, by reducing the gate length L) may not reduce the effective channel length Leff. In addition, due to the protruding shape of the recessed gate structure, better gate control can be achieved. Thus, the device area can be reduced while maintaining comparable or even better device leakage performance. On the other hand, the protruding shape of the recessed gate structure in the recessed gate transistor may also introduce higher manufacturing complexity and device variation compared to the flat gate transistor. The structure, function and process of the planar gate transistor and the recessed gate transistor will be described in detail below.

[0055] Figure 7A side view of a cross section of an exemplary semiconductor device 700 with a recessed gate transistor 702 and a flat gate transistor 704 according to some aspects of the present disclosure is shown. The semiconductor device 700 may include a peripheral circuit (e.g., peripheral circuit 202) disclosed herein. In some embodiments, the recessed gate transistor 702 is part of a page buffer (e.g., page buffer 304) disclosed herein, and the flat gate transistor 704 is part of another peripheral circuit 202 (e.g., I / O circuit including data bus 318 and / or interface 316) disclosed herein in addition to the page buffer 304. That is, the semiconductor device 700 may include a page buffer with a recessed gate transistor 702 and a different peripheral circuit with a flat gate transistor 704. For example, the page buffer may be formed using a recessed gate transistor 702 instead of a flat gate transistor 704, thereby reducing the size of the page buffer without sacrificing device leakage performance, while some or all of the other peripheral circuits may be formed using flat gate transistors instead of recessed gate transistors 702 to balance manufacturing complexity and device variation. It should also be understood that the semiconductor device 700 is not limited to peripheral circuits of a memory device, and may include any semiconductor device 700 including a mixed type of recessed gate transistors 702 and planar gate transistors 704 .

[0056] Each recessed gate transistor 702 or flat gate transistor 704 may be a MOS field effect transistor (MOSFET) located on a substrate 701, which may include silicon (e.g., single crystal silicon c-Si), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), or any other suitable material. The semiconductor device 700 may include isolation 703, such as shallow trench isolation (STI), located between adjacent recessed gate transistors 702 and flat gate transistors 704 in the substrate 701 to reduce current leakage. The isolation 703 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high dielectric constant (high-k) dielectric (e.g., aluminum oxide, hafnium oxide, zirconium oxide, etc.). In some embodiments, the high-k dielectric material includes any dielectric having a dielectric constant or k value higher than the dielectric constant of silicon nitride (k>7). In some embodiments, the isolation 703 includes silicon oxide.

[0057] It should be pointed out that in Figure 7The x-axis and y-axis are added to further illustrate the spatial relationship of the components in the semiconductor device 700. The substrate 701 includes two lateral surfaces (e.g., top and bottom surfaces) extending laterally along the x-direction (i.e., lateral direction or width direction). As used herein, when a substrate (e.g., substrate 701) of a semiconductor device (e.g., semiconductor device 700) is located in the lowest plane of the semiconductor device in the y-direction (vertical direction or thickness direction), whether a component (e.g., layer or device) of the semiconductor device is located "on", "above" or "below" another component (e.g., layer or device) is determined relative to the substrate along the y-direction. The same concept will be used throughout the present disclosure to describe spatial relationships.

[0058] like Figure 7 As shown in , in some embodiments, the recessed gate transistor 702 and the flat gate transistor 704 are formed by complementary MOS (CMOS) technology and include pairs of adjacent P-type transistors (e.g., PMOS) and N-type transistors (NMOS). The P-type recessed gate transistor 706 may include an N-well 714 located in the substrate 701 and having a recess, and the N-type recessed gate transistor 707 may include a P-well 715 located in the substrate 701 and having a recess. The P-well 715 may be doped with any suitable P-type dopant, such as boron (B) or gallium (Ga), and the N-well 714 may be doped with any suitable N-type dopant, such as phosphorus (P) or arsenic (As). It should be understood that Figure 7 The wells 714 and 715 in the substrate 701 are for illustrative purposes only. Depending on the doping type of the substrate 701, the N-well 714 or the P-well 715 may be omitted or may have different ranges and boundaries in the substrate 701. Each recessed gate transistor 702 may also include a recessed gate structure 719 extending into the recess of the well 714 or 715 in the substrate 701. For example, the recessed gate structure 719 of the P-type recessed gate transistor 706 may extend into the recess of the N-well 714, and the recessed gate structure 719 of the N-type recessed gate transistor 707 may extend into the recess of the P-well 715. That is, the recessed gate structure 719 may have two parts in a side view: a protruding portion located below the top surface of the substrate 701 and a flat portion located above the top surface of the substrate 701. As described above in connection with Figure 6BAs described above, the depth and slope of the protruding portion of each recessed gate structure 719 determine Ld, which in turn affects the effective channel length Leff of the corresponding recessed gate transistor 702. In some embodiments, the depth of the protruding portion of the recessed gate structure 719 (i.e., the depth of the recessed gate structure 719 protruding into the substrate 701) is between 50 nm and 100 nm (e.g., 50 nm, 55 nm, 60 nm, 65 nm, 70 nm, 75 nm, 80 nm, 85 nm, 90 nm, 95 nm, 100 nm, any range with a lower limit defined by any of these values, or any range defined by any two of these values).

[0059] In some embodiments, the recessed gate structure 719 includes a curved gate dielectric 718 and a recessed gate electrode 716 on the curved gate dielectric 718. Figure 7 As shown in , according to some embodiments, a recess is formed in the region of the substrate 701 where the recessed gate transistor 702 is formed. Each recess can be surrounded by an N-well 714 or a P-well 715. That is, the portion of the substrate 701 where the well 714 or 715 is formed can be removed from the top surface to form the recess, as described in detail below in connection with the manufacturing process. In some embodiments, the depth of the recess is the same as the depth of the protruding portion of the recessed gate structure 719 and is between 50nm and 100nm (e.g., 50nm, 55nm, 60nm, 65nm, 70nm, 75nm, 80nm, 85nm, 90nm, 95nm, 100nm, any range bounded by any of these values ​​or within any range bounded by any two of these values).

[0060] A curved gate dielectric 718 may be formed on the sidewalls and bottom surface of each recess. As a result, in accordance with some embodiments, the curved gate dielectric 718 has a curved shape in a side view that follows the shape of the sidewalls and bottom of the recess. The curved gate dielectric 718 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. In some embodiments, the curved gate dielectric 718 includes silicon oxide, i.e., a curved gate oxide. In accordance with some embodiments, the recessed gate electrode 716 is located above and in contact with the curved gate dielectric 718. Figure 7As shown in , the recessed gate electrode 716 may also include two parts in a side view: an extended portion below the top surface of the substrate 701 and a flat portion above the top surface of the substrate 701. That is, the recess in the substrate 701 may be filled with a curved gate dielectric 718 and the extended portion of the recessed gate electrode 716. The recessed gate electrode 716 may include any suitable conductive material, such as polysilicon, a metal (e.g., tungsten, copper, aluminum, etc.), a metal compound (e.g., titanium nitride, tantalum nitride, etc.), or a silicide. In some embodiments, the recessed gate electrode 716 includes polysilicon, i.e., recessed gate polysilicon.

[0061] like Figure 7 As shown in , each recessed gate transistor 702 may also include a pair of sources and drains separated by a recessed gate structure 719. For example, the P-type recessed gate transistor 706 may include a P-type source 732 and a P-type drain 732 located in the N-well 714. The P-type source and drain 732 may be separated by the recessed gate structure 719 (i.e., the curved gate dielectric 718 and the recessed gate electrode 716). Similarly, the N-type recessed gate transistor 707 may include an N-type source 733 and an N-type drain 733 located in the P-well 715. The N-type source and drain 733 may be separated by the recessed gate structure 719 (i.e., the curved gate dielectric 718 and the recessed gate electrode 716). The P-type source and drain 732 may be doped with any suitable P-type dopant, such as B or Ga, and the N-type source and drain 733 may be doped with any suitable N-type dopant, such as P or Ar. As described above in connection with Figure 6B As described above, the junction depth (ie, the depth of the drain / source 732 or 733) also affects the effective channel length Leff of the corresponding recessed gate transistor 702. Figure 7 As shown in , in some embodiments, the recessed gate structure 719 extends below the source and drain 732 or 733. That is, the lower end of the recessed gate structure 719 can be lower than the lower end of the source and drain 732 or 733.

[0062] In some embodiments, each recessed gate transistor 702 further includes a spacer 720 located on the sidewalls of the planar portion (i.e., the portion above the substrate 701) of the recessed gate electrode 716. The spacer 720 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. In some embodiments, the spacer 720 includes silicon nitride. It should be understood that each recessed gate transistor 702 may include or be coupled to Figure 7 Additional components not shown in the drawings, such as additional dielectric layers or contacts (eg, source and drain contacts).

[0063] Similarly, if Figure 7As shown in , the P-type planar gate transistor 708 may include an N-well 722 located in the substrate 701, and the N-type planar gate transistor 709 may include a P-well 723 located in the substrate 701. The N-well 722 may be doped with any suitable N-type dopant, such as P or Ar, and the P-well 723 may be doped with any suitable P-type dopant, such as B or Ga. It should be understood that Figure 7 The wells 722 and 723 in the recessed gate transistor 702 are for illustration purposes only. Depending on the doping type of the substrate 701, the N-well 722 or the P-well 723 may be omitted or may have different extents and boundaries in the substrate 701. Each flat gate transistor 704 may also include a flat gate structure 727. According to some embodiments, unlike the recessed gate structure 719, the flat gate structure 727 does not extend into the substrate 701. In some embodiments, due to the presence of the protruding portion of the recessed gate structure 719, the depth of the well 714 or 715 in the recessed gate transistor 702 is greater than the depth of the well 722 or 723 in the flat gate transistor 704.

[0064] In some embodiments, the planar gate structure 727 includes a planar gate dielectric 726 and a planar gate electrode 724 located on the planar gate dielectric 726. According to some embodiments, unlike the recessed gate transistor 702, no recess is formed in the region of the substrate 701 where the planar gate transistor 704 is formed. Thus, the planar gate dielectric 726 can be formed on the top surface of the substrate 701. As a result, according to some embodiments, the planar gate dielectric 726 has a straight line shape in a side view. The planar gate dielectric 726 can include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. In some embodiments, the planar gate dielectric 726 includes silicon oxide, i.e., a planar gate oxide. According to some embodiments, the planar gate electrode 724 is located above and in contact with the planar gate dielectric layer 726. Unlike the recessed gate transistor 702, the entirety of the planar gate electrode 724 can be located above the top surface of the substrate 701. The planar gate electrode 724 can include any suitable conductive material, such as polysilicon, a metal, a metal compound, or a silicide. In some embodiments, the planar gate electrode 724 includes polysilicon, ie, planar gate polysilicon.

[0065] like Figure 7As shown in , each flat gate transistor 704 may further include a pair of source and drain located in the well 722 or 723. For example, the P-type flat gate transistor 708 may include a P-type source 730 and a P-type drain 730 located in the N-well 722, and the N-type flat gate transistor 709 may include an N-type source 731 and an N-type drain 731 located in the P-well 723. The P-type source and drain 730 may be doped with any suitable P-type dopant, such as B or Ga, and the N-type source and drain 731 may be doped with any suitable N-type dopant, such as P or Ar. In some embodiments, the doping concentration of the source / drain 732 or 733 in the recessed gate transistor 702 is different from the doping concentration of the source / drain 730 or 731 in the flat gate transistor 704, so that the threshold voltage of the recessed gate transistor 702 is different from the threshold voltage of the flat gate transistor 704. For example, the doping concentration of the source / drain 732 or 733 in the recessed gate transistor 702 and the doping concentration of the source / drain 730 or 731 in the flat gate transistor 704 may be controlled in such a way that the threshold voltage of the flat gate transistor 704 is greater than the threshold voltage of the recessed gate transistor 702 .

[0066] In some embodiments, each planar gate transistor 704 further includes a spacer 728 located on the sidewalls of the planar gate electrode 724. The spacer 728 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. In some embodiments, the spacer 728 includes silicon nitride. It should be understood that each planar gate transistor 704 may include or be coupled to Figure 7 Additional components not shown in the drawings, such as additional dielectric layers or contacts (eg, source and drain contacts).

[0067] Contact as above Fig. 6A and Figure 6B As described above, compared to the flat gate transistor 704, the recessed gate transistor 702 can increase Ld due to the protruding shape of the recessed gate structure, thereby reducing the gate length L in the plan view while maintaining the same effective gate length Leff. As a result, in some embodiments, the dimension (e.g., gate length L) of the flat gate transistor 704 in the plan view is greater than the dimension (e.g., gate length L) of the recessed gate transistor 702.

[0068] Contact as above Figure 1A and Figure 1B As described above, the semiconductor device 700 may be an example of a second semiconductor structure 104 bonded to a first semiconductor structure 102 having a memory cell array. Fig. 8A A side view of a cross section of an exemplary 3D memory device 800 is shown according to some embodiments. Figure 1B As an example of the 3D memory device 101 described above, the 3D memory device 800 is a bonded chip including a first semiconductor structure 802 and a second semiconductor structure 804 stacked on the first semiconductor structure 802. According to some embodiments, the first semiconductor structure 802 and the second semiconductor structure 804 are bonded at a bonding interface 806 located therebetween. Fig. 8A As shown, the first semiconductor structure 802 may include a substrate 808, which may include silicon (e.g., single crystal silicon c-Si), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), or any other suitable material.

[0069] The first semiconductor structure 802 may include a device layer 810 located above the substrate 808. The semiconductor device 700 having the recessed gate transistor 702 and the flat gate transistor 704 may be an example of the device layer 810. In some embodiments, the device layer 810 includes peripheral circuits, and the peripheral circuits include a page buffer 812 and other peripheral circuits 814 (e.g., I / O circuits). In some embodiments, the page buffer 812 includes a plurality of recessed gate transistors 816, and the other peripheral circuits 814 include a plurality of flat gate transistors 818, as described above in connection with Figure 7 Isolation (e.g., STI) and doped regions (e.g., source and drain of transistors 816 and 818) may also be formed in substrate 808. According to some embodiments, transistors 816 and 818 are high-speed with advanced logic processes (e.g., 90nm, 65nm, 45nm, 32nm, 28nm, 20nm, 16nm, 14nm, 10nm, 7nm, 5nm, 3nm, 2nm, etc. technology nodes).

[0070] In some embodiments, the first semiconductor structure 802 further includes an interconnect layer 820 located above the device layer 810 to transmit electrical signals to and from the peripheral circuits 812 and 814. The interconnect layer 820 may include a plurality of interconnects (also referred to herein as "contacts"), including lateral interconnect lines and vertical interconnect via (VIA) contacts. As used herein, the term "interconnect" may broadly include any appropriate type of interconnect, such as middle-of-line (MEOL) interconnects and back-end-of-line (BEOL) interconnects. The interconnect layer 820 may further include one or more interlayer dielectric (ILD) layers (also referred to as "intermetal dielectric (IMD) layers"), in which the interconnect lines and VIA contacts may be formed. That is, the interconnect layer 820 may include interconnect lines and VIA contacts located in multiple ILD layers. In some embodiments, the devices in the device layer 810 are coupled to each other through the interconnects in the interconnect layer 820. For example, the page buffer 812 may be coupled to other peripheral circuits 814 through the interconnect layer 820.

[0071] like Fig. 8A As shown, the first semiconductor structure 802 may also include a bonding layer 822 located above the interconnect layer 820 and the device layer 810 at the bonding interface 806. The bonding layer 822 may include a plurality of bonding contacts 824 and a dielectric electrically isolating the bonding contacts 824. The bonding contacts 824 may include a conductive material. The remaining area of ​​the bonding layer 822 may be formed using a dielectric material. The bonding contacts 824 and the surrounding dielectric in the bonding layer 822 may be used for hybrid bonding. Similarly, as Fig. 8A As shown in , the second semiconductor structure 804 may also include a bonding layer 826 located above the bonding layer 822 of the first semiconductor structure 802 at the bonding interface 806. The bonding layer 826 may include a plurality of bonding contacts 828 and a dielectric electrically isolating the bonding contacts 828. The bonding contacts 828 may include a conductive material. The remaining area of ​​the bonding layer 826 may be formed using a dielectric material. The bonding contacts 828 and the surrounding dielectric in the bonding layer 826 may be used for hybrid bonding. According to some embodiments, the bonding contacts 828 are in contact with the bonding contacts 824 at the bonding interface 806.

[0072] The second semiconductor structure 804 can be bonded to the top of the first semiconductor structure 802 in a face-to-face manner at a bonding interface 806. In some embodiments, the bonding interface 806 is provided between the bonding layer 822 and the bonding layer 826 as a result of hybrid bonding (also referred to as "metal / dielectric hybrid bonding"), which is a direct bonding technology (e.g., forming a bond between surfaces without the need for an intermediate layer such as solder or adhesive) and can simultaneously obtain metal-metal bonding and dielectric-dielectric bonding. In some embodiments, the bonding interface 806 is where the bonding layer 822 and the bonding layer 826 meet and bond. In practice, the bonding interface 806 can be a layer of a certain thickness including the top surface of the bonding layer 822 of the first semiconductor structure 802 and the bottom surface of the bonding layer 826 of the second semiconductor structure 804.

[0073] In some embodiments, the second semiconductor structure 804 further includes an interconnect layer 830 located above the bonding layer 826 to transmit electrical signals. The interconnect layer 830 may include multiple interconnects, such as MEOL interconnects and BEOL interconnects. In some embodiments, the interconnects in the interconnect layer 830 also include local interconnects such as bit line contacts and word line contacts. The interconnect layer 830 may also include one or more ILD layers, in which interconnect lines and VIA contacts may be formed.

[0074] In some embodiments, the second semiconductor structure 804 includes a NAND flash memory device, wherein the memory cells are provided in the form of an array of NAND memory strings 838 over the interconnect layer 830 and the bonding layer 826. According to some embodiments, each NAND memory string 838 extends vertically through a plurality of pairs, each pair including a conductive layer 834 and a dielectric layer 836. The stacked alternating conductive layers 834 and dielectric layers 836 are also referred to herein as a memory stack 832. According to some embodiments, the alternating conductive layers 834 and dielectric layers 836 in the memory stack 832 alternate in a vertical direction.

[0075] In some embodiments, each NAND memory string 838 is a "charge trapping" type NAND memory string including a semiconductor channel 842 and a memory film 840. In some embodiments, the semiconductor channel 842 includes silicon, such as amorphous silicon, polycrystalline silicon, or monocrystalline silicon. In some embodiments, the memory film 840 is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trapping / storage layer"), and a barrier layer. Each NAND memory string 838 can have a cylindrical shape (e.g., a columnar shape). According to some embodiments, the semiconductor channel 842 and the tunneling layer, storage layer, and barrier layer of the memory film 840 are arranged in this order along the direction from the middle of the column to the outer surface of the column. In some embodiments, the NAND memory string 838 also includes a plurality of control gates (each of which is part of a word line). Each conductive layer 834 in the memory stack 832 can act as a control gate for each memory cell of the NAND memory string 838.

[0076] In some embodiments, the second semiconductor structure 804 also includes a semiconductor layer 848 disposed above the memory stack 832 and the NAND memory string 838. The semiconductor layer 848 can be a thinned substrate on which the memory stack 832 and the NAND memory string 838 are formed. In some embodiments, the semiconductor layer 848 includes single crystal silicon. The semiconductor layer 848 can also include isolation and doping regions (e.g., functioning as an array common source (ACS) for the NAND memory string 838, which is not shown). It should be understood that the NAND memory string 838 is not limited to a "charge trap" type NAND memory string, and can be a "floating gate" type NAND memory string in other examples. The semiconductor layer 848 can include polysilicon as a source plate for a "floating gate" type NAND memory string.

[0077] like Fig. 8AAs shown, the second semiconductor structure 804 may further include a pad lead-out interconnect layer 850 located above the semiconductor layer 848. The pad lead-out interconnect layer 850 may include interconnects located in one or more ILD layers, for example, contact pads 852. The pad lead-out interconnect layer 850 and the interconnect layer 830 may be formed on opposite sides of the semiconductor layer 848. In some embodiments, the interconnects in the pad lead-out interconnect layer 850 can transmit electrical signals between the 3D memory device 800 and an external circuit, for example, to achieve pad lead-out purposes. In some embodiments, the second semiconductor structure 804 further includes one or more contacts 854, which extend through the semiconductor layer 848 to electrically connect the pad lead-out interconnect layer 850 and the interconnect layers 830 and 820. As a result, the peripheral circuits 812 and 814 can be coupled to the array of NAND memory strings 838 through the interconnect layers 830 and 820 and the bonding contacts 828 and 824. That is, the array of NAND memory strings 838 may be coupled to the page buffer 812 across the bonding interface 806. In addition, the peripheral circuits 812 and 814 and the array of NAND memory strings 838 may be coupled to external circuits through the contacts 854 and the pad lead-out interconnect layer 850.

[0078] Figure 8B A cross-sectional view of another exemplary 3D memory device 801 according to some aspects of the present disclosure is shown. Figure 1A In one example of the 3D memory device 100 described above, the 3D memory device 801 is a bonded chip, the bonded chip including a second semiconductor structure 803 and a first semiconductor structure 805 stacked on the second semiconductor structure 803. Fig. 8A 801 represents an example of a bonded chip, in which a first semiconductor structure 805 and a second semiconductor structure 803 are formed separately and bonded in a face-to-face manner at a bonding interface 807. It should be understood that the details of similar structures in the 3D memory devices 800 and 801 (e.g., materials, manufacturing processes, functions, etc.) may not be repeated below.

[0079] The second semiconductor structure 803 may include a substrate 809 and a memory stack 811 including alternating conductive layers 813 and dielectric layers 815 located above the substrate 809. In some embodiments, an array of NAND memory strings 817 each extend vertically through the alternating conductive layers 813 and dielectric layers 815 in the memory stack 811 above the substrate 809. Each NAND memory string 817 may include a semiconductor channel 821 and a memory film 819. The NAND memory string 817 may be a "charge trap" type NAND memory string or a "floating gate" type NAND memory string.

[0080] In some embodiments, the second semiconductor structure 803 also includes an interconnect layer 827 located above the memory stack 811 and the NAND memory string 817 to transmit electrical signals to and from the NAND memory string 817. The interconnect layer 827 may include a plurality of interconnects, including interconnect lines and VIA contacts. In some embodiments, the interconnects in the interconnect layer 827 also include local interconnects such as bit line contacts and word line contacts. In some embodiments, the second semiconductor structure 803 also includes a bonding layer 829 located above the interconnect layer 827 and the memory stack 811 and the NAND memory string 817 at the bonding interface 807. The bonding layer 829 may include a plurality of bonding contacts 855 and a dielectric surrounding the bonding contacts 855 and electrically isolating them.

[0081] like Figure 8B As shown, the first semiconductor structure 805 includes another bonding layer 851 located above the bonding layer 829 at the bonding interface 807. The bonding layer 851 may include a plurality of bonding contacts 853 and a dielectric surrounding and electrically isolating the bonding contacts 853. According to some embodiments, the bonding contacts 853 are in contact with the bonding contacts 855 at the bonding interface 807. In some embodiments, the first semiconductor structure 805 also includes an interconnect layer 857 located above the bonding layer 851 to transmit electrical signals. The interconnect layer 857 may include a plurality of interconnects, including interconnect lines and VIA contacts.

[0082] The first semiconductor structure 805 may also include a device layer 831 located above the interconnect layer 857 and the bonding layer 851. The semiconductor device 700 having the recessed gate transistor 702 and the flat gate transistor 704 may be an example of the device layer 831. In some embodiments, the device layer 831 includes peripheral circuits, and the peripheral circuits include a page buffer 835 and other peripheral circuits 837 (e.g., I / O circuits). In some embodiments, the page buffer 835 includes a plurality of recessed gate transistors 839, and the other peripheral circuits 837 include a plurality of flat gate transistors 841, as described above in connection with Figure 7 According to some embodiments, with advanced logic processes (e.g., 90nm, 65nm, 45nm, 32nm, 28nm, 20nm, 16nm, 14nm, 10nm, 7nm, 5nm, 3nm, 2nm, etc. technology nodes), transistors 839 and 841 are high-speed.

[0083] In some embodiments, the first semiconductor structure 805 further includes a semiconductor layer 833 disposed on the device layer 831. The semiconductor layer 833 may be located on and in contact with the peripheral circuits 835 and 837. The semiconductor layer 833 may be a thinned substrate on which the transistors 839 and 841 are formed. In some embodiments, the semiconductor layer 833 includes single crystal silicon. The semiconductor layer 833 may also include isolation and doping regions.

[0084] like Figure 8B As shown, the first semiconductor structure 805 may further include a pad lead-out interconnect layer 843 located above the semiconductor layer 833. The pad lead-out interconnect layer 843 may include interconnects located in one or more ILD layers, such as contact pads 845. In some embodiments, the interconnects in the pad lead-out interconnect layer 843 can transmit electrical signals between the 3D memory device 801 and external circuits, for example, to achieve pad lead-out purposes. In some embodiments, the first semiconductor structure 805 further includes one or more contacts 847, which extend through the semiconductor layer 833 to couple the pad lead-out interconnect layer 843 and the interconnect layers 857 and 827. As a result, the peripheral circuits 835 and 837 can also be coupled to the array of NAND memory strings 817 through the interconnect layers 857 and 827 and the bonding contacts 853 and 855. That is, the array of NAND memory strings 817 can be coupled to the page buffer 835 across the bonding interface 807. Furthermore, the peripheral circuits 835 and 837 and the array of NAND memory strings 817 may be electrically connected to external circuits through contacts 847 and pad lead-out interconnect layer 843 .

[0085] To further reduce the occupied area of ​​the peripheral circuits, the peripheral circuits of the 3D memory device can be arranged in multiple planes stacked in a vertical direction, which is different from arranging them in the same plane (e.g., Fig. 8A and Figure 8B ) are located on the same substrate. For example, Figure 8C A side view of a cross section of yet another exemplary 3D memory device 860 is shown according to some embodiments. Figure 1B In one example of the 3D memory device 101 described above, the 3D memory device 860 is a bonded chip including a first semiconductor structure 862 and a second semiconductor structure 864 stacked on the first semiconductor structure 862. Fig. 8A800 in the embodiment of the present invention, the 3D memory device 860 represents an example of a bonded chip in which a first semiconductor structure 862 and a second semiconductor structure 864 are formed separately and bonded in a face-to-face manner at a bonding interface 886. It should be understood that the details of similar structures in the 3D memory devices 800 and 860 (e.g., materials, manufacturing processes, functions, etc.) may not be repeated below.

[0086] and Fig. 8A Different from the first semiconductor structure 802 including a single device layer 810, Figure 8C The first semiconductor structure 862 of the 3D memory device 860 in the embodiment may include a plurality of device layers located in different planes in a vertical direction, for example, a first device layer 866 and a second device layer 868 stacked on the first device layer 866. The first device layer 866 and the second device layer 868 may include a first semiconductor layer 870 and a second semiconductor layer 874, respectively. In some embodiments, each semiconductor layer 870 or 874 includes single crystal silicon. Figure 8C As shown in , in some embodiments, the first device layer 866 includes a plurality of recessed gate transistors 872 formed in the semiconductor layer 870. The recessed gate transistor 702 can be an example of a recessed gate transistor 872 in the first device layer 866. The first device layer 866 can include a page buffer having recessed gate transistors 872 as described in the present disclosure. In some embodiments, all transistors in the first device layer 866 are recessed gate transistors 872. That is, according to some embodiments, the first device layer 866 does not include any flat gate transistors.

[0087] like Figure 8C As shown in , in some embodiments, the second device layer 868 includes a plurality of flat gate transistors 876 formed on the semiconductor layer 874. The flat gate transistor 704 can be an example of a flat gate transistor 876 in the second device layer 868. The second device layer 868 can include peripheral circuits other than the page buffer, such as I / O circuits, having the flat gate transistor 876 as described in the present disclosure. In some embodiments, all transistors in the second device layer 868 are flat gate transistors 876. That is, according to some embodiments, the second device layer 868 does not include any recessed gate transistors. By separating the flat gate transistors 876 and the recessed gate transistors 872 into different device layers in different planes, the flat gate transistors 876 and the recessed gate transistors 872 can be manufactured according to different processes, thereby reducing manufacturing complexity.

[0088] In some embodiments, a through silicon contact (TSC) 878 is formed through the semiconductor layer 874 between the planar gate transistor 876 and the recessed gate transistor 872 to electrically connect the planar gate transistor 876 and the recessed gate transistor 872 in different device layers.

[0089] and Fig. 8A Similar to the second semiconductor structure 804 in the 3D memory device 860, the second semiconductor structure 864 of the 3D memory device 860 can also include an array of NAND memory strings 880 extending vertically through the memory stack 882. The flat gate transistors 876 and recessed gate transistors 872 in the first semiconductor structure 862 can be connected through the TSC 878 and the above-mentioned Fig. 8A The other interconnects and bonding contacts described in detail are electrically connected to the NAND memory string 838. It should be understood that the number of device layers in the first semiconductor structure 862 and the relative positions and orientations of the flat gate transistor 876 and the recessed gate transistor 872 in the first semiconductor structure 862 are not limited to Figure 8C , and there may be variations in other examples. In one example, the relative positions of the flat gate transistor 876 and the recessed gate transistor 872 may be relative to Figure 8C In another example, the relative directions of the flat gate transistor 876 and the recessed gate transistor 872 can be changed from facing the same direction to face to face or back to back. It should also be understood that in other examples, the relative positions and directions of the first semiconductor structure 862 and the second semiconductor structure 864 can also be changed.

[0090] In some embodiments, the flat gate transistor 876 and the recessed gate transistor 872 are not only in different device layers in different planes, but also in different semiconductor structures. Fig.8D A side view of a cross section of yet another exemplary 3D memory device 861 is shown according to some embodiments. Figure 1B In one example of the 3D memory device 101 described above, the 3D memory device 861 is a bonded chip including a first semiconductor structure 863 and a second semiconductor structure 865 stacked on the first semiconductor structure 863. Fig. 8A Similar to the 3D memory device 800 in FIG. 8 , the 3D memory device 861 represents an example of a bonded chip in which a first semiconductor structure 863 and a second semiconductor structure 865 are formed separately and bonded in a face-to-face manner at a bonding interface 887. It should be understood that the details of similar structures in the 3D memory devices 800 and 861 (e.g., materials, manufacturing processes, functions, etc.) may not be repeated below.

[0091] and Figure 8C Unlike the 3D memory device 860 in which all the device layers 866 and 868 in the first semiconductor structure 862 are located, according to some embodiments, at least the first device layer 869 is located in the second semiconductor structure 865 of the 3D memory device 816. That is, in addition to the array of NAND memory strings 881 extending vertically through the memory stack 883, the second semiconductor structure 865 can also include a first device layer 869, the first device layer 869 including a semiconductor layer 875 (e.g., a single crystal silicon layer) and a plurality of flat gate transistors 877 formed on the semiconductor layer 875. A TSC 879 can be formed through the semiconductor layer 875 to electrically connect the NAND memory strings 881 and the flat gate transistors 877. The first device layer 869 can include peripheral circuits, such as I / O circuits, with flat gate transistors 877 as described in the present disclosure in addition to the page buffer. In some embodiments, all transistors in the first device layer 869 are flat gate transistors 877. That is, according to some embodiments, the first device layer 869 does not include any recessed gate transistors.

[0092] like Fig.8D As shown in , the first semiconductor structure 863 may include a second device layer 867 having a semiconductor layer 871 (e.g., a single crystal silicon layer). In some embodiments, the second device layer 867 includes a plurality of recessed gate transistors 873 formed in the semiconductor layer 871. The recessed gate transistor 702 may be an example of a recessed gate transistor 873 in the second device layer 867. The second device layer 867 may include a page buffer having recessed gate transistors 873 as described in the present disclosure. In some embodiments, all transistors in the second device layer 867 are recessed gate transistors 873. That is, according to some embodiments, the second device layer 867 does not include any flat gate transistors. By separating the flat gate transistors 877 and the recessed gate transistors 873 into different device layers in different planes and into different semiconductor structures, the flat gate transistors 877 and the recessed gate transistors 873 may be manufactured according to different processes, thereby reducing manufacturing complexity.

[0093] It should be understood that the number of device layers in each semiconductor structure 863 or 865 and the relative positions and directions of the flat gate transistor 877 and the recessed gate transistor 873 are not limited to Fig.8D The examples shown in FIG. 8 and may vary in other examples. In one example, the relative positions of the flat gate transistor 877 and the recessed gate transistor 873 may be relative to Fig.8DIn another example, the relative directions of the flat gate transistor 877 and the recessed gate transistor 873 can be changed from face to face to face to face in the same direction or back to back. It should also be understood that in other examples, the relative positions and directions of the first semiconductor structure 863 and the second semiconductor structure 865 can also be changed.

[0094] Fig.12 A block diagram of an exemplary system 1200 having a memory device according to some aspects of the present disclosure is shown. The system 1200 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a car computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other electronic device having a memory device located therein. Fig.12 As shown in , system 1200 may include a host 1208 and a memory system 1202, the memory system 1202 having one or more memory devices 1204 and a memory controller 1206. The host 1208 may be a processor of an electronic device, such as a central processing unit (CPU), or may be a system on a chip (SoC), such as an application processor (AP). The host 1208 may be configured to send data to the memory device 1204 or receive data from the memory device 1204.

[0095] Memory device 1204 can be any memory device disclosed herein, such as 3D memory devices 100 and 101, memory device 200, and 3D memory devices 800, 801, 860, and 861. In some embodiments, each memory device 1204 includes peripheral circuits having one or more page buffers. According to the scope of the present disclosure, the page buffers (the dominant factor in chip size) have recessed gate transistors instead of flat gate transistors, thereby reducing device size while maintaining comparable or even better device leakage performance. Peripheral circuits other than page buffers can still use flat gate transistors, which can reduce manufacturing complexity and device structure and performance variations compared to using recessed gate transistors.

[0096] According to some embodiments, the memory controller 1206 is coupled to the memory device 1204 and the host 1208, and is configured to control the memory device 1204. The memory controller 1206 can manage data stored in the memory device 1204 and communicate with the host 1208. In some embodiments, the memory controller 1206 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 1206 is designed to operate in a high duty cycle environment, such as an SSD or an embedded multimedia card (eMMC), which is used as a data storage device for mobile devices such as smart phones, tablets, laptops, etc. and enterprise storage arrays. The memory controller 1206 can be configured to control the operation of the memory device 1204, such as read, erase, and program operations. The memory controller 1206 may also be configured to manage various functions related to data stored in or to be stored in the memory device 1204, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 1206 is further configured to process error correction codes (ECC) related to data read from or written to the memory device 1204. Any other suitable functions may also be performed by the memory controller 1206, such as formatting the memory device 1204. The memory controller 1206 may communicate with an external device (e.g., a host 1208) according to a specific communication protocol. For example, the memory controller 1206 can communicate with an external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a high-speed PCI (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc.

[0097] The memory controller 1206 and the one or more memory devices 1204 may be integrated into various types of storage devices, for example, included in the same package (e.g., a universal flash storage (UFS) package or an eMMC package). That is, the memory system 1202 may be implemented and packaged into different types of terminal electronic products. Fig.13AIn one example shown, the memory controller 1206 and the single memory device 1204 may be integrated into a memory card 1302. The memory card 1302 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 1302 may also include a processor that connects the memory card 1302 to a host (e.g., Fig.12 The memory card connector 1304 is coupled to the host 1208 in FIG. Fig. 13B In another example shown, the memory controller 1206 and the plurality of memory devices 1204 may be integrated into an SSD 1306. The SSD 1306 may also include a processor that interfaces the SSD 1306 with a host (e.g., Fig.12 In some implementations, the storage capacity and / or operating speed of the SSD 1306 is greater than the storage capacity and / or operating speed of the memory card 1302.

[0098] Fig.9A -9J illustrates a fabrication process for forming an exemplary semiconductor device having a recessed gate transistor and a planar gate transistor according to some aspects of the present disclosure. Fig.10 A flow chart of a method 1000 for forming an exemplary 3D memory device according to some aspects of the present disclosure is shown. Fig.11 A flow chart of a method 1100 for forming an exemplary semiconductor device having a recessed gate transistor and a planar gate transistor according to some aspects of the present disclosure is shown. Fig.9A –9J, Fig.10 and Fig.11 Examples of semiconductor devices shown include Figure 7 The semiconductor device 700 shown in FIG. Fig.9A –9J, Fig.10 and Fig.11 It should be understood that the operations shown in methods 1000 and 1100 are not exclusive, and other operations may be performed before, after, or between any of the operations shown. In addition, some of the operations may be performed simultaneously or in different order. Fig.10 and Fig.11 Executed in the order shown.

[0099] refer to Fig.10 , method 1000 begins at operation 1002, in which a first semiconductor structure including an array of NAND memory strings is formed on a first substrate. Figure 8BAs shown in , an array of NAND memory strings 817 is formed on a substrate 809. The method 1000 proceeds to operation 1004, as shown in FIG. Fig.10 As shown, in this operation, a first bonding layer including a plurality of first bonding contacts is formed over an array of NAND memory strings. Figure 8B As shown in FIG. 8 , a bonding layer 829 including bonding contacts 855 is formed over the array of NAND memory strings 817. In some embodiments, to form the first semiconductor structure, a flat gate transistor is also formed. The flat gate transistor can be formed into a device layer, which can be stacked one on top of the array of NAND memory strings, i.e., formed in different planes. For example, Fig.8D As shown in FIG. 8 , a flat gate transistor 877 is formed in a semiconductor layer 875 located above an array of NAND memory strings 817 .

[0100] Method 1000 proceeds to operation 1006, such as Fig.10 As shown, in this operation, a second semiconductor structure including a recessed gate transistor is formed on a second substrate. The recessed gate transistor may include a recessed gate structure extending into the second substrate. In some embodiments, the second semiconductor structure also includes a flat gate transistor formed on the second substrate. In order to form a recessed gate transistor and a flat gate transistor on the same substrate, as shown in FIG. Fig.11 As shown in FIG. 1 , in operation 1102, a first well is formed in a substrate. The substrate may be a silicon substrate.

[0101] like Fig.9A As shown in FIG. 1 , a plurality of isolations 902 (e.g., STI) are formed in a silicon substrate 900. For example, these isolations are formed using wet / dry etching and thin film deposition of silicon oxide. The isolations 902 can divide the silicon substrate 900 into a plurality of regions, and a plurality of transistors can be formed in the plurality of regions, respectively. Fig.9A As shown, N well 904 and P well 906 are then formed in silicon substrate 900. In some embodiments, N well 904 and P well 906 are formed in regions for forming planar gate transistors. N well 904 and P well 906 can be patterned using photolithography and aligned between isolation 902, followed by ion implantation of corresponding N-type dopants and P-type dopants.

[0102] like Fig.11 As shown in , in operation 1104, a second well is formed in the substrate. In some embodiments, the depth of the second well is greater than the depth of the first well. Fig. 9BAs shown, an N-well 910 is formed in a silicon substrate 900. The N-well 910 may be part of a P-type recessed gate transistor, and thus may be formed into a region for forming a P-type recessed gate transistor. To form the N-well 910, in some embodiments, a mask layer 908 is formed on the silicon substrate 900, and then the mask layer 908 is patterned to expose a region where the N-well 910 will be formed. The mask layer 908 may include a soft mask layer, such as a photoresist layer, and / or may include a hard mask layer, such as a silicon oxide layer. The mask layer 908 may be patterned and aligned between the isolations 902 using photolithography and wet / dry etching. The mask layer 908 may be used to perform ion implantation of N-type dopants (such as P or As) into the intended region between the isolations 902, thereby forming the N-well 910. In some implementations, ion implantation conditions of the N-well 904 , the P-well 906 , and the N-well 910 are controlled such that the depth of the N-well 910 is greater than the depths of the N-well 904 and the P-well 906 .

[0103] like Fig. 9C As shown in , a P-well 912 is formed in a silicon substrate 900. The P-well 912 may be part of an N-type recessed gate transistor, and thus may be formed into a region for forming an N-type recessed gate transistor. To form the P-well 912, in some embodiments, a mask layer 909 is formed on the silicon substrate 900, and then the mask layer 909 is patterned to expose a region where the P-well 912 will be formed. The mask layer 909 may include a soft mask layer, such as a photoresist layer, and / or may include a hard mask layer, such as a silicon oxide layer. The mask layer 909 may be patterned and aligned between the isolations 902 using photolithography and wet / dry etching. The mask layer 909 may be used to perform ion implantation of P-type dopants (e.g., B or Ga) into the intended region between the isolations 902, thereby forming the P-well 912. In some implementations, ion implantation conditions of the N-well 904 , the P-well 906 , and the P-well 912 are controlled such that the depth of the P-well 912 is greater than the depths of the N-well 904 and the P-well 906 .

[0104] like Fig.11 As shown, in operation 1106, a recess is formed in the first well of the substrate so that the recess is surrounded by the first well. In some embodiments, the depth of the recess is between 50 nm and 100 nm. Fig.9DAs shown in , recesses 914 are formed in the N-well 910 and the P-well 912, respectively, by (for example) the same etching process. In some embodiments, a mask layer 911 is formed on the silicon substrate 900, and then patterned to expose the regions in the N-well 910 and the P-well 912 where the recesses 914 will be formed. The mask layer 911 may include a soft mask layer, such as a photoresist layer, and / or may include a hard mask layer, such as a silicon oxide layer. The mask layer 911 may be patterned using photolithography and wet / dry etching. Thereafter, etching of the silicon substrate 900 is performed using the mask layer 911, thereby forming recesses 914 in the wells 910 and 912. The etching process may include dry etching and / or wet etching. In some embodiments, the etching process is a dry etching process, such as reactive ion etching (RIE). The etching conditions (for example, etching rate and etching duration) may be controlled to control the depth of the recess 914. In some embodiments, the depth of the recess 914 is between 50 nm and 100 nm. Fig.9D As shown in FIG. 1 , recess 914 is formed only in wells 910 and 912 of the recessed gate transistor, but not in wells 904 and 906 of the planar gate transistor.

[0105] like Fig.11 As shown in , in operation 1108, a curved gate dielectric on the sidewalls and bottom surface of the recess and a flat gate dielectric on the substrate are formed. In some embodiments, to form the curved gate dielectric and the flat gate dielectric, a sacrificial dielectric layer is formed on the sidewalls and bottom surface of the recess, the sacrificial dielectric layer is removed, a gate dielectric layer is formed on the sidewalls and bottom surface of the recess, and the gate dielectric layer is patterned.

[0106] like Figure 9J As shown in FIG. , in each recess 914 (eg Fig.9D A curved gate dielectric 931 is formed on the sidewall and bottom surface of the silicon substrate 900, and a flat gate dielectric 925 is formed on the silicon substrate 900. In order to form the curved gate dielectric 931 and the flat gate dielectric 925, as shown in Fig.9EAs shown in , a gate dielectric layer 916 can be formed on the sidewalls and bottom surface of each recess 914 and on the top surface of the silicon substrate 900 (e.g., wells 904 and 906) by the same deposition process. In some embodiments, a layer of dielectric material, such as silicon oxide, is deposited using one or more thin film deposition processes including, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. For example, a silicon oxide layer can be deposited using in-situ steam generation (ISSG) to form the gate dielectric layer 916. In some embodiments, before forming the gate dielectric layer 916, a sacrificial dielectric layer (not shown) is formed on the sidewalls and bottom surface of the recess 914 using, for example, thermal oxidation to remove defects on the sidewalls and bottom surface of the recess 914 caused by the etching process. Thereafter, before forming the gate dielectric layer 916, the sacrificial dielectric layer is removed using, for example, wet etching. As shown in FIG. Fig.9I and Figure 9J As shown, the gate dielectric layer 916 can be patterned using photolithography and etching processes in sequential steps or in the same step to form a flat gate dielectric 925 and a curved gate dielectric 931.

[0107] like Fig.11 As shown, in step 1110, a recessed gate electrode on the curved gate dielectric and a flat gate electrode on the flat gate dielectric are formed. In some embodiments, to form the recessed gate electrode and the flat gate electrode, a gate electrode layer is formed on the curved gate dielectric to fill the recess, the gate electrode layer is flattened, and the flattened gate electrode layer is patterned.

[0108] like Figure 9J As shown in FIG. 1 , a recessed gate electrode 920 is formed on a curved gate dielectric 931, and a flat gate electrode 922 is formed on a flat gate dielectric 925. In order to form the recessed gate electrode 920 and the flat gate electrode 922, as shown in FIG. Fig.9F As shown in FIG. 1 , a gate electrode layer 918 is formed on the gate dielectric layer 916. The recess 914 ( Fig.9E ). In some embodiments, a layer of conductive material, such as polysilicon, is deposited on the gate dielectric layer 916 using one or more thin film deposition processes including but not limited to CVD, PVD, ALD, or any combination thereof. According to the surface flatness of the gate electrode layer 918 affected by the depth of the recess 914, a planarization process, such as chemical mechanical polishing (CMP), may be performed to planarize the top surface of the gate electrode layer 918. Figure 9G As shown, a recessed gate electrode 920 and a planar gate electrode 922 are formed by patterning the gate electrode layer 918 using photolithography and etching processes in the same step.

[0109] like Fig.11 As shown, in operation 1112, a spacer is formed on the sidewall of the planar gate electrode above the substrate and on the sidewall of the recessed gate electrode above the substrate. Figure 9H As shown, a spacer 924 is formed on the sidewalls of the planar gate electrode 922 and on the sidewalls of the recessed gate electrode 920 on the silicon substrate 900. In some embodiments, to form the spacer 924, one or more thin film deposition processes including but not limited to CVD, PVD, ALD, or any combination thereof are used to deposit a layer of dielectric material (not shown), such as silicon nitride, on the sidewalls and top surfaces of the recessed gate electrode 920 and the planar gate electrode 922 and on the gate dielectric layer 916. Thereafter, the deposited layer of dielectric material is patterned using photolithography and etching processes in the same step to remove portions located on the recessed gate electrode 920, the planar gate electrode 922, and the top surface of the gate dielectric layer 916, leaving portions located on the sidewalls of the recessed gate electrode 920 and the planar gate electrode 922 to form the spacer 924.

[0110] like Fig.11 As shown, in operation 1114, a first source and a first drain separated by a curved gate dielectric and a recessed gate dielectric are formed in the first well. Fig.9I As shown, a P-type source 932 and a P-type drain 932 separated by a curved gate dielectric 931 and a recessed gate electrode 920 are formed in the N-well 910. In order to form the P-type source and drain 932, in some embodiments, a mask layer 930 is formed on the silicon substrate 900, and then the mask layer 930 is patterned to expose the area where the P-type source and drain 932 will be formed. The mask layer 930 may include a soft mask layer, such as a photoresist layer, and / or may include a hard mask layer, such as a silicon oxide layer. The mask layer 930 may be patterned and aligned with the N-well 910 using photolithography and wet / dry etching. The mask layer 930 may be used to perform ion implantation of a P-type dopant (e.g., B or Ga) into the N-well 910 to form the P-type source and drain 932 separated by the curved gate dielectric 931 and the recessed gate electrode 920.

[0111] like Fig.11 As shown, in operation 1116, a second source and a second drain are formed in the second well. Figure 9JAs shown, an N-type source 934 and an N-type drain 934 separated by a curved gate dielectric 931 and a recessed gate electrode 920 are formed in the P-well 912. In order to form the N-type source and drain 934, in some embodiments, a mask layer 933 is formed on the silicon substrate 900, and then the mask layer 933 is patterned to expose the area where the N-type source and drain 934 will be formed. The mask layer 933 may include a soft mask layer, such as a photoresist layer, and / or may include a hard mask layer, such as a silicon oxide layer. The mask layer 933 may be patterned and aligned with the P-well 912 using photolithography and wet / dry etching. The mask layer 933 may be used to perform ion implantation of an N-type dopant (e.g., P or As) into the P-well 912 to form the N-type source and drain 934 separated by the curved gate dielectric 931 and the recessed gate electrode 920.

[0112] like Fig.9I As shown, next, a P-type source and drain 926 and an N-type source and drain 928 are formed in the N-well 904 and the P-well 906 of the planar gate transistor, respectively, using photolithography and subsequent ion implantation of corresponding P-type dopants and N-type dopants. In some embodiments, the ion implantation conditions of the P-type source and drain 926, the N-type source and drain 928, the P-type source and drain 932, and the N-type source and drain 934 make the doping concentrations of the P-type source and drain 932 and the N-type source and drain 934 of the recessed gate transistor different from the doping concentrations of the P-type source and drain 926 and the N-type source and drain 928 of the planar gate transistor.

[0113] In some embodiments, to form a second semiconductor structure including a recessed gate transistor, a recessed gate transistor is formed in the first device layer, and a flat gate transistor is formed in the second device layer. The first device layer and the second device layer may be stacked one on top of the other, i.e., formed in different planes. For example, Figure 8C As shown in , a recessed gate transistor 872 is formed in a semiconductor layer 870 (eg, a second substrate), and a planar gate transistor 876 is formed on a semiconductor layer 874 above the recessed gate transistor 872 .

[0114] refer to Fig.10 , method 1000 proceeds to operation 1008, in which a second bonding layer including a plurality of second bonding contacts is formed over the recessed gate transistor. Figure 8B As shown in FIG. 1 , a bonding layer 851 including bonding contacts 853 is formed over the array of recessed gate transistors 839. The method 1000 proceeds to operation 1010, as shown in FIG. Fig.10As shown, in this operation, the first semiconductor structure and the second semiconductor structure are bonded in a face-to-face manner so that the array of NAND memory strings is coupled to the recessed gate transistor across the bonding interface. The bonding can be a hybrid bonding. In some embodiments, after bonding, the second semiconductor structure is located above the first semiconductor structure. In some embodiments, after bonding, the first semiconductor structure is located above the second semiconductor structure.

[0115] like Fig. 8A As shown, the second semiconductor structure 804 having the NAND memory string 838 is turned upside down. The downward bonding layer 826 is bonded to the upward bonding layer 822, that is, in a face-to-face manner, thereby forming a bonding interface 806. In some embodiments, a treatment process is applied to the bonding surface before bonding, such as plasma treatment, wet treatment and / or heat treatment. After bonding, the bonding contacts 828 in the bonding layer 826 are aligned with the bonding contacts 824 in the bonding layer 822 and contact each other, so that the NAND memory string 838 can be coupled to the device layer 810 (e.g., peripheral circuits 812 and 814). Similarly, as Figure 8B As shown in , the first semiconductor structure 805 with the peripheral circuits 835 and 837 is turned upside down. The downward bonding layer 851 is bonded to the upward bonding layer 829, that is, in a face-to-face manner, thereby forming a bonding interface 807. After bonding, the bonding contacts 853 in the bonding layer 851 and the bonding contacts 855 in the bonding layer 829 are aligned and contact each other, so that the NAND memory string 817 can be coupled to the device layer 831 (e.g., the peripheral circuits 835 and 837).

[0116] Method 1000 proceeds to operation 1012, such as Fig.10 As shown in , in this operation, one of the first substrate and the second substrate is thinned, and the one substrate is located on the other substrate of the first substrate and the second substrate. Fig. 8A As shown in , since the substrate of the second semiconductor structure 804 having the NAND memory string 838 is located above the substrate of the first semiconductor structure 802 having the peripheral circuits 812 and 814, the substrate of the second semiconductor structure 804 is thinned using a CMP and / or etching process to form a semiconductor layer 848. Similarly, as Figure 8B As shown in , since the substrate of the first semiconductor structure 805 having the peripheral circuits 835 and 837 is located above the substrate of the second semiconductor structure 803 having the NAND memory string 817, the substrate of the first semiconductor structure 805 is thinned using a CMP and / or etching process to form a semiconductor layer 833.

[0117] Method 1000 proceeds to operation 1014, as shown in FIG. 14, in which an interconnect layer is formed on the thinned first or second substrate. Fig. 8A As shown in FIG. 8 , a pad lead-out interconnection layer 850 is formed on the semiconductor layer 848 (the thinned top substrate). Figure 8B As shown, a pad lead-out interconnection layer 843 is formed on the semiconductor layer 833 (the thinned top substrate).

[0118] According to one aspect of the present disclosure, a method for forming a 3D memory device is disclosed. A first semiconductor structure including an array of NAND memory strings is formed on a first substrate. A second semiconductor structure including a recessed gate transistor is formed on a second substrate. The recessed gate transistor includes a recessed gate structure extending deep into the second substrate. The first semiconductor structure and the second semiconductor structure are bonded in a face-to-face manner so that the array of NAND memory strings is coupled to the recessed gate transistor across a bonding interface.

[0119] In some embodiments, to form the second semiconductor structure, a recess is formed in the second substrate, a gate dielectric is formed on sidewalls and a bottom surface of the recess, and a gate electrode is formed on the gate dielectric.

[0120] In some embodiments, to form the second semiconductor structure, a well is formed in the second substrate such that the recess is located in the well, and a source and a drain separated by the recessed gate structure are formed.

[0121] In some embodiments, to form the first semiconductor structure, a first bonding layer including a plurality of first bonding contacts is formed over the array of NAND memory strings. In some embodiments, to form the second semiconductor structure, a second bonding layer including a plurality of second bonding contacts is formed over the recessed gate transistor. In some embodiments, after the bonding, the first bonding contact contacts the second bonding contact at the bonding interface.

[0122] In some embodiments, after the bonding, one of the first substrate and the second substrate is thinned, the one substrate being located on the other of the first substrate and the second substrate, and an interconnection layer is formed on the thinned first substrate or the second substrate.

[0123] In some embodiments, the bonding comprises mixed bonding.

[0124] In some embodiments, to form the second semiconductor structure, the recessed gate transistor and the planar gate transistor are formed on the second substrate.

[0125] In some embodiments, to form the second semiconductor structure, the recessed gate transistor is formed in a first device layer, and a planar gate transistor is formed in a second device layer.

[0126] In some embodiments, the first device layer and the second device layer are stacked on top of each other.

[0127] In some embodiments, to form the second semiconductor structure, the recessed gate transistor is formed on the second substrate, and to form the first semiconductor structure, a planar gate transistor is formed in a device layer.

[0128] In some embodiments, the device layer and the array of NAND memory strings are arranged on top of each other.

[0129] According to another aspect of the present disclosure, a method for forming a semiconductor device is disclosed. A recess is formed in a substrate. A first gate dielectric is formed on the sidewalls and bottom surface of the recess and a second gate dielectric is formed on the substrate. A first gate electrode is formed on the first gate dielectric and a second gate electrode is formed on the second gate dielectric.

[0130] In some embodiments, the depth of the depression is between 50 nm and 100 nm.

[0131] In some embodiments, a first well and a second well are formed in the substrate such that the recess is located in the first well and the second gate dielectric is located on the second well, a first source and a first drain separated by the first gate dielectric and the first gate electrode are formed in the first well, and a second source and a second drain are formed in the second well.

[0132] In some embodiments, each of the first source, the first drain, the second source, and the second drain is doped.

[0133] In some embodiments, the doping concentration of the first source and the first drain is different from the doping concentration of the second source and the second drain.

[0134] In some embodiments, the depth of the first well is greater than the depth of the second well.

[0135] In some embodiments, in order to form the first gate dielectric and the second gate dielectric, a sacrificial dielectric layer is formed on the sidewalls and the bottom surface of the recess, the sacrificial dielectric layer is removed, a gate dielectric layer is formed on the sidewalls and the bottom surface of the recess, and the gate dielectric layer is patterned.

[0136] In some embodiments, to form the first gate electrode and the second gate electrode, a gate electrode layer is formed on the gate dielectric layer to fill the recess, the gate electrode layer is planarized, and the planarized gate electrode layer is patterned.

[0137] In some embodiments, a spacer is formed on a sidewall of the second gate electrode located above the substrate and on a sidewall of the first gate electrode located above the substrate.

[0138] The description of the above specific embodiments can be easily modified and / or adjusted for various applications. Therefore, based on the teaching and guidance provided herein, it is intended that such adjustments and modifications fall within the meaning and equivalents of the disclosed embodiments.

[0139] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. A method for forming a three-dimensional (3D) memory device, comprising: forming a first semiconductor structure including an array of NAND memory strings on a first substrate; A second semiconductor structure including a peripheral circuit is formed on a second substrate, wherein the peripheral circuit includes a flat gate transistor and a recessed gate transistor, wherein the recessed gate transistor includes a recessed gate structure extending deep into the second substrate, wherein forming the second semiconductor structure includes: forming the recessed gate transistor in a first device layer; and forming a flat gate transistor in a second device layer above the first device layer; and The first semiconductor structure and the second semiconductor structure are bonded in a face-to-face manner such that the array of NAND memory strings are coupled to the recessed gate transistors across a bonding interface.

2. The method according to claim 1, wherein: Forming the second semiconductor structure includes: forming a recess in the second substrate; forming a gate dielectric on sidewalls and a bottom surface of the recess; and A gate electrode is formed on the gate dielectric.

3. The method according to claim 2, wherein: Forming the second semiconductor structure further includes: forming a well in the second substrate such that the recess is located in the well; and A source and a drain separated by the recessed gate structure are formed.

4. The method according to any one of claims 1 to 3, wherein: Forming the first semiconductor structure includes forming a first bonding layer including a plurality of first bonding contacts over the array of NAND memory strings; Forming the second semiconductor structure includes forming a second bonding layer including a plurality of second bonding contacts over the recessed gate transistor; and After the bonding, the first bonding contact is in contact with the second bonding contact at the bonding interface.

5. The method according to any one of claims 1 to 4, further comprising: After the bonding, thinning one of the first substrate and the second substrate, the one substrate being located on the other of the first substrate and the second substrate; as well as An interconnection layer is formed on the thinned first substrate or the second substrate.

6. The method according to any one of claims 1 to 5, wherein: The bonding includes mixed bonding.

7. The method according to claim 1, wherein: The first device layer and the second device layer are stacked on each other.

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