Image correction method and related device

Abstract

The present invention discloses an image correction method and related devices. The method includes: obtaining a distortion coefficient matrix from an on-chip ROM based on an interpolation method and writing it into the DDR; storing the rearranged image into the DDR; reading a row or a column in the distortion coefficient matrix in the DDR and reading the block image, and performing image correction using the interpolation method. If the current block image has not completed the correction of all pixels corresponding to the row or the column, continue to read the remaining block images and correct them until the correction of all pixels corresponding to the row or the column is completed. When the correction of all pixels corresponding to the row or the column is completed, cache and output the corrected image and perform the pixel correction corresponding to the next row or column. By rearranging data in a certain way according to this method, the processing cycle can be reduced, and by performing row-by-row or column-by-column correction on the pixels corresponding to the distortion correction coefficients, the continuity and real-time performance of image correction can be ensured. The above method can be used for the rapid correction of high-resolution original graphics.

Description

Technical Field

[0001] This specification relates to the field of image processing. More specifically, the present invention relates to an image correction method and related devices. Background Art

[0002] During the process of a camera capturing an image, due to factors such as the manufacturing errors of the lens and the design, manufacturing, alignment, and environmental control of the imaging system itself, the projection rays between the image and the object cannot strictly meet the requirement of straight-line propagation within the entire field of view. Therefore, geometric correction of the distorted image is required to achieve a suitable visual effect. When performing distortion correction on high-resolution video images, a large amount of data needs to be processed in real time. When the memory of the hardware system is fixed, how to improve the speed of image correction has become an urgent problem to be solved.

[0003] Therefore, it is necessary to propose an image correction method to at least partially solve the problems existing in the prior art. Summary of the Invention

[0004] A series of simplified concepts are introduced in the Summary of the Invention section, which will be further elaborated in detail in the Detailed Description section. The Summary of the Invention section of the present invention does not mean to attempt to define the key features and essential technical features of the claimed technical solution, nor does it mean to attempt to determine the protection scope of the claimed technical solution.

[0005] To at least partially solve the above problems, in a first aspect, the present invention proposes an image correction method, which includes:

[0006] Obtain a distortion coefficient matrix from the on-chip ROM based on the interpolation method and write it into the DDR, where the distortion coefficient matrix includes the correspondence between the original image and the corrected image;

[0007] Store the rearranged image in the DDR, where the rearranged image is an image obtained by rearranging the data of the original image;

[0008] Read a row or a column in the distortion coefficient matrix in the DDR and read the block image to perform image correction based on the interpolation method. If the current block image has not completed the correction of all pixels corresponding to the row or the column, continue to read the remaining block images and correct them until the correction of all pixels corresponding to the row or the column is completed, where the block image is an image obtained by evenly dividing the rearranged image into a target number of images;

[0009] When the correction of all pixels corresponding to the row or the column is completed, cache and output the corrected image and perform the pixel correction corresponding to the next row or column.

[0010] Optionally, before storing the rearranged image in the DDR, it further includes:

[0011] Rearrange the data of the original image to obtain a rearranged image.

[0012] Optionally, after storing the rearranged image in the DDR, the following steps are further included:

[0013] Obtain a block image based on the above rearranged image.

[0014] Optionally, the above method further includes:

[0015] Obtain the above original image by using ping-pong operation.

[0016] Optionally, the above interpolation method is bilinear interpolation.

[0017] Optionally, the above target quantity is determined based on the resolution of the above original image and the memory of the calibration processor.

[0018] Optionally, when all the pixels corresponding to the above row or column are corrected, caching and outputting the corrected image and performing pixel correction for the corresponding next row or column includes:

[0019] When all the pixels corresponding to the above row or column are corrected, cache and output the corrected image, and when there is a vacancy of one row in the memory of the calibration processor, perform pixel correction for the corresponding next row or next column.

[0020] In a second aspect, the present invention also proposes an image correction device, including:

[0021] A first acquisition unit, configured to obtain a distortion coefficient matrix from the on-chip ROM based on an interpolation method and write it into the DDR, where the above distortion coefficient matrix includes the correspondence between the original image and the corrected image;

[0022] A second acquisition unit, configured to store the rearranged image in the DDR, where the above rearranged image is an image obtained by rearranging the data of the original image;

[0023] An image correction unit, configured to read a row or a column in the above distortion coefficient matrix in the DDR and read the block image to perform image correction based on an interpolation method. If the current block image has not completed all pixel corrections corresponding to the above row or column, continue to read the remaining block images and correct them until all pixels corresponding to the above row or column are corrected, where the above block image is an image obtained by evenly dividing the above rearranged image into a target quantity;

[0024] An output control unit, configured to cache and output the corrected image and perform pixel correction for the corresponding next row or column when all pixels corresponding to the above row or column are corrected.

[0025] In a third aspect, an electronic device includes: a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program stored in the memory, it implements the steps of the image correction method according to any one of the first aspects described above.

[0026] In a fourth aspect, the present invention also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, it implements the image correction method according to any one of the first aspects described above.

[0027] In summary, by using the interpolation method in this method to obtain the high-resolution distortion coefficient matrix corresponding to the on-chip ROM, the picture correction accuracy can be improved. By rearranging and partitioning the data of the original picture, and rearranging the data in a certain way, the reading time can be reduced. At the same time, the partitioning process can save on-chip space. And by correcting the pixels corresponding to the distortion correction coefficients row by row or column by column, the continuity and real-time performance of image correction can be ensured. It can be seen that through the above method, real-time and fast correction of large-resolution images can be completed without upgrading the hardware conditions.

[0028] For the image correction method of the present invention, other advantages, objectives, and features of the present invention will be partially reflected by the following description, and will also be understood by those skilled in the art through the research and practice of the present invention. Description of the Drawings

[0029] By reading the detailed description of the preferred embodiments below, various other advantages and benefits will become clear to those of ordinary skill in the art. The drawings are only for the purpose of showing the preferred embodiments and are not considered to be a limitation of this specification. Moreover, throughout the drawings, the same reference numerals are used to represent the same components. In the drawings:

[0030] Figure 1 It is a schematic flowchart of an image correction method provided by an embodiment of the present application;

[0031] Figure 2 It is a schematic diagram of the principle of rearranging the original image data provided by an embodiment of the present application;

[0032] Figure 3 It is a schematic diagram of the principle of partitioning the rearranged image provided by an embodiment of the present application;

[0033] Figure 4 It is a schematic diagram of the structure of a ping-pong operation provided by an embodiment of the present application;

[0034] Figure 5 It is a schematic flowchart of the data operation in a state machine provided by an embodiment of the present application;

[0035] Figure 6 Schematic structural diagram of an image correction device provided by an embodiment of the present application;

[0036] Figure 7 Schematic structural diagram of an electronic device provided by an embodiment of the present application. Detailed implementation manners

[0037] Embodiments of the present application provide an image correction method and related devices, which can quickly correct distorted images.

[0038] The terms "first", "second", "third", "fourth", etc. (if any) in the specification, claims and drawings of the present application are used to distinguish similar objects, and do not necessarily describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices. The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments.

[0039] Please refer to Figure 1 , which is a possible schematic diagram of an image correction process provided by an embodiment of the present application, and specifically may include: S110 - S140.

[0040] S110, obtaining a distortion coefficient matrix from the on-chip ROM based on the interpolation method and writing it into the DDR, where the distortion coefficient matrix includes the correspondence between the original image and the corrected image;

[0041] Specifically, the space in the on-chip ROM (Read Only Memory) is limited. In order to compress the space, developers downsample the distortion coefficient matrix to obtain a forward mapping coefficient matrix with a smaller occupied space, and store the forward mapping coefficient matrix in the ROM. Before image correction, the interpolation method is used to obtain a higher-resolution distortion coefficient matrix according to the forward distortion coefficient matrix and write it into the DDR. Such a higher-resolution distortion coefficient matrix helps to make the image correction effect better.

[0042] S120, storing the rearranged image into the DDR, where the rearranged image is an image obtained by rearranging the data of the original image;

[0043] Specifically, rearranging the data of the original image according to a certain logic can greatly improve the reading efficiency, reduce the processing time, and ensure the real-time nature of the calibration process;

[0044] S130, read one row or one column of the above distortion coefficient matrix in the DDR and read the block image to perform image calibration based on the interpolation method. If the current block image has not completed the calibration of all pixels corresponding to the above one row or one column, continue to read and calibrate the remaining block images until the calibration of all pixels corresponding to the above one row or one column is completed. Among them, the above block image is an image obtained by evenly dividing the above rearranged image into a target number of images;

[0045] Specifically, read one row or one column of the distortion coefficient matrix in the DDR and read the block image to perform image calibration using the interpolation method. At this time, the current block image may not include the distortion points corresponding to all pixels corresponding to the above one row or one column due to image distortion. Then, continue to read and calibrate the subsequent block images until the calibration of all pixels corresponding to the above one row or one column is completed.

[0046] S140, when the calibration of all pixels corresponding to the above one row or one column is completed, cache and output the calibrated image and perform the pixel calibration corresponding to the next row or column.

[0047] Specifically, when the calibration of all pixels corresponding to the above one row or one column is completed, output the calibrated image and simultaneously perform the pixel calibration corresponding to the next row or column to ensure the continuity of the image calibration.

[0048] In summary, without improving the hardware processing capacity, by performing interpolation calculation on the distortion coefficient matrix in the on-chip ROM through this method, the image calibration accuracy can be improved. At the same time, by rearranging the data of the high-resolution image and performing block processing, the image can be calibrated using the existing hardware conditions. Rearranging the data in a certain way can reduce the processing cycle, and by performing row-by-row or column-by-column calibration on the pixels corresponding to the distortion correction coefficients, the continuity and real-time nature of the image calibration can be ensured. Through the above method, it can be used for the rapid calibration of high-resolution original graphics.

[0049] Please refer to Figure 2 , which is a schematic diagram of the principle of rearranging the original image data provided by the embodiment of the present application;

[0050] In some examples, before storing the above rearranged image in the DDR, it further includes:

[0051] Rearrange the data of the original image to obtain a rearranged image.

[0052] Specifically, as Figure 2As shown, the interpolation method is used to represent the first distorted pixel point with r11, r12, r21, and r22, the second distorted pixel point with r13, r14, r23, and r24, the third distorted pixel point with r31, r32, r41, and r42, and the fourth distorted pixel point with r33, r34, r43, and r44. If the processor processes line by line, then to obtain a pixel point, two lines of processing need to be executed, consuming two processing cycles. The original image is rearranged and written into a Double Data Rate Synchronous Dynamic Random Access Memory (DDR). The random access memory (RAM) reads the rearranged data in the DDR. RAM1 - RAM4 represent the 4 channels of the RAM. At this time, reading the first column data of the four channels can complete the reading of the first distorted pixel point, and at this time, only one processing cycle is required to read one distorted pixel point.

[0053] Please refer to Figure 3 , which is a schematic diagram of the principle of rearranging and dividing an image provided by an embodiment of this application. In some examples, after storing the rearranged image in the DDR, the following steps are further included:

[0054] Obtain a divided image based on the above rearranged image.

[0055] Specifically, as Figure 3 shows the dividing scheme of an image with a resolution of 1280×1024. Figure 3 As shown in the left half, the block coefficient matrix numbered B1,1 contains 4 rows and 8 columns, a total of 32 pixel points. According to this allocation scheme, the above picture can be divided into 1024÷4 = 256 rows and 1280÷8 = 160 columns. As Figure 3 shown in the right half, the above image can be divided into 256×160 blocks.

[0056] Please refer to Figure 4 , which is a schematic diagram of a possible ping - pong operation structure provided by this application. In some examples, the above method further includes:

[0057] Obtain the above original image by using a ping - pong operation.

[0058] Specifically, the input data passes through the input data stream selection unit 401. In the first buffering period, the data stream is stored in the data buffer unit 1 402. In the second buffering period, through the switching of the input data selection unit 401, the data is cached in the data buffer unit 2 403. At the same time, the data in the data buffer unit 1 402 is sent to the arithmetic processing unit 405 through the output data selection unit 404 for arithmetic processing. In the third buffering period, through the re-switching of the input data selection unit 401, the input data is cached in the data buffer unit 1. At the same time, the data in the data buffer unit 2 403 is sent to the arithmetic processing unit 405 through the output data selection unit 404 for arithmetic processing. This cycle continues. By using this method, the continuity of image information loading and processing can be achieved, and the efficiency of the corrected image operation can be improved.

[0059] In some examples, the above interpolation method is the bilinear interpolation method.

[0060] Specifically, the principle of the image interpolation algorithm is bilinear interpolation. Bilinear interpolation is extended from linear interpolation. The bilinear interpolation algorithm is simple and easy to implement, without considering the calculation order of interpolation, that is, calculating the interpolation in the x direction first and then in the y direction, or calculating the interpolation in the y direction first and then in the x direction, and the results are the same. The calculation formula of bilinear interpolation is as follows: I[x,y] = I[x i ,y i (1 - x f )(1 - y f ) + I[x i + 1,y i x f (1 - y f ) + I[x i ,y i + 1](1 - x f )y f + I[x i ,y i+1 + 1,y f x f

[0061] where I[x,y] represents the gray value of the interpolation point at (x, y), and x f and y f respectively represent the horizontal distance and vertical distance from the interpolation point (x, y) to the pixel point (x i ,y i ).

[0062] In some examples, the above target quantity is determined based on the resolution of the above original picture and the memory of the correction processor.

[0063] Specifically, when the resolution of the original image is large and the memory of the processor is small, the above-mentioned target quantity should be appropriately increased. When the resolution of the original image is small and the memory of the processor is large, the above-mentioned target quantity can be appropriately decreased.

[0064] In some examples, when all the pixel corrections corresponding to the above-mentioned row or column are completed, caching the output corrected image and performing pixel corrections corresponding to the next row or column includes:

[0065] When all the pixel corrections corresponding to the above-mentioned row or column are completed, cache the output corrected image, and when there is a vacancy in a row in the memory of the correction processor, perform pixel corrections corresponding to the next row or the next column.

[0066] Specifically, in order to improve the processing speed, the above operations use a pipelining operation mode. The correction processor does not process the next original image after the current original image processing is completed, but after the current row processing is completed, the subsequent data advances one row forward to be prepared for processing. This kind of processing is beneficial to improving the processing speed.

[0067] Please refer to Figure 5 , Figure 5 which is a schematic diagram of the data operation process in a possible state machine provided by an embodiment of the present application;

[0068] Specifically, this state machine mainly completes two major functions. First, use the state machine to complete power-on initialization, reading of image cache, reading of coefficient cache, storage of update information, update of data cache, etc. operations: when the state machine is powered on or receives a frame start signal, it enters the waiting state A. At this time, the coefficient writing to the DDR cache is not completed. When the coefficient writing to the DDR cache is completed, it enters the pre-reading state B. When the data of the first 12 rows of cache is read from the DDR, it enters the initialization table state C. After the initialization of the block information table is completed, it enters the coefficient reading state D. Second, perform image interpolation operations. In order to improve the processing speed, this part of the operation uses a pipelining operation mode: read 1 row from the DDR row by row, map the coefficients, and record the block information of the updated image, and enter the state of updating the image cache state E. When the block data update required for the coefficient interpolation of one row is completed, it enters the idle state. When there is more than 1 row of space in the coefficient FIFO (First Input First Output) cache, it enters the coefficient reading state D. And in the state E, the FIFO reads and updates the information of one block. At this time, it enters the state of reading the DDR state G. After completing the DDR reading and cache update of one block, it enters the state E; in this way, when there is one row of coefficient space left in the coefficient cache FIFO, it will trigger the first part of the data preparation operation, read the coefficients of one row or one column, judge the updated data, and perform data update, so as to improve the processing speed and meet the requirements of real-time processing.

[0069] Please refer to Figure 6 , an embodiment of the image correction device in the embodiment of the present application may include:

[0070] A first acquisition unit 201, configured to acquire a distortion coefficient matrix from the on-chip ROM based on an interpolation method and write it into the DDR, where the distortion coefficient matrix includes the correspondence between the original image and the corrected image;

[0071] A second acquisition unit 202, configured to store the rearranged image in the DDR, where the rearranged image is an image obtained by rearranging the data of the original image;

[0072] An image correction unit 203, configured to read a row or a column in the distortion coefficient matrix in the DDR and read the block image to perform image correction based on an interpolation method. If the current block image has not completed the correction of all pixels corresponding to the row or the column, continue to read the remaining block images and correct them until the correction of all pixels corresponding to the row or the column is completed, where the block image is an image obtained by evenly dividing the rearranged image into a target number of images;

[0073] An output control unit 204, configured to cache and output the corrected image and perform pixel correction corresponding to the next row or column when the correction of all pixels corresponding to the row or the column is completed.

[0074] Please refer to Figure 7 , Figure 7 which is a schematic diagram of an embodiment of an electronic device provided by the embodiment of the present application.

[0075] As Figure 7 shown, the embodiment of the present application further provides an electronic device 300, including a memory 310, a processor 320, and a computer program 311 stored on the memory 320 and executable on the processor. When the processor 320 executes the computer program 311, the steps of any method for image correction described above are implemented.

[0076] Since the electronic device introduced in this embodiment is the device used to implement an image correction device in the embodiment of the present application, based on the method introduced in the embodiment of the present application, those skilled in the art can understand the specific implementation manners and various variations of the electronic device in this embodiment. Therefore, the specific implementation of how this electronic device implements the method in the embodiment of the present application will not be described in detail here. As long as the device used by those skilled in the art to implement the method in the embodiment of the present application belongs to the scope protected by the present application.

[0077] In the specific implementation process, when the computer program 311 is executed by the processor, it can implement Figure 1 any implementation manner in the corresponding embodiment.

[0078] It should be noted that in the above embodiments, the descriptions of the various embodiments have their own emphases. For parts not described in detail in a certain embodiment, reference may be made to the relevant descriptions of other embodiments.

[0079] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system, or a computer program product. Therefore, the present application can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0080] The present application is described with reference to the flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each flow and / or block in the flowchart and / or block diagram, as well as the combination of flows and / or blocks in the flowchart and / or block diagram, can be realized by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded computer, or other programmable data processing devices to generate a machine, such that the instructions executed by the processor of the computer or other programmable data processing devices generate means for realizing the functions specified in Figure 1 one or more of the processes or multiple processes and / or blocks Figure 1 one or more of the blocks or multiple blocks.

[0081] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, such that the instructions stored in the computer-readable memory generate a manufactured article including instruction means, and the instruction means realizes the functions specified in Figure 1 one or more of the processes or multiple processes and / or blocks Figure 1 one or more of the blocks or multiple blocks.

[0082] These computer program instructions can also be loaded onto a computer or other programmable data processing device, such that a series of operation steps are executed on the computer or other programmable device to generate a computer-implemented process, and thus the instructions executed on the computer or other programmable device provide steps for realizing the functions specified in Figure 1 one or more of the processes or multiple processes and / or blocks Figure 1 one or more of the blocks or multiple blocks.

[0083] The embodiments of the present application also provide a computer program product, which includes computer software instructions. When the computer software instructions run on a processing device, the processing device is caused to execute as Figure 1The process in image correction in the corresponding embodiment.

[0084] A computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions according to the embodiments of the present application are wholly or partially generated. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions may be transmitted from a website, a computer, a server, or a data center to another website, computer, server, or data center in a wired manner (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or a wireless manner (such as infrared, wireless, microwave, etc.). The computer-readable storage medium may be any available medium that can be stored by a computer or a data storage device such as a server or a data center that includes one or more integrated available media. The available medium may be a magnetic medium (such as a floppy disk, a hard disk, a magnetic tape), an optical medium (such as a DVD), or a semiconductor medium (such as a solid state disk (SSD)), etc.

[0085] Those skilled in the art can clearly understand that for the convenience and conciseness of description, the specific working processes of the above-described systems, devices, and units can refer to the corresponding processes in the foregoing method embodiments and will not be elaborated herein.

[0086] In several embodiments provided in the present application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of units is only a logical function division, and there may be other division methods in actual implementation. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Another point is that the displayed or discussed coupling, direct coupling, or communication connection to each other may be through some interfaces, and the indirect coupling or communication connection of devices or units may be in an electrical, mechanical, or other form.

[0087] The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place or distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0088] In addition, in each embodiment of the present application, each functional unit can be integrated into a processing unit, or each unit can exist physically alone, or two or more units can be integrated into one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of a software functional unit.

[0089] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods in each embodiment of the present application. The foregoing storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical discs that can store program codes.

[0090] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of each embodiment of the present application.

Claims

1. An image correction method, characterized in that, Including: Obtaining a distortion coefficient matrix from the on-chip ROM based on interpolation method and writing it into the DDR, where the distortion coefficient matrix includes the correspondence between the original image and the corrected image; Rearranging the data of the original image to be read in parallel through multiple channels of the RAM, so that the reading of each distorted pixel point is completed within one processing cycle, obtaining a rearranged image; Storing the rearranged image into the DDR, where the rearranged image is an image obtained by rearranging the data of the original image; Reading a row or a column in the distortion coefficient matrix in the DDR and reading the block images for image correction based on interpolation method. If the current block image has not completed the correction of all pixels corresponding to the row or the column, continue to read and correct the remaining block images until the correction of all pixels corresponding to the row or the column is completed. Here, the block image is an image obtained by evenly dividing the rearranged image into a target number of images; the target number is determined based on the resolution of the original image and the memory of the correction processor; When the correction of all pixels corresponding to the row or the column is completed, caching and outputting the corrected image. When there is a vacant row in the memory of the correction processor, perform the pixel correction corresponding to the next row or the next column.

2. The method according to claim 1, characterized in that, After storing the rearranged image into the DDR, it further includes: Obtaining block images based on the rearranged image.

3. The method according to claim 1, wherein The method further includes: Obtaining the original image by using ping-pong operation.

4. The method according to claim 1, wherein The interpolation method is bilinear interpolation method.

5. An image correction device, characterized in that, Including: A first obtaining unit, configured to obtain a distortion coefficient matrix from the on-chip ROM based on interpolation method and write it into the DDR, where the distortion coefficient matrix includes the correspondence between the original image and the corrected image; A second obtaining unit, configured to rearrange the data of the original image to be read in parallel through multiple channels of the RAM, so that the reading of each distorted pixel point is completed within one processing cycle, obtaining a rearranged image; storing the rearranged image into the DDR, where the rearranged image is an image obtained by rearranging the data of the original image; An image correction unit, configured to read a row or a column in the distortion coefficient matrix in the DDR and read the block images for image correction based on interpolation method. If the current block image has not completed the correction of all pixels corresponding to the row or the column, continue to read and correct the remaining block images until the correction of all pixels corresponding to the row or the column is completed. Here, the block image is an image obtained by evenly dividing the rearranged image into a target number of images; the target number is determined based on the resolution of the original image and the memory of the correction processor; An output control unit, configured to cache and output the corrected image when the correction of all pixels corresponding to the row or the column is completed, and perform the pixel correction corresponding to the next row or the next column when there is a vacant row in the memory of the correction processor.

6. An electronic device, comprising: A memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor is configured to implement the steps of the image correction method according to any one of claims 1-4 when executing the computer program stored in the memory.

7. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, it implements the image correction method according to any one of claims 1-4.

Images