Semiconductor device including a semiconductor pattern

Abstract

A semiconductor device is disclosed, comprising a first conductive line and a second conductive line spaced apart from the first conductive line. A semiconductor pattern is disposed between the first and second conductive lines. The semiconductor pattern includes a first semiconductor pattern having impurities of a first conductivity type and disposed adjacent to the first conductive line. A second semiconductor pattern having impurities of a second conductivity type is disposed adjacent to the second conductive line. A third semiconductor pattern is disposed between the first and second semiconductor patterns. The third semiconductor pattern includes a first region disposed adjacent to the first semiconductor pattern and a second region disposed between the first and second semiconductor patterns. At least one of the first and second regions includes an intrinsic semiconductor layer. A first gate line intersects the first region, and a second gate line intersects the second region.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2020-0058999, filed on May 18, 2020, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] Exemplary embodiments of the present invention relate to semiconductor devices including semiconductor patterns. Background Technology

[0003] Techniques are being developed for setting stacked structures on a substrate to provide highly integrated semiconductor devices. The stacked structure can include multiple semiconductor patterns. Each of the multiple semiconductor patterns can have a minimum size to maintain desired electrical characteristics. Therefore, research is underway on various techniques that can maintain the desired electrical characteristics of multiple semiconductor patterns while minimizing the size of each of the multiple semiconductor patterns. Summary of the Invention

[0004] Exemplary embodiments of the present invention provide semiconductor devices with excellent electrical characteristics and high integration.

[0005] According to an exemplary embodiment of the present invention, a semiconductor device includes a first conductive line and a second conductive line spaced apart from the first conductive line. A semiconductor pattern is disposed between the first conductive line and the second conductive line. The semiconductor pattern includes a first semiconductor pattern disposed adjacent to the first conductive line, the first semiconductor pattern having a first conductivity type impurity. A second semiconductor pattern is disposed adjacent to the second conductive line. The second semiconductor pattern has a second conductivity type impurity different from the first conductivity type impurity. A third semiconductor pattern is disposed between the first semiconductor pattern and the second semiconductor pattern. The third semiconductor pattern includes a first region disposed adjacent to the first semiconductor pattern and a second region disposed between the first region and the second semiconductor pattern. At least one of the first region and the second region includes an intrinsic semiconductor layer. A first gate line intersects the first region, and a second gate line intersects the second region.

[0006] According to an exemplary embodiment of the present invention, a semiconductor device includes a plurality of semiconductor patterns stacked on a substrate. Each of the plurality of semiconductor patterns extends in a first direction parallel to an upper surface of the substrate. Each of the plurality of semiconductor patterns includes: a first semiconductor pattern having a first conductivity type impurity; a second semiconductor pattern having a second conductivity type impurity different from the first conductivity type impurity; and a third semiconductor pattern disposed between the first semiconductor pattern and the second semiconductor pattern. The third semiconductor pattern includes a first region disposed adjacent to the first semiconductor pattern and a second region disposed between the first region and the second semiconductor pattern. At least one of the first region and the second region includes an intrinsic semiconductor layer. A first conductor is connected to the plurality of semiconductor patterns. A plurality of second conductors are spaced apart from the first conductor. Each of the plurality of second conductors extends in a second direction parallel to the upper surface of the substrate and intersecting the first direction. Each of the second conductors is connected to a corresponding semiconductor pattern among the plurality of semiconductor patterns. A first gate line is configured to be adjacent to the plurality of semiconductor patterns and extends upward in a third direction intersecting the first and second directions. A second gate line is configured to be adjacent to the plurality of semiconductor patterns. The second gate line extends upward in a third direction and is parallel to the first gate line. The first gate line intersects the first region, and the second gate line intersects the second region.

[0007] According to an exemplary embodiment of the present invention, a semiconductor device includes a plurality of semiconductor patterns disposed on a substrate. Each of the plurality of semiconductor patterns extends in a first direction parallel to an upper surface of the substrate. The plurality of semiconductor patterns are arranged in a second direction intersecting the first direction. Each of the plurality of semiconductor patterns includes: a first semiconductor pattern having a first conductivity type impurity; a second semiconductor pattern having a second conductivity type impurity different from the first conductivity type impurity; and a third semiconductor pattern disposed between the first semiconductor pattern and the second semiconductor pattern. The third semiconductor pattern includes a first region disposed adjacent to the first semiconductor pattern and a second region disposed between the first region and the second semiconductor pattern. At least one of the first region and the second region includes an intrinsic semiconductor layer. A first conductor is connected to the plurality of semiconductor patterns. A plurality of second conductors are spaced apart from the first conductor. Each of the plurality of second conductors extends upward in a third direction intersecting the first and second directions. Each of the second conductors is connected to a corresponding semiconductor pattern among the plurality of semiconductor patterns. A first gate line is disposed adjacent to the plurality of semiconductor patterns and extends in the second direction. A second gate line is disposed adjacent to the plurality of semiconductor patterns. The second gate line extends in the second direction and is parallel to the first gate line. The first gate line intersects the first region, and the second gate line intersects the second region. Attached Figure Description

[0008] Figure 1 , Figure 5 , Figure 7 , Figure 9 , Figure 11 , Figure 13 , Figure 15 , Figure 17 , Figure 19 , Figure 21 , Figure 23 and Figure 25 This is a perspective view of a semiconductor device according to an exemplary embodiment of the present invention; and

[0009] Figures 2 to 4 as well as Figure 6 , Figure 8 , Figure 10 , Figure 12 , Figure 14 , Figure 16 , Figure 18 , Figure 20 , Figure 22 , Figure 24 and Figure 26 This is a plan view of the layout of a semiconductor device according to an exemplary embodiment of the present invention. Detailed Implementation

[0010] Figure 1 This is a perspective view of a semiconductor device according to an exemplary embodiment of the present invention. Figures 2 to 4 Is with Figure 1 A plan view of the layout of a portion of the corresponding semiconductor device. Each of the semiconductor devices according to exemplary embodiments of the present invention may include a thyristor dynamic random access memory (DRAM) without capacitors. In exemplary embodiments, each of the semiconductor devices may include a gate voltage-applied thyristor having a vertically stacked structure.

[0011] Reference Figure 1 Each of the semiconductor devices according to exemplary embodiments of the present invention may include a substrate 21, an interlayer insulating layer 25, a gate dielectric layer 42, a source line SL, multiple bit lines BL, multiple semiconductor patterns SP, multiple first gate lines G1, multiple second gate lines G2, and multiple select gate lines SG. A first direction D1, a second direction D2 intersecting the first direction D1, and a third direction D3 intersecting the first direction D1 and the second direction D2 may be defined on the substrate 21. Figures 1 to 2 In the exemplary embodiment shown, the first direction D1 may correspond to a row direction parallel to the upper surface of the substrate 21. The second direction D2 may correspond to a column direction also parallel to the upper surface of the substrate 21. Figures 1 to 2In the exemplary embodiment shown, the first direction D1 and the second direction D2 may be perpendicular to each other. However, in other exemplary embodiments, the first direction D1 and the second direction D2 may intersect each other at various different angles. The third direction D3 may correspond to a vertical direction perpendicular to the upper surface of the substrate 21 and perpendicular to the first direction D1 and the second direction D2. For example, the third direction D3 may be the thickness direction of the substrate 21.

[0012] The source line SL may extend from the substrate 21 in the second direction D2 and the third direction D3. In an exemplary embodiment, the source line SL may be in the form of a wall. In an exemplary embodiment, the source line SL may correspond to a common anode line. The source line SL may be referred to as the "first conductor".

[0013] Multiple bit lines BL may be spaced apart from source lines SL. Each of the multiple bit lines BL may extend in a second direction D2. In an exemplary embodiment, each of the multiple bit lines BL may include a line shape, a bar shape, a column shape, or a combination thereof. However, exemplary embodiments of the inventive concept are not limited thereto. Figure 1 In the exemplary embodiment shown, multiple bit lines BL can be stacked in parallel on a third direction D3. In the exemplary embodiment, each of the multiple bit lines BL can be referred to as a "second conductor". Each of the multiple bit lines BL can correspond to a cathode line.

[0014] Each of the plurality of semiconductor patterns SP may extend in a first direction D1. In an exemplary embodiment, each of the plurality of semiconductor patterns SP may include a line shape, a strip shape, a column shape, or a combination thereof. However, exemplary embodiments of the inventive concept are not limited thereto. In an exemplary embodiment, at least a portion of the plurality of semiconductor patterns SP may be arranged parallel to a second direction D2. In an exemplary embodiment, as... Figure 1 In the exemplary embodiment shown, at least a portion of the plurality of semiconductor patterns SP can also be arranged parallel to a third direction D3. For example, the semiconductor patterns SP can be arranged at multiple different heights from the substrate 21 along the third direction D3, and the plurality of semiconductor patterns SP can be arranged to be spaced apart from each other in a second direction D2 at the respective different heights. Each of the plurality of semiconductor patterns SP can be electrically connected to a source line SL and a corresponding bit line BL. For example, one lateral side of each of the plurality of semiconductor patterns SP can contact the source line SL, and another lateral side of each of the plurality of semiconductor patterns SP can contact a bit line in the plurality of bit lines BL. The plurality of bit lines BL can be electrically connected to the source line SL via the plurality of semiconductor patterns SP.

[0015] In an exemplary embodiment, each of the plurality of first gate lines G1, the plurality of second gate lines G2, and the plurality of select gate lines SG may include a dual-gate structure. For example, each of the plurality of first gate lines G1 may include a pair of first gate lines G1. Each of the plurality of second gate lines G2 may include a pair of second gate lines G2. Each of the plurality of select gate lines SG may include a pair of select gate lines SG.

[0016] Each of the plurality of first gate lines G1, the plurality of second gate lines G2, and the plurality of select gate lines SG may extend longitudinally on the third direction D3. Each of the plurality of first gate lines G1, the plurality of second gate lines G2, and the plurality of select gate lines SG may extend across some of the corresponding semiconductor patterns SP in the plurality of semiconductor patterns SP. In an exemplary embodiment, the plurality of first gate lines G1, the plurality of second gate lines G2, and the plurality of select gate lines SG may be arranged in parallel.

[0017] like Figures 1 to 2 In the exemplary embodiment shown, a plurality of first gate lines G1 may be arranged in parallel along a second direction D2. A plurality of second gate lines G2 may be arranged in parallel along a first direction D1 with respect to the plurality of first gate lines G1. A plurality of second gate lines G2 may be arranged in parallel along a second direction D2. A plurality of select gate lines SG may be arranged in parallel along a first direction D1 with respect to the plurality of first gate lines G1. A plurality of select gate lines SG may be arranged in parallel along a second direction D2.

[0018] The gate dielectric layer 42 may (e.g., on the second direction D2) be disposed between each of the plurality of first gate lines G1, the plurality of second gate lines G2, and the plurality of select gate lines SG and a corresponding semiconductor pattern SP among the plurality of semiconductor patterns SP. For example, as Figure 2 In the exemplary embodiment shown, the gate dielectric layer 42 may (e.g., in the second direction D2) directly contact each lateral side of the third semiconductor pattern SP3. Each of the plurality of first gate lines G1 and the plurality of second gate lines G2 may correspond to a word line.

[0019] In an exemplary embodiment, substrate 21 may include a semiconductor substrate, such as a single-crystal silicon wafer or a silicon-on-insulator (SOI) wafer. In an exemplary embodiment, each of the source line SL, the plurality of bit lines BL, the plurality of first gate lines G1, the plurality of second gate lines G2, and the plurality of select gate lines SG may include a material selected from metals, metal nitrides, metal silicides, metal oxides, conductive carbon, polysilicon, or combinations thereof. For example, each of the source line SL, the plurality of bit lines BL, the plurality of first gate lines G1, the plurality of second gate lines G2, and the plurality of select gate lines SG may include W, WN, Ru, Ti, TiN, Ta, TaN, Co, Pt, or combinations thereof.

[0020] In an exemplary embodiment, the interlayer insulating layer 25 may include a material selected from silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, high-k dielectric, silicon boron nitride (SiBN), silicon carbonitride (SiCN), or combinations thereof. The gate dielectric layer 42 may include a material selected from silicon oxide, silicon nitride, silicon oxynitride, high-k dielectric, or combinations thereof. A portion of the interlayer insulating layer 25 may be disposed between adjacent gate lines.

[0021] Reference Figure 2 In an exemplary embodiment, each of the semiconductor patterns SP can be disposed (e.g., in the first direction D1) between a source line SL and a corresponding bit pad 39 in the bit pad 39. Each bit line BL can be disposed on a corresponding bit pad 39 in the bit pad 39. For example, the bit line BL can directly contact the corresponding bit pad 39. In an exemplary embodiment, the bit pad 39 can include a material selected from metals, metal nitrides, metal silicides, metal oxides, conductive carbon, polysilicon, or combinations thereof. For example, the bit pad 39 can include W, WN, Ru, Ti, TiN, Ta, TaN, Co, Pt, or combinations thereof.

[0022] like Figure 2 In the exemplary embodiments shown, each semiconductor pattern SP may include a first semiconductor pattern SP1, a second semiconductor pattern SP2, and a third semiconductor pattern SP3. In the exemplary embodiments, each semiconductor pattern SP may include at least one material selected from silicon, germanium, silicon-germanium, silicon carbide (SiC), and indium gallium zinc oxide (IGZO). In the exemplary embodiments, each semiconductor pattern SP may include a single-crystal semiconductor layer, a polycrystalline semiconductor layer, an amorphous semiconductor layer, or a combination thereof. For example, in the exemplary embodiments, each semiconductor pattern SP may include a single-crystal silicon layer, a polycrystalline silicon layer, an amorphous silicon layer, or a combination thereof.

[0023] like Figure 2In an exemplary embodiment, a first semiconductor pattern SP1 may be (e.g., in the first direction D1) positioned adjacent to a source line SL. The source line SL may be electrically connected to the first semiconductor pattern SP1 via a first barrier layer 31. The lateral edges of the first barrier layer 31 (e.g., lateral edges in the first direction D1) may directly contact the source line SL, and opposite lateral edges (e.g., opposite lateral edges in the first direction D1) may directly contact the first semiconductor pattern SP1. A second semiconductor pattern SP2 may be (e.g., in the first direction D1) positioned adjacent to a bit pad 39. A bit line BL may be electrically connected to the second semiconductor pattern SP2 via the bit pad 39 and a second barrier layer 33. The lateral edges of the second barrier layer 33 (e.g., lateral edges in the first direction D1) may directly contact the second semiconductor pattern SP2, and opposite lateral edges (e.g., opposite lateral edges in the first direction D1) may directly contact the bit pad 39. A third semiconductor pattern SP3 may be (e.g., in the first direction D1) positioned between the first semiconductor pattern SP1 and the second semiconductor pattern SP2.

[0024] like Figure 2 In an exemplary embodiment, the third semiconductor pattern SP3 may include a first region R1, a second region R2, and a third region R3 arranged in the first direction D1. For example, as shown... Figure 2 In the exemplary embodiment shown, a first region R1 may be disposed between a second region R2 and a third region R3 (e.g., in the first direction D1). The first region R1 may be continuous with the side surfaces of the second region R2 and the third region R3. For example, the lateral end of the first region R1 (e.g., the lateral end in the first direction D1) may directly contact the lateral ends of the second region R2 and the third region R3, respectively. The second region R2 may be disposed between the first region R1 and a second semiconductor pattern SP2 (e.g., in the first direction D1). The second region R2 may be continuous with the side surfaces of the first region R1 and the second semiconductor pattern SP2. For example, the lateral end of the second region R2 (e.g., the lateral end in the first direction D1) may directly contact the lateral ends of the first region R1 and the second semiconductor pattern SP2, respectively. The third region R3 may be disposed between the first region R1 and the first semiconductor pattern SP1 (e.g., in the first direction D1). The third region R3 may be continuous with the side surfaces of the first region R1 and the first semiconductor pattern SP1. For example, the lateral end of the third region R3 (e.g., the lateral end in the first direction D1) can directly contact the lateral end of the first region R1 and the lateral end of the first semiconductor pattern SP1, respectively.

[0025] In an exemplary embodiment, each of the first region R1, second region R2, and third region R3 of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 may include a material selected from silicon, germanium, silicon-germanium, silicon carbide (SiC), indium gallium zinc oxide (IGZO), or combinations thereof. In an exemplary embodiment, each of the first region R1, second region R2, and third region R3 of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 may include a single-crystal semiconductor layer, a polycrystalline semiconductor layer, an amorphous semiconductor layer, or combinations thereof. For example, each of the first region R1, second region R2, and third region R3 of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 may include a single-crystal silicon layer, a polycrystalline silicon layer, an amorphous silicon layer, or combinations thereof.

[0026] The first semiconductor pattern SP1 may include a first conductivity type impurity. The first conductivity type impurity may include an N-type impurity or a P-type impurity. In an exemplary embodiment, the first conductivity type impurity may include an N-type impurity. The first semiconductor pattern SP1 may include a silicon layer containing an N-type impurity. In an exemplary embodiment, the N-type impurity may include a material selected from P, As, or combinations thereof. The P-type impurity may include a material selected from B, BF, or combinations thereof.

[0027] The second semiconductor pattern SP2 may include a second conductivity type impurity, different from the first conductivity type impurity. For example, the second conductivity type impurity may include an N-type impurity or a P-type impurity. For example, the first conductivity type impurity may include an N-type impurity, while the second conductivity type impurity may include a P-type impurity. In another exemplary embodiment, the first conductivity type impurity may include a P-type impurity, while the second conductivity type impurity may include an N-type impurity. In an exemplary embodiment, the second conductivity type impurity may include a P-type impurity. The second semiconductor pattern SP2 may include a silicon layer containing a P-type impurity.

[0028] At least one of the first region R1 and the second region R2 of the third semiconductor pattern SP3 may include an intrinsic semiconductor layer. For example, at least one of the first region R1 and the second region R2 may include an intrinsic silicon layer. However, exemplary embodiments of the present invention are not limited thereto. For example, in an exemplary embodiment, each of the first region R1, the second region R2, and the third region R3 of the third semiconductor pattern SP3 may include an intrinsic semiconductor layer. In an exemplary embodiment, the third region R3 of the third semiconductor pattern SP3 may include a semiconductor layer containing N-type impurities. However, exemplary embodiments of the present invention are not limited thereto. For example, in an exemplary embodiment, the third region R3 of the third semiconductor pattern SP3 may be omitted. In an exemplary embodiment, each of the first region R1 and the second region R2 may include an intrinsic semiconductor layer.

[0029] In an exemplary embodiment, the first region R1 may include an intrinsic semiconductor layer, while the second region R2 may include a semiconductor layer containing impurities of a first conductivity type. In another exemplary embodiment, the first region R1 may include a semiconductor layer containing impurities of a second conductivity type, while the second region R2 may include an intrinsic semiconductor layer.

[0030] A pair of first gate lines G1 may (e.g., in the second direction D2) be respectively disposed on opposite side surfaces of the first region R1 of the third semiconductor pattern SP3, and may intersect with the first region R1. In an exemplary embodiment, the pair of first gate lines G1 may include a dual-gate structure. The pair of first gate lines G1 may be electrically equivalent. A pair of second gate lines G2 may (e.g., in the second direction D2) be respectively disposed on opposite side surfaces of the second region R2 of the third semiconductor pattern SP3, and may intersect with the second region R2. The pair of second gate lines G2 may include a dual-gate structure. The pair of second gate lines G2 may be electrically equivalent.

[0031] In an exemplary embodiment, the operating current can be applied to the pair of second gate lines G2 in a direction different from the operating current (operating current) applied to the pair of first gate lines G1. In an exemplary embodiment, a first operating current of approximately +1.5V can be applied to the pair of first gate lines G1, and simultaneously, a second operating current of approximately -1.5V can be applied to the pair of second gate lines G2. In another exemplary embodiment, a first operating current of approximately -2V can be applied to the pair of first gate lines G1, and simultaneously, a second operating current of approximately +2V can be applied to the pair of second gate lines G2.

[0032] A pair of select gate lines SG may (e.g., in the second direction D2) be disposed on opposite side surfaces of the third region R3 of the third semiconductor pattern SP3 and may intersect with the third region R3. The pair of select gate lines SG may include a dual-gate structure. The pair of select gate lines SG may be electrically equivalent. A gate dielectric layer 42 may be disposed between a pair of first gate lines G1 and the first region R1 of the third semiconductor pattern SP3 (e.g., in the second direction D2), between a pair of second gate lines G2 and the second region R2 of the third semiconductor pattern SP3 (e.g., in the second direction D2), and between a pair of select gate lines SG and the third region R3 of the third semiconductor pattern SP3 (e.g., in the second direction D2).

[0033] A first barrier layer 31 may be disposed (e.g., in the first direction D1) between the source line SL and the first semiconductor pattern SP1. The first barrier layer 31 may directly contact the source line SL and the first semiconductor pattern SP1. A second barrier layer 33 may be disposed (e.g., in the first direction D1) between the bit pad 39 and the second semiconductor pattern SP2. The second barrier layer 33 may directly contact the bit pad 39 and the second semiconductor pattern SP2. In an exemplary embodiment, each of the first barrier layer 31 and the second barrier layer 33 may include Ti, TiN, Ta, TaN, metal silicide, or combinations thereof.

[0034] Refer again Figure 1 and Figure 2 In an exemplary embodiment, a source line SL, multiple bit lines BL, multiple semiconductor patterns SP, multiple first gate lines G1, and multiple second gate lines G2 can constitute multiple thyristor DRAM cells. In a semiconductor device according to an exemplary embodiment of the present invention, the thyristor of the semiconductor device can have a high conductivity state or a low conductivity state. In the high conductivity state, a relatively large current flows through the thyristor, and in the low conductivity state, a relatively small current flows through the thyristor when the same forward bias voltage is applied to the thyristor. A semiconductor device (e.g., a thyristor DRAM cell) according to an exemplary embodiment of the present invention can use the high conductivity state and low conductivity state of the thyristor to have "1" and "0" states.

[0035] In an exemplary embodiment, each of the semiconductor devices may include a plurality of semiconductor patterns SP stacked on a substrate 21. Some of the plurality of semiconductor patterns SP may be sequentially and vertically stacked on the substrate 21 in a third direction D3. Each of the plurality of semiconductor patterns SP may extend longitudinally in a first direction D1 parallel to the upper surface of the substrate 21. Each of the plurality of semiconductor patterns SP may include a first semiconductor pattern SP1 containing impurities of a first conductivity type, a second semiconductor pattern SP2 containing impurities of a second conductivity type different from the first conductivity type impurities, and a third semiconductor pattern SP3 disposed between the first semiconductor pattern SP1 and the second semiconductor pattern SP2 (e.g., in the first direction D1). The third semiconductor pattern SP3 may include a first region R1 disposed adjacent to the first semiconductor pattern SP1 and a second region R2 disposed between the first region R1 and the second semiconductor pattern SP2. At least one of the first region R1 and the second region R2 may include an intrinsic semiconductor layer.

[0036] The semiconductor device may include source lines SL connected to a plurality of semiconductor patterns SP. The semiconductor device may also include a plurality of bit lines BL spaced apart from the source lines SL. Each of the plurality of bit lines BL may extend longitudinally in a second direction D2 parallel to the upper surface of the substrate 21 and intersecting a first direction D1. Each of the plurality of bit lines BL may be connected to a corresponding semiconductor pattern SP among the plurality of semiconductor patterns SP. The semiconductor device may include a first gate line G1, which (e.g., in the second direction D2) is configured to be adjacent to a first region R1 of a third semiconductor pattern SP3 and extend in a third direction D3 intersecting the first direction D1 and the second direction D2. The semiconductor device may include a second gate line G2, which (e.g., in the second direction D2) is configured to be adjacent to a second region R2 of the third semiconductor pattern SP3 and parallel to the first gate line G1. The first gate line G1 may intersect the first region R1. The second gate line G2 may intersect the second region R2.

[0037] The third semiconductor pattern SP3 may include a third region R3 disposed between the first region R1 and the first semiconductor pattern SP1. The semiconductor device may include a selection gate line SG, which (e.g., in the second direction D2) is configured to be adjacent to the third region R3 of the plurality of semiconductor patterns SP and parallel to the first gate line G1 and the second gate line G2. The selection gate line SG may intersect the third region R3.

[0038] Reference Figure 3 ,and Figure 2 In contrast to the exemplary embodiments, Figure 3In an exemplary embodiment, the second semiconductor pattern SP2 may be (e.g., in the first direction D1) positioned adjacent to the source line SL, and the first semiconductor pattern SP1 may be (e.g., in the first direction D1) positioned adjacent to the bit line BL. The source line SL may be electrically connected to the second semiconductor pattern SP2 via the first barrier layer 31. For example, the lateral end of the second semiconductor pattern SP2 (e.g., the lateral end in the first direction D1) may directly contact the lateral end of the third region R3 of the third semiconductor pattern SP3 and the lateral end of the first barrier layer 31, respectively. The first semiconductor pattern SP1 may be (e.g., in the first direction D1) positioned adjacent to the bit pad 39. The bit line BL may be electrically connected to the first semiconductor pattern SP1 via the bit pad 39 and the second barrier layer 33. The third semiconductor pattern SP3 may be (e.g., in the first direction D1) positioned between the first semiconductor pattern SP1 and the second semiconductor pattern SP2. Figure 3 In an exemplary embodiment, the third semiconductor pattern SP3 may include a first region R1, a second region R2, and a third region R3. The second region R2 may be disposed between the first region R1 and the first semiconductor pattern SP1 (e.g., in the first direction D1). The third region R3 may be disposed between the first region R1 and the second semiconductor pattern SP2 (e.g., in the first direction D1).

[0039] Reference Figure 4 In an exemplary embodiment, a third semiconductor pattern SP3 may be disposed (e.g., in the first direction D1) between the first semiconductor pattern SP1 and the second semiconductor pattern SP2. The third semiconductor pattern SP3 may include a first region R1, a second region R2, and a third region R3. However, compared with... Figure 2 The exemplary embodiments shown are the opposite of those shown. Figure 4In an exemplary embodiment, a first region R1 of the third semiconductor pattern SP3 may be disposed between the second region R2 and the first semiconductor pattern SP1 (e.g., in the first direction D1). The first region R1 may be continuous with the side surfaces of the second region R2 and the first semiconductor pattern SP1. For example, the lateral end of the first region R1 (e.g., the lateral end in the first direction D1) may directly contact the lateral ends of the second region R2 and the first semiconductor pattern SP1, respectively. The second region R2 may be disposed between the first region R1 and the third region R3 (e.g., in the first direction D1). The second region R2 may be continuous with the side surfaces of the first region R1 and the third region R3. For example, the lateral end of the second region R2 (e.g., the lateral end in the first direction D1) may directly contact the lateral ends of the first region R1 and the third region R3, respectively. The third region R3 may be disposed between the second region R2 and the second semiconductor pattern SP2 (e.g., in the first direction D1). The third region R3 may be continuous with the side surfaces of the second region R2 and the second semiconductor pattern SP2. For example, the lateral end of the third region R3 (e.g., the lateral end in the first direction D1) can directly contact the lateral end of the second region R2 and the lateral end of the second semiconductor pattern SP2, respectively. However, similar to Figure 2 An exemplary embodiment, in Figure 4 In an exemplary embodiment, the first gate line G1 may (e.g., in the second direction D2) be adjacent to the first region R1 of the third semiconductor pattern SP3, the second gate line G2 may (e.g., in the second direction D2) be adjacent to the second region R2 of the third semiconductor pattern SP3, and the selected gate line SG may (e.g., in the second direction D2) be adjacent to the third region R3 of the third semiconductor pattern SP3.

[0040] Figure 5 This is a perspective view of a semiconductor device according to an exemplary embodiment of the present invention. Figure 6 Is with Figure 5 A plan view of the layout of a portion of the corresponding semiconductor device.

[0041] Reference Figure 5 and Figure 6 In an exemplary embodiment, each of the plurality of first gate lines G1, the plurality of second gate lines G2, and the plurality of select gate lines SG may include a gate-all-around (GAA) structure. For example, each of the plurality of first gate lines G1 may surround the upper surface, lower surface, and side surface of a first region R1. Each of the plurality of second gate lines G2 may surround the upper surface, lower surface, and side surface of a second region R2. Each of the plurality of select gate lines SG may surround the upper surface, lower surface, and side surface of a third region R3.

[0042] Figure 7A perspective view of a semiconductor device according to an exemplary embodiment of the inventive concept. Figure 8 is associated with Figure 7 A plan view of a layout of a semiconductor device corresponding to a part of

[0043] Referring to Figure 7 and Figure 8 In an exemplary embodiment, each of the plurality of first gate lines G1 may cross only one side surface of the first region R1 in the third direction D3. Each of the plurality of second gate lines G2 may cross only one side surface of the second region R2 in the third direction D3. Each of the plurality of selection gate lines SG may cross only one side surface of the third region R3 in the third direction D3. For example, as shown in the exemplary embodiment of Figure 8 the second gate line G2 (e.g., in the second direction D2) is adjacent to only one side of the second region R2 of the third semiconductor pattern SP3, the first gate line G1 (e.g., in the second direction D2) is adjacent to only one side of the first region R of the third semiconductor pattern SP3, and the selection gate line SG (e.g., in the second direction D2) is adjacent to only one side of the third region R3 of the third semiconductor pattern SP3.

[0044] Figure 9 A perspective view of a semiconductor device according to an exemplary embodiment of the inventive concept. Figure 10 is associated with Figure 9 A plan view of a layout of a semiconductor device corresponding to a part of

[0045] Referring to Figure 9 and Figure 10 In an exemplary embodiment, each of the plurality of source lines SL may extend longitudinally from the substrate 21 in the third direction D3. The plurality of source lines SL may be arranged parallel to each other in the second direction D2 and spaced apart from each other in the second direction D2. In an exemplary embodiment, each of the plurality of source lines SL may include a line shape, a bar shape, a column shape, or a combination thereof. However, the exemplary embodiments of the inventive concept are not limited thereto. Each of the plurality of source lines SL may be referred to as a "first wire".

[0046] As Figure 10 shown in the exemplary embodiment of Figure 2 the third semiconductor pattern SP3 may include a first region R1 and a second region R2. Contrary to the exemplary embodiment of Figure 10In an exemplary embodiment, the third semiconductor pattern SP3 does not include a third region R3. A first region R1 may be (e.g., in the first direction D1) disposed between the second region R2 and the first semiconductor pattern SP1. The first region R1 may be continuous with the side surfaces of the second region R2 and the first semiconductor pattern SP1. For example, the lateral end of the first region R1 (e.g., the lateral end in the first direction D1) may directly contact the lateral ends of the second region R2 and the first semiconductor pattern SP1, respectively. The second region R2 may be (e.g., in the first direction D1) disposed between the first region R1 and the second semiconductor pattern SP2. The second region R2 may be continuous with the side surfaces of the first region R1 and the second semiconductor pattern SP2. For example, the lateral end of the second region R2 (e.g., the lateral end in the first direction D1) may directly contact the lateral ends of the first region R1 and the second semiconductor pattern SP2, respectively.

[0047] Each of the plurality of first gate lines G1 may include a pair of first gate lines G1. The pair of first gate lines G1 may be (e.g., in the second direction D2) respectively disposed on opposite side surfaces of the first region R1. Each of the plurality of second gate lines G2 may include a pair of second gate lines G2. The pair of second gate lines G2 may be (e.g., in the second direction D2) respectively disposed on opposite side surfaces of the second region R2.

[0048] Figure 11 This is a perspective view of a semiconductor device according to an exemplary embodiment of the present invention. Figure 12 Is with Figure 11 A plan view of the layout of a portion of the corresponding semiconductor device.

[0049] Reference Figure 11 and Figure 12 In an exemplary embodiment, each of the plurality of source lines SL may extend longitudinally from the substrate 21 on a third-direction D3. Each of the plurality of first gate lines G1 and the plurality of second gate lines G2 may include a gate-all-around (GAA) structure.

[0050] Figure 13 This is a perspective view of a semiconductor device according to an exemplary embodiment of the present invention. Figure 14 Is with Figure 13 A plan view of the layout of a portion of the corresponding semiconductor device.

[0051] Reference Figure 13 and Figure 14In an exemplary embodiment, each of the plurality of source lines SL may extend longitudinally from the substrate 21 in the third direction D3. Each of the plurality of first gate lines G1 may intersect only one side surface of the first region R1 in the third direction D3. Each of the plurality of second gate lines G2 may intersect only one side surface of the second region R2 in the third direction D3. For example, as... Figure 14 In the exemplary embodiment, the second gate line G2 (e.g., in the second direction D2) is adjacent to only one side of the second region R2 of the third semiconductor pattern SP3, and the first gate line G1 (e.g., in the second direction D2) is adjacent to only one side of the first region R1 of the third semiconductor pattern SP3.

[0052] Figure 15 This is a perspective view of a semiconductor device according to an exemplary embodiment of the present invention. Figure 16 Is with Figure 15 A plan view of the layout of a portion of the corresponding semiconductor device.

[0053] Reference Figure 15 and Figure 16 In an exemplary embodiment, multiple source lines SL stacked sequentially can be disposed on substrate 21. The multiple source lines SL can be stacked parallel to each other in a third direction D3 and can be spaced apart from each other in the third direction D3. The multiple source lines SL can extend longitudinally in a second direction D2. Each of the multiple bit lines BL can extend longitudinally in the third direction D3. The multiple bit lines BL can be arranged parallel to each other in the second direction D2 and can be spaced apart from each other in the second direction D2. Each of the multiple bit lines BL can directly contact the side surface of the corresponding bit pad 39.

[0054] like Figure 16 In the exemplary embodiment shown, each of the plurality of semiconductor patterns SP may include a first semiconductor pattern SP1, a second semiconductor pattern SP2, and a third semiconductor pattern SP3. The third semiconductor pattern SP3 may include a first region R1 and a second region R2. Each of the plurality of first gate lines G1 and the plurality of second gate lines G2 may extend longitudinally in a second direction D2. The plurality of first gate lines G1 may be arranged parallel to each other in a third direction D3. The plurality of second gate lines G2 may be arranged parallel to each other in a third direction D3.

[0055] Each of the plurality of first gate lines G1 and the plurality of second gate lines G2 may include a dual-gate structure. Each of the plurality of first gate lines G1 may include a pair of first gate lines G1. The pair of first gate lines G1 may intersect the upper and lower surfaces of the first region R1 respectively in the second direction D2. The pair of first gate lines G1 may be configured to be adjacent to the upper and lower surfaces of the first region R1 in the third direction D3. Each of the plurality of second gate lines G2 may include a pair of second gate lines G2. The pair of second gate lines G2 may intersect the upper and lower surfaces of the second region R2 respectively in the second direction D2. The pair of second gate lines G2 may be configured to be adjacent to the upper and lower surfaces of the second region R2 in the third direction D3.

[0056] Figure 17 This is a perspective view of a semiconductor device according to an exemplary embodiment of the present invention. Figure 18 Is with Figure 17 A plan view of the layout of a portion of the corresponding semiconductor device.

[0057] Reference Figure 17 and Figure 18 In an exemplary embodiment, multiple source lines SL may be stacked parallel to each other in a third direction D3 and may extend longitudinally in a second direction D2. Multiple bit lines BL may be arranged parallel to each other in the second direction D2 and may extend longitudinally in the third direction D3. Each of the multiple first gate lines G1 and the multiple second gate lines G2 may include a gate-all-around (GAA) structure. For example, each of the multiple first gate lines G1 may surround the upper surface, lower surface, and side surface of a first region R1. Each of the multiple second gate lines G2 may surround the upper surface, lower surface, and side surface of a second region R2.

[0058] Figure 19 This is a perspective view of a semiconductor device according to an exemplary embodiment of the present invention. Figure 20 Is with Figure 19 A plan view of the layout of a portion of the corresponding semiconductor device.

[0059] Reference Figure 19 and Figure 20 In an exemplary embodiment, multiple source lines SL can be stacked parallel to each other in the third direction D3 and can extend longitudinally in the second direction D2. Multiple bit lines BL can be arranged parallel to each other in the second direction D2 and can extend longitudinally in the third direction D3. Each of the multiple first gate lines G1 can intersect the upper surface of the first region R1 in the second direction D2. Each of the multiple second gate lines G2 can intersect the upper surface of the second region R2 in the second direction D2. Figure 20In the exemplary embodiment, each of the plurality of first gate lines G1 may (e.g., on the third-direction D3) be adjacent to only one side of the first region R1 of the third semiconductor pattern SP3. Each of the plurality of second gate lines G2 may (e.g., on the third-direction D3) be adjacent to only one side of the second region R2 of the third semiconductor pattern SP3.

[0060] Figure 21 This is a perspective view of a semiconductor device according to an exemplary embodiment of the present invention. Figure 22 Is with Figure 21 A plan view of the layout of a portion of the corresponding semiconductor device.

[0061] Reference Figure 21 and Figure 22 In an exemplary embodiment, the source line SL may extend from the substrate 21 in a second direction D2 and a third direction D3. In an exemplary embodiment, the source line SL may have the form of a wall. Multiple bit lines BL may be arranged parallel to each other in the second direction D2 and may extend longitudinally in the third direction D3.

[0062] Each of the plurality of semiconductor patterns SP may include a first semiconductor pattern SP1, a second semiconductor pattern SP2, and a third semiconductor pattern SP3. The third semiconductor pattern SP3 may include a first region R1, a second region R2, and a third region R3. Each of the plurality of first gate lines G1, the plurality of second gate lines G2, and the plurality of select gate lines SG may extend longitudinally in the second direction D2. The plurality of first gate lines G1 may be arranged in parallel in the third direction D3. The plurality of second gate lines G2 may be arranged in parallel in the third direction D3. The plurality of select gate lines SG may be arranged in parallel in the third direction D3.

[0063] Each of the plurality of first gate lines G1, the plurality of second gate lines G2, and the plurality of select gate lines SG may include a dual-gate structure. Each of the plurality of first gate lines G1 may include a pair of first gate lines G1. Each of the plurality of second gate lines G2 may include a pair of second gate lines G2. Each of the plurality of select gate lines SG may include a pair of select gate lines SG. The pair of select gate lines SG may intersect the upper and lower surfaces of the third region R3 in the second direction D2, respectively. For example, the plurality of first gate lines G1 may (e.g., in the third direction D3) be adjacent to the first region R1 of the third semiconductor pattern SP3. The plurality of second gate lines G2 may (e.g., in the third direction D3) be adjacent to the second region R2 of the third semiconductor pattern SP3. The plurality of select gate lines SG may (e.g., in the third direction D3) be adjacent to the third region R3 of the third semiconductor pattern SP3.

[0064] A semiconductor device according to each exemplary embodiment of the present invention may include a plurality of semiconductor patterns SP located on a substrate 21. Each of the plurality of semiconductor patterns SP may extend longitudinally in a first direction D1 parallel to the upper surface of the substrate 21. Some of the plurality of semiconductor patterns SP may be disposed parallel to the upper surface of the substrate 21, while being arranged parallel to other semiconductor patterns SP in a second direction D2 intersecting the first direction D1. Each of the plurality of semiconductor patterns SP may include a first semiconductor pattern SP1 containing impurities of a first conductivity type, a second semiconductor pattern SP2 containing impurities of a second conductivity type different from the first conductivity type impurities, and a third semiconductor pattern SP3 disposed between the first semiconductor pattern SP1 and the second semiconductor pattern SP2 (e.g., in the first direction D1). Figure 22 In an exemplary embodiment, the third semiconductor pattern SP3 may include a first region R1 and a second region R2, wherein the first region R1 is disposed closer to the first semiconductor pattern SP1 than the second region R2, and the second region R2 is disposed between the first region R1 and the second semiconductor pattern SP2. At least one of the first region R1 and the second region R2 may include an intrinsic semiconductor layer.

[0065] A semiconductor device may include source lines SL connected to a plurality of semiconductor patterns SP. The semiconductor device may include a plurality of bit lines BL spaced apart from the source lines SL. Each of the plurality of bit lines BL may extend longitudinally in a third direction D3 intersecting a first direction D1 and a second direction D2. Each of the plurality of bit lines BL may be connected to a corresponding semiconductor pattern SP among the plurality of semiconductor patterns SP. The semiconductor device may include a first gate line G1, which (e.g., in the third direction D3) is configured to be adjacent to a first region R1 of a third semiconductor pattern SP3 and extend in the second direction D2. The semiconductor device may include a second gate line G2, which (e.g., in the third direction D3) is configured to be adjacent to a second region R2 of the third semiconductor pattern SP3 and parallel to the first gate line G1. The first gate line G1 may intersect the first region R1. The second gate line G2 may intersect the second region R2.

[0066] The third semiconductor pattern SP3 may include (e.g., in the first direction D1) a third region R3 disposed between the first region R1 and the first semiconductor pattern SP1. The semiconductor device may include a selection gate line SG, which (e.g., in the third direction D3) is configured to be adjacent to the third region R3 of the third semiconductor pattern SP3 and parallel to the first gate line G1 and the second gate line G2. The selection gate line SG may intersect the third region R3.

[0067] Figure 23This is a perspective view of a semiconductor device according to an exemplary embodiment of the present invention. Figure 24 Is with Figure 23 A plan view of the layout of a portion of the corresponding semiconductor device.

[0068] Reference Figure 23 and Figure 24 In an exemplary embodiment, the source line SL may extend from the substrate 21 in the second direction D2 and the third direction D3. Multiple bit lines BL may be arranged parallel to each other in the second direction D2 and may be spaced apart from each other in the second direction D2. Each of the multiple first gate lines G1, multiple second gate lines G2, and multiple select gate lines SG may include a gate-all-around (GAA) structure. Each of the multiple select gate lines SG may surround the upper surface, lower surface, and side surface of the third region R3.

[0069] Figure 25 This is a perspective view of a semiconductor device according to an exemplary embodiment of the present invention. Figure 26 Is with Figure 25 A plan view of the layout of a portion of the corresponding semiconductor device.

[0070] Reference Figure 25 and Figure 26 In an exemplary embodiment, the source line SL may extend from the substrate 21 in the second direction D2 and the third direction D3. Multiple bit lines BL may be arranged parallel to each other in the second direction D2 and may be spaced apart in the second direction D2. Each of the multiple first gate lines G1 may intersect the upper surface of the first region R1 in the second direction D2. Each of the multiple second gate lines G2 may intersect the upper surface of the second region R2 in the second direction D2. Each of the multiple select gate lines SG may intersect the upper surface of the third region R3 in the second direction D2. For example, as... Figure 26 In the exemplary embodiment, each of the plurality of first gate lines G1 may (e.g., on the third-direction D3) be adjacent to only one side of the first region R1 of the third semiconductor pattern SP3. Each of the plurality of second gate lines G2 may (e.g., on the third-direction D3) be adjacent to only one side of the second region R2 of the third semiconductor pattern SP3. Each of the plurality of select gate lines SG may (e.g., on the third-direction D3) be adjacent to only one side of the third region R3 of the third semiconductor pattern SP3.

[0071] According to an exemplary embodiment of the present invention, a third semiconductor pattern including at least one intrinsic semiconductor layer is provided between a first semiconductor pattern and a second semiconductor pattern. A first gate line and a second gate line are configured to cross the third semiconductor pattern. The third semiconductor pattern including at least one intrinsic semiconductor layer can have a structure that provides high integration while maintaining excellent electrical characteristics. Therefore, a semiconductor device with excellent electrical characteristics while having high integration can be realized.

[0072] Although exemplary embodiments of the inventive concept have been described with reference to the accompanying drawings, those skilled in the art should understand that various modifications can be made without departing from the scope of the inventive concept and without changing its essential characteristics. Therefore, the above exemplary embodiments should be considered in a descriptive sense only and not for limiting purposes.

Claims

1. A semiconductor device comprising: a first wire; a second wire spaced apart from the first wire and extending in a first direction, wherein the first direction is parallel to an upper surface of a substrate; a semiconductor pattern provided between the first wire and the second wire and extending in a second direction, wherein the second direction is parallel to the upper surface of the substrate and intersects the first direction, the semiconductor pattern including: a first semiconductor pattern provided adjacent to the first wire, the first semiconductor pattern having a first conductivity type impurity; a second semiconductor pattern provided adjacent to the second wire, the second semiconductor pattern having a second conductivity type impurity different from the first conductivity type impurity; and a third semiconductor pattern provided between the first semiconductor pattern and the second semiconductor pattern, the third semiconductor pattern including a first region provided adjacent to the first semiconductor pattern and a second region provided between the first region and the second semiconductor pattern, wherein at least one of the first region and the second region includes an intrinsic semiconductor layer; a first gate line intersecting the first region and extending in a third direction, wherein the third direction intersects the first direction and the second direction; and a second gate line intersecting the second region and extending in the third direction, and wherein the second gate line is adjacent to the first gate line in the second direction.

2. The semiconductor device according to claim 1, wherein Each of the first region and the second region includes the intrinsic semiconductor layer.

3. The semiconductor device according to claim 1, wherein the first region includes the intrinsic semiconductor layer; and the second region includes a semiconductor layer having the first conductivity type impurity.

4. The semiconductor device according to claim 1, wherein the first region includes a semiconductor layer having the second conductivity type impurity; and the second region includes the intrinsic semiconductor layer.

5. The semiconductor device according to claim 1, wherein The second region is continuous with the first region.

6. The semiconductor device according to claim 1, wherein Each of the first semiconductor pattern, the second semiconductor pattern, and the third semiconductor pattern includes at least one material selected from silicon, germanium, silicon-germanium, and indium gallium zinc oxide.

7. The semiconductor device according to any one of Claims 1-6, wherein The third semiconductor pattern further includes a third region provided between the first region and the first semiconductor pattern or provided between the second region and the second semiconductor pattern.

8. The semiconductor device according to claim 7, further comprising: a select gate line intersecting the third region.

9. The semiconductor device according to claim 7, wherein The third region includes the intrinsic semiconductor layer.

10. The semiconductor device according to claim 7, wherein The third region includes a semiconductor layer having the first conductivity type impurity.

11. A semiconductor device comprising: a plurality of semiconductor patterns disposed on a substrate, each of the plurality of semiconductor patterns extending in a first direction, wherein the first direction is parallel to an upper surface of the substrate, each of the plurality of semiconductor patterns including: a first semiconductor pattern having a first conductivity type impurity; a second semiconductor pattern having a second conductivity type impurity different from the first conductivity type impurity; and a third semiconductor pattern disposed between the first semiconductor pattern and the second semiconductor pattern, wherein the third semiconductor pattern includes a first region disposed adjacent to the first semiconductor pattern and a second region disposed between the first region and the second semiconductor pattern, wherein at least one of the first region and the second region includes an intrinsic semiconductor layer; a first wire connected to the plurality of semiconductor patterns; a plurality of second wires spaced apart from the first wire, each of the plurality of second wires extending in a second direction, each of the second wires connected to a corresponding semiconductor pattern of the plurality of semiconductor patterns, wherein the second direction is parallel to the upper surface of the substrate and intersects the first direction; a first gate line disposed adjacent to the plurality of semiconductor patterns and extending in a third direction, wherein the third direction intersects the first direction and the second direction; and a second gate line disposed adjacent to the plurality of semiconductor patterns, the second gate line extending in the third direction and parallel to the first gate line, wherein the first gate line intersects the first region and the second gate line intersects the second region, and wherein the second gate line is adjacent to the first gate line in the first direction.

12. The semiconductor device according to claim 11, wherein Each of the first region and the second region includes the intrinsic semiconductor layer.

13. The semiconductor device according to claim 11 or 12, wherein The third semiconductor pattern further includes a third region disposed between the first region and the first semiconductor pattern or disposed between the second region and the second semiconductor pattern.

14. The semiconductor device of claim 13, further comprising: a select gate line disposed adjacent to the plurality of semiconductor patterns, the select gate line extending in the third direction and parallel to the first gate line and the second gate line, wherein the select gate line intersects the third region.

15. The semiconductor device according to claim 13, wherein The third region includes the intrinsic semiconductor layer.

16. A semiconductor device, comprising: a plurality of semiconductor patterns disposed on a substrate, each of the plurality of semiconductor patterns extending in a first direction parallel to an upper surface of the substrate, wherein the plurality of semiconductor patterns are arranged in a second direction intersecting the first direction, each of the plurality of semiconductor patterns including: a first semiconductor pattern having a first conductivity type impurity; a second semiconductor pattern having a second conductivity type impurity different from the first conductivity type impurity; and a third semiconductor pattern disposed between the first semiconductor pattern and the second semiconductor pattern, wherein the third semiconductor pattern includes a first region disposed adjacent to the first semiconductor pattern and a second region disposed between the first region and the second semiconductor pattern, wherein at least one of the first region and the second region includes an intrinsic semiconductor layer; a first wire connected to the plurality of semiconductor patterns; a plurality of second conductive lines spaced apart from the first conductive lines, each of the plurality of second conductive lines extending in a third direction crossing the first direction and the second direction, wherein each of the second conductive lines is connected to a corresponding one of the plurality of semiconductor patterns; a first gate line disposed adjacent to the plurality of semiconductor patterns and extending in the second direction; and a second gate line disposed adjacent to the plurality of semiconductor patterns, the second gate line extending in the second direction and parallel to the first gate line, wherein the first gate line crosses the first region and the second gate line crosses the second region.

17. The semiconductor device according to claim 16, wherein Each of the first region and the second region includes an intrinsic semiconductor layer.

18. The semiconductor device according to claim 16 or 17, wherein The third semiconductor pattern further includes a third region disposed between the first region and the first semiconductor pattern or between the second region and the second semiconductor pattern.

19. The semiconductor device of claim 18, further comprising: a select gate line disposed adjacent to the plurality of semiconductor patterns, the select gate line extending in the second direction and parallel to the first gate line and the second gate line, wherein the select gate line crosses the third region.

20. The semiconductor device of Claim 18, wherein, The third region includes an intrinsic semiconductor layer.

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