Energy storage capacitor and method for preparing the same

Abstract

The present invention provides an energy storage capacitor, comprising a substrate, an insulating layer, a bottom electrode, a ferroelectric film, an antiferroelectric film and a top electrode. The substrate is provided with a first groove structure, and the insulating layer covers the inner wall and the top surface of the first groove structure to form a second groove structure; the bottom electrode, the ferroelectric film, the antiferroelectric film and the top electrode are sequentially stacked and arranged in the second groove structure to form different groove structures, and one groove structure of two adjacent groove structures covers the inner wall and the top surface of the other groove structure, thereby improving the maximum polarization strength and the breakdown electric field strength, thereby improving the energy storage density of the dielectric capacitor. The present invention also provides a preparation method of the energy storage capacitor.

Description

Technical Field

[0001] The present invention relates to the field of micro-nano electronic materials and functional devices, and in particular to an energy storage capacitor and a preparation method thereof. Background Art

[0002] Dielectric capacitors generally use the polarization of dipoles in the dielectric to store electrical energy. They have extremely high power density, that is, ultra-fast charge and discharge rates, which are inherent advantages that other types of energy storage systems such as batteries or electrochemical capacitors do not have. And as a pure solid-state material, dielectric capacitors also have great advantages over batteries and electrochemical capacitors in terms of maximum operating voltage, charge and discharge rate, output power, cycle life, leakage current and ease of manufacturing. However, due to its relatively low energy storage density, its application range is limited in scenarios that require high energy density. Therefore, if the energy storage density of dielectric capacitors can be increased to a higher level, its application prospects will be broader.

[0003] From the perspective of the properties of dielectric capacitors, their energy storage density is mainly controlled by the selection of dielectric materials, and dielectric materials with high energy storage performance need to have high maximum polarization intensity, low residual polarization intensity, high breakdown electric field intensity and good dielectric properties. Compared with several typical dielectric materials currently available, antiferroelectric materials have the greatest advantage. In general, antiferroelectrics show no residual polarization intensity on a macro scale, but under the action of a very strong external electric field, their crystal structure can be transformed into a ferroelectric phase, and their PE characteristic curve shows a double hysteresis loop characteristic. When the electric field intensity is small, the hysteresis loop disappears, so antiferroelectric materials show unique characteristics in energy storage.

[0004] Traditional antiferroelectric materials, such as PbZrO3-based antiferroelectric ceramics, AgNbO3-based antiferroelectric ceramics, and BaTiO3-based antiferroelectric ceramics, show extremely high energy storage density and energy storage efficiency, and are potential candidate materials for high-performance energy storage capacitors. However, their complex preparation process, high crystallization temperature, and low breakdown electric field strength also limit their application scope. In addition, these films require a large deposition thickness, which is not conducive to the preparation of nano energy storage capacitors and three-dimensional integration. In comparison, ZrO2 and HfO2 materials have the advantages of very thin deposition thickness, simple composition, mature ALD preparation process, compatibility with CMOS process, and good dielectric properties, and are more suitable for the development of nano energy storage capacitors and three-dimensional integration. However, energy storage capacitors prepared from a single HZO antiferroelectric film have disadvantages such as low maximum polarization strength and low breakdown electric field strength, so it is difficult to further improve their energy storage density.

[0005] The Chinese patent application with publication number CN111769122 A discloses an antiferroelectric memory, including a substrate; a source electrode and a drain electrode, which are arranged at both ends of the substrate; an antiferroelectric thin film structure layer, which is arranged on the substrate, and the antiferroelectric thin film structure layer includes a first antiferroelectric layer, an intermediate electrode, a second antiferroelectric layer and a top electrode in order from the substrate upward; wherein there is a work function difference between the top electrode, the intermediate electrode and the substrate. The patent application sets up a double antiferroelectric sandwich structure, and it can be seen that during the charging and discharging process of the antiferroelectric memory in the patent application, the antiferroelectric layer will produce huge strain and cracks, which makes the breakdown of the antiferroelectric layer smaller and the actual life shorter, making it difficult to further improve the energy storage efficiency of the capacitor.

[0006] Therefore, it is necessary to develop a new type of energy storage capacitor and a preparation method thereof to solve the above problems existing in the prior art. Summary of the invention

[0007] The object of the present invention is to provide an energy storage capacitor and a preparation method thereof, so as to improve the maximum polarization strength and breakdown electric field strength of the energy storage capacitor.

[0008] To achieve the above-mentioned purpose, the present invention provides an energy storage capacitor, comprising a substrate, an insulating layer, a bottom electrode, a ferroelectric film, an antiferroelectric film and a top electrode stacked in sequence, wherein the substrate is provided with a first groove structure, and the insulating layer covers the inner wall and the top surface of the first groove structure to form a second groove structure; the bottom electrode, the ferroelectric film, the antiferroelectric film and the top electrode are stacked in sequence in the second groove structure to form different groove structures, and one groove structure of two adjacent groove structures covers the inner wall and the top surface of the other groove structure.

[0009] The beneficial effects of the energy storage capacitor described in the present invention are: the substrate is provided with a first groove structure, the insulating layer covers the inner wall and the top surface of the first groove structure to form a second groove structure; the bottom electrode, the ferroelectric film, the antiferroelectric film and the top electrode are stacked in sequence on the second groove structure to form different groove structures, and one groove structure of two adjacent groove structures covers the inner wall and the top surface of the other groove structure, thereby improving the maximum polarization strength and the breakdown electric field strength, thereby improving the energy storage density of the dielectric capacitor.

[0010] Preferably, the aspect ratio of the first groove structure is 1:1-100:1. The beneficial effect thereof is: improving energy density.

[0011] Preferably, the thickness of the insulating layer is in the range of 50-300 nm, and the thickness of the bottom electrode and the top electrode are both in the range of 10-200 nm. The beneficial effect is that the insulating layer, the bottom electrode and the top electrode have a certain thickness, which can effectively prevent the ferroelectric film from diffusing toward the substrate, and can effectively prevent short circuit and reduce leakage current.

[0012] Preferably, the insulating layer is made of silicon dioxide, and the bottom electrode and the top electrode are made of any one or two of TiN, TaN and Ru. The beneficial effects are: silicon dioxide has stable chemical properties and can effectively prevent electrical contact between the substrate and the bottom electrode, and the bottom electrode and the top electrode made of any one or two of TiN, TaN and Ru have good conformal deposition characteristics.

[0013] Preferably, the thickness of the ferroelectric film is in the range of 1-25 nm. The beneficial effects are: prolonging the actual service life of the ferroelectric film during repeated charge and discharge of the capacitor, and effectively improving the energy storage density of the ferroelectric film.

[0014] Preferably, the ferroelectric film is a hafnium oxide film doped with at least one of Si, Al and Y. Its beneficial effects are: doping the hafnium oxide film with Si and Al elements whose atomic radius is smaller than Hf is conducive to the stability of the tetragonal phase of hafnium oxide, thereby improving the energy storage density and energy storage efficiency of the capacitor; doping the hafnium oxide film with an appropriate amount of Y element whose atomic radius is larger than Hf is conducive to the stability of the cubic phase of hafnium oxide, thereby improving the energy storage density of the capacitor.

[0015] Preferably, the ferroelectric thin film has a general structural formula of Hf x Zr 1-x O2, where 0.5≤x≤0.9. Its beneficial effect is: Hf x Zr 1-x O2 thin film can affect the ferroelectricity of the capacitor by changing the Zr content and further optimize the capacitor.

[0016] Preferably, the thickness of the antiferroelectric film is in the range of 1-25 nm. The beneficial effects are: prolonging the actual service life of the antiferroelectric film during repeated charge and discharge of the capacitor, and effectively improving the energy storage density of the antiferroelectric film.

[0017] Preferably, the antiferroelectric film is a hafnium oxide film doped with at least one of Si, Al and La. Its beneficial effects are: doping the hafnium oxide film with Si and Al elements whose atomic radius is smaller than Hf can induce the hafnium oxide film to have antiferroelectric properties, thereby improving the energy storage density and energy storage efficiency of the capacitor; doping the hafnium oxide film with an appropriate amount of La elements whose atomic radius is larger than Hf can stabilize the antiferroelectric phase region, increase the ferroelectric-antiferroelectric phase transition electric field, and thus improve the energy storage density of the capacitor.

[0018] Preferably, the antiferroelectric film has a general structural formula of Hf x Zr 1-x O2, where 0.1≤x≤0.4. Its beneficial effect is: Hf x Zr 1-x O2 thin film can affect the antiferroelectricity of the capacitor by changing the Zr content and further optimize the capacitor.

[0019] In a second aspect, the present invention further provides a method for preparing the energy storage capacitor, comprising the following steps:

[0020] S1: after the first trench structure is formed in the substrate, an insulating layer covering the inner wall and top surface of the first trench structure is formed by a thermal oxidation method;

[0021] S2: using an atomic layer deposition method to form the bottom electrode, the ferroelectric film, the antiferroelectric film and the top electrode which are sequentially stacked and arranged on the second groove structure.

[0022] The beneficial effect of the preparation method of the energy storage capacitor described in the present invention is that after forming an insulating layer covering the inner wall and top surface of the first groove structure, an atomic layer deposition method is used to form the bottom electrode, the ferroelectric film, the antiferroelectric film and the top electrode stacked in sequence on the second groove structure. It can be prepared in a three-dimensional groove structure and has the advantages of good conformality, good consistency and high density. Compared with traditional perovskite antiferroelectric material energy storage capacitors, it has the advantage of being compatible with CMOS back-end processes, and the size and density of the substrate grooves have low restrictions on the ALD method, so that the energy density of the capacitor can be further improved by optimizing the size and density of the substrate grooves.

[0023] Preferably, in the step S1, the step of opening the first trench structure on the substrate includes: controlling the depth-to-width ratio of the first trench structure opened on the substrate to be 1:1-100:1.

[0024] Further preferably, in step S2, the step of using an atomic layer deposition method to form the bottom electrode, the ferroelectric film, the antiferroelectric film and the top electrode stacked sequentially in the second groove structure comprises:

[0025] A third groove structure is obtained by forming the bottom electrode covering the inner wall and the top surface of the second groove structure by a first atomic layer deposition method;

[0026] A fourth trench structure is obtained by forming the ferroelectric thin film covering the inner wall and the top surface of the third trench structure using a second atomic layer deposition method;

[0027] A fifth groove structure is obtained by forming the antiferroelectric thin film covering the inner wall and the top surface of the fourth groove structure by a third atomic layer deposition method;

[0028] The sixth trench structure is obtained by forming the top electrode covering the inner wall and the top surface of the fifth trench structure using the fourth atomic layer deposition method.

[0029] Further preferably, step S3 is also included: after forming an electrode pattern on the surface of the top electrode, etching is performed according to the electrode pattern to form a plurality of independent top electrode units; and the ferroelectric film and the antiferroelectric film are etched using the plurality of top electrode units as templates until the bottom electrode is exposed.

[0030] Further preferably, the method further comprises step S4: annealing the device obtained in step S3 for 30 seconds to 60 minutes at a temperature of 350-450 degrees Celsius and in an atmosphere of nitrogen or a mixture of nitrogen and hydrogen. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 A schematic diagram of the structure of an energy storage capacitor according to an embodiment of the present invention;

[0032] Figure 2 It is a schematic diagram of a structure obtained after a first trench structure is opened on a substrate according to an embodiment of the present invention;

[0033] Figure 3 For Figure 2 A schematic diagram of a structure formed after an insulating layer is deposited on the structure shown;

[0034] Figure 4 For Figure 3 Schematic diagram of the structure obtained after depositing the bottom electrode on the structure shown;

[0035] Figure 5 For Figure 4 Schematic diagram of the structure obtained after depositing a ferroelectric thin film on the structure shown;

[0036] Figure 6 For Figure 5 Schematic diagram of the structure obtained after depositing an antiferroelectric thin film on the structure shown;

[0037] Figure 7 A schematic diagram of a process for preparing an energy storage capacitor according to an embodiment of the present invention;

[0038] Figure 8 is a schematic flow chart of step S2;

[0039] Fig. 9 It is a schematic diagram of the structure obtained after executing step S3 after step S24 is completed;

[0040] Fig.10 for Fig. 9 a top view of the structure shown;

[0041] Fig.11 It is a schematic diagram of the process of step S3. DETAILED DESCRIPTION

[0042] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein should be understood by people with general skills in the field to which the present invention belongs. "Including" and similar words used in this article mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0043] In order to solve the problems existing in the prior art, an embodiment of the present invention provides an energy storage capacitor including a substrate, an insulating layer, a bottom electrode, a ferroelectric film, an antiferroelectric film and a top electrode, and a preparation method of the energy storage capacitor, so as to improve the storage energy density and power density of the energy storage capacitor, have strong stability, and be compatible with CMOS back-end processes.

[0044] Figure 1 Schematic diagram of the structure of an energy storage capacitor according to an embodiment of the present invention.

[0045] In the embodiment of the present invention, refer to Figure 1The energy storage capacitor includes a substrate 11, an insulating layer 31, a bottom electrode 41, a ferroelectric film 51, an antiferroelectric film 61 and a top electrode 71, wherein the insulating layer 31 covers the top surface of the substrate 11; the bottom electrode 41 covers the top surface of the insulating layer 31; the ferroelectric film 51 covers the top surface of the bottom electrode 41; the antiferroelectric film 61 covers the top surface of the ferroelectric film 51; and the top electrode 71 covers the top surface of the antiferroelectric film 61.

[0046] In some specific embodiments, the substrate 11 is made of any one of silicon, germanium and gallium arsenide.

[0047] In some specific embodiments, the insulating layer 31 is made of SiO 2 .

[0048] In some specific embodiments, the bottom electrode 41 and the top electrode 71 are both metal films, and the constituent material of the metal films is any one of TiN, TaN and Ru or any combination of any two of them.

[0049] Figure 2 It is a schematic diagram of a structure obtained after a first trench structure is opened on a substrate according to an embodiment of the present invention.

[0050] Figure 3 For Figure 2 Schematic diagram of the structure formed after depositing an insulating layer on the basis of the structure shown.

[0051] In some embodiments, reference Figure 2 and Figure 3 The substrate 11 is provided with a first trench structure 21 , and the insulating layer 31 covers the inner wall and the top surface of the first trench structure 21 to form a second trench structure 32 .

[0052] In some embodiments, the insulating layer 31 is made of SiO 2 .

[0053] In some embodiments, the thickness of the insulating layer 31 is in the range of 50-300 nm.

[0054] In some embodiments, the aspect ratio of the first trench structure 21 is 1:1-100:1.

[0055] In some embodiments, the bottom electrode 41 , the ferroelectric film 51 , the antiferroelectric film 61 and the top electrode 71 are sequentially stacked and disposed in the second trench structure 32 to form different trench structures.

[0056] In some embodiments, one groove structure of two adjacent groove structures covers the inner wall and the top surface of the other groove structure.

[0057] Figure 4For Figure 3 Schematic diagram of the structure obtained after depositing the bottom electrode on the structure shown. Figure 3 and Figure 4 The bottom electrode 41 covers the inner wall and top surface of the second groove structure 32 to form a third groove structure 42 .

[0058] In some embodiments, the thickness of the bottom electrode 41 is in the range of 10-200 nm.

[0059] Figure 5 For Figure 4 Schematic diagram of the structure obtained after depositing a ferroelectric thin film on the structure shown. Figure 4 and Figure 5 The ferroelectric film 51 covers the interior and top surface of the third trench structure 42 to form a fourth trench structure 52 .

[0060] In some embodiments, the thickness of the ferroelectric film 51 is in the range of 1-25 nm.

[0061] In some embodiments, the ferroelectric film 51 is a hafnium oxide film doped with at least one of Si, Al and Y elements.

[0062] In some embodiments, the ferroelectric film 51 has a general structural formula of Hf x Zr 1-x O2, where 0.5≤x≤0.9.

[0063] Figure 6 For Figure 5 Schematic diagram of the structure obtained after depositing an antiferroelectric thin film on the structure shown. Figure 5 and Figure 6 The antiferroelectric film 61 covers the interior and top surface of the fourth trench structure 52 to form a fifth trench structure 62 .

[0064] In some embodiments, the thickness of the antiferroelectric film 61 is in the range of 1-25 nm.

[0065] In some embodiments, the antiferroelectric film 61 is a hafnium oxide film doped with at least one of Si, Al and La.

[0066] In some embodiments, the antiferroelectric film 61 has a general structural formula of Hf x Zr 1-x O2, where 0.1≤x≤0.4.

[0067] Reference Figure 1 and Figure 6 The top electrode 71 covers the sidewalls and top surface of the fifth trench structure 62 to form a sixth trench structure 72 .

[0068] In some embodiments, the thickness of the top electrode 71 is in the range of 10-200 nm.

[0069] The present invention also provides a method for preparing the energy storage capacitor, referring to Figure 7 , including the following steps:

[0070] S1: after the first trench structure is formed in the substrate, an insulating layer covering the inner wall and top surface of the first trench structure is formed by a thermal oxidation method;

[0071] S2: using an atomic layer deposition method to form the bottom electrode, the ferroelectric film, the antiferroelectric film and the top electrode which are sequentially stacked and arranged on the second groove structure.

[0072] In the step S1 of some embodiments, the step of opening the first trench structure on the substrate includes: controlling the depth-to-width ratio of the first trench structure opened on the substrate to be 1:1-100:1.

[0073] In step S2 of some embodiments, referring to Figure 8 The steps of using an atomic layer deposition method to form the bottom electrode, the ferroelectric film, the antiferroelectric film and the top electrode stacked sequentially on the second groove structure include:

[0074] S21: forming the bottom electrode covering the inner wall and top surface of the second groove structure by a first atomic layer deposition method to obtain a third groove structure;

[0075] S22: forming the ferroelectric thin film covering the inner wall and the top surface of the third trench structure by a second atomic layer deposition method to obtain a fourth trench structure;

[0076] S23: forming the antiferroelectric thin film covering the inner wall and top surface of the fourth trench structure by a third atomic layer deposition method to obtain a fifth trench structure;

[0077] S24: A sixth trench structure is obtained by forming the top electrode covering the inner wall and top surface of the fifth trench structure using a fourth atomic layer deposition method.

[0078] In some embodiments, after step S24 is completed, step S3 is executed.

[0079] Fig. 9 It is a schematic diagram of the structure obtained after executing step S3 after step S24 is completed. Fig.10 for Fig. 9 Top view of the structure shown. Fig.11 It is a schematic diagram of the process of step S3.

[0080] Reference Figures 9 to 11 , the step S3 comprises:

[0081] S31: after forming an electrode pattern on the surface of the top electrode, etching is performed according to the electrode pattern to form a plurality of top electrode units independent of each other;

[0082] S32: using the plurality of top electrode units as templates, etching the ferroelectric film and the antiferroelectric film until the bottom electrode is exposed.

[0083] In some embodiments, after step S32 is completed, step S4 is performed, which includes: annealing the device obtained in step S3 for 30 seconds to 60 minutes at a temperature of 350-450 degrees Celsius and in an atmosphere of nitrogen or a mixture of nitrogen and hydrogen.

[0084] The technical solution of the present invention is described in detail below through specific embodiments.

[0085] Example 1

[0086] Embodiment 1 provides an energy storage capacitor, which is a three-dimensional energy storage capacitor based on ferroelectric-antiferroelectric coupling.

[0087] In the energy storage capacitor of Example 1, the constituent material of the substrate is Si, the constituent material of the insulating layer is SiO2, and it also includes a bottom electrode arranged on the SiO2 insulating layer; a ferroelectric film arranged on the bottom electrode; an antiferroelectric film arranged on the ferroelectric film; and a top electrode arranged on the antiferroelectric film.

[0088] In step S1 of embodiment 1, the first groove structure of the substrate has a depth-to-width ratio of 20:1, and the inner wall is smooth.

[0089] In the step S1, a layer of SiO2 is oxidized on the surface of the substrate as an insulating layer by thermal oxidation method, the thermal oxidation temperature is controlled to be 950°C, the oxidants are H2O and O2, the O2 flow rate is 50L / min, the H2O is sufficient, and the thermal oxidation is performed for 2h to obtain an insulating layer of SiO2 with a thickness of 300nm.

[0090] In the step S21, a TiN bottom electrode is deposited on the insulating layer using a first atomic layer deposition method. In the first atomic layer deposition method: the Ti source is 50 sccm TDMAT, wherein the carrier gas is N2, the pulse time is controlled to be 2s, and the purge time is 10s. The N source is 50 sccm NH3 plasma, wherein the carrier gas is Ar gas, the flow rate of NH3 is 100 sccm, the RF power is 2500W, the pulse time is 17s, and the purge time is 10s; the deposition temperature is controlled to be 200°C, and after 200 ALD cycles, the thickness of the TiN bottom electrode is 20nm.

[0091] In step S22, a second atomic layer deposition method is used to prepare a substrate having a general structure of Hf 0.5 Zr 0.5 O2 ferroelectric film. In the second atomic layer deposition method, the Hf source is 80sccm TDMAH, wherein the carrier gas is N2, the pulse time is 0.3s, and the purge time is 10s; the Zr source is 80sccm TDMAZ, wherein the carrier gas is N2, the pulse time is 0.3s, and the purge time is 10s; the O source is 150sccm O2 plasma, wherein the carrier gas is Ar gas, the flow rate of O2 is 130sccm, the RF power is 2500W, the pulse time is 8s, and the purge time is 10s; the ratio of HfO2 to ZrO2 is controlled to be 1:1, the deposition temperature is 280℃, and HfO2 is obtained after 13 ALD cycles. 0.5 Zr 0.5 The thickness of the O2 ferroelectric film is 1 nm.

[0092] In the step S23, a third atomic deposition method is used to prepare a ferroelectric film having a general structure of Hf 0.25 Zr 0.75 In the third atomic deposition method, the Hf source is 80sccm TDMAH, wherein the carrier gas is N2, the pulse time is 0.3s, and the purge time is 10s; the Zr source is 80sccm TDMAZ, wherein the carrier gas is N2, the pulse time is 0.3s, and the purge time is 10s; the O source is 150sccm O2 plasma, wherein the carrier gas is Ar gas, the flow rate of O2 is 130sccm, the RF power is 2500W, the pulse time is 8s, and the purge time is 10s; the ratio of HfO2 to ZrO2 is controlled to be 1:3, the deposition temperature is 280°C, and HfO2 is obtained after 113 ALD cycles. 0.25 Zr 0.75 The thickness of the O2 antiferroelectric film is 9 nm.

[0093] In the step S24, a TiN bottom electrode is prepared on the antiferroelectric film by using the fourth atomic layer deposition method. In the fourth atomic layer deposition method, the Ti source is 50 sccm TDMAT, wherein the carrier gas is N2, the pulse time is 2s, and the purge time is 10s; the N source is 50 sccm NH3 plasma, wherein the carrier gas is Ar gas, the flow rate of NH3 is 100 sccm, the RF power is 2500W, the pulse time is 17s, and the purge time is 10s; the deposition temperature is controlled to be 200°C, and after 500 ALD cycles, the thickness of the TiN bottom electrode is 50nm.

[0094] In step S31, an electrode pattern is formed on the top electrode by photolithography, and the electrode area is 50×50 μm 2 ; Then SF6 plasma is used to etch away the TiN outside the pattern to separate the top electrode units.

[0095] In step S32, the top electrode unit is used as a template, and BCl3 gas is used to convert Hf 0.5 Zr 0.5 O2 and Hf 0.25 Zr 0.75 O2 is etched away until the bottom electrode is exposed.

[0096] In the step S4, the device obtained after the step S32 is annealed in a mixed atmosphere of N2 and H2 for 30 minutes at a temperature of 420°C.

[0097] Example 2

[0098] Embodiment 2 provides an energy storage capacitor, which is a three-dimensional energy storage capacitor based on ferroelectric-antiferroelectric coupling.

[0099] In the energy storage capacitor of Example 2, the constituent material of the substrate is Si, the constituent material of the insulating layer is SiO2, and it also includes a bottom electrode arranged on the SiO2 insulating layer; a ferroelectric film arranged on the bottom electrode; an antiferroelectric film arranged on the ferroelectric film; and a top electrode arranged on the antiferroelectric film.

[0100] In step S1 of embodiment 2, the first groove structure of the substrate has a depth-to-width ratio of 20:1, and the inner wall is smooth.

[0101] In the step S1, a layer of SiO2 is oxidized on the surface of the substrate as an insulating layer by thermal oxidation method, the thermal oxidation temperature is controlled to be 950°C, the oxidants are H2O and O2, the O2 flow rate is 50L / min, the H2O is sufficient, and the thermal oxidation is performed for 2h to obtain an insulating layer of SiO2 with a thickness of 300nm.

[0102] In the step S21, a TiN bottom electrode is deposited on the insulating layer by a first atomic layer deposition method. In the first atomic layer deposition method, the Ti source is 50 sccm TDMAT, wherein the carrier gas is N2, the pulse time is 2s, and the purge time is 10s; the N source is 50 sccm NH3 plasma, wherein the carrier gas is Ar gas, the flow rate of NH3 is 100 sccm, the RF power is 2500W, the pulse time is 17s, and the purge time is 10s; the deposition temperature is controlled to be 200°C, and after 200 ALD cycles, the thickness of the TiN bottom electrode is 20nm.

[0103] In step S22, a second atomic layer deposition method is used to prepare a substrate having a general structure of Hf 0.5 Zr 0.5 O2 ferroelectric film. In the second atomic layer deposition method, the Hf source is 80sccm TDMAH, wherein the carrier gas is N2, the pulse time is 0.3s, and the purge time is 10s; the Zr source is 80sccm TDMAZ, wherein the carrier gas is N2, the pulse time is 0.3s, and the purge time is 10s; the O source is 150sccm O2 plasma, wherein the carrier gas is Ar gas, the flow rate of O2 is 130sccm, the RF power is 2500W, the pulse time is 8s, and the purge time is 10s; the ratio of HfO2 to ZrO2 is controlled to be 1:1, the deposition temperature is 280℃, and HfO2 is obtained after 38 ALD cycles. 0.5 Zr 0.5 The thickness of the O2 ferroelectric film is 3 nm.

[0104] In the step S23, a third atomic deposition method is used to prepare a ferroelectric film having a general structure of Hf 0.25 Zr 0.75 In the third atomic deposition method, the Hf source is 80sccm TDMAH, wherein the carrier gas is N2, the pulse time is 0.3s, and the purge time is 10s; the Zr source is 80sccm TDMAZ, wherein the carrier gas is N2, the pulse time is 0.3s, and the purge time is 10s; the O source is 150sccm O2 plasma, wherein the carrier gas is Ar gas, the flow rate of O2 is 130sccm, the RF power is 2500W, the pulse time is 8s, and the purge time is 10s; the ratio of HfO2 to ZrO2 is controlled to be 1:3, the deposition temperature is 280°C, and HfO2 is obtained after 88 ALD cycles. 0.25 Zr 0.75 The thickness of the O2 antiferroelectric film is 7 nm.

[0105] In the step S24, a TiN bottom electrode is prepared on the antiferroelectric film by using the fourth atomic layer deposition method. In the fourth atomic layer deposition method, the Ti source is 50 sccm TDMAT, wherein the carrier gas is N2, the pulse time is 2s, and the purge time is 10s; the N source is 50 sccm NH3 plasma, wherein the carrier gas is Ar gas, the flow rate of NH3 is 100 sccm, the RF power is 2500W, the pulse time is 17s; the purge time is 10s, the deposition temperature is 200°C, and after 500 ALD cycles, the thickness of the TiN bottom electrode is 50nm.

[0106] In step S31, an electrode pattern is formed on the top electrode by photolithography, and the electrode area is 50×50 μm 2 ; Then SF6 Plasma is used to etch away the TiN outside the pattern to separate the top electrode units.

[0107] In step S32, the top electrode unit is used as a template, and BCl3 gas is used to convert Hf 0.5 Zr 0.5 O2 and Hf 0.25 Zr 0.75 O2 is etched away until the bottom electrode is exposed.

[0108] In the step S4, the device obtained after the step S32 is annealed in a mixed atmosphere of N2 and H2 for 60 minutes at a temperature of 420°C.

[0109] Example 3

[0110] Embodiment 3 provides an energy storage capacitor, which is a three-dimensional energy storage capacitor based on ferroelectric-antiferroelectric coupling.

[0111] In the energy storage capacitor of Example 3, the constituent material of the substrate is Si, the constituent material of the insulating layer is SiO2, and it also includes a bottom electrode arranged on the SiO2 insulating layer; a ferroelectric film arranged on the bottom electrode; an antiferroelectric film arranged on the ferroelectric film; and a top electrode arranged on the antiferroelectric film.

[0112] In step S1 of embodiment 3, the first groove structure of the substrate has a depth-to-width ratio of 20:1, and the inner wall is smooth.

[0113] In the step S1, a layer of SiO2 is oxidized on the surface of the substrate as an insulating layer by thermal oxidation method, the thermal oxidation temperature is controlled to be 950°C, the oxidants are H2O and O2, the O2 flow rate is 50L / min, the H2O is sufficient, and the thermal oxidation is performed for 2h to obtain an insulating layer of SiO2 with a thickness of 300nm.

[0114] In the step S21, a TiN bottom electrode is deposited on the insulating layer by a first atomic layer deposition method. In the first atomic layer deposition method, the Ti source is 50 sccm TDMAT, wherein the carrier gas is N2, the pulse time is 2s, and the purge time is 10s; the N source is 50 sccm NH3 plasma, wherein the carrier gas is Ar gas, the flow rate of NH3 is 100 sccm, the RF power is 2500W, the pulse time is 17s, and the purge time is 10s; the deposition temperature is controlled to be 200°C, and after 200 ALD cycles, the thickness of the TiN bottom electrode is 20nm.

[0115] In step S22, a second atomic layer deposition method is used to prepare a substrate having a general structure of Hf 0.5 Zr 0.5 O2 ferroelectric film. In the second atomic layer deposition method, the Hf source is 80sccm TDMAH, wherein the carrier gas is N2, the pulse time is 0.3s, and the purge time is 10s; the Zr source is 80sccm TDMAZ, wherein the carrier gas is N2, the pulse time is 0.3s, and the purge time is 10s; the O source is 150sccm O2 plasma, wherein the carrier gas is Ar gas, the flow rate of O2 is 130sccm, the RF power is 2500W, the pulse time is 8s, and the purge time is 10s; the ratio of HfO2 to ZrO2 is controlled to be 1:1, the deposition temperature is 280℃, and HfO2 is obtained after 63 ALD cycles. 0.5 Zr 0.5 The thickness of the O2 ferroelectric film is 5 nm.

[0116] In the step S23, a third atomic deposition method is used to prepare a ferroelectric film having a general structure of Hf 0.25 Zr 0.75 In the third atomic deposition method, the Hf source is 80sccm TDMAH, wherein the carrier gas is N2, the pulse time is 0.3s, and the purge time is 10s; the Zr source is 80sccm TDMAZ, wherein the carrier gas is N2, the pulse time is 0.3s, and the purge time is 10s; the O source is 150sccm O2 plasma, wherein the carrier gas is Ar gas, the flow rate of O2 is 130sccm, the RF power is 2500W, the pulse time is 8s, and the purge time is 10s; the ratio of HfO2 to ZrO2 is controlled to be 1:3, the deposition temperature is 280°C, and HfO2 is obtained after 63 ALD cycles. 0.25 Zr 0.75 The thickness of the O2 antiferroelectric film is 5 nm.

[0117] In the step S24, a TiN bottom electrode is prepared on the antiferroelectric film by using the fourth atomic layer deposition method. In the fourth atomic layer deposition method, the Ti source is 50 sccm TDMAT, wherein the carrier gas is N2, the pulse time is 2s, and the purge time is 10s; the N source is 50 sccm NH3 plasma, wherein the carrier gas is Ar gas, the flow rate of NH3 is 100 sccm, the RF power is 2500W, the pulse time is 17s; the purge time is 10s, the deposition temperature is 200°C, and after 500 ALD cycles, the thickness of the TiN bottom electrode is 50nm.

[0118] In step S31, an electrode pattern is formed on the top electrode by photolithography, and the electrode area is 50×50 μm 2 ; Then SF6 Plasma is used to etch away the TiN outside the pattern to separate the top electrode units.

[0119] In step S32, the top electrode unit is used as a template, and BCl3 gas is used to convert Hf 0.5 Zr 0.5 O2 and Hf 0.25 Zr 0.75 O2 is etched away until the bottom electrode is exposed.

[0120] In the step S4, the device obtained after the step S32 is annealed in a mixed atmosphere of N2 and H2 for 60 minutes at a temperature of 420°C.

[0121] Comparative Example 1

[0122] This comparative example provides a comparative energy storage capacitor, which is different from the comparative energy storage capacitor of Example 1 in that the comparative energy storage capacitor does not contain a ferroelectric film.

[0123] The maximum polarization strength, breakdown strength and energy storage density of the energy storage capacitors of Examples 1-3 and the comparative energy storage capacitor of Comparative Example 1 are tested below. The results are shown in Table 1.

[0124] Table 1

[0125]

[0126] The testing process was recorded in "Antiferroelectrics for Energy Storage Applications: a Review" published in Advanced Materials Technologies in 2018 and "Research Progress in Antiferroelectric Energy Storage Ceramics" published in Electronic Components and Materials in 2020.

[0127] It can be seen from Table 1 that, compared with the comparative energy storage capacitor of Comparative Example 1, the maximum polarization intensity and breakdown electric field strength of the energy storage capacitors of Examples 1-3 of the present invention are improved, thereby increasing the energy storage density.

[0128] Although the embodiments of the present invention are described in detail above, it is obvious to those skilled in the art that various modifications and variations can be made to these embodiments. However, it should be understood that such modifications and variations are within the scope and spirit of the present invention as described in the claims. Moreover, the present invention described herein may have other embodiments and may be implemented or realized in a variety of ways.

Claims

1. An energy storage capacitor, characterized in that: It includes a substrate, an insulating layer, a bottom electrode, a ferroelectric film, an antiferroelectric film and a top electrode which are stacked in sequence: The substrate is provided with a first groove structure, the insulating layer covers the inner wall and the top surface of the first groove structure to form a second groove structure; the bottom electrode covers the inner wall and the top surface of the second groove structure to form a third groove structure; the ferroelectric film covers the inner part and the top surface of the third groove structure to form a fourth groove structure; the antiferroelectric film covers the inner part and the top surface of the fourth groove structure to form a fifth groove structure; The top electrode covers the sidewalls and top surface of the fifth trench structure to form a sixth trench structure; The ferroelectric film is a hafnium oxide film doped with Al element, and the antiferroelectric film is a hafnium oxide film doped with Al element.

2. The energy storage capacitor according to claim 1, characterized in that The aspect ratio of the first trench structure is 1:1-100:

1.

3. The energy storage capacitor according to claim 1, characterized in that The thickness of the insulating layer is in the range of 50-300 nm, and the thickness of the bottom electrode and the top electrode are both in the range of 10-200 nm.

4. The energy storage capacitor according to claim 3, characterized in that The insulating layer is made of silicon dioxide, and the bottom electrode and the top electrode are made of any one or two of TiN, TaN and Ru.

5. The energy storage capacitor according to claim 1, characterized in that The thickness of the ferroelectric film and the antiferroelectric film are both in the range of 1-25 nm.

6. A method for preparing an energy storage capacitor according to any one of claims 1 to 5, characterized in that: The following steps are involved: S1: after the first trench structure is formed in the substrate, an insulating layer covering the inner wall and top surface of the first trench structure is formed by a thermal oxidation method; S2: using an atomic layer deposition method to form the bottom electrode, the ferroelectric film, the antiferroelectric film and the top electrode which are sequentially stacked and arranged on the second groove structure.

7. The method for preparing an energy storage capacitor according to claim 6, characterized in that: In the step S1, the step of opening the first trench structure in the substrate includes: The aspect ratio of the first trench structure opened on the substrate is controlled to be 1:1-100:

1.

8. The method for preparing an energy storage capacitor according to claim 6, characterized in that: In the step S2, the step of using an atomic layer deposition method to form the bottom electrode, the ferroelectric film, the antiferroelectric film and the top electrode stacked in sequence on the second groove structure includes: A third groove structure is obtained by forming the bottom electrode covering the inner wall and the top surface of the second groove structure by a first atomic layer deposition method; A fourth trench structure is obtained by forming the ferroelectric thin film covering the inner wall and the top surface of the third trench structure using a second atomic layer deposition method; A fifth groove structure is obtained by forming the antiferroelectric thin film covering the inner wall and the top surface of the fourth groove structure by a third atomic layer deposition method; The sixth trench structure is obtained by forming the top electrode covering the inner wall and the top surface of the fifth trench structure using the fourth atomic layer deposition method.

9. The method for preparing an energy storage capacitor according to claim 8, characterized in that: The step S3 is also included: After forming an electrode pattern on the surface of the top electrode, etching is performed according to the electrode pattern to form a plurality of top electrode units independent of each other; The ferroelectric film and the antiferroelectric film are etched using the plurality of top electrode units as templates until the bottom electrode is exposed.

10. The method for preparing an energy storage capacitor according to claim 9, characterized in that: The step S4 is also included: The device obtained in step S3 is annealed for 30 seconds to 60 minutes at a temperature of 350 to 450 degrees Celsius and in an atmosphere of nitrogen or a mixed gas of nitrogen and hydrogen.

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