A Capacitor Switching Method for Successive Approximation Analog-to-Digital Converters with Low Common-Mode Voltage Variation

Abstract

The present invention claims protection for a capacitor switching method in a successive approximation analog-to-digital converter with low common-mode voltage variation, belongs to the field of analog integrated circuit design, and is used for the design of switching logic of differential capacitor arrays. The successive approximation analog-to-digital converter with low common-mode voltage variation designed by the present invention does not add additional circuits and power consumption through a special switching sequence design. While achieving excellent working performance, the amplitude of the common-mode voltage variation at the comparator input terminal during the entire operation is significantly reduced compared to traditional and many improved capacitor switches. The lower common-mode voltage variation at the comparator input terminal is very beneficial to the normal operation of the comparator with a preamplifier in a high-precision successive approximation analog-to-digital converter, thereby improving the overall performance of the converter. The capacitor switch designed by the present invention has strong approximation and can be applied to most successive approximation analog-to-digital conversion circuits with differential capacitor array structures, and is also applicable to capacitor upper plate sampling and lower plate sampling modes.

Description

Technical Field

[0001] The present invention belongs to the field of analog integrated circuit design, and in particular relates to a capacitance switch design of a differential capacitance successive approximation analog-to-digital converter. Background Art

[0002] Capacitive DAC is the most mainstream design solution for successive approximation analog-to-digital converters. Figure 2 This is a standard successive approximation ADC structure diagram. In a 10-bit or higher precision successive approximation ADC, since the offset voltage of the comparator latch stage is much larger than the minimum voltage that the converter needs to distinguish, one or more preamplifiers need to be added in front of the comparator to amplify the voltage difference provided by the capacitor DAC, thereby covering the offset voltage of the comparator latch stage and effectively reducing the impact of the latch stage kickback noise on the capacitor DAC. However, the amplifier circuit has a suitable common-mode voltage operating range, which is usually not too large, and the total range within the gain reduction of 3dB is generally not more than Exceeding this range can cause the amplifier's performance to plummet, even to the point of inoperability, impacting the entire converter's operation. Successive approximation ADCs, known for their simple structure and low power consumption, don't justify the use of specialized, complex, and power-hungry amplifiers to mitigate this problem. Traditional capacitor DAC switch designs have a common-mode variation range that's consistent with the entire measurement range. In recent years, many improvements to capacitor DAC switches have focused on improving power consumption, enhancing performance in low-precision ADCs. While this reduction in common-mode voltage variation has been achieved, it still falls short of the amplifier's normal operating conditions required for high-precision ADCs. Therefore, current designs often limit the common-mode voltage variation by sacrificing voltage range and narrowing the conversion range to ensure proper operation of the comparator preamplifier in high-precision SAR ADC designs. Summary of the Invention

[0003] The present invention aims to solve the above problems in the prior art. It proposes a capacitor switching method for a successive approximation analog-to-digital converter with low common-mode voltage variation. The technical solution of the present invention is as follows:

[0004] A method for switching capacitors in a successive approximation analog-to-digital converter with low common-mode voltage variation, comprising: sampling the input signal using an upper plate sampling method or a lower plate sampling method, and completing analog-to-digital conversion using the successive approximation switching method described in this patent after sampling is completed, wherein the upper plate sampling method is to keep all capacitors connected to V ref In the case of , the signal is sampled directly at the comparator input, such as Figure 3 The sampling method of the lower plate is to connect V cm , the input signal is sampled at the lower plate of the capacitor, such as Figure 4 As shown, after that disconnect Vcm and return the lower plate of the capacitor to V ref The sampling of the input signal is completed. The analog-to-digital conversion uses a comparator and a logic circuit to control the switch to perform successive approximation conversion according to the method described in this patent.

[0005] Furthermore, when the upper plate sampling method is adopted, for any differential capacitor array with upper plate sampling, the capacitor samples the input signal first; during sampling, the highest-order capacitor group is connected to GND, and all other capacitors are connected to V ref Reference voltage; after sampling, it enters the holding phase, at which time V xp =V ip , V xn =V in , where V xp 、V xn are the positive and negative input voltages of the comparator, V ip 、V in It is the positive and negative terminal voltage of the differential input signal, and then enters the state of preparing for comparison.

[0006] Furthermore, when the sampling method of the lower plate is adopted: for any differential capacitor array with upper plate sampling, the capacitor samples the input signal first; when sampling, V xp and V xn Access V cm , V cm for Reference voltage, V xp The lower plates of all MSB capacitors on the side are connected to V in , V xn The lower plates of all MSB capacitors on the side are connected to V ip , while all LSB segment capacitors on both sides remain at V ref , where V xp 、V xn are the positive and negative input voltages of the comparator, V ip 、V in The positive and negative voltages of the differential input signal are disconnected. cm , then connect the highest group of capacitors to GND, and all other capacitors to V ref , enters the holding phase, at this time, V xp =V ref -V in , V xn =V ref -V ip , and V xp -V xn =V ip -V in , enter the state of preparing for comparison.

[0007] Furthermore, the conversion by analog-to-digital conversion specifically includes: performing the first comparison directly after sampling, if the first comparison result is 1, that is, V xp >V xn , then the negative input terminal, that is, V xn The highest capacitor C1 on the side is connected from GND to V ref ,at this time and Prepare for the second comparison; if the first comparison result is 0, that is, V xp <V xn , then the positive input terminal, that is, V xp The highest capacitor C1 on the side is connected from GND to V ref ,at this time and Prepare for a second comparison; the result of the second comparison will determine whether to operate on the capacitor on one side of the positive or negative input terminal until the conversion is completed; and no matter what the result of the first comparison is, the subsequent operations are the same.

[0008] Furthermore, if the second comparison result is 1, that is, V xp >V xn , then the positive input side, that is, V xp The second highest capacitor C2 is V ref Connect to GND; at this time V xp decline Right now Perform the third comparison. If the comparison result is 1, the next capacitor C3 is changed from V ref Connect to GND, then Then prepare for the next comparison; if the third comparison result is 0, the previous capacitor C2 is switched from GND back to V ref Then, the next capacitor C3 is changed from V ref Connect to GND, then Then prepare for the next comparison; repeat this process continuously, that is, when the comparison result of the Nth time is 1, the capacitor CN is changed from V ref Connect to GND and continue to compare; when the Nth comparison result is 0, the previous capacitor C(N-1) is switched from GND back to V ref Then, the next capacitor CN is changed from V ref Connect to GND and continue comparing until all bits are compared.

[0009] Furthermore, if the second comparison result is 0, that is, V xp <V xn , then the negative input side, that is, V xn The second highest capacitor C2 is V refConnect to GND. At this time, V xn decline Right now Perform the third comparison. If the comparison result is 0, the next capacitor C3 is changed from V ref Connect to GND, then Then prepare for the next comparison; if the third comparison result is 1, the capacitor C2 of the previous bit is adjusted from GND back to V ref Then, the next capacitor C3 is changed from V ref Connect to GND, then Then prepare for the next comparison; repeat this process continuously, that is, when the Nth comparison result is 0, the capacitor CN is changed from V ref Connect to GND and continue to compare; when the Nth comparison result is 1, the previous capacitor C(N-1) is switched from GND back to V ref Then, the next capacitor CN is changed from V ref Connect to GND and continue comparing until all bits are compared.

[0010] Furthermore, the successive approximation analog-to-digital converter is applicable to different types of differential capacitive DAC circuits, including binary and segmented types.

[0011] Furthermore, when a 12-bit two-segment capacitor array successive approximation analog-to-digital converter is used, the capacitor array is divided into two segments, specifically 6+5+1, with 6 bits in the LSB low-order segment and 5 bits in the MSB high-order segment plus a redundant capacitor. Let the unit capacitance be C, and the LSB segment capacitances are C, 2C, ..., 2 5 C, and the MSB segment is C, 2C, ..., 2 4 C and a redundant capacitor C, the reference voltage V ref =V dd .

[0012] The advantages and beneficial effects of the present invention are as follows:

[0013] The capacitor array and logic design of the present invention does not use an additional specific voltage value to drive the comparator input common mode voltage to maintain the same value during the entire hold conversion phase. arrive In V dd = 2.5V, the comparator preamplifier can work well most of the time, and only loses 8dB of gain in rare extreme cases. In contrast, under the same conditions, the existing traditional capacitor switching logic will cause the preamplifier to completely fail to work properly. The common mode voltage at the comparator input of the monotonic (MCS) capacitor switching logic is to V ref , and the distribution is more concentrated near V refOn one side, the preamplifier is essentially non-functional. For successive approximation analog-to-digital converters with 10 bits or more, a comparator preamplifier is almost indispensable. Compared to many existing methods that sacrifice other performance or add auxiliary circuits to meet operating conditions, the method of the present invention maintains the common-mode voltage within a narrow range without adding additional circuitry, without sacrificing range and other parameter performance, and ensures the normal operation of the preamplifier in the subsequent comparator. It is an excellent solution for the design of high-precision successive approximation comparators. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 4-bit example diagram of a capacitor array switching method for a successive approximation analog-to-digital converter according to a preferred embodiment of the present invention;

[0015] Figure 2 This is the typical basic structural block diagram of the successive approximation analog-to-digital converter;

[0016] Figure 3 Schematic diagram of the capacitive switch method of the present invention sampling on the upper plate;

[0017] Figure 4 It is a schematic diagram of sampling on the lower plate of the capacitance switch method of the present invention. DETAILED DESCRIPTION

[0018] The following will describe the technical solutions in the embodiments of the present invention in detail with reference to the accompanying drawings. The described embodiments are only a part of the embodiments of the present invention.

[0019] The technical solution of the present invention to solve the above technical problems is:

[0020] The method of the present invention can be applied to most successive approximation analog-to-digital converters, including different types of differential capacitance DAC circuits, binary type, segmented type, etc.

[0021] Taking a 12-bit two-segment capacitor array successive approximation analog-to-digital converter as an example, the specific implementation of the method of the present invention is introduced. The capacitor array is divided into two segments, specifically 6+5+1, with the LSB segment (low segment) being 6 bits and the MSB (high segment) being 5 bits plus a redundant capacitor. Let the unit capacitance be C, and the LSB segment capacitances are C, 2C, ..., 2 5 C, and the MSB segment is C, 2C, ..., 2 4 C and a redundant capacitor C(dummy). Reference voltage V ref =V dd , ensuring maximum range and voltage utilization. The upper plate sampling and lower plate sampling operations differ except for the sampling operation, and all other subsequent operations are the same.

[0022] First, the capacitor samples the input signal. Figure 3 As shown, when the capacitor array uses the upper plate for sampling, during the sampling period, the highest-order capacitor group is connected to GND, and all other capacitors are connected to V ref After the sampling is completed, it enters the holding phase, at which time V xp =V ip , V xn =V in . Where V xp 、V xn are the positive and negative input voltages of the comparator, V ip 、V in is the differential input positive and negative terminal voltage. Figure 4 As shown, if the lower plate sampling is used, V xp and V xn Access V cm (Right now ), V xp The lower plates of all MSB capacitors on the side are connected to V in , V xn The lower plates of all MSB capacitors on the side are connected to V ip , while all LSB segment capacitors on both sides remain at V ref After that, disconnect V cm , then connect the highest group of capacitors to GND, and all other capacitors to V ref , enters the holding phase. At this time, V xp =V ref -V in , V xn =V ref -V ip , and V xp -V xn =V ip -V in .

[0023] After sampling, the first comparison is performed directly. If the first comparison result is 1, that is, V xp >V xn , then the negative input terminal, that is, V xn The highest capacitor C1 on the side is connected from GND to V ref ,at this time and Prepare for the second comparison; if the first comparison result is 0, that is, V xp <V xn , then the positive input terminal, that is, V xp The highest capacitor C1 on the side is connected from GND to V ref ,at this time and Prepare for a second comparison. The result of the second comparison will determine whether to operate on the capacitor on either side of the positive or negative input until the conversion is complete. Regardless of the result of the first comparison, the subsequent operations are the same.

[0024] If the second comparison result is 1, that is, V xp >V xn , then the positive input side, that is, V xp The second highest capacitor C2 is V ref Connect to GND. At this time, V xp decline Right now Perform the third comparison. If the comparison result is 1, the next capacitor C3 is changed from V ref Connect to GND, then Then prepare for the next comparison. If the third comparison result is 0, the capacitor C2 of the previous bit is switched from GND back to V ref Then, the next capacitor C3 is changed from V ref Connect to GND, then Then prepare for the next comparison. This process is repeated continuously. When the comparison result of the Nth time is 1, the capacitor CN is changed from V ref Connect to GND and continue to compare. When the Nth comparison result is 0, the previous capacitor C(N-1) is switched from GND back to V ref Then, the next capacitor CN is changed from V ref Connect to GND and continue comparing until all 12 bits are compared.

[0025] If the second comparison result is 0, that is, V xp <V xn , then the negative input side, that is, V xn The second highest capacitor C2 is V ref Connect to GND. At this time, V xn decline Right now Perform the third comparison. If the comparison result is 0, the next capacitor C3 is changed from V ref Connect to GND, then Then prepare for the next comparison. If the third comparison result is 1, the capacitor C2 of the previous bit is switched from GND back to V ref Then, the next capacitor C3 is changed from V ref Connect to GND, then Then prepare for the next comparison. This process is repeated continuously. When the comparison result of the Nth time is 0, the capacitor CN is changed from V refConnect to GND and continue to compare. When the Nth comparison result is 1, the capacitor C(N-1) of the previous bit is switched from GND back to V ref Then, the next capacitor CN is changed from V ref Connect to GND and continue comparing until all 12 bits are compared.

[0026] After all bit comparisons are completed, the digital logic in the analog-to-digital converter outputs the digital conversion result, completing a successive approximation analog-to-digital conversion.

[0027] Only when the differential input is When the common mode voltage approaches the critical value, the small differential mode will appear briefly during the conversion process. Even so, the comparator preamplifier gain is only slightly reduced. At other times, the preamplifier can operate within the excellent performance range, which meets the correct operation of the subsequent comparator.

[0028] Table 1 Comparison of common mode voltage changes between the method of the present invention and the traditional and popular improved methods

[0029]

[0030]

[0031] Table 1 lists the designs of various capacitor arrays, the traditional type, the existing popular improved type - monotonic switch (MCS) type, and the comparison with the method of the present invention. It can be seen that the traditional type has a V dd =V ref The maximum voltage utilization of the preamplifier is not enough to make it work properly. ref This will also cause the gain of the preamplifier to fluctuate greatly and deviate from the normal operating range. The switching method of the present invention reduces the common mode voltage variation range to 1 / 4 Vref, which can meet the normal operation of the comparator preamplifier under maximum voltage utilization.

[0032] In the above-mentioned embodiment of the present application, a 12-bit successive approximation analog-to-digital converter adopts this switching method for low common-mode voltage variation. By using this switching method on a capacitor DAC, the common-mode voltage variation at the comparator input is kept within a relatively small range during the conversion process, and the comparator preamplifier can operate normally throughout the entire process without the need for additional circuitry or means. This is an excellent solution for the design of high-precision successive approximation comparators.

[0033] It should also be noted that the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, commodity, or apparatus that includes a series of elements includes not only those elements but also other elements not explicitly listed, or includes elements inherent to such process, method, commodity, or apparatus. In the absence of further limitations, an element defined by the phrase "comprises a ..." does not exclude the presence of other identical elements in the process, method, commodity, or apparatus that includes the element.

[0034] The above embodiments should be understood as merely illustrating the present invention and not as limiting the scope of protection of the present invention. After reading the contents of the present invention, technicians may make various changes or modifications to the present invention, and these equivalent changes and modifications also fall within the scope defined by the claims of the present invention.

Claims

1. A method for capacitor switching in a successive approximation analog-to-digital converter with low common-mode voltage variation, characterized in that: include: The input signal is sampled using the upper plate sampling method or the lower plate sampling method. After sampling, the analog-to-digital conversion is completed using the successive approximation switching method. The upper plate sampling method is to keep all capacitors connected to V ref In the case of , the signal is sampled directly at the comparator input, and the sampling method of the lower plate is to connect V cm , the input signal is sampled at the lower plate of the capacitor, and then V cm and return the lower plate of the capacitor to V ref Complete the sampling of the input signal, where the analog-to-digital conversion uses a comparator and a logic circuit to control the switch for successive approximation conversion; When the upper plate sampling method is used, for any differential capacitor array with upper plate sampling, the capacitor samples the input signal first; during sampling, the highest-order capacitor group is connected to GND, and all other capacitors are connected to V ref Reference voltage; after sampling, it enters the holding phase, at which time V xp =V ip , V xn =V in , where V xp 、V xn are the positive and negative input voltages of the comparator, V ip 、V in It is the positive and negative voltage of the differential input signal, and then enters the state of preparing for comparison; When the bottom plate sampling method is used: For any differential capacitor array with top plate sampling, the capacitor first samples the input signal; when sampling, V xp and V xn Access V cm , V cm for Reference voltage, V xp The lower plates of all MSB capacitors on the side are connected to V in , V xn The lower plates of all MSB capacitors on the side are connected to V ip , while all LSB segment capacitors on both sides remain at V ref , where V xp 、V xn are the positive and negative input voltages of the comparator, V ip 、V in The positive and negative terminal voltages of the differential input signal are disconnected. cm , then connect the highest group of capacitors to GND, and all other capacitors to V ref , enters the holding phase, at this time, V xp =V ref -V in , V xn =V ref -V ip , and V xp -V xn =V ip -V in , enter the state of preparing for comparison.

2. The method for capacitance switching of a successive approximation analog-to-digital converter with low common-mode voltage variation according to claim 1, characterized in that: The conversion using analog-to-digital conversion specifically includes: performing the first comparison directly after sampling, if the first comparison result is 1, that is, V xp >V xn , then the negative input terminal, that is, V xn The highest capacitor C1 on the side is connected from GND to V ref ,at this time and Prepare for the second comparison; if the first comparison result is 0, that is, V xo <V xn , then the positive input terminal, that is, V xo The highest capacitor C1 on the side is connected from GND to V ref ,at this time and Prepare for a second comparison; the result of the second comparison will determine whether to operate on the capacitor on one side of the positive or negative input terminal until the conversion is completed; and no matter what the result of the first comparison is, the subsequent operations are the same.

3. The capacitor switching method of a successive approximation analog-to-digital converter with low common-mode voltage variation according to claim 2, characterized in that: If the second comparison result is 1, that is, V xp >V xn , then the positive input side, that is, V xp The second highest capacitor C2 is V ref Connect to GND; at this time V xp decline Right now Perform the third comparison. If the comparison result is 1, the next capacitor C3 is changed from V ref Connect to GND, then Then prepare for the next comparison; if the third comparison result is 0, the previous capacitor C2 is switched from GND back to V ref Then, the next capacitor C3 is changed from V ref Connect to GND, then Then prepare for the next comparison; repeat this process continuously, that is, when the comparison result of the Nth time is 1, the capacitor CN is changed from V ref Connect to GND and continue to compare; when the Nth comparison result is 0, the previous capacitor C(N-1) is switched from GND back to V ref Then, the next capacitor CN is changed from V ref Connect to GND and continue comparing until all bits are compared.

4. The capacitor switching method of a successive approximation analog-to-digital converter with low common-mode voltage variation according to claim 3, characterized in that: If the second comparison result is 0, that is, V xp <V xn , then the negative input side, that is, V xn The second highest capacitor C2 is V ref Connect to GND, then V xn decline Right now Perform the third comparison. If the comparison result is 0, the next capacitor C3 is changed from V ref Connect to GND, then Then prepare for the next comparison; if the third comparison result is 1, the capacitor C2 of the previous bit is adjusted from GND back to V ref Then, the next capacitor C3 is changed from V ref Connect to GND, then Then prepare for the next comparison; repeat this process continuously, that is, when the Nth comparison result is 0, the capacitor CN is changed from V ref Connect to GND and continue to compare; when the Nth comparison result is 1, the previous capacitor C(N-1) is switched from GND back to V ref Then, the next capacitor CN is changed from V ref Connect to GND and continue comparing until all bits are compared.

5. The method for capacitor switching of a successive approximation analog-to-digital converter with low common-mode voltage variation according to claim 1, characterized in that: The successive approximation analog-to-digital converter is suitable for different types of differential capacitive DAC circuits, including binary and segmented types.

6. The method for capacitor switching of a successive approximation analog-to-digital converter with low common-mode voltage variation according to claim 5, characterized in that: When a 12-bit two-segment capacitor array successive approximation analog-to-digital converter is used, the capacitor array is divided into two segments, specifically 6+5+1, with 6 bits in the LSB low-order segment and 5 bits in the MSB high-order segment plus a redundant capacitor. Let the unit capacitance be C, and the LSB segment capacitances are C, 2C, ..., 2 5 C, and the MSB segment is C, 2C, ..., 2 4 C and a redundant capacitor C, the reference voltage V ref =V dd .

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