Semiconductor package including capacitor

Abstract

Semiconductor package including capacitors. A semiconductor package includes: a sub-semiconductor package disposed above a substrate, the sub-semiconductor package including: a sub-semiconductor chip having a chip pad on an upper surface, a molding layer surrounding a side surface of the sub-semiconductor chip, and a redistribution layer formed above the sub-semiconductor chip and the molding layer, the redistribution layer including a redistribution conductive layer connected to the chip pad of the sub-semiconductor chip and extending to an edge of the molding layer, while having a redistribution pad at an end thereof; a first sub-package interconnector connected to the redistribution pad to electrically connect the sub-semiconductor chip and the substrate; a capacitor formed in the molding layer and including a first electrode, a second electrode, and a main body, the first electrode and the second electrode having upper surfaces respectively connected to the redistribution conductive layer.

Description

Technical Field

[0001] The present patent document relates to a semiconductor package, and more particularly, to a semiconductor package including a capacitor. Background Art

[0002] Recently, the demand for high-speed operation and large-capacity data processing of semiconductor devices has increased. For this reason, it is necessary to increase the number of signals sent to the semiconductor devices at the same time or the signal transmission speed.

[0003] However, there is a problem that as semiconductor devices operate at high speed and the number of signals transmitted simultaneously increases, power / ground noise increases. Therefore, a method of adding a capacitor (i.e., a decoupling capacitor) to a power transmission path for stabilizing power / ground supply is currently used. Summary of the invention

[0004] In an embodiment, a semiconductor package may include: a substrate; a sub-semiconductor package disposed above the substrate, the sub-semiconductor package including: a sub-semiconductor chip having a chip pad on an upper surface thereof; a molding layer surrounding a side surface of the sub-semiconductor chip; and a redistribution layer formed above the sub-semiconductor chip and the molding layer, the redistribution layer including a redistribution conductive layer connected to the chip pad of the sub-semiconductor chip and extending to an edge of the molding layer and having a redistribution pad at an end thereof; a first sub-package interconnector connected to the redistribution pad to electrically connect the sub-semiconductor chip and the substrate; a capacitor formed in the molding layer and including a first electrode, a second electrode, and a main body portion between the first electrode and the second electrode, the first electrode and the second electrode having upper surfaces respectively connected to the redistribution conductive layer; and at least one main semiconductor chip formed above the sub-semiconductor package and electrically connected to the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 is a plan view illustrating a semiconductor package according to an embodiment of the present disclosure.

[0006] Figure 2 is an example Figure 1 A plan view of a portion of a semiconductor package is shown with a first chip stack, a second chip stack, and an interconnector connected to the first chip stack and the second chip stack omitted.

[0007] Figure 3 is an example Figure 1 A cross-sectional view of a semiconductor package is shown.

[0008] Figure 4 is an example Figure 1 A plan view of a sub-semiconductor package.

[0009] Figure 5 It is along Figure 4 A cross-sectional view taken along line A2-A2′.

[0010] Figure 6 It is along Figure 4 A cross-sectional view taken along line A3-A3′.

[0011] Fig. 7A is a diagram for explaining an example of the effect of the semiconductor package according to the embodiment of the present disclosure.

[0012] Figure 7B It is a diagram for explaining the effects of the semiconductor package according to the comparative example.

[0013] Figure 8 is a cross-sectional view illustrating a semiconductor package according to another embodiment of the present disclosure.

[0014] Fig. 9 is an example Figure 8 A plan view of a sub-semiconductor package.

[0015] Fig.10 It is along Fig. 9 A cross-sectional view taken along line A4-A4′.

[0016] Fig.11 It is along Fig. 9 A cross-sectional view taken along line A5-A5′.

[0017] Fig. 12A is a diagram for explaining an example of the effect of a semiconductor package according to another embodiment of the present disclosure.

[0018] Fig. 12B It is a diagram for explaining the effects of the semiconductor package according to the comparative example.

[0019] Fig.13 is a cross-sectional view illustrating a semiconductor package according to another embodiment of the present disclosure.

[0020] Fig.14 is a plan view illustrating a sub-semiconductor package in a semiconductor package according to another embodiment of the present disclosure.

[0021] Fig.15 It is along Fig.14 A cross-sectional view taken along line A6-A6′.

[0022] Fig.16 It is along Fig.14 A cross-sectional view taken along line A7-A7′.

[0023] Fig.17Ais a diagram for explaining an example of the effect of a semiconductor package according to another embodiment of the present disclosure.

[0024] Fig. 17B It is a diagram for explaining the effect of the semiconductor package of the comparative example.

[0025] Fig.18 A block diagram illustrating an example electronic system employing a memory card including a semiconductor package according to an embodiment is shown.

[0026] Fig.19 A block diagram illustrating another electronic system including a semiconductor package according to an embodiment is shown. DETAILED DESCRIPTION

[0027] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0028] The drawings are not necessarily drawn to scale. In some cases, the proportions of at least some structures in the drawings may have been exaggerated in order to clearly illustrate some features of the described embodiments. When a specific example is presented in a drawing or description of two or more layers of a multilayer structure, the relative positional relationship of such layers shown or the arrangement order of these layers reflects the specific implementation of the described or illustrated example, and different relative positional relationships or arrangement orders of these layers may be possible. In addition, the described or illustrated examples of multilayer structures may not reflect all layers present in a specific multilayer structure (for example, one or more additional layers may exist between the two illustrated layers). As a specific example, when the first layer in the described or illustrated multilayer structure is referred to as "on" or "above" the second layer or "on" or "above" the substrate, the first layer may be directly formed on the second layer or substrate, but it may also represent a structure in which one or more other intermediate layers may exist between the first layer and the second layer or substrate.

[0029] Figure 1 is a plan view illustrating a semiconductor package according to an embodiment of the present disclosure. Figure 2 is an example Figure 1 A plan view of a portion of a semiconductor package is shown with a first chip stack, a second chip stack, and an interconnector connected to the first chip stack and the second chip stack omitted. Figure 3 is an example Figure 1 A cross-sectional view of a semiconductor package. Figure 1 and Figure 2 They are top views of a semiconductor package and a portion thereof, respectively. Figure 3 Illustrated along the Figure 1 and Figure 2 A cross section taken along line A1-A1′. Figure 4 is an example Figure 1A plan view of a sub-semiconductor package, Figure 5 It is along Figure 4 A cross-sectional view taken along line A2-A2′, and Figure 6 It is along Figure 4 A cross-sectional view taken along line A3-A3′.

[0030] First, refer to Figures 1 to 3 , a semiconductor package according to an embodiment of the present disclosure may include a substrate 100 , a sub-semiconductor package 110 disposed over the substrate 100 , and a first chip stack 120 and a second chip stack 130 disposed over the sub-semiconductor package 110 .

[0031] The substrate 100 may be a substrate such as a printed circuit board (PCB) for a semiconductor package, which has a circuit and / or a wiring structure to transmit an electrical signal.

[0032] The substrate 100 may have an upper surface and a lower surface located opposite to the upper surface. The sub-semiconductor package 110, the first chip stack 120, and the second chip stack 130 may be arranged above the upper surface of the substrate 100. The external connection terminal 140 for connecting the semiconductor package to the outside may be arranged above the lower surface of the substrate 100. For reference, the upper surface and the lower surface to be described below are expressions indicating the relative positions of the various surfaces of the components, and do not indicate the absolute positions. For example, in a case where the semiconductor package is turned upside down as opposed to the illustration, the surface on which the sub-semiconductor package 110 and the first chip stack 120 and the second chip stack 130 are arranged may be the lower surface of the substrate 100, and the surface on which the external connection terminal 140 is arranged may be the upper surface of the substrate 100.

[0033] The substrate 100 may include an upper surface substrate pad 102 and a lower surface substrate pad 104. The upper surface substrate pad 102 may be disposed on the upper surface of the substrate 100 to electrically connect the sub-semiconductor package 110, the first chip stack 120 and the second chip stack 130 to the substrate 100. The lower surface substrate pad 104 may be disposed on the lower surface of the substrate 100 to electrically connect the external connection terminal 140 to the substrate 100. For reference, the substrate pad may mean a conductive element or terminal exposed on the surface of the substrate 100 to electrically connect the substrate 100 to other components. As an example, the upper surface substrate pad 102 may be a bonding finger for wiring bonding, and the lower surface substrate pad 104 may be a ballland for bonding with a solder ball. The upper surface substrate pad 102 and the lower surface substrate pad 104 may be connected to the circuit and / or wiring structure inside the substrate 100.

[0034] The upper surface substrate pad 102 may be disposed at two side edges of the substrate 100 that do not overlap with the sub-semiconductor package 110. For example, the upper surface substrate pad 102 may be disposed at two side edges of the substrate 100 in the first direction. For reference, the first side of the two sides in the first direction may correspond to Figure 1 and Figure 2 The upper side of Figure 3 In addition, the second side of the two sides in the first direction may correspond to Figure 1 and Figure 2 The lower side, and Figure 3 In the present embodiment, the upper surface substrate pads 102 may be arranged in a row at each side of the two side edges of the substrate 100 in a second direction intersecting the first direction. However, the present embodiment is not limited thereto. The number, arrangement, etc. of the upper surface substrate pads 102 may be modified in various ways at each side of the two side edges of the substrate 100.

[0035] The sub-semiconductor package 110 may have a smaller plane area than the upper surface of the substrate 100. The sub-semiconductor package 110 may be disposed to expose at least both side edges in the first direction and / or the upper surface substrate pad 102 of the substrate 100. As an example, the sub-semiconductor package 110 may be disposed in a central area of ​​the substrate 100. The sub-semiconductor package 110 may be attached to the upper surface of the substrate 100 by an insulating adhesive material (not shown) such as a die attach film (DAF).

[0036] The sub semiconductor package 110 may include a sub semiconductor chip 114 , a sub mold layer 116 surrounding lower and side surfaces of the sub semiconductor chip 114 , and a redistribution structure 118 formed over upper surfaces of the sub semiconductor chip 114 and the sub mold layer 116 .

[0037] The sub-semiconductor chip 114 may be a semiconductor chip that performs various functions required for the operation of the first main semiconductor chip 124 and / or the second main semiconductor chip 134. As an example, in the case where each of the first main semiconductor chip 124 and the second main semiconductor chip 134 includes a non-volatile memory such as a NAND flash memory, the sub-semiconductor chip 114 may include a controller for controlling the first main semiconductor chip 124 and the second main semiconductor chip 134. However, the present embodiment is not limited thereto, and the sub-semiconductor chip 114 may include a volatile memory such as a dynamic random access memory (DRAM) and a static RAM (SRAM), a non-volatile memory such as a NAND flash memory, a resistive RAM (RRAM), a phase change RAM (PRAM), a magnetoresistive RAM (MRAM), and a ferroelectric RAM (FRAM), or other various active elements or passive elements.

[0038] The sub-semiconductor chip 114 may have a lower surface facing the upper surface of the substrate 100, an upper surface located opposite to the lower surface, and a side surface connecting the upper surface and the lower surface. In the present embodiment, the sub-semiconductor chip 114 may have four side surfaces. The four side surfaces may be located at two sides in the first direction and two sides in the second direction, respectively. For reference, the first side of the two sides in the second direction may correspond to Figure 1 and Figure 2 The right side of the second direction may correspond to Figure 1 and Figure 2 on the left side.

[0039] The sub-semiconductor chip 114 may be located in a central region of the sub-semiconductor package 110. This is to make the lengths of redistribution conductive layers 118B, which will be described later, as similar as possible to each other.

[0040] The sub-chip pads 115 may be disposed on the upper surface of the sub-semiconductor chip 114. The sub-semiconductor chip 114 may have a relatively small plane area, and the number of the sub-chip pads 115 may be relatively large. As an example, it may be assumed that the sub-semiconductor chip 114 is a memory controller and the first main semiconductor chip 124 and the second main semiconductor chip 134 are memories. In this case, although the size of the sub-semiconductor chip 114 is reduced with the development of technology, a large number of sub-chip pads 115 corresponding to a large number of input / output signals may be required in order to connect the corresponding first chip stack 120 and the second chip stack 130 to the sub-semiconductor chip 114 through independent channels. Due to this fact, the sub-chip pads 115 may be arranged along the entire edge of the sub-semiconductor chip 114. That is, the sub-chip pads 115 may be arranged along the first side edge and the second side edge of the sub-semiconductor chip 114 in the first direction, and along the first side edge and the second side edge of the sub-semiconductor chip 114 in the second direction.

[0041] The sub-molding layer 116 may have an upper surface substantially at the same height as the upper surface of the sub-semiconductor chip 114, while surrounding the side surface of the sub-semiconductor chip 114. Therefore, the sub-molding layer 116 may expose the sub-chip pad 115 and the upper surface of the sub-semiconductor chip 114. In the present embodiment, the sub-molding layer 116 may cover the lower surface of the sub-semiconductor chip 114. However, the present embodiment is not limited thereto. In another embodiment, the sub-molding layer 116 may have a lower surface substantially at the same height as the lower surface of the sub-semiconductor chip 114. The sub-molding layer 116 may include various molding materials such as epoxy molding compound (EMC).

[0042] The redistribution structure 118 may extend onto the upper surface of the sub-mold layer 116 while being electrically connected to the sub-chip pad 115. In other words, the sub-semiconductor package 110 according to the present embodiment may be a fan-out package.

[0043] In detail, the redistribution structure 118 may include a first redistribution insulating layer 118A, a redistribution conductive layer 118B, and a second redistribution insulating layer 118C. The first redistribution insulating layer 118A may be formed above the upper surface of the sub-semiconductor chip 114 and the sub-molding layer 116. The first redistribution insulating layer 118A may have an opening exposing the sub-chip pad 115. The redistribution conductive layer 118B may be formed above the first redistribution insulating layer 118A. The redistribution conductive layer 118B may be electrically connected to the sub-chip pad 115 through the opening of the first redistribution insulating layer 118A. The second redistribution insulating layer 118C may cover the first redistribution insulating layer 118A and the redistribution conductive layer 118B. The second redistribution insulating layer 118C may have an opening exposing the end of the redistribution conductive layer 118B. The first redistribution insulating layer 118A and the second redistribution insulating layer 118C may include an insulating material such as an oxide, a nitride, or a nitride oxide. Alternatively, the first redistribution insulating layer 118A and the second redistribution insulating layer 118C may include a resin material such as epoxy, polyimide, polybenzoxazole (PBO), benzocyclobutene (BCB), silicone or acrylate. The redistribution conductive layer 118B may include a metal material such as gold, copper or a copper alloy.

[0044] Specifically, the portion of the redistribution conductive layer 118B exposed through the opening of the second redistribution insulating layer 118C will be referred to as the redistribution pad 118BP hereinafter. The redistribution conductive layer 118B may extend from the sub-chip pad 115, and each redistribution conductive layer 118B may have a linear portion with a relatively small width and a plate-like end portion with a relatively large width and located at the end of the linear portion. The opening of the second redistribution insulating layer 118C may expose the plate-like end portion of the redistribution conductive layer 118B, and may have a planar area that is less than or equal to the planar area of ​​the plate-like end portion while overlapping with the plate-like end portion. Figure 1 and Figure 2In the top view of FIG. 1 , for the convenience of explanation, the first redistribution insulating layer 118A and the second redistribution insulating layer 118C of the redistribution structure 118 are not illustrated. Similar to the arrangement of the upper surface substrate pads 102, the redistribution pads 118BP may be disposed at the first side edge and the second side edge of the sub-mold layer 116 in the first direction. In addition, the redistribution pads 118BP may be arranged in a row in the second direction at each of the first side edge and the second side edge of the sub-mold layer 116. However, the present disclosure is not limited thereto, and at each of the first side edge and the second side edge of the sub-mold layer 116, the number, arrangement, etc. of the redistribution pads 118BP may be modified in various ways.

[0045] According to the arrangement of the redistribution pads 118BP, the redistribution conductive layer 118B may extend from the sub-chip pads 115 disposed at the first side edge of the sub-semiconductor chip 114 in the first direction and the second direction to the redistribution pads 118BP disposed at the first side edge of the sub-molding layer 116 in the first direction. In addition, the redistribution conductive layer 118B may extend from the sub-chip pads 115 disposed at the second side edge of the sub-semiconductor chip 114 in the first direction and the second direction to the redistribution pads 118BP disposed at the second side edge of the sub-molding layer 116 in the first direction. The redistribution conductive layer 118B extending from the two side edges of the sub-semiconductor chip 114 in the second direction may have a curved shape toward the redistribution pads 118BP. In addition, the redistribution conductive layers 118B extending from the two side edges of the sub-semiconductor chip 114 in the first direction may not need to be bent because these redistribution conductive layers 118B face the redistribution pads 118BP. However, in order to have a length similar to that of the redistribution conductive layer 118B extending from both side edges of the sub-semiconductor chip 114 in the second direction, the redistribution conductive layer 118B extending from both side edges of the sub-semiconductor chip 114 in the first direction may also have a curved shape. As a result, the redistribution conductive layer 118B may have a tornado-like shape, for example, a spiral shape, centered on the sub-semiconductor chip 114. Through this connection scheme, the variation in length of the redistribution conductive layer 118B may be reduced.

[0046] The sub-package interconnector 117 may connect the redistribution pad 118BP and the upper surface substrate pad 102. By this fact, the sub-semiconductor chip 114 and the substrate 100 may be electrically connected. The sub-package interconnector 117 may be a bonding wire having a first end connected to the upper surface substrate pad 102 and a second end connected to the redistribution pad 118BP. However, the present embodiment is not limited thereto, and various types of electrical interconnectors may be used as the sub-package interconnector 117.

[0047] The first chip stack 120 may include a plurality of first main semiconductor chips 124. The first main semiconductor chips 124 may be formed above the sub-semiconductor package 110, and may be stacked in a vertical direction with respect to the upper surface of the substrate 100. Although the present embodiment illustrates a case where the first chip stack 120 includes four first main semiconductor chips 124, the present disclosure is not limited thereto, and the number of first main semiconductor chips 124 included in the first chip stack 120 may be modified to one or more first main semiconductor chips 124 in various ways.

[0048] Each first master semiconductor chip 124 may include a NAND flash memory as described above. However, the present disclosure is not limited thereto, and each first master semiconductor chip 124 may include a volatile memory such as a dynamic random access memory (DRAM) and a static RAM (SRAM), or a non-volatile memory such as a resistive RAM (RRAM), a phase change RAM (PRAM), a magnetoresistive RAM (MRAM), and a ferroelectric RAM (FRAM).

[0049] The first main semiconductor chip 124 may be arranged in a direction toward the second side in the first direction (eg, in a direction toward Figure 1 The lower side and Figure 3 By this fact, a first chip stack 120 having a stepped shape when viewed as a whole can be formed. The offset stacking direction of the first main semiconductor chips 124 can be referred to as a first offset direction. According to such an offset stacking, except for the uppermost first main semiconductor chip 124 among the first main semiconductor chips 124, the first side edge of the upper surface of each of the remaining first main semiconductor chips 124 can be exposed without being covered by the first main semiconductor chip 124 placed immediately thereon. For example, Figure 1 The upper side of the upper surface of each of the remaining first main semiconductor chips 124 and Figure 3 The left side of the upper surface of each of the remaining first main semiconductor chips 124 may be exposed. The first side edge of the upper surface of the uppermost first main semiconductor chip 124 may be exposed without being covered by the lowermost second main semiconductor chip 134 of the second chip stack 130 to be described later. The first chip pads 125 may be disposed on such exposed portions of the first main semiconductor chips 124. A plurality of first chip pads 125 may be arranged in a row at the first side edge of the upper surface of each first main semiconductor chip 124 in the second direction. However, the present disclosure is not limited thereto, and the number and arrangement of the first chip pads 125 at the first side edge of the upper surface of each first main semiconductor chip 124 may be variously modified. For reference, because Figure 1The top view of FIG. 1 does not illustrate a portion of the first chip stack 120 that is hidden by the second chip stack 130 , so a portion of the first chip stack 120 , for example, a first side edge portion of the lowermost first main semiconductor chip 124 , is illustrated.

[0050] Each first main semiconductor chip 124 may be attached to the sub semiconductor package 110 or the first main semiconductor chip 124 immediately thereunder through the first adhesive layer 122. The first adhesive layer 122 may be formed on the lower surface of each first main semiconductor chip 124 to have a shape overlapping the lower surface.

[0051] The first chip stack 120 or the first main semiconductor chip 124 may have a smaller plane area than the sub-semiconductor package 110, and may have a larger plane area than the sub-semiconductor chip 114. The first chip stack 120 may be disposed to expose at least the redistribution pads 118BP disposed at both side edges of the sub-semiconductor package 110 in the first direction.

[0052] The first interconnector 127 can connect the first chip pads 125 adjacent in the vertical direction to each other, and can electrically connect the first chip pad 125 of the lowermost first main semiconductor chip 124 to the upper surface substrate pad 102 provided at the first side edge of the substrate 100 in the first direction. By this fact, the first main semiconductor chips 124 can be electrically connected to each other, and the first chip stack 120 can be electrically connected to the substrate 100. The first interconnector 127 can be a bonding wire. However, the present embodiment is not limited thereto, and various types of electrical interconnectors can be used as the first interconnector 127.

[0053] The second chip stack 130 may include a plurality of second main semiconductor chips 134. The second main semiconductor chips 134 may be formed above the first chip stack 120 and may be stacked in a vertical direction. Although the present embodiment illustrates a case where the second chip stack 130 includes four second main semiconductor chips 134, the present disclosure is not limited thereto, and the number of second main semiconductor chips 134 included in the second chip stack 130 may be modified in various ways to one or more second main semiconductor chips 134. In addition, although in the present embodiment, the number of second main semiconductor chips 134 included in the second chip stack 130 is the same as the number of first main semiconductor chips 124 included in the first chip stack 120, it should be noted that these numbers may be different from each other.

[0054] Each second main semiconductor chip 134 may include a NAND flash memory as described above. However, the present disclosure is not limited thereto, and each second main semiconductor chip 134 may include a volatile memory such as a dynamic random access memory (DRAM) and a static RAM (SRAM), or a non-volatile memory such as a resistive RAM (RRAM), a phase change RAM (PRAM), a magnetoresistive RAM (MRAM), and a ferroelectric RAM (FRAM). In the present embodiment, the second main semiconductor chip 134 is the same semiconductor chip as the first main semiconductor chip 124. However, in another embodiment, the second main semiconductor chip 134 may be a semiconductor chip different from the first main semiconductor chip 124.

[0055] The second main semiconductor chip 134 may be arranged in a direction toward the first side in the first direction (eg, in a direction toward the Figure 1 The upper side and Figure 3 By this fact, a second chip stack 130 having a stepped shape when viewed as a whole can be formed. The offset stacking direction of the second main semiconductor chips 134 can be referred to as a second offset direction. The second offset direction can be opposite to the first offset direction. According to this offset stacking, except for the uppermost second main semiconductor chip 134 among the second main semiconductor chips 134, the second side of the upper surface of each of the remaining second main semiconductor chips 134 can be exposed without being covered by the second main semiconductor chip 134 placed immediately thereon. For example, Figure 1 The lower side edge of the upper surface of each of the remaining second main semiconductor chips 134 and Figure 3 The right side edge of the upper surface of each of the remaining second main semiconductor chips 134 may be exposed. The uppermost second main semiconductor chip 134 may be in a state where its entire upper surface is exposed. The second chip pads 135 may be disposed on the exposed portions of the remaining second main semiconductor chips 134 except the uppermost second main semiconductor chip 134, and the second chip pads 135 of the uppermost second main semiconductor chip 134 may also be disposed at the same position as the second chip pads 135 of the remaining second main semiconductor chips 134. A plurality of second chip pads 135 may be arranged in a row at the second side edge of the upper surface of each second main semiconductor chip 134 in the second direction. However, the present disclosure is not limited thereto, and the number and arrangement of the second chip pads 135 at the second side edge of the upper surface of each second main semiconductor chip 134 may be modified in various ways.

[0056] In the case where the second main semiconductor chips 134 are the same semiconductor chips as the first main semiconductor chips 124 , each second main semiconductor chip 134 may correspond to a state in which each first main semiconductor chip 124 is rotated 180 degrees around an axis extending in a vertical direction.

[0057] Each second main semiconductor chip 134 may be attached to the second main semiconductor chip 134 disposed immediately therebelow or the uppermost first main semiconductor chip 124 of the first chip stack 120 through the second adhesive layer 132. The second adhesive layer 132 may be formed on the lower surface of each second main semiconductor chip 134 to have a shape overlapping the lower surface.

[0058] The second chip stack 130 or the second main semiconductor chip 134 may have a smaller plane area than the sub-semiconductor package 110, and may have a larger plane area than the sub-semiconductor chip 114. The second chip stack 130 may be arranged to expose at least two side edges in the first direction of the sub-semiconductor package 110. That is, the second chip stack 130 may be arranged to expose the redistribution pad 118BP.

[0059] The second interconnector 137 can connect the second chip pads 135 adjacent in the vertical direction to each other, and can electrically connect the second chip pads 135 of the lowermost second main semiconductor chip 134 to the upper surface substrate pad 102 provided at the second side edge of the substrate 100 in the first direction. By this fact, the second main semiconductor chips 134 can be electrically connected to each other, and the second chip stack 130 can be electrically connected to the substrate 100. The second interconnector 137 can be a bonding wire. However, the present embodiment is not limited thereto, and various types of electrical interconnectors can be used as the second interconnector 137.

[0060] exist Figure 1 and Figure 2 In the top view of FIG. 1 , for easy distinction, the sub-package interconnect 117, the first interconnect 127 and the second interconnect 137 are illustrated with solid lines and dashed lines. However, it should be noted that, of course, such solid lines and dashed lines do not reflect the actual shapes of the interconnects 117, 127 and 137.

[0061] The sub-semiconductor package 110, the first chip stack 120, and the second chip stack 130 may be covered by a mold layer 150 formed over the substrate 100. The mold layer 150 may include various molding materials such as EMC.

[0062] The external connection terminal 140 may include a solder ball. However, the present disclosure is not limited thereto, and various conductive terminals such as a bump may be used as the external connection terminal 140.

[0063] In the above-mentioned semiconductor package, the first chip stack 120 can be identified as a single semiconductor chip, while being connected to the upper surface substrate pad 102 of the substrate 100 through the first interconnector 127. In addition, the second chip stack 130 can be identified as another single semiconductor chip different from the first chip stack 120, while being connected to the upper surface substrate pad 102 of the substrate 100 through the second interconnector 137. The sub-semiconductor chip 114 can be connected to the upper surface substrate pad 102 of the substrate 100 through the redistribution structure 118 and the sub-package interconnector 117.

[0064] In addition, in the above-mentioned semiconductor package, the sub-package interconnector 117 can be connected to the upper surface substrate pad 102 alone, the first interconnector 127 can be connected to the upper surface substrate pad 102 alone, the second interconnector 137 can be connected to the upper surface substrate pad 102 alone, the sub-package interconnector 117 and the first interconnector 127 can be connected to the upper surface substrate pad 102 together, or the sub-package interconnector 117 and the second interconnector 137 can be connected to the upper surface substrate pad 102 together. The upper surface substrate pad 102 connected to the sub-package interconnector 117 alone can be used as a power supply voltage supply pad or a signal transmission pad of the sub-semiconductor chip 114. The upper surface substrate pad 102 connected to the first interconnector 127 alone can be used as a power supply voltage supply pad or a signal transmission pad of the first chip stack 120. The upper surface substrate pad 102 connected to the second interconnector 137 alone can be used as a power supply voltage supply pad or a signal transmission pad of the second chip stack 130. The upper surface substrate pad 102 commonly connected to the sub-package interconnector 117 and the first interconnector 127, and / or the upper surface substrate pad 102 commonly connected to the sub-package interconnector 117 and the second interconnector 137 can be used as a ground voltage supply pad. This can mean that power is supplied or a signal is transmitted from the substrate 100 to each of the sub-semiconductor chips 114, the first chip stack 120, and the second chip stack 130.

[0065] Specifically, power supply or signal transmission to the sub-semiconductor chip 114 may be performed through the redistribution conductive layer 118B. However, because a large number of redistribution conductive layers 118B are disposed in a limited space, the spacing and / or line width of the redistribution conductive layer 118B may be reduced. In this case, the impedance of the redistribution conductive layer 118B may increase, and thus a problem of interrupting power supply may be caused. In order to solve this problem, as Figure 2 As shown in the plan view of FIG. 1 , the sub-semiconductor package 110 may further include a capacitor (see the dashed square) connected to the redistribution conductive layer 118B. Figures 4 to 6 The capacitor is described in more detail.

[0066] Reference Figures 4 to 6, the sub-chip pads 115 on the upper surface of the sub-semiconductor chip 114 may include a signal sub-chip pad 115-S, a ground sub-chip pad 115-G, and a power sub-chip pad 115-P. The redistribution conductive layer 118B may include a signal redistribution conductive layer 118B-S connected to the signal sub-chip pad 115-S, a ground redistribution conductive layer 118B-G connected to the ground sub-chip pad 115-G, and a power redistribution conductive layer 118B-P connected to the power sub-chip pad 115-P. The signal redistribution pad 118BP-S may be disposed at an end of the signal redistribution conductive layer 118B-S, the ground redistribution pad 118BP-G may be disposed at an end of the ground redistribution conductive layer 118B-G, and the power redistribution pad 118BP-P may be disposed at an end of the power redistribution conductive layer 118B-P. The sub-semiconductor chip 114 may be removed from the substrate (see FIG. 1 ) through the signal redistribution conductive layer 118B-S. Figures 1 to 3 In addition, the ground redistribution conductive layer 118B-G can be connected to the substrate (see Figures 1 to 3 100 in FIG. 100 ) provides a ground voltage for the sub-semiconductor chip 114. In addition, the power redistribution conductive layer 118B-P can be connected to the substrate (see FIG. 100 ). Figures 1 to 3 100 in the substrate 100) provides a power supply voltage to the sub-semiconductor chip 114. That is, the ground redistribution conductive layers 118B-G and the power redistribution conductive layers 118B-P may correspond to a power supply path from the substrate 100 to the sub-semiconductor chip 114.

[0067] A capacitor 160 including a first electrode 162, a second electrode 164, and a body portion 166 therebetween may be provided in the sub-molding layer 116. The body portion 166 may have various structures as long as it can store charges according to a voltage applied to the first electrode 162 and the second electrode 164. As an example, the capacitor 160 may be an MLCC (Multilayer Ceramic Capacitor). In this case, the body portion 166 may have a structure in which a plurality of ceramic dielectric layers and a plurality of internal electrodes are alternately stacked.

[0068] The capacitor 160 may be embedded in the sub-molding layer 116 together with the sub-semiconductor chip 114. That is, the side surface and the lower surface of the capacitor 160 may be surrounded by the sub-molding layer 116. On the other hand, the upper surface of the capacitor 160 (specifically, the upper surface of the first electrode 162 and the second electrode 164) may be exposed by being located at substantially the same height as the upper surface of the sub-molding layer 116. The upper surface of the first electrode 162 may be connected to the ground redistribution conductive layer 118B-G, and the upper surface of the second electrode 164 may be connected to the power redistribution conductive layer 118B-P. More specifically, the ground redistribution conductive layer 118B-G and the power redistribution conductive layer 118B-P may be connected to the upper surface of the first electrode 162 and the upper surface of the second electrode 164, respectively, through the opening of the first redistribution insulating layer 118A. On the other hand, the body portion 166 may be insulated from the redistribution conductive layer 118B. For this reason, there may be no opening in the portion of the first redistribution insulating layer 118A corresponding to the body portion 166. For reference, for ease of description, the first electrode 162 of the capacitor 160 is represented by a non-shaded rectangle, and the second electrode 164 of the capacitor 160 is represented by a shaded rectangle. However, the shading is only used to distinguish the first electrode 162 from the second electrode 164. In addition, the planar shapes of the first electrode 162 and the second electrode 164 may also be modified in various ways.

[0069] As described above, the redistribution conductive layer 118B may also be connected to the sub-chip pad 115 through the opening of the first redistribution insulating layer 118A. Therefore, the upper surface of the first electrode 162 and the upper surface of the second electrode 164 may be located at substantially the same height as the upper surface of the sub-chip pad 115. The upper surface of the main body portion 166 may be located at a lower level than the upper surface of the first electrode 162 and / or the second electrode 164, as shown in the figure. In this case, the first redistribution insulating layer 118A and the sub-mold layer 116 may be between the main body portion 166 and the redistribution conductive layer 118B. However, in another embodiment, the upper surface of the main body portion 166 may be located at substantially the same height as the upper surface of the first electrode 162 and / or the second electrode 164.

[0070] The capacitor 160 may be connected to the sub-chip pad 115 that supplies the power supply voltage and the ground voltage to the sub-semiconductor chip 114, and may play a role in preventing power shortages from occurring during the operation of the sub-semiconductor chip 114. When the capacitor 160 is disposed adjacent to the sub-semiconductor chip 114, the power supply path may be shortened to more efficiently perform the function. In the present embodiment, the capacitor 160 may be disposed closer to the sub-chip pad 115 than the redistribution pad 118BP.

[0071] In the present embodiment, four capacitors 160 may be respectively disposed to face four side surfaces of the sub semiconductor chip 114. However, the present disclosure is not limited thereto, and the number and positions of the capacitors 160 may be modified in various ways.

[0072] In addition, one or more signal redistribution conductive layers 118B-S may be disposed between the ground redistribution conductive layer 118B-G and the power redistribution conductive layer 118B-P. The ground redistribution conductive layer 118B-G and the power redistribution conductive layer 118B-P may be used to shield the signal redistribution conductive layer 118B-S therebetween. Therefore, interference between the signal redistribution conductive layer 118B-S disposed between the ground redistribution conductive layer 118B-G and the power redistribution conductive layer 118B-P and another signal redistribution conductive layer 118B-S may be suppressed. For reference, in this case, the main body portion 166 may overlap with one or more signal redistribution conductive layers 118B-S disposed between the ground redistribution conductive layer 118B-G and the power redistribution conductive layer 118B-P.

[0073] According to the above-described semiconductor package, the following effects can be achieved.

[0074] First, since the sub-chip pads 115 are arranged along the entire edge of the sub-semiconductor chip 114, a relatively large number of sub-chip pads 115 can be arranged compared to the size of the sub-semiconductor chip 114. In addition, by redistributing the sub-chip pads 115 using the fan-out technology, the connection between the sub-chip pads 115 and the chip pads 125 and 135 of the main semiconductor chips 124 and 134 can be easily achieved. For example, if the bonding wiring is directly connected to the sub-semiconductor chip 114, the setting of the sub-chip pads 115 may be limited due to physical limitations such as the size and moving radius of the wiring capillary. On the other hand, as in the present embodiment, if the sub-chip pads 115 are redistributed using the redistribution pads 118BP by the fan-out technology, the design can be unaffected by such limitations.

[0075] Furthermore, since the sub-semiconductor package 110 that is larger than the first main semiconductor chip 124 is disposed below the first chip stack 120 by using the fan-out technology, the first chip stack 120 can be stably formed. In a structure in which the first chip stack 120 is formed on the sub-semiconductor chip 114, if the sub-semiconductor chip 114 is smaller than the first main semiconductor chip 124, a problem of tilting the first chip stack 120 may be caused. By substantially increasing the area of ​​the sub-semiconductor chip 114 by using the fan-out technology, such a problem may not be caused.

[0076] In addition, by adjusting the shape and / or arrangement of the redistribution conductive layer 118B connecting the sub-chip pad 115 and the redistribution pad 118BP so that the redistribution conductive layer 118B has a similar length, the operating characteristics of the semiconductor package can be ensured. For example, when there is a first channel connected to the substrate 100 from the first chip stack 120 and a second channel connected to the substrate 100 from the second chip stack 130, the path of the first channel and the path of the second channel can have similar lengths. Therefore, the transmission rate of the signal (e.g., data) can be prevented from becoming different from channel to channel to the greatest extent.

[0077] Furthermore, by disposing the capacitor 160 adjacent to the sub-semiconductor chip 114 in the sub-mold layer 116 , power supply to the sub-semiconductor chip 114 may be assisted even if the pitch and / or line width of the redistribution conductive layer 118B is reduced.

[0078] Furthermore, by placing one or more signal redistribution conductive layers 118B-S between the ground redistribution conductive layer 118B-G and the power redistribution conductive layer 118B-P, interference between the signal redistribution conductive layers 118B-S may be suppressed.

[0079] Furthermore, compared to the case where the capacitor is arranged around the sub-semiconductor package 110, when the capacitor 160 is provided to be connected to the redistribution conductive layer 118B in the sub-semiconductor package 110 as in the present embodiment, the AC path through the capacitor 160 can be shortened. Therefore, the impedance of the power supply path can be further reduced. This will refer to Fig. 7A and Figure 7B Further description.

[0080] Fig. 7A is a diagram for explaining an example of the effect of the semiconductor package according to the embodiment of the present disclosure, and Figure 7B It is a diagram for explaining the effects of the semiconductor package according to the comparative example. Figure 7B A case different from the present embodiment is illustrated in which the capacitor 160 ′ is individually provided around the sub-semiconductor package 110 .

[0081] Reference Fig. 7A Because the capacitor 160 is connected to a certain point of each of the ground redistribution conductive layer 118B-G and the power redistribution conductive layer 118B-P, a short AC path can be formed that passes through a portion of the power redistribution conductive layer 118B-P, the capacitor 160, and a portion of the ground redistribution conductive layer 118B-G (see the dotted arrow).

[0082] On the other hand, referring to Figure 7B, a long AC path (see the dotted arrow) can be formed that passes through the entire power redistribution conductive layer 118-P, the sub-package interconnector 117, the substrate 100, the external connection terminal 140 for providing a power supply voltage, the substrate 100, the capacitor 160′, the substrate 100, the external connection terminal 140 for providing a ground voltage, the substrate 100, the sub-package interconnector 117, and the entire ground redistribution conductive layer 118B-G.

[0083] Results, such as Fig. 7A As shown in the present embodiment, a short AC path passing through the capacitor 160 can be formed, and thus the impedance of the power supply path can be reduced. Therefore, power supply can be easily performed.

[0084] Figure 8 is a cross-sectional view illustrating a semiconductor package according to another embodiment of the present disclosure, Fig. 9 is an example Figure 8 A plan view of a sub-semiconductor package, Fig.10 It is along Fig. 9 A cross-sectional view taken along line A4-A4′, and Fig.11 It is along Fig. 9 A cross-sectional view taken along line A5-A5′. Figure 8 Based on the Figure 1 Hereinafter, differences from the above-described embodiment will be mainly described.

[0085] First, refer to Figures 9 to 11The sub-semiconductor package 210 of the present embodiment may include a sub-semiconductor chip 214, a sub-mold layer 216 surrounding at least the side surface of the sub-semiconductor chip 214, a redistribution structure including a first redistribution insulating layer 218A, a redistribution conductive layer 218B, and a second redistribution insulating layer 218C and formed above the upper surface of the sub-semiconductor chip 214 and the sub-mold layer 216, and a capacitor 260 disposed in the sub-mold layer 216 and including a first electrode 262, a second electrode 264, and a body portion 266 therebetween. The sub-chip pad 215 may be disposed on the upper surface of the sub-semiconductor chip 214. The sub-chip pad 215 may include a signal sub-chip pad 215-S, a ground sub-chip pad 215-G, and a power sub-chip pad 215-P. The redistribution conductive layer 218B may include a signal redistribution conductive layer 218B-S connected to the signal sub-chip pad 215-S, a ground redistribution conductive layer 218-G connected to the ground sub-chip pad 215-G, and a power redistribution conductive layer 218B-P connected to the power sub-chip pad 215-P. The signal redistribution pad 218BP-S may be disposed at an end of the signal redistribution conductive layer 218B-S, the ground redistribution pad 218BP-G may be disposed at an end of the ground redistribution conductive layer 218B-G, and the power redistribution pad 218BP-P may be disposed at an end of the power redistribution conductive layer 218B-P. The ground redistribution conductive layer 218B-G may be connected to the ground sub-chip pad 215-G and the first electrode 262 of the capacitor 260 through the opening of the first redistribution insulating layer 218A. The power redistribution conductive layer 218B-P may be connected to the power sub-die pad 215 -P and the second electrode 264 of the capacitor 260 through the opening of the first redistribution insulating layer 218A.

[0086] Furthermore, the sub semiconductor package 210 may further include sub vias 270 connected to the first electrode 262 and the second electrode 264 of the capacitor 260 , respectively.

[0087] The upper surfaces of the sub-vias 270 may be respectively connected to the lower surfaces of the first and second electrodes 262 and 264. The sub-vias 270 may extend from the lower surfaces of the first and second electrodes 262 and 264 to the lower surface of the sub-mold layer 216 by passing through the sub-mold layer 216. The lower surface of the sub-vias 270 may be exposed by being located at the same height as the lower surface of the sub-mold layer 216.

[0088] The sub-semiconductor package 210 may be electrically connected to the substrate through the interconnector 280 connected to the exposed lower surface of the sub-through hole 270 (see Figure 8200 in). The interconnectors 280 connected to the sub-vias 270 will be referred to as second sub-package interconnectors 280 to distinguish them from the first sub-package interconnectors described later. The second sub-package interconnectors 280 may include conductors having various three-dimensional shapes such as balls and columns, rather than conductors having two-dimensional shapes such as wiring. For example, the second sub-package interconnector 280 may include solder balls or metal bumps. Although not shown, an additional insulating layer may be provided between the lower surface of the sub-molding layer 216 and the second sub-package interconnector 280. An opening may be formed in the additional insulating layer to expose the sub-vias 270 to connect to the second sub-package interconnector 280.

[0089] In the following, reference will be made to Figure 8 The electrical connection between the sub-semiconductor package 210 and the substrate 200 is described in more detail together. Figure 1 The cross section of line A1-A1′ shows Figure 8 , so that the capacitor 260, and the sub-via 270 and the second sub-package interconnector 280 connected thereto are actually invisible. However, for ease of description, one capacitor 260 and the sub-via 270 and the second sub-package interconnector 280 connected thereto are illustrated.

[0090] Reference Figure 8 and Figures 9 to 11 Together, the sub-semiconductor package 210 may be electrically connected to the substrate 200 through the first sub-package interconnector 217 and the second sub-package interconnector 280 .

[0091] The first sub-package interconnector 217 may be substantially the same as the sub-package interconnector 117 of the above-described embodiment. That is, the first sub-package interconnector 217 may connect the redistribution pad 218BP and the substrate 200 to each other, thereby providing electrical connection between the sub-semiconductor chip 214 and the substrate 200. The first sub-package interconnector 217 may be a bonding wire.

[0092] On the other hand, the second sub-package interconnector 280 may be connected to the redistribution conductive layer 218B through the sub-via 270 and each of the first electrode 262 and the second electrode 264 of the capacitor 260. Specifically, the second sub-package interconnector 280 may be connected to a certain point in the redistribution conductive layer 218B except the redistribution pad 218BP. Thus, an electrical connection between the sub-semiconductor chip 214 and the substrate 200 may be provided.

[0093] Because the second sub-package interconnector 280 is interposed between the sub-semiconductor package 210 and the substrate 200, unlike the sub-molding layer 116 of the above-mentioned embodiment, the sub-molding layer 216 can be spaced apart from the substrate 200 by a predetermined distance while not being attached to the substrate 200. The distance can correspond to the height of the second sub-package interconnector 280. The second sub-package interconnector 280 can provide an electrical connection between the sub-semiconductor package 210 and the substrate 200, and can also play a role in supporting the sub-semiconductor package 210. A plurality of second sub-package interconnectors 280 can be disposed to overlap each of the first electrode 262 and the second electrode 264 of the capacitor 260. Because the first electrode 262 and the second electrode 264 of the capacitor 260 are disposed along the periphery of the sub-semiconductor chip 214, the second sub-package interconnector 280 can fully support the sub-semiconductor package 210. In addition, one or more dummy second sub-package interconnectors 281 that are not connected to the sub-through hole 270 can be additionally disposed above the lower surface of the sub-molding layer 216. The dummy second sub-package interconnector 281 may prevent the sub-semiconductor package 210 from tilting in a direction or may withstand pressure generated when the first chip stack 220 and the second chip stack 230 are mounted over the sub-semiconductor package 210 .

[0094] Figure 8 A first chip stack 220 and a second chip stack 230 may also be included that are disposed above the sub-semiconductor package 210. The first chip stack 220 may include a plurality of first main semiconductor chips 224 and a first adhesive layer 222 for attaching each first main semiconductor chip 224 to a structure below it. The first main semiconductor chips 224 may be stacked offset in a first offset direction so that a first chip pad 225 disposed on an upper surface of each first main semiconductor chip 224 is exposed. The first chip stack 220 may be electrically connected to the substrate 200 through a first interconnector 227. The second chip stack 230 includes a plurality of second main semiconductor chips 234 and a second adhesive layer 232 for attaching each second main semiconductor chip 234 to a structure below it. The second main semiconductor chips 234 may be stacked offset in a second offset direction so that a second chip pad 235 disposed on an upper surface of each second main semiconductor chip 234 is exposed. The second chip stack 230 may be electrically connected to the substrate 200 through a second interconnector 237. The first chip laminate 220 and the second chip laminate 230 may be covered with a mold layer 250. External connection terminals 240 may be disposed over a lower surface of the substrate 200.

[0095] According to the semiconductor package of the present embodiment, all the advantages of the semiconductor package of the above-described embodiment can be obtained.

[0096] Furthermore, as in the present embodiment, when a sub-via 270 connected to each of the first electrode 262 and the second electrode 264 of the capacitor 260 is provided in the sub-semiconductor package 210, and a second sub-package interconnector 280 connecting the sub-semiconductor package 210 and the substrate 200 is provided, the DC path between the sub-semiconductor package 210 and the substrate 200 can be shortened, thereby reducing the impedance of the power supply path. Furthermore, a plurality of DC paths can be formed, so that the inductance of the power supply path can be reduced. As a result, power supply between the sub-semiconductor package 210 and the substrate 200 can be made easier. This will be referred to Fig. 12A and Fig. 12B Further description.

[0097] Fig. 12A is a diagram for explaining an example of the effect of a semiconductor package according to another embodiment of the present disclosure; and Fig. 12B 1 is a diagram for explaining the effect of a semiconductor package according to a comparative example. Fig. 12B A case where there are no capacitors and sub-vias is illustrated.

[0098] Reference Fig. 12A A relatively long DC path (see dashed arrow ①) can be formed through the redistribution conductive layer 218B, the first sub-package interconnector 217, and the substrate 200. In addition, a relatively short DC path (see dashed arrow ②) can be formed through a portion of the redistribution conductive layer 218B, the capacitor 260, the sub-via 270, the second sub-package interconnector 280, and the substrate 200.

[0099] That is, a short DC path can be obtained as shown by the dashed arrow ②, and a plurality of DC paths can be formed as shown by the dashed arrows ① and ②.

[0100] On the other hand, referring to Fig. 12B , in the comparative example, only a relatively long direct current path (see the dotted arrow) passing through the redistribution conductive layer 218B′, the first sub-package interconnector 217 ′, and the substrate 200 ′ may be formed.

[0101] Results, such as Fig. 12A According to the present embodiment, a short DC path and a plurality of DC paths can be formed, thereby reducing the impedance and inductance of the power supply path. Therefore, power supply can be easily performed.

[0102] Fig.13 is a cross-sectional view illustrating a semiconductor package according to another embodiment of the present disclosure, Fig.14 is a plan view illustrating a sub-semiconductor package of a semiconductor package according to another embodiment of the present disclosure, Fig.15 It is along Fig.14 A cross-sectional view taken along line A6-A6′, and Fig.16 It is along Fig.14 Hereinafter, differences from the above-described embodiment will be mainly described.

[0103] First, refer to Figures 14 to 16 , similar to the above-mentioned embodiment, the sub-semiconductor package 310 of the present embodiment may include a sub-semiconductor chip 314, a sub-mold layer 316 surrounding at least the side surface of the sub-semiconductor chip 314, a redistribution structure including a first redistribution insulating layer 318A, a redistribution conductive layer 318B, and a second redistribution insulating layer 318C and formed above the upper surface of the sub-semiconductor chip 314 and the sub-mold layer 316, and a capacitor 360 disposed in the sub-mold layer 316 and including a first electrode 362, a second electrode 364, and a body portion (not shown) therebetween. The sub-chip pad 315 may be disposed on the upper surface of the sub-semiconductor chip 314. The sub-chip pad 315 may include a signal sub-chip pad 315-S, a ground sub-chip pad 315-G, and a power sub-chip pad 315-P. The redistribution conductive layer 318B may include a signal redistribution conductive layer 318B-S connected to the signal sub-chip pad 315-S, a ground redistribution conductive layer 318B-G connected to the ground sub-chip pad 315-G, and a power redistribution conductive layer 318B-P connected to the power sub-chip pad 315-P. The signal redistribution pad 318BP-S may be disposed at an end of the signal redistribution conductive layer 318B-S, the ground redistribution pad 318BP-G may be disposed at an end of the ground redistribution conductive layer 318B-G, and the power redistribution pad 318BP-P may be disposed at an end of the power redistribution conductive layer 318B-P. The ground redistribution conductive layer 318B-G may be connected to the ground sub-chip pad 315-G and the first electrode 362 of the capacitor 360 through the opening of the first redistribution insulating layer 318A. The power redistribution conductive layer 318B-P may be connected to the power sub-die pad 315 -P and the second electrode 364 of the capacitor 360 through the opening of the first redistribution insulating layer 318A.

[0104] Furthermore, the sub semiconductor package 310 may further include sub vias 370 connected to the ground redistribution conductive layers 318B-G and the power redistribution conductive layers 318B-P, respectively.

[0105] The sub-via 370 may be formed to be spaced apart from each of the first electrode 362 and the second electrode 364 of the capacitor 360. However, as described later, the sub-via 370 may also be disposed closer to the sub-chip pad 315 than the redistribution pad 318BP to shorten the DC path. In addition, the sub-via 370 may be located between the first electrode 362 and the ground redistribution pad 318BP-G and between the second electrode 364 and the power redistribution pad 318BP-P.

[0106] The sub-via 370 may be formed to penetrate the sub-mold layer 316 and extend from the upper surface to the lower surface of the sub-mold layer 316. That is, the upper surface of the sub-via 370 may be exposed by being located at substantially the same height as the upper surface of the sub-mold layer 316, and the lower surface of the sub-via 370 may be exposed by being located at substantially the same height as the lower surface of the sub-mold layer 316. Each of the ground redistribution conductive layers 318B-G and the power redistribution conductive layers 318B-P may be connected to the upper surface of the sub-via 370 through the opening in the first redistribution insulating layer 318A.

[0107] The sub-semiconductor package 310 may be electrically connected to the substrate through a second sub-package interconnector 380 connected to the lower surface of the sub-via 370 (see Fig.13 300). The second sub-package interconnector 380 may include conductors having various three-dimensional shapes (such as balls and pillars) rather than two-dimensional shapes (such as wiring). For example, the second sub-package interconnector 380 may include solder balls or metal bumps. Although not shown, an additional insulating layer may be provided between the lower surface of the sub-molding layer 316 and the second sub-package interconnector 380. An opening may be formed in the additional insulating layer to expose the sub-via 370 to connect to the second sub-package interconnector 380.

[0108] In the following, reference will be made to Fig.13 The electrical connection between the sub-semiconductor package 310 and the substrate 300 is described in more detail together. Figure 1 The cross section of line A1-A1′ shows Fig.13 , so that the capacitor 360, the sub-via 370 and the second sub-package interconnector 380 are actually invisible. However, for the convenience of description, one capacitor 360 and the sub-via 370 and the second sub-package interconnector 380 near the one capacitor 360 are illustrated.

[0109] Reference Fig.13 and Figures 14 to 16 Together, the sub-semiconductor package 310 may be electrically connected to the substrate 300 through the first sub-package interconnector 317 and the second sub-package interconnector 380 .

[0110] The first sub-package interconnector 317 may be substantially the same as the first sub-package interconnector 217 of the above-described embodiment. That is, the first sub-package interconnector 317 may provide electrical connection between the sub-semiconductor chip 314 and the substrate 300 by connecting the redistribution pad 318BP and the substrate 300 to each other. The first sub-package interconnector 317 may be a bonding wire.

[0111] On the other hand, the second sub-package interconnector 380 may be connected to the redistribution conductive layer 318B through the sub-via 370. Specifically, the second sub-package interconnector 380 may be connected to a point in the redistribution conductive layer 318B other than the redistribution pad 318BP. Thus, an electrical connection between the sub-semiconductor chip 314 and the substrate 300 may be provided.

[0112] Because the second sub-package interconnector 380 is interposed between the sub-semiconductor package 310 and the substrate 300, the sub-molding layer 316 may not be attached to the substrate 300 and may be spaced apart from the substrate 300 by a predetermined distance. The distance may correspond to the height of the second sub-package interconnector 380. The second sub-package interconnector 380 provides an electrical connection between the sub-semiconductor package 310 and the substrate 300, and may also support the sub-semiconductor package 310. A plurality of second sub-package interconnectors 380 may be disposed adjacent to the first electrode 362 and the second electrode 364 of the capacitor 360, respectively. That is, because the second sub-package interconnectors 380 are disposed along the periphery of the sub-semiconductor chip 314, the second sub-package interconnectors 380 may fully support the sub-semiconductor package 310. A dummy second sub-package interconnector 381 that is not connected to the sub-through hole 370 may be additionally disposed above the lower surface of the sub-molding layer 316. The dummy second sub-package interconnector 381 may prevent the sub-semiconductor package 310 from tilting in one direction or may withstand pressure generated when the first chip stack 320 and the second chip stack 330 are mounted over the sub-semiconductor package 310 .

[0113] Fig.13A first chip stack 320 and a second chip stack 330 may also be included that are disposed above the sub-semiconductor package 310. The first chip stack 320 may include a plurality of first main semiconductor chips 324 and a first adhesive layer 322 for attaching the first main semiconductor chips 324 to a structure below the first chip stack. The first main semiconductor chips 324 may be offset stacked in a first offset direction so that a first chip pad 325 disposed on the upper surface of each first main semiconductor chip 324 is exposed. The first chip stack 320 may be electrically connected to the substrate 300 through a first interconnector 327. The second chip stack 330 includes a plurality of second main semiconductor chips 334 and a second adhesive layer 332 for attaching each second main semiconductor chip 334 to a structure below the second chip stack. The second main semiconductor chips 334 may be offset stacked in a second offset direction so that a second chip pad 335 disposed on the upper surface of each second main semiconductor chip 334 is exposed. The second chip stack 330 may be electrically connected to the substrate 300 through a second interconnector 337. The first chip laminate 320 and the second chip laminate 330 may be covered with a mold layer 350. External connection terminals 340 may be disposed over a lower surface of the substrate 300.

[0114] According to the semiconductor package of the present embodiment, all the advantages of the semiconductor package of the above-described embodiment can be obtained.

[0115] Specifically, compared to a case where there is no sub-via in the sub-semiconductor package 310, when a sub-via 370 connected to each of the ground redistribution conductive layer 318B-G and the power redistribution conductive layer 318B-P is provided in the sub-semiconductor package 310, and a second sub-package interconnector 380 connecting the sub-via 370 and the substrate 300 is provided, the DC path between the sub-semiconductor package 310 and the substrate 300 can be shortened, thereby reducing the power supply path of the power supply. In addition, multiple DC paths can be formed, thereby reducing the inductance of the power supply path. As a result, power can be supplied more easily between the sub-semiconductor package 310 and the substrate 300. This will refer to Fig.17A and Fig. 17B Further description.

[0116] Fig.17A is a diagram for explaining an example of the effect of a semiconductor package according to another embodiment of the present disclosure, and Fig. 17B 1 is a diagram for explaining the effect of a semiconductor package of a comparative example. Fig. 17B A case where no sub through-hole exists in the sub semiconductor package 310 is shown.

[0117] Reference Fig.17A, a relatively long DC path (see dashed arrow ①) can be formed through the redistribution conductive layer 318B, the first sub-package interconnector 317, and the substrate 300. In addition, a relatively short DC path (see dashed arrow ②) can be formed through a portion of the redistribution conductive layer 318B, the sub-via 370, the second sub-package interconnector 380, and the substrate 300.

[0118] That is, a short direct current path can be obtained as shown by the dotted arrow ②, and further, a plurality of direct current paths can be formed as shown by the dotted arrows ① and ②.

[0119] On the other hand, refer to Fig. 17B , in the comparative example, only a relatively long direct current path (see the dotted arrow) is formed passing through the redistribution conductive layer 318B′, the first sub-package interconnector 317 ′, and the substrate 300 ′.

[0120] Results, such as Fig.17A According to the present embodiment, a short DC path and a plurality of DC paths can be formed, thereby reducing the impedance and inductance of the power supply path. Therefore, power supply can be easily performed.

[0121] According to the embodiments of the present disclosure, a high-capacity and multifunctional semiconductor package can be realized by forming a chip stack including one or more main semiconductor chips over a sub-semiconductor package. In addition, power supply in a semiconductor package can be assisted by providing a capacitor in the sub-semiconductor package.

[0122] Fig.18 A block diagram of an exemplary electronic system is shown, which includes a memory card 7800 employing at least one of the semiconductor packages according to the embodiments. The memory card 7800 includes a memory 7810 such as a nonvolatile memory device and a memory controller 7820. The memory 7810 and the memory controller 7820 can store data or read out the stored data. At least one of the memory 7810 and the memory controller 7820 can include at least one of the semiconductor packages according to the described embodiments.

[0123] The memory 7810 may include a nonvolatile memory device to which the technology of the embodiments of the present disclosure is applied. The memory controller 7820 may control the memory 7810 so that stored data is read out or data is stored in response to a read / write request from the host 7830 .

[0124] Fig.19A block diagram of an exemplary electronic system 8710 is shown, which includes at least one of the semiconductor packages according to the described embodiments. The electronic system 8710 may include a controller 8711, an input / output device 8712, and a memory 8713. The controller 8711, the input / output device 8712, and the memory 8713 may be connected to each other through a bus 8715 that provides a data movement path.

[0125] In an embodiment, the controller 8711 may include one or more microprocessors, digital signal processors, microcontrollers and / or logic devices capable of performing the same functions as these components. The controller 8711 or the memory 8713 may include one or more semiconductor packages according to an embodiment of the present disclosure. The input / output device 8712 may include at least one selected from a keypad, a keyboard, a display device, a touch screen, etc. The memory 8713 is a device for storing data. The memory 8713 may store commands and / or data to be executed by the controller 8711, etc.

[0126] The memory 8713 may include a volatile memory device such as a DRAM and / or a non-volatile memory device such as a flash memory. For example, the flash memory may be installed in an information processing system such as a mobile terminal or a desktop computer. The flash memory may constitute a solid state disk (SSD). In this case, the electronic system 8710 may stably store a large amount of data in the flash memory system.

[0127] The electronic system 8710 may also include an interface 8714 configured to send data to and receive data from a communication network. The interface 8714 may be of a wired or wireless type. For example, the interface 8714 may include an antenna or a wired or wireless transceiver.

[0128] The electronic system 8710 may be implemented as a mobile system, a personal computer, an industrial computer, or a logic system that performs various functions. For example, the mobile system may be any one of a personal digital assistant (PDA), a portable computer, a tablet computer, a mobile phone, a smart phone, a wireless phone, a laptop computer, a memory card, a digital music system, and an information transmission / reception system.

[0129] If electronic system 8710 represents equipment capable of performing wireless communications, electronic system 8710 can be used in a communication system using technology such as CDMA (Code Division Multiple Access), GSM (Global System for Mobile Communications), NADC (North American Digital Cellular), E-TDMA (Enhanced Time Division Multiple Access), WCDMA (Wideband Code Division Multiple Access), CDMA2000, LTE (Long Term Evolution), or Wibro (Wireless Broadband Internet).

[0130] Although various embodiments have been described for illustrative purposes, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the present teachings as defined by the following claims.

[0131] CROSS-REFERENCE TO RELATED APPLICATIONS

[0132] This application claims priority from Korean Patent Application No. 10-2020-0061540, filed on May 22, 2020, which is hereby incorporated by reference in its entirety.

Claims

1. A semiconductor package, comprising: substrate; A sub-semiconductor package, the sub-semiconductor package is arranged above the substrate, the sub-semiconductor package comprises: a sub-semiconductor chip, the upper surface of the sub-semiconductor chip having a chip pad; a molding layer, the molding layer surrounding the side surface of the sub-semiconductor chip; and a redistribution layer, the redistribution layer is formed above the sub-semiconductor chip and the molding layer, the redistribution layer comprises a redistribution conductive layer, the redistribution conductive layer is connected to the chip pad of the sub-semiconductor chip and extends to the edge of the molding layer, and has a redistribution pad at the end of the redistribution conductive layer; a first sub-package interconnector connected to the redistribution pad to electrically connect the sub-semiconductor chip and the substrate; a capacitor formed in the mold layer and including a first electrode, a second electrode, and a body portion between the first electrode and the second electrode, the first electrode and the second electrode having upper surfaces respectively connected to the redistribution conductive layer; and at least one main semiconductor chip formed over the sub-semiconductor package and electrically connected to the substrate, wherein the sub-semiconductor package further includes a sub-through hole that penetrates the molding layer while being connected to a lower surface of each of the first electrode and the second electrode, and Wherein, the semiconductor package further comprises: A second sub-package interconnector is disposed between the mold layer and the substrate, the second sub-package interconnector being connected to the sub-via.

2. The semiconductor package according to claim 1, wherein: The redistribution conductive layer includes a ground redistribution conductive layer to which a ground voltage is applied and a power redistribution conductive layer to which a power voltage is applied, and Wherein, the first electrode is connected to the ground redistribution conductive layer, and the second electrode is connected to the power redistribution conductive layer.

3. The semiconductor package according to claim 2, wherein: The redistribution conductive layer further includes at least one signal redistribution conductive layer, and the at least one signal redistribution conductive layer is located between the ground redistribution conductive layer and the power redistribution conductive layer.

4. The semiconductor package according to claim 3, wherein: The body portion overlaps the at least one signal redistribution conductive layer.

5. The semiconductor package according to claim 2, wherein: Each of the first electrode and the second electrode is disposed closer to the chip pad than the redistribution pad.

6. The semiconductor package according to claim 1, wherein: The redistribution layer further includes a redistribution insulating layer formed between the redistribution conductive layer and upper surfaces of the sub-semiconductor chip and the molding layer, and The redistribution conductive layer is connected to the chip pad, the first electrode and the second electrode through an opening formed in the redistribution insulating layer.

7. The semiconductor package according to claim 1, wherein: The first sub-package interconnect includes a bonding wire, and Wherein, the second sub-package interconnector includes at least one of a solder ball and a conductive bump.

8. The semiconductor package according to claim 1, further comprising: A dummy second sub-package interconnector is disposed between the molding layer and the substrate without being connected to the sub-via.

9. The semiconductor package according to claim 1, wherein: a first DC path passes through the redistribution conductive layer, the first sub-package interconnector, and the substrate, and Wherein, the second DC path passes through the redistribution conductive layer, the first electrode or the second electrode, the sub-via, the second sub-package interconnector and the substrate.

10. The semiconductor package according to claim 1, wherein The at least one master semiconductor chip includes a memory, and The sub-semiconductor chip includes a memory controller.

11. A semiconductor package, comprising: substrate; A sub-semiconductor package, the sub-semiconductor package is arranged above the substrate, the sub-semiconductor package comprises: a sub-semiconductor chip, the upper surface of the sub-semiconductor chip having a chip pad; a molding layer, the molding layer surrounding the side surface of the sub-semiconductor chip; and a redistribution layer, the redistribution layer is formed above the sub-semiconductor chip and the molding layer, the redistribution layer comprises a redistribution conductive layer, the redistribution conductive layer is connected to the chip pad of the sub-semiconductor chip and extends to the edge of the molding layer, and has a redistribution pad at the end of the redistribution conductive layer; a first sub-package interconnector connected to the redistribution pad to electrically connect the sub-semiconductor chip and the substrate; a capacitor formed in the mold layer and including a first electrode, a second electrode, and a body portion between the first electrode and the second electrode, the first electrode and the second electrode having upper surfaces respectively connected to the redistribution conductive layer; and at least one main semiconductor chip formed over the sub-semiconductor package and electrically connected to the substrate, The sub-semiconductor package further includes a sub-through hole, which penetrates the molding layer and has an upper surface connected to the redistribution conductive layer. Wherein, the semiconductor package further comprises: a second sub-package interconnector, the second sub-package interconnector being disposed between the molding layer and the substrate, the second sub-package interconnector being connected to the sub-via, wherein a first DC path passes through the redistribution conductive layer, the first sub-package interconnector and the substrate, and Wherein, a second DC path passes through the redistribution conductive layer, the sub-via, the second sub-package interconnector and the substrate.

12. The semiconductor package according to claim 11, wherein The sub-via is connected to the redistribution conductive layer connected to the first electrode while being spaced apart from the first electrode, and The sub-via is connected to the redistribution conductive layer connected to the second electrode and is spaced apart from the second electrode.

13. The semiconductor package according to claim 11, wherein: The sub-via is disposed between the first electrode and the redistribution pad or between the second electrode and the redistribution pad.

14. The semiconductor package according to claim 11, wherein The first sub-package interconnect includes a bonding wire, and Wherein, the second sub-package interconnector includes at least one of a solder ball and a conductive bump.

15. The semiconductor package according to claim 11, further comprising: A dummy second sub-package interconnector is disposed between the molding layer and the substrate without being connected to the sub-via.

16. The semiconductor package according to claim 11, wherein Each of the first electrode and the second electrode is disposed closer to the chip pad than the redistribution pad.

17. The semiconductor package according to claim 11, wherein: The redistribution layer further includes a redistribution insulating layer formed between the redistribution conductive layer and upper surfaces of the sub-semiconductor chip and the molding layer, and The redistribution conductive layer is connected to the chip pad, the first electrode and the second electrode through an opening formed in the redistribution insulating layer.

18. The semiconductor package according to claim 11, wherein The at least one master semiconductor chip includes a memory, and The sub-semiconductor chip includes a memory controller.

19. A semiconductor package, comprising: substrate; A sub-semiconductor package, the sub-semiconductor package is arranged above the substrate, the sub-semiconductor package comprises: a sub-semiconductor chip, the upper surface of the sub-semiconductor chip having a chip pad; a molding layer, the molding layer surrounding the side surface of the sub-semiconductor chip; and a redistribution layer, the redistribution layer is formed above the sub-semiconductor chip and the molding layer, the redistribution layer comprises a redistribution conductive layer, the redistribution conductive layer is connected to the chip pad of the sub-semiconductor chip and extends to the edge of the molding layer, and has a redistribution pad at the end of the redistribution conductive layer; a first sub-package interconnector connected to the redistribution pad to electrically connect the sub-semiconductor chip and the substrate; a capacitor formed in the mold layer and including a first electrode, a second electrode, and a body portion between the first electrode and the second electrode, the first electrode and the second electrode having upper surfaces respectively connected to the redistribution conductive layer; and at least one main semiconductor chip formed over the sub-semiconductor package and electrically connected to the substrate, wherein the substrate comprises a substrate pad disposed at each of a first side edge and a second side edge of the substrate in a first direction, and Wherein, the at least one main semiconductor chip comprises: at least one first master semiconductor chip connected to the substrate pad disposed at the first side edge of the substrate through a first interconnector; and At least one second master semiconductor chip is connected to the substrate pad disposed at the second side edge of the substrate through a second interconnector.

20. The semiconductor package according to claim 19, wherein The at least one first main semiconductor chip includes a plurality of first main semiconductor chips stacked offset from a first side toward a second side in the first direction, and The at least one second main semiconductor chip includes a plurality of second main semiconductor chips stacked offset from the second side toward the first side in the first direction.

21. The semiconductor package according to claim 19, wherein The redistribution pad is disposed at each of a first side edge and a second side edge of the molding layer in the first direction, and Among them, the first sub-package interconnector connects the redistribution pad arranged at the first side edge of the molding layer and the substrate pad arranged at the first side edge of the substrate, and connects the redistribution pad arranged at the second side edge of the molding layer and the substrate pad arranged at the second side edge of the substrate.

22. The semiconductor package according to claim 21, wherein The chip pads of the sub-semiconductor chip are arranged along a first side edge and a second side edge of the sub-semiconductor chip in the first direction, and along a first side edge and a second side edge of the sub-semiconductor chip in a second direction perpendicular to the first direction.

23. The semiconductor package according to claim 22, wherein: The chip pads disposed at first side edges of the sub-semiconductor chip in the first direction and the second direction extend toward the redistribution pads disposed at first side edges of the molding layer in the first direction, and The chip pads disposed at the second side edges of the sub-semiconductor chip in the first direction and the second direction extend toward the redistribution pads disposed at the second side edge of the molding layer in the first direction.

24. The semiconductor package according to claim 19, wherein Each of the first electrode and the second electrode is disposed closer to the chip pad than the redistribution pad.

25. The semiconductor package according to claim 19, wherein The redistribution layer further includes a redistribution insulating layer formed between the redistribution conductive layer and upper surfaces of the sub-semiconductor chip and the molding layer, and The redistribution conductive layer is connected to the chip pad, the first electrode and the second electrode through an opening formed in the redistribution insulating layer.

26. The semiconductor package according to claim 19, wherein The at least one master semiconductor chip includes a memory, and The sub-semiconductor chip includes a memory controller.

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