A light detector comprising a reflector having an air gap adjacent to a light detection region

Abstract

The present invention relates to a photodetector including a reflector having an air gap adjacent to a photodetection region. The photodetector includes a photodetection region in a semiconductor substrate and a reflector in the semiconductor substrate extending at least partially along a sidewall of the photodetection region. The reflector includes an air gap defined in the semiconductor substrate. The reflector allows the use of thinner germanium for the photodetection region. The air gap may have various internal features to direct electromagnetic radiation toward the photodetection region.

Description

Technical Field

[0001] The present disclosure relates to light detectors, and more particularly, to light detectors including a reflector including an air gap adjacent to a light detection region. Background Art

[0002] A photodetector (also called a photosensor) senses electromagnetic radiation, such as light, and converts the radiation into an electronic signal. A photodetector may include a pn or pin junction that converts photons into an electric current. A photodetector may include, for example, a photodiode and a phototransistor, among other structures.

[0003] Germanium is commonly used as a light detecting material in semiconductor photodetectors because it absorbs electromagnetic radiation very well compared to other materials. One challenge of using germanium in photodetectors is that the light detecting region must have a thickness greater than 1 micron in order to absorb longer wavelength electromagnetic radiation, e.g., >1 micron. However, forming germanium at such a thickness can be expensive and time consuming. A light detecting region with a larger area can be used, but it uses more area than expected. Other methods to avoid using thicker germanium include using: metal mirrors, oxide-filled trenches, or waveguides underneath the light detector region to guide the electromagnetic radiation to the smaller germanium layer. In one approach, a germanium-tin alloy is used for the light detecting region. The problem with the aforementioned methods is that they cannot be integrated with complementary metal oxide semiconductor (CMOS) or bipolar CMOS (bi-CMOS) devices. Summary of the invention

[0004] Aspects of the present disclosure provide a photodetector including: a photodetection region in a semiconductor substrate; and a reflector in the semiconductor substrate extending at least partially along a sidewall of the photodetection region, the reflector including an air gap defined in the semiconductor substrate.

[0005] Other aspects of the present disclosure provide a method including: forming a light detection region in a semiconductor substrate; and forming a reflector in the semiconductor substrate extending at least partially along a sidewall of the light detection region, the reflector including an air gap defined in the semiconductor substrate.

[0006] The foregoing and other features of the disclosure will be apparent from the following more particular description of embodiments of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Embodiments of the present disclosure will be described in detail with reference to the following drawings, wherein like reference numerals represent like elements, and wherein:

[0008] Figure 1 A cross-sectional view of a light detector including a reflector with an air gap is shown according to an embodiment of the present disclosure.

[0009] Figure 2 A cross-sectional view of a light detector including a reflector with an air gap according to other embodiments of the present disclosure is shown.

[0010] Figure 3 A cross-sectional view of forming an optical semiconductor material according to an embodiment of the method of the present disclosure is shown.

[0011] Figure 4 A cross-sectional view showing the formation of an opening adjacent to an optical semiconductor material according to an embodiment of a method of the present disclosure is shown.

[0012] Figure 5 A cross-sectional view of sealing an opening adjacent to an optical semiconductor material to form a reflector having an air gap and a light detector including the reflector is shown according to an embodiment of a method of the present disclosure.

[0013] Figure 6 A plan view of a light detector including a reflector with an air gap is shown according to an embodiment of the present disclosure.

[0014] Figure 7 A plan view of a light detector including a reflector with an air gap according to other embodiments of the present disclosure is shown.

[0015] Figure 8 A cross-sectional view of a light detector including a reflector with an air gap is shown according to an embodiment of the present disclosure.

[0016] Fig. 9 A cross-sectional view of a light detector including a reflector with an air gap according to other embodiments of the present disclosure is shown.

[0017] Fig.10 A cross-sectional view of a light detector including a reflector with an air gap is shown according to an embodiment of the present disclosure.

[0018] Fig.11 A cross-sectional view of a light detector including a reflector with an air gap according to other embodiments of the present disclosure is shown.

[0019] Fig.12 A cross-sectional view of initially forming an opening adjacent to a light detection region is shown according to an embodiment of a method of the present disclosure.

[0020] Fig.13 A cross-sectional view showing forming an opening adjacent to a light detection region according to an embodiment of a method of the present disclosure is shown.

[0021] Fig.14 A cross-sectional view showing sealing an opening adjacent to a light detection region to form a reflector having an air gap and a light detector including the reflector according to an embodiment of a method of the present disclosure.

[0022] Fig.15 A plan view of a light detector including a reflector with an air gap according to an embodiment of the present disclosure is shown.

[0023] Fig.16 A cross-sectional view showing the formation of an opening in a semiconductor substrate according to an embodiment of the method of the present disclosure is shown.

[0024] Fig.17 A cross-sectional view of sealing an opening to form a reflector with an air gap is shown according to an embodiment of the method of the present disclosure.

[0025] Fig.18 A cross-sectional view showing forming an opening for a light detection region adjacent to a reflector according to an embodiment of a method of the present disclosure is shown.

[0026] Fig.19 A cross-sectional view showing forming a light detection region adjacent to a reflector to form a light detector according to an embodiment of a method of the present disclosure.

[0027] Fig. 20 A cross-sectional view illustrating an optional step of forming a liner in an opening adjacent to a light detection region according to an embodiment of a method of the present disclosure.

[0028] Fig.21 A plan view of a light detector including a reflector with an air gap is shown according to an alternative embodiment of the present disclosure.

[0029] Fig. 22 A plan view of a light detector including a reflector with an air gap according to other alternative embodiments of the present disclosure is shown.

[0030] Fig.23 A cross-sectional view of a light detector including a reflector with an air gap is shown according to an alternative embodiment of the present disclosure.

[0031] Fig.24 A cross-sectional view of a light detector including a reflector with an air gap according to other alternative embodiments of the present disclosure is shown.

[0032] It should be noted that the drawings of the present disclosure are not necessarily drawn to scale. The drawings are intended to depict only typical aspects of the present disclosure and therefore should not be considered to limit the scope of the present disclosure. In the drawings, like reference numerals represent like elements between the drawings. DETAILED DESCRIPTION

[0033] In the following description, reference is made to the accompanying drawings which form a part of the present invention, and in which specific exemplary embodiments in which the present teachings may be practiced are shown by way of illustration. The description of these embodiments is detailed enough to enable those skilled in the art to practice the present teachings, and it should be understood that other embodiments may be used and may be modified without departing from the scope of the present teachings. Therefore, the following description is illustrative only.

[0034] It will be understood that when an element such as a layer, region, or substrate is referred to as being "on" or "above" another element, it may be directly on the other element or there may be intervening elements. Conversely, when an element is referred to as being "directly on" or "directly above" another element, there are no intervening elements. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element or there may be intervening elements. Conversely, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements.

[0035] References in the specification to "one embodiment" or "an embodiment" of the present disclosure and other variations thereof mean that the specific features, structures, characteristics, etc. described in conjunction with the embodiment are included in at least one embodiment of the present disclosure. Therefore, the phrases "in one embodiment" or "in an embodiment" and any other variations appearing throughout the specification do not necessarily refer to the same embodiment. It should be understood that, for example, the use of any of " / ", "and / or", and "at least one of" in the case of "A / B", "A and / or B", and "at least one of A and B" is intended to include selecting only the first listed option (a), or only the second listed option (B), or both options (A and B) at the same time. As other examples, in the case of "A, B, and / or C" and "at least one of A, B, and C," these phrases are intended to include selecting only the first listed option (A), or only the second listed option (B), or only the third listed option (C), or only the first and second listed options (A and B), or only the first and third listed options (A and C), or only the second and third listed options (B and C), or all three options (A, B, and C). As will be apparent to one of ordinary skill in the art, this scenario can be extended to many of the items listed.

[0036] Figure 1 and Figure 21 shows a cross-sectional view of a photodetector 100 according to various embodiments of the present disclosure. The photodetector 100 includes a photodetection region 102 in a semiconductor substrate 104. The semiconductor substrate 104 may include any now known or later developed form of a semiconductor substrate for creating an active region of a transistor device. For example, the substrate 124 may include a bulk substrate, a fin, a nanowire, etc. For purposes of description, the substrate 124 may be a semiconductor fin. The substrate 124 may include, but is not limited to, silicon, germanium, silicon germanium, silicon carbide, and a semiconductor material consisting essentially of one or more semiconductor materials having a chemical formula of Al X1 Ga X2 In X3 As Y1 P Y2 N Y3 Sb Y4 A material composed of a III-V compound semiconductor of a defined composition, wherein X1, X2, X3, Y1, Y2, Y3 and Y4 represent relative proportions, each of which is greater than or equal to zero and X1+X2+X3+Y1+Y2+Y3+Y4=1 (1 is the total relative molar amount). Other suitable substrates include those having a composition of Zn A1 Cd A2 Se B1 Te B2 II-VI compound semiconductors, where A1, A2, B1 and B2 are relative proportions, each of which is greater than or equal to zero and A1+A2+B1+B2=1 (1 is the total molar amount). The semiconductor substrate 104 can be an n-type semiconductor, that is, a semiconductor material listed above and doped with an n-type dopant. The n-type dopant is introduced into the semiconductor to generate free electrons (by "donating" electrons to the semiconductor) and has more valence electrons than the semiconductor. Common n-type dopants in semiconductors such as silicon include: phosphorus (P), arsenic (As) or antimony (Sb).

[0037] The light detection region 102 can be any light absorbing or optical semiconductor material, such as, but not limited to, germanium, silicon, gallium arsenide, gallium nitride, gallium phosphide, indium gallium arsenide, indium arsenic antimonide, or mercury cadmium telluride. The optical semiconductor material is typically selected for its ability to absorb electromagnetic radiation (e.g., light of a target wavelength). The optical semiconductor material can be an intrinsic form of the semiconductor material used, i.e., without dopants therein. The light detection region 102 can be a vertically oriented structure, such as a fin, or can be more three-dimensional, such as a cube, cylinder, etc.

[0038] The light detection region 102 may take the form of a pair of different photodiode formats. For example, Figure 1 , 810 shows a light detection region 102 arranged to create an avalanche photodiode (APD) 106. In this case, the light detection region 102 includes an optical semiconductor material 110, such as intrinsic germanium, in a p-type semiconductor liner layer 112 in an n-type semiconductor substrate 104, and a p-type semiconductor layer 116 located above the optical semiconductor material 110. In contrast, Figure 2 , 9 11 shows a light detection region 102 arranged to create a PIN photodiode 118. In this case, the light detection region 102 includes an optical semiconductor material 120, such as intrinsic germanium, in an n-type semiconductor substrate 104, and has a p-type semiconductor layer 122 above the optical semiconductor material 120. Figure 2 , 9 In FIGS. 1 and 11 , the p-type semiconductor liner 112 is omitted.

[0039] According to an embodiment of the present disclosure, the photodetector 100 includes a reflector 140 extending at least partially along a sidewall 142 of a photodetection region 102 in a semiconductor substrate 104. Incident electromagnetic radiation 146 is reflected by the reflector 140 toward the sidewall 142 of the photodetection region 102 to allow absorption of the electromagnetic radiation, such as light. As will be described, although the reflector 140 is oriented parallel to the path of the incident electromagnetic radiation 146, the reflector 140 is configured to direct the electromagnetic radiation 146 toward the sidewall 142 of the photodetection region 102. Depending on the horizontal cross-sectional shape of the photodetection region 102, the reflector 140 can be positioned in any position and in any number to provide the desired redirection of the electromagnetic radiation toward the sidewall 142 of the photodetection region. For example, Figure 1 and Figure 2 The cross-sectional view of shows reflectors 140 along two sidewalls 142 of the light detection region 102; however, as will be described herein, more than two or less than two reflectors 140 may be disposed around the light detection region 102. Alternatively, the reflectors 140 may surround the light detection region 102. In contrast to conventional photodetectors, the reflectors 140 may include an air gap 144 defined in the semiconductor substrate 104. The air gap 144 is oriented parallel to the path (arrow) of incident electromagnetic radiation 146, such as light. Due to the reflectivity of the reflectors 140, the light detection region 102 may be thinner than conventional light detection regions, which reduces the cost and complexity of forming the light detection region 102 and allows the light detector 100 to be integrated into conventional CMOS and bi-CMOS devices. The degree to which the light detection region 102 is thinner than conventional regions may vary depending on many factors, such as, but not limited to: the type of electromagnetic radiation, the type of optical semiconductor material, the number of reflections produced by the reflector, the absorption rate of the optical semiconductor material, etc.

[0040] refer to Figure 1 and 2 , the air gap 144 extends vertically along substantially all of the sidewalls 142 of the light detection region 102, for example, >85% of the height of the sidewalls 142. That is, the longitudinal extent of the air gap 144 extends vertically along substantially all of the sidewalls 142 of the light detection region 102, and may extend to a depth equal to or greater than the depth of the sidewalls 142. Figure 1 and Figure 2 150, the air gap 144 is defined in a dielectric 148 within a trench 150. The dielectric 148 may have a different refractive index than the semiconductor substrate 104 and may include, for example, silicon oxide (doped like borophosphosilicate glass (BPSG) or undoped) or other dielectrics. In this example, the silicon oxide is more reflective than the semiconductor substrate 104. Other dielectrics may be less reflective within the semiconductor substrate 104. The dielectric 148 includes a pinch-off closure 152 that seals the air gap 144.

[0041] refer to Figure 3-7 , showing the formation of Figure 1 and 2 1. An embodiment of a method for forming an air gap 144 as shown. Generally, the method includes: forming a light detection region 102 in a semiconductor substrate 104, and forming a reflector 140 in the semiconductor substrate 104 extending at least partially along a sidewall 142 of the light detection region 102. As described above, the reflector 140 includes an air gap 144 defined in the semiconductor substrate 104. The order in which the light detection region 102 or the reflector 140 are formed can vary. Figure 3-7 In the example of FIG. 1 , forming the light detection region 102 occurs before forming the reflector 140 .

[0042] like Figure 3As shown, the semiconductor substrate 104 may have a patterned mask 160 formed thereon, which is used to etch a trench 162 for the light detection area 102. The mask 160 may include any mask material now known or later developed. Common masking materials are photoresists (resists) and nitrides. Nitrides are generally considered to be "hard masks". The mask 160 may include a developable organic planarization layer (OPL) on the layer to be etched, a developable anti-reflective coating (ARC) layer on the developable OPL, and a photoresist mask layer on the developable ARC layer. Etching generally refers to removing material from a substrate (or a structure formed on a substrate), and is generally performed with a mask in place so that material can be selectively removed from certain areas of the substrate while leaving material unaffected in other areas of the substrate. There are generally two types of etching, (i) wet etching and (ii) dry etching. Wet etching is performed using a solvent (e.g., an acid), which can be selected for its ability to selectively dissolve a given material (such as an oxide) while leaving another material (such as polysilicon) relatively intact. This ability to selectively etch a given material is fundamental to many semiconductor manufacturing processes. Wet etching will generally etch uniform materials (e.g., oxides) isotropically, but wet etching can also anisotropically etch single crystal materials (e.g., silicon wafers). Dry etching can be performed using plasma. A plasma system can operate in several modes by adjusting the parameters of the plasma. Ordinary plasma etching produces energetic free radicals that react on the surface of the wafer that are electrically neutral. Since neutral particles attack the wafer from all angles, the process is isotropic. Ion milling or sputter etching bombards the wafer with high-energy ions of a rare gas that approach the wafer approximately from one direction, so the process is highly anisotropic. Reactive ion etching (RIE) operates under intermediate conditions between sputtering and plasma etching and can be used to produce deep narrow features, such as STI trenches. Here, RIE can be used to form trench 162.

[0043] Figure 3 Also shown is the formation of optical semiconductor material 110, 120 (eg, intrinsic germanium) in trench 162 to form at least a portion of light detection region 102 ( Figure 5). The optical semiconductor materials 110, 120 may be epitaxially grown, for example, in the trenches 162. The terms "epitaxial growth" and "epitaxial formation and / or growth" refer to growing semiconductor material on a deposition surface of a semiconductor material (e.g., semiconductor substrate 104), wherein the grown semiconductor material may have the same crystal properties as the semiconductor material of the deposition surface. In an epitaxial growth process, the chemical reactants provided by the source gas are controlled and system parameters are set so that the deposited atoms arrive at the deposition surface of the semiconductor substrate with sufficient energy to move on the surface and orient themselves to the crystal arrangement of atoms of the deposition surface. Thus, the epitaxial semiconductor material may have the same crystal properties as the deposition surface on which the epitaxial semiconductor material is formed. For example, an epitaxial semiconductor material deposited on a {100} crystal plane may adopt a {100} orientation. In some embodiments, the epitaxial growth process may be selective for formation on a semiconductor surface and may not deposit material on a dielectric surface (e.g., mask 160), such as a silicon dioxide or silicon nitride surface.

[0044] exist Figure 3 In the embodiment, the light detection area 102 and Figure 2 , that is, it includes only intrinsic germanium and does not include the p-type semiconductor layer 112 ( Figure 1 ).for Figure 1 In an embodiment, ion implantation may be performed to create the p-type semiconductor layer 112 , ie, before epitaxially growing the optical semiconductor material 110 . Figure 3 Also shown is a p-type semiconductor layer 116 formed over the optical semiconductor material 110 to complete the formation of the light detection region 102. The p-type semiconductor layer 116 can be formed, for example, by implanting p-type dopant ions into the optical semiconductor region 110. P-type dopants are introduced into the semiconductor to generate free holes (by "accepting" electrons from semiconductor atoms and simultaneously "releasing" holes); the acceptor atom must have one less valence electron than the host semiconductor. Boron (B) is the most common acceptor in silicon technology, but alternatives include indium and gallium. After processing, the mask 160 can be removed, for example, using any known ashing process.

[0045] Figure 4 The formation of a patterned mask 164 is shown, and the patterned mask 164 is used to etch the reflector 140 ( Figure 5 ) groove 150. Mask 164 may include any mask material now known or later developed. In this embodiment, the reflector 140 ( Figure 1 and 2The trench 150 of the CMOS or bi-CMOS device can be etched as a deep trench, for example, with a depth of 1 to 6 microns. The trench 150 can be simultaneously etched to form trenches for trench isolation in other parts of the CMOS or bi-CMOS device. After this process, the mask 164 can be removed, for example, using any known ashing process. Figure 5 Shown is a deposited dielectric 148. As described above, dielectric 148 has a different reflectivity than semiconductor substrate 104 and may include a more reflective material such as, for example, silicon oxide.

[0046] "Deposition" may include any now known or later developed technique suitable for the material to be deposited, including but not limited to, for example: chemical vapor deposition (CVD), low pressure CVD (LPCVD), plasma enhanced CVD (PECVD), semi-atmospheric CVD (SACVD) and high density plasma CVD (HDPCVD), rapid thermal CVD (RTCVD), ultra-high vacuum CVD (UHVCVD), limited reaction process CVD (LRPCVD), metal organic CVD (MOCVD), sputtering deposition, ion beam deposition, electron beam deposition, laser assisted deposition, thermal oxidation, thermal nitridation, spin coating, physical vapor deposition (PVD), atomic layer deposition (ALD), chemical oxidation, molecular beam epitaxy (MBE), electroplating, evaporation. Here, the dielectric 148 may be deposited by ALD. As noted, the dielectric 148 includes a pinch-off closure 152 that seals the air gap 144.

[0047] like Figure 1 and Figure 2 As shown, the photodetector 100 may also include a first contact 130 to the p-type semiconductor layers 116, 122 and a second contact 132 to the n-type semiconductor substrate 104. The dielectric 148 for pinching off the air gap 144 may also provide an interlayer dielectric (ILD) in which the contacts 130, 132 to the photodetector 100 are provided, or an additional dielectric may be deposited. That is, the dielectric may provide an ILD for back-end processing. The contacts 130, 132 may be formed using any now known or later developed integrated circuit manufacturing technology.

[0048] More about Figure 4 The formation of the mask 164 and the groove 150 using the mask 164 determines the layout of the reflector 140. Figure 6 As shown in the plan view in FIG. 1 , the groove 150 may extend around and / or surround the light detection region 102 through the air gap 144, or as shown in FIG. Figure 7 As shown, the groove 150 can be an independent, isolated groove. The reflector 140 and its air gap 144 can have the same arrangement as the groove 150. Figure 6 In FIG. 1 , an air gap 144 surrounds the light detection region 102 . Figure 7It is also shown that a plurality of reflectors 140 can be provided in a discrete, spaced arrangement around the optical semiconductor materials 110, 120. That is, the air gap 144 includes a plurality of spaced air gaps 144 around the light detection region 102, thereby producing a plurality of reflectors. Here, forming the reflector 140 includes forming a plurality of air gaps 144 around the light detection region 102, and thus forming a plurality of reflectors 140 around the light detection region 102. Figure 7 A plurality of reflectors 140 are shown arranged radially aligned and circumferentially spaced about the light detection region 102. It is emphasized that any arrangement of reflectors 140 may be employed to produce the desired redirection of electromagnetic radiation toward the sidewalls 142 of the optical semiconductor material 110, 120.

[0049] Figure 8-11 100. In these embodiments, the air gap 144 extends vertically along a portion of the sidewall 142 of the light detection region 102. That is, the vertical extent of the air gap 144 extends only along a portion of the vertical extent of the sidewall 142 of the light detection region 102. Figure 8 and Fig. 9 In FIG. 1 , the air gap 144 has a concave inner surface 170. Fig.10 and 11 , the air gap 144 includes a plurality of interconnected inner surfaces 172 that produce a polygonal cross-section. In the example shown, the polygonal cross-section is an octagon; however, any polygonal cross-section that can be formed using the etching process described herein may be employed, for example, a hexagon, a square, a rectangle, etc.

[0050] refer to Figure 3 and 12 -14, the formation will now be described Figure 8-11 Again, the method includes forming a light detection region 102 in a semiconductor substrate 104, and forming a reflector 140 in the semiconductor substrate 104 that extends at least partially along a sidewall 142 of the light detection region 102. Figure 3 and 12 -14, forming the light detection region 102 occurs before forming the reflector 140. For simplicity, Figure 13-14 The left side shows only Fig. 9 The light detection area 102 Figure 8 and 9 The formation of the reflector 140 of the embodiment, the right side only shows the Fig.11 The light detection area 102 Fig.10 and 11 Recognize that the teachings of these figures also apply to Figure 8 and10 The light detection area 102 of the embodiment of FIG. Any differences in processing will be made where appropriate.

[0051] As stated in this article, Figure 3 The formation of the light detection region 102 is shown, including: forming optical semiconductor materials 110, 120, such as intrinsic germanium, in the trench 162; and forming a p-type semiconductor layer 116 on the optical semiconductor material 110 to complete the formation of the light detection region 102. Figure 8 and 10 In the embodiment, before epitaxially growing the optical semiconductor material 110, the p-type semiconductor layer 112 may be formed, for example, by ion implantation.

[0052] Fig.12 Shown in Figure 3 A patterned mask 176 is formed on the light detection region 102. The patterned mask 176 is used to etch the reflector 140 ( Figure 8-11 , 14) opening 178 ( Fig.13 ), for example, as shallow trenches. Mask 176 may include any mask material now known or later developed. Mask 176 may be formed over any previously formed mask (not shown) used to form optical semiconductor materials 110, 120, and patterned by the two masks. In this embodiment, as shown in FIG. Fig.12 As shown, an initial opening 180 (eg, depth <1 micron) may be etched into the semiconductor substrate 104 adjacent to the sidewall 142 of the light detection region 102, for example, by RIE. In addition to creating the initial opening 180, Fig.12 The etching does not extend into the semiconductor substrate 104 .

[0053] like Fig.13 As shown, a next etch may be performed to create an opening 178 for the reflector 140 ( Fig.14 ). The next etch may continue to use mask 176, or mask 176 may be removed, for example, using any known ashing process. Fig.13 As shown on the left, in order to form Figure 8 and 9 In an embodiment, the next etch may include creating a concave inner surface 170 ( Figure 8 , 9 ) isotropically etched (e.g., additional RIE) of the opening 178. Here, the opening 178 can be generally spherical or bulbous. The etching, e.g., chemistry, intensity, duration, etc., can be controlled to create a desired concavity, e.g., radius, focus, etc., to direct electromagnetic radiation toward the sidewall 142 of the light detection region 102. In contrast, as Fig.13 As shown on the right side, in order to form Fig.10 and 11In an embodiment of the present invention, the next etch may include one or more crystallographic etches that create openings 178 having a plurality of interconnected inner surfaces 172, thereby creating a polygonal cross-section ( Fig.10 , 11 ). Any number of crystal etches may be performed to reveal the desired crystal planes within opening 178, for example, <101> , <100> , <110> , <111> etc. In the example shown, the polygonal cross section is an octagon; however, any polygonal cross section that can be formed using the etching processes described herein may be used. The crystal etch, e.g., chemistry, intensity, duration, etc., may be controlled to create the desired inner surface 172, e.g., length, angle between surfaces, etc., to direct electromagnetic radiation toward the sidewall 142 of the light detection region 102. If the mask 176 is still in place, the mask 176 may be removed, e.g., using any known ashing process.

[0054] Fig.14 A dielectric 182 is shown deposited to seal the opening 178 and create a reflector 140 having an air gap 144 in the semiconductor substrate 104. The dielectric 182 may be any now known or later developed dielectric capable of sealing the opening 178, i.e., it creates a pinch-off closure 184 that seals the air gap 144. In one non-limiting example, the dielectric 182 may include silicon oxide.

[0055] like Figure 8-11 As shown, contacts 130, 132 may be formed using any now known or later developed integrated circuit fabrication technique, such as in an interlayer dielectric (ILD) 168 over photodetector 100. Dielectric 168 may be the same material as dielectric 182, or may be a different dielectric.

[0056] More about Fig.12 The formation of the mask 176 and the opening 178 using the mask 176 determines the layout of the reflector 140. Figure 7 , the openings 178 may be separate, isolated openings similar to those described with respect to the grooves 150. In this manner, a plurality of reflectors 140 may be provided in a discrete, spaced-apart arrangement around the light detection region 102. Figure 7 A plurality of reflectors 140 are shown arranged to be radially aligned and circumferentially spaced around the light detection region 102 (i.e., the optical semiconductors 110, 120). Thus, the reflectors 140 and their air gaps 144 may have the same arrangement. It is emphasized that any arrangement of the reflectors 140 may be employed to create the desired redirection of electromagnetic radiation toward the sidewalls 142 of the light detection region 102. Fig.15As shown in the plan view of FIG. 1 , the mask 176 can be patterned to create a plurality of connected openings 186. After etching, the air gap 144 can thus include a plurality of interconnected voids 188 in the semiconductor substrate 104, for example, in a horizontal plane, the plurality of interconnected voids 188 together forming a single trench or void. In this way, the air gap 144 can surround the light detection region 102.

[0057] refer to Figure 16-19 , showing another embodiment of a method of forming a light detector 100. Again, the method generally includes forming a light detection region 102 in a semiconductor substrate 104, and forming a reflector 140 in the semiconductor substrate 104 extending at least partially along a sidewall 142 of the light detection region 102. Figure 3-5 Compared with 12-14, Figure 16-19 , forming the light detection region 102 occurs after forming the reflector 140 .

[0058] Fig.16 The formation of a patterned mask 190 for etching the reflector 140 ( Fig.19 ). Semiconductor substrate 104 may be as described herein, for example, an n-type doped semiconductor. Mask 190 may include any mask material now known or later developed. The formation of mask 190 and openings 192 using it determines the layout of reflector 140. In this embodiment, openings 192 for reflector 140 may be etched as shallow trenches, for example, with a depth of <5 microns. Openings 192 may be independent, discrete openings, such as Figure 7 As shown, or can be connected to form a single trench or void together. For example, after etching, as Fig.15 As shown after sealing in FIG. 1 , the air gap 144 may include a plurality of interconnected voids 194 in the semiconductor substrate 104, for example, in a horizontal plane, the plurality of interconnected voids 194 collectively forming a single trench or void. In this manner, the reflector 140 with the air gap 144 may surround the light detection region 102. Other arrangements of discrete reflectors 140 may also be formed in this manner.

[0059] Fig.17A pinch-off closure 196 is shown formed to seal the opening 192 and form an air gap 144 of the reflector 140. In this embodiment, the pinch-off closure 196 can be formed by epitaxially growing a semiconductor (e.g., silicon germanium (SiGe). Thus, the pinch-off closure 196 includes a semiconductor. The epitaxial growth merges the upper region of the opening 192 to form the air gap 144. A first semiconductor layer 198 (e.g., silicon) can then be formed over the pinch-off closure 196. As will be described, the thickness of the first semiconductor layer 198 can be controlled to control the thickness of the reflector 140 relative to the light detection region 102 ( Fig.19 )'s sidewall 142 may be positioned vertically, for example, above, below, or flush with an upper surface of the light detection region 102.

[0060] Fig.18 A number of additional steps are also shown. Fig.18 Shown is the formation of shallow trench isolation (STI) 204. STI 204 is a trench etched into semiconductor substrate 104 and filled with an insulating material, such as silicon oxide, to isolate one region of the substrate from an adjacent region of the substrate. Fig.18 Also shown is the formation of a patterned mask 208 for forming an opening 210 for the formation of an optical light detecting material. The mask 208 may include any mask material now known or later developed. The mask 208 and the formation of the opening 210 using it determine the optical semiconductor material 212 ( Fig.19 ) and the light detection region 102 ( Fig.19 ) layout, which can be customized in terms of, for example, shape, size, proximity to reflector 140.

[0061] Fig.19 The opening 210 ( Fig.17 ) to form the light detection region 102. The optical semiconductor material 212 may include any material described herein, for example, intrinsic germanium. The optical semiconductor material 212 may be epitaxially grown, for example, in the opening 210. Prior to forming the optical semiconductor material 212, if an avalanche photodiode is desired, the opening 210 ( Fig.18 ) may be doped with a p-type dopant to form a p-type semiconductor layer (e.g. Figure 1 112), for example, by ion implantation or epitaxial growth of a p-type doped layer prior to forming the optical semiconductor material 212. Fig.19 Also shown is the formation of a p-type contact 220, such as a p-type doped polysilicon line, on the optical semiconductor region 212. Subsequent processing may include any now known or later developed back-end processing technique.

[0062] refer to Fig. 20, an optional process for forming the reflector 140 may include forming a liner 230 on at least a portion of an inner surface 232 of an opening for forming the air gap 144. In this case, an opening is formed, a liner is formed, and the opening is sealed to form the air gap 144. The liner 230 may be formed using any now known or later developed deposition technique (e.g., ALD or oxidation), and the position of the liner may be customized using any suitable etching process if desired. As described herein, the opening for the air gap 144 may take a variety of forms. Any of the openings in the semiconductor substrate 104 described herein (e.g., Figure 4 Groove 150, Fig.13 Opening 178 or Fig.16 The opening 192 in the can have a liner 230 applied thereto. In addition, the liner 230 can be applied to the plurality of interconnected voids 188, 194 ( Fig.15 ) of the air gap 144. Fig. 20 For the sake of brevity, Fig.13 104. Various forms of openings are collectively shown in the figure. The liner 230 includes at least one material having a reflectivity different from the reflectivity provided by the inner surface 232 (i.e., the inner surface of the semiconductor substrate 104). The liner 230 may include a material that is more reflective than the semiconductor substrate 104, or a material that is less reflective than the semiconductor substrate 104. The liner 230 may include, for example, a dielectric, such as silicon oxide, which may increase the reflectivity, or it may include an anti-reflective layer for reducing the reflectivity, or it may include both but in different regions. The liner 230 may also include a portion 230A that is more reflective than the semiconductor substrate 104 and a portion 230B that is less reflective than the semiconductor substrate 104. In the latter case, for example, the portion 230A may be formed, and then the portion 230B may be formed, where it is desired to be formed above the portion 230A. Alternatively, a portion of the first portion formed may be removed, for example, by etching, and replaced with another portion. In any case, the customization of the liner material and the positioning of the liner 230 may thereby allow the reflectivity of the reflector 140 to be customized.

[0063] Although a particular arrangement of the reflector 140 has been described herein, it is emphasized that the reflector 140 including the air gap 144 may have any desired arrangement to direct electromagnetic radiation toward the sidewalls 142 of the light detection region 102 (i.e., the optical semiconductor material 110, 120, 212). Fig.21 A reflector 140 is shown including air gaps 144, each having a pair of interconnected voids 188, 194 spaced circumferentially around a cylindrical optical semiconductor material 110, 120, 212 (creating a generally peanut-shaped air gap cross-section). Fig. 22Another example is shown in which the reflectors 140 including the air gaps 144 are spaced apart only along a pair of sidewalls 142 of a vertical fin-shaped (rectangular in cross-section) light detection region 102 .

[0064] In addition to various horizontal layouts, any reflector 140 can be customized in vertical extent and vertical position relative to the light detection region 102 to provide electromagnetic radiation of a desired reflectivity toward the sidewall 142 of the light detection region. In terms of vertical position, the reflector 140 can be flush with the upper surface of the light detection region 102 (i.e., the optical semiconductor material 110, 120, 212). Alternatively, as Fig.23 As shown in the cross-sectional view of FIG. 1 , the reflector 140 may be below the light detection region 102, or as shown in FIG. Fig.24 As shown in the cross-sectional view of , the reflector 140 can be above the light detection region 102. The dopant concentrations in the various portions described herein can also be tailored to produce a desired light detector 100. In addition, while a particular order of dopant types has been described herein, one skilled in the art will recognize that the order can be switched, for example, using n-type dopants where p-type dopants are employed, and using p-type dopants where n-type dopants are employed.

[0065] Embodiments of the present disclosure provide a photodetector that is easy to manufacture and can be integrated into CMOS and bi-CMOS devices. The reflector includes a buried air gap that acts as a reflector adjacent to the optical semiconductor material, thereby allowing the use of thinner optical semiconductor materials. Therefore, the present disclosure is conducive to reducing the thickness of, for example, an intrinsic germanium light detection region. Although the light detection region is thin, due to the reflectivity provided by the reflector, the light detection region can still absorb electromagnetic radiation, and in particular, absorb electromagnetic radiation of longer wavelengths. Although the air gap is arranged parallel to the path of the incident electromagnetic radiation, the air gap provides a desired reflectivity.

[0066] The method described above can be used in the manufacture of photonic chips and / or integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in the form of raw wafers as bare chips (i.e., as a single wafer with multiple unpackaged chips) or in a packaged form. In the latter case, the chip is mounted in a single-chip package (such as a plastic carrier whose leads are fixed to a motherboard or other higher-level carrier) or a multi-chip package (such as a ceramic carrier, which has one or both of surface interconnects and / or buried interconnects). In any case, the chip is then integrated with other chips, discrete circuit elements and / or other signal processing devices as part of (a) an intermediate product (such as a motherboard) or (b) a final product. The final product can be any product that includes a photonic chip and / or an integrated circuit chip, from toys and other low-end applications to advanced computer products with displays, telecommunications devices, keyboards or other input devices, and central processing units.

[0067] The terms used herein are only used for the purpose of describing specific embodiments and are not intended to limit the present disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms "one", "an" and "said" are intended to also include plural forms. It will also be understood that when used in this specification, the terms "include" and / or "comprise" specify the existence of stated features, integers, steps, operations, elements and / or components, but do not exclude the existence or addition of one or more other features, integers, steps, operations, elements, components and / or their, groups. "Optional" or "optionally" means that the event or situation described subsequently may or may not occur, and the description includes examples of events occurring and examples of events not occurring.

[0068] As used throughout the specification and claims herein, approximate language may be applied to modify any quantitative representation that may be permissibly varied without causing a change in the basic function associated therewith. Therefore, values ​​modified by terms or terms such as "about," "approximately," and "substantially" are not limited to the exact values ​​specified. In at least some cases, approximate language may correspond to the precision of the instrument used to measure the value. Here and throughout the specification and claims, range limitations may be combined and / or interchanged, unless otherwise indicated by context or language, such ranges are identified and include all subranges contained therein. "Approximate" applied to a particular value of a range applies to both values, and may indicate + / -10% of the value unless otherwise dependent on the precision of the instrument for measuring the value.

[0069] The corresponding structures, materials, actions, and equivalents of all means or step-plus-function elements in the claims below are intended to include any structure, material, or action for performing the function in combination with other claimed elements specifically claimed. The description of the present disclosure has been presented for the purpose of illustration and description, but is not intended to be exhaustive or to limit the present disclosure to the disclosed form. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the present disclosure. The embodiments are selected and described in order to best explain the principles and practical applications of the present disclosure, and to enable other persons of ordinary skill in the art to understand the present disclosure of various embodiments with various modifications suitable for the intended specific use.

Claims

1. A light detector comprising: a light detection region in a semiconductor substrate, wherein the semiconductor substrate comprises an n-type semiconductor, and the light detection region comprises intrinsic germanium in a p-type semiconductor liner and a p-type semiconductor layer located on the intrinsic germanium in the p-type semiconductor liner; and A reflector in the semiconductor substrate extends at least partially along a sidewall of the light detection region, the reflector comprising an air gap defined in the semiconductor substrate.

2. The optical detector according to claim 1, wherein The air gap is oriented parallel to the path of incident electromagnetic radiation.

3. The light detector according to claim 1, wherein The air gap extends vertically along all sidewalls of the light detection region.

4. The light detector according to claim 1, wherein The air gap extends vertically along a portion of the sidewall of the light detection region.

5. The light detector according to claim 1, wherein The air gap includes a plurality of interconnected voids in the semiconductor substrate.

6. The light detector according to claim 1, wherein The air gap includes a concave inner surface.

7. The light detector according to claim 1, wherein The air gap includes a plurality of interconnected interior surfaces creating a polygonal cross-section.

8. The light detector according to claim 1, wherein The air gap surrounds the light detection area.

9. The light detector according to claim 1, wherein The air gap includes a plurality of spaced-apart air gaps surrounding the light detection region.

10. The light detector of claim 1, further comprising a lining along at least a portion of an inner surface of the air gap.

11. The light detector according to claim 10, wherein The liner includes at least one of a dielectric and an anti-reflective layer.

12. The light detector according to claim 1, wherein The air gap is defined in a dielectric within the deep trench, and wherein the dielectric includes a pinch-off closure that seals the air gap.

13. The light detector according to claim 1, wherein The air gap includes a pinch-off closure that includes a semiconductor.

14. The light detector according to claim 1, wherein The air gap includes a pinch-off closure including a dielectric.

15. A method comprising: forming a light detection region in a semiconductor substrate, wherein the semiconductor substrate comprises an n-type semiconductor, and the light detection region comprises intrinsic germanium in a p-type semiconductor liner and a p-type semiconductor layer located on the intrinsic germanium in the p-type semiconductor liner; and A reflector is formed in the semiconductor substrate and extends at least partially along a sidewall of the light detection region, the reflector including an air gap defined in the semiconductor substrate.

16. The method according to claim 15, wherein: Forming the light detection region occurs before forming the reflector.

17. The method according to claim 15, wherein: Forming the reflector includes forming an opening in the semiconductor substrate, forming a liner on at least a portion of an inner surface of the opening, and sealing the opening to form the air gap.

18. The method according to claim 15, wherein: Forming the reflector includes forming a plurality of air gaps surrounding the light detection region.

19. The method according to claim 15, wherein: Forming the reflector includes forming an opening in the semiconductor substrate using crystal etching, and sealing the opening to form the air gap.

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