A semiconductor quantum well laser and a preparation method thereof

Abstract

The present invention relates to the field of optical communication technologies, and particularly relates to a semiconductor quantum well laser and a preparation method thereof. The epitaxial structure of the laser includes a substrate, a buffer layer, a lower confinement layer, an active layer, an upper confinement layer, and a contact layer, which are sequentially arranged from bottom to top; a ridge waveguide and a plurality of etching grooves are provided on the upper protective layer, the etching grooves are distributed on the ridge waveguide, and the etching grooves divide the ridge waveguide into a plurality of discontinuous ridge waveguide segments. The present invention realizes effects similar to chirping, apodization, or phase shift grating to achieve a narrow linewidth output, and at the same time, complex processes such as grating manufacturing and secondary epitaxial growth can be avoided, simplifying the preparation process of the laser.

Description

Technical Field

[0001] The present invention relates to the field of optical communication technologies, and particularly relates to a semiconductor quantum well laser and a preparation method thereof. Background Art

[0002] In application fields such as optical communication, the semiconductor lasers used in the market are mainly FP lasers (Fabry-Perot semiconductor lasers), DFB lasers (Distributed Feedback Laser semiconductor lasers), DBR lasers (distributed Bragg reflector semiconductor lasers), and external cavity lasers.

[0003] The linewidth characteristic of a semiconductor laser determines the performance of an optical fiber communication system. With the rapid development of optical fiber communication technologies, the application of narrow linewidth semiconductor lasers with a linewidth below the MHz level is becoming more and more extensive. In addition, in fields that require precise measurement, such as lidar, fiber optic hydrophones, fiber optic temperature measurement, and long-distance coherent detection, the requirements for the linewidth of semiconductor lasers are increasing day by day.

[0004] The fabrication of FP lasers is simple and the cost is low, but it is difficult to achieve single longitudinal mode laser. Although single longitudinal mode DFB lasers can achieve single longitudinal mode laser and the cost has been reduced to a marketable level, in the manufacturing process, there are not only complex processes such as grating manufacturing and secondary epitaxial growth, but also expensive equipment is required. At the same time, the linewidth of DFB lasers is usually in the MHz level and it is difficult to meet the requirements of narrow linewidth. The preparation process of DBR semiconductor lasers is relatively more complex than that of DFB, and the linewidth difference is not significant.

[0005] Semiconductor external cavity lasers can narrow the linewidth to below 100 kHz, but their power is usually low, the fabrication of gratings or fiber gratings is difficult, the coupling with semiconductor chips is difficult, and they are easily affected by external environments such as vibration.

[0006] To achieve single longitudinal mode output of an FP laser, researchers in Ireland proposed the Slotted FP laser. A series of etched slots are periodically arranged on a waveguide to modulate the output spectrum of the laser by perturbing the resonant cavity, thereby achieving single-mode output of the laser. All the slot widths of the laser are about 1 micron, and the etching depth is the same as the height of the ridge waveguide. By adjusting the period of the etched slots, different wavelength outputs can be achieved. They obtained a set of laser arrays with different output wavelengths. This method integrates an electro-absorption modulator behind the etched slot ridge waveguide, and a laser similar to a DBR can be obtained. To further reduce the linewidth of the FP laser, some people proposed to increase the etching depth to a position where the active layer can be cut off. This method can obtain a narrower linewidth, but the deep etching process with an etching depth-to-width ratio of at least 4 or more is difficult, and the quality of the etched cross-section is difficult to control and guarantee.

[0007] To reduce the linewidth from the perspective of DFB lasers, Chen Xiangfei et al. proposed the Reconstructed Equivalent Chirp (REC) technology in 2004. This technology is similar to a sampled Bragg grating. Based on a uniform seed grating, by designing and fabricating a special sampling structure with a larger period, such as forming equivalent phase shifts, equivalent apodizations, etc. in the ±1st order channels of the sampled grating, the same functions and effects of confining and selecting light as those of a real phase shift grating, an apodized grating, etc. can be achieved. Its advantages are that the sampling period is on the order of microns, which simplifies the manufacturing process of complex grating structures, improves the control accuracy of wavelengths at the same time, and can also narrow the linewidth to below the MHz level. However, this method cannot avoid complex processes with high difficulties and costs, such as grating manufacturing and secondary epitaxial growth. Summary of the Invention

[0008] A semiconductor quantum well laser, whose epitaxial structure includes a substrate, a buffer layer, a lower confinement layer, an active layer, an upper confinement layer, and a contact layer arranged in sequence from bottom to top;

[0009] Preferably, the epitaxial structure further includes: a lower waveguide layer, an upper waveguide layer, a transition layer, a lower protection layer, an etching stop layer, and an upper protection layer;

[0010] The lower waveguide layer is located between the lower confinement layer and the active layer, the upper waveguide layer and the transition layer are located between the active layer and the upper confinement layer in sequence from bottom to top, and the lower protection layer, the etching stop layer, and the upper protection layer are arranged between the upper confinement layer and the contact layer in sequence from bottom to top;

[0011] As an example, the epitaxial structure includes a substrate, a buffer layer, a lower confinement layer, an active layer, an upper confinement layer, a lower protection layer, an etching stop layer, an upper protection layer, and a contact layer arranged in sequence from bottom to top;

[0012] As an example, the epitaxial structure includes a substrate, a buffer layer, a lower confinement layer, a lower waveguide layer, an active layer, an upper waveguide layer, a transition layer, an upper confinement layer, and a contact layer, which are sequentially arranged from bottom to top;

[0013] A ridge waveguide and a plurality of etching grooves are formed by etching or corrosion on the upper protective layer. The etching grooves are distributed on the ridge waveguide, and the ridge waveguide is divided into a plurality of discontinuous ridge waveguide segments by the etching grooves;

[0014] According to the present invention, the coupling coefficient between the segments of the ridge waveguide, and / or the length of each segment of the ridge waveguide, and / or the width of the etching groove, and / or the depth of the etching groove are distributed in a tapered distribution, a chirped distribution, or a phase shift distribution along the axial direction of the resonant cavity.

[0015] Preferably, the distribution of the coupling coefficient between the segments of the ridge waveguide, the length of each segment of the ridge waveguide, the width of the etching groove, and the depth of the etching groove along the axial direction of the resonant cavity includes at least two of a tapered distribution, a chirped distribution, or a phase shift distribution.

[0016] Preferably, the lengths of the segments of the ridge waveguide in the middle region of the ridge waveguide are distributed in a chirped distribution or a phase shift distribution. Preferably, the lengths of the segments of the ridge waveguide in the two side regions are equivalently tapered distributed;

[0017] Preferably, the lengths of the segments of the ridge waveguide within the middle 1 / 3 range of the ridge waveguide are distributed in a chirped distribution or a phase shift distribution, and the lengths of the segments of the ridge waveguide within each 1 / 3 range on both sides are equivalently tapered distributed;

[0018] Preferably, the width and / or depth of the etching groove in the middle region of the ridge waveguide are distributed in a chirped distribution or a phase shift distribution. Preferably, the width of the etching groove in the two side regions is equivalently tapered distributed;

[0019] Preferably, the width and / or depth of the etching groove within the middle 1 / 3 range of the ridge waveguide are distributed in a chirped distribution or a phase shift distribution, and the width and / or depth of the etching groove within each 1 / 3 range on both sides are equivalently tapered distributed;

[0020] Preferably, the coupling coefficient between the segments within the middle region of the ridge waveguide is distributed in a chirped distribution or a phase shift distribution. Preferably, the coupling coefficients in the two side regions are equivalently tapered distributed;

[0021] Preferably, the coupling coefficient between the segments within the middle 1 / 3 range of the ridge waveguide is distributed in a chirped distribution or a phase shift distribution, and the coupling coefficients within each 1 / 3 range on both sides are equivalently tapered distributed;

[0022] Preferably, the ratio of the length of each segment of the ridge waveguide to the width of the etching groove is greater than 1 (i.e., the duty cycle is greater than 0.5). For example, each segment of the ridge waveguide and the etching groove are equivalently tapered distributed, and the duty cycle varies within 0.75 - 0.95.

[0023] Preferably, each segment of the ridge waveguide and the etching grooves are distributed in an equivalent apodization, and the distribution is a cosine distribution.

[0024] The apodization distribution refers to a structure with a specific function distribution state, which commonly includes Gaussian distribution, cosine distribution, Hamming function distribution, such as cosine distribution; the chirp distribution refers to a structure in which the period of the distribution state changes linearly; the phase shift distribution structure refers to a structure in which the period of the distribution state has a phase mutation.

[0025] Preferably, side grooves are arranged on both sides of the ridge waveguide parallel to the ridge direction, and the width of the side grooves is 10-20 μm;

[0026] Preferably, the depth of the side grooves is the same as the height of the ridge waveguide;

[0027] According to the present invention, the depth of the ridge waveguide is 1-2.6 μm, and the ridge width is 2-4 μm;

[0028] Preferably, the width of the etching grooves is in the same direction as the length of the ridge waveguide, so as to divide the ridge waveguide into several ridge waveguide segments, and the length of the etching grooves is the same as or different from the width of the ridge waveguide;

[0029] Preferably, the width of the etching grooves is 0.5-2.5 μm, the depth is 1-2 μm, and preferably, the depth-to-width ratio of the etching grooves is less than 4;

[0030] Preferably, the bottom of the etching grooves is located in the N-InP buffer layer, the P-InGaAsP upper confinement layer or the P-InP lower protection layer;

[0031] Preferably, the ridge height of the ridge waveguide is the same as or different from the depth of the etching grooves; preferably, the depths of different etching grooves are the same or different;

[0032] According to the embodiment of the present invention, the active layer includes several layers of In x Ga 1-x As y P 1-y quantum wells, the number of layers of the quantum wells ≥ 3 layers, preferably, ≥ 4 layers, such as 4 layers;

[0033] The value range of x is 0-1, and the value range of y is 0-1; the bandgap E g is determined according to the designed wavelength of the laser, and the values of x and y need to satisfy the formula:

[0034] E g = 2.75 - 1.33y - 1.4x + 0.33xy - (0.758 - 0.28y)x(1 - x) - (0.21 - 0.109x)y(1 - y);

[0035] For example, the In x Ga 1-x As y P 1-y quantum well is In 0.557 Ga 0.443 As 0.95 P 0.05 quantum well. Preferably, the thickness of the In 0.557 Ga 0.443 As 0.95 P 0.05 quantum well is 6 nm.

[0036] Preferably, there is a potential barrier between adjacent In x Ga 1-x As y P 1-y quantum wells. In the potential barrier, the values of x and y in the In x Ga 1-x As y P 1-y material are different from those in the quantum well. Preferably, the potential barrier is In 0.738 Ga 0.262 As 0.568 P 0.432 and preferably, the thickness of the potential barrier is 10 nm.

[0037] Preferably, the substrate is an N + -InP substrate;

[0038] Preferably, the buffer layer is N-InP with a thickness of 1 - 2 μm; preferably, the thickness of the buffer layer is 1.2 - 1.8 μm, such as 1 μm, 1.1 μm, 1.3 μm, 1.4 μm, 1.5 μm, 1.7 μm, 1.9 μm, 2 μm.

[0039] The upper confinement layer is P-InGaAsP with a thickness of 0.1 - 0.2 μm; preferably, the thickness of the upper confinement layer is 0.13 - 0.18 μm, such as 0.12 μm, 0.15 μm, 0.16 μm, 0.18 μm, 0.19 μm.

[0040] The lower confinement layer is N-InGaAsP with a thickness of 0.1 - 0.2 μm; preferably, the thickness of the lower confinement layer is 0.12 - 0.17 μm, such as 0.11 μm, 0.14 μm, 0.15 μm, 0.16 μm, 0.18 μm.

[0041] The upper protective layer and the lower protective layer are P-InP with a thickness of 1.5 - 2.5 μm; preferably, the thickness of the upper protective layer and the lower protective layer is 1.8 - 2.2 μm, such as 1.6 μm, 1.7 μm, 1.9 μm, 2.1 μm, 2.3 μm, 2.4 μm.

[0042] The etching stop layer is P-InGaAsP with a thickness of 0.01 - 0.02 μm, such as 0.01 μm, 0.02 μm.

[0043] The materials of the semiconductor quantum well laser can be different material systems such as InGaAsP / InP system, GaAlN / GaN system, InGaAs / GaAs system, InGaAsAl / GaAs system, etc.

[0044] According to the embodiment of the present invention, the materials used for the quantum well and the barrier include InGaAsP, GaAlN, InGaAs, InGaAsAl.

[0045] According to the embodiment of the present invention, the material used for the barrier is different from the material composition of the quantum well.

[0046] According to the embodiment of the present invention, the substrate materials include InP, GaN, GaAs.

[0047] The present invention also provides a method for manufacturing the above semiconductor quantum well laser, including the following steps:

[0048] Prepare an epitaxial wafer, etch a ridge waveguide and an etching groove on the epitaxial wafer, and evaporate electrodes to obtain a chip.

[0049] According to the present invention, after evaporating the electrodes, the following steps are further included: dissociate the chip into bars along the crystal orientation, and evaporate optical films on the light-emitting and backlight end faces of the bars.

[0050] According to the present invention, the preparation of the epitaxial wafer specifically includes the following steps:

[0051] Use MBE or MOCVD to grow a primary epitaxial structure, and the epitaxial structure sequentially includes a substrate, a buffer layer, a lower confinement layer, an active layer, an upper confinement layer, and a contact layer along the crystal orientation.

[0052] Preferably, the epitaxial structure further includes: a lower waveguide layer, an upper waveguide layer, a transition layer, a lower protective layer, an etching stop layer, and an upper protective layer;

[0053] The lower waveguide layer is located between the lower confinement layer and the active layer, the upper waveguide layer and the transition layer are sequentially located between the active layer and the upper confinement layer from bottom to top, and the lower protective layer, the etching stop layer, and the upper protective layer are sequentially arranged between the upper confinement layer and the contact layer from bottom to top;

[0054] As an example, the epitaxial structure includes a substrate, a buffer layer, a lower confinement layer, an active layer, an upper confinement layer, a lower protection layer, an etching stop layer, an upper protection layer, and a contact layer, which are sequentially arranged from bottom to top;

[0055] As an example, the epitaxial structure includes a substrate, a buffer layer, a lower confinement layer, a lower waveguide layer, an active layer, an upper waveguide layer, a transition layer, an upper confinement layer, and a contact layer, which are sequentially arranged from bottom to top;

[0056] The substrate, buffer layer, lower confinement layer, active layer, upper confinement layer, lower protection layer, etching stop layer, upper protection layer, lower waveguide layer, upper waveguide layer, transition layer, and contact layer have the definitions as described above.

[0057] Preferably, growing the active layer includes alternately growing quantum well layers and barriers. For example: first grow a quantum well layer, and then grow a barrier on the surface of the quantum well layer, repeat several times until the thickness meets the requirements, and the top layer is a quantum well layer.

[0058] For example: on an N+-InP substrate, MBE or MOCVD epitaxial growth at 550 - 650 °C with a doping concentration of 2×10 18 , a 1 - μm - thick N - InP buffer layer; grow an N - InGaAsP lower confinement layer with a doping concentration of 0.4×10 18 , a 0.1 - μm - thick N - InGaAsP lower confinement layer; grow an active region containing multiple InGaAsP quantum wells; grow a P - InGaAsP upper confinement layer with a doping concentration of 0.4×10 18 , a 0.1 - μm - thick P - InGaAsP upper confinement layer; grow a P - InP lower protection layer with a doping concentration of 0.4×10 18 , a 0.12 - μm - thick P - InP lower protection layer; grow a P - InGaAsP etching stop layer with a doping concentration of 0.4×10 18 , a 0.015 - μm - thick P - InGaAsP etching stop layer; grow a P - InP upper protection layer with a doping concentration of 1×10 18 , a 1.6 - μm - thick P - InP upper protection layer; grow a P+-InGaAs contact layer with a doping concentration of 10×10 18 , a 0.2 - μm - thick P+-InGaAs contact layer.

[0059] According to the present invention, etching a ridge waveguide and an etching groove on the epitaxial wafer includes the following steps: depositing a dielectric film on the epitaxial wafer, lithographically defining the ridge waveguide and the etching groove, etching the dielectric film, etching or corroding to form the ridge waveguide and the etching groove structure, and removing the mask.

[0060] For example: deposit a 250 - nm - thick SiO2 mask layer on the chip surface; lithographically form a ridge pattern including an etching groove; ICP etch the SiO2 mask layer; remove the photoresist;

[0061] Preferably, the contact layer is etched using an etching solution or dry etching, for example: etching the P+-InGaAs contact layer using an etching solution of H3PO4:H2O2:H2O with a ratio of 1:1:10;

[0062] Preferably, at room temperature, the upper protective layer or the upper confinement layer is etched using an etching solution or dry etching, for example: etching the P-InP upper protective layer using an etching solution of HCl:H3PO4 with a ratio of 1:3 to form a ridge waveguide structure and removing the SiO2 mask layer.

[0063] In the formed ridge waveguide structure, the etching depth is 1 - 1.6 μm, the ridge width is 0.5 - 2.5 μm, for example 2 μm; the length of the etching groove is the same as the size and direction of the width of the ridge waveguide; the width of the etching groove is 0.5 - 2.5 μm, for example 2 μm; the depth of the etching groove is 1 - 2 μm; the depth-to-width ratio of the etching groove is less than 4;

[0064] When the height of the ridge waveguide and the depth of the etching groove are different, or the depths of different etching grooves are different, the etching steps are as follows:

[0065] Deposit a 250 nm SiO2 mask layer on the chip surface; lithography to form a ridge pattern; ICP etch the SiO2 mask layer; strip the resist; select an appropriate etching solution to etch or dry etch the contact layer, for example: etching the P+-InGaAs contact layer using an etching solution of H3PO4:H2O2:H2O with a ratio of 1:1:10, and at room temperature, select an appropriate etching solution to etch or dry etch the upper protective layer or the upper confinement layer, for example: etching the P-InP upper protective layer using an etching solution of HCl:H3PO4 with a ratio of 1:3 to form a ridge waveguide structure; deposit a 250 nm SiO2 mask layer on the chip surface; lithography to define the etching groove; ICP etch the SiO2 mask layer; strip the resist; etch or dry etch to a predetermined depth.

[0066] When the height of the ridge waveguide and the depth of the etching groove are different, and the depths of different etching grooves are different, the etching steps are as follows:

[0067] a. Deposit a 250-nm SiO2 mask layer on the chip surface; perform photolithography to form a ridge pattern; use ICP to etch the SiO2 mask layer; strip the photoresist; b. Select an appropriately proportioned etching solution to etch or perform dry etching on the contact layer. For example, use an etching solution of H3PO4:H2O2:H2O with a ratio of 1:1:10 to etch the P+-InGaAs contact layer. At room temperature, select an appropriate etching solution to etch or perform dry etching on the upper protection layer or the upper confinement layer. For example, use an etching solution of HCl:H3PO4 with a ratio of 1:3 to etch the P-InP upper protection layer to form a ridge waveguide structure; deposit a 250-nm SiO2 mask layer on the chip surface; perform photolithography to define the etching groove; use ICP to etch the SiO2 mask layer; strip the photoresist; etch or dry-etch to a set depth; c. Repeat step b several times according to different values of the etching groove depth.

[0068] According to the present invention, if the etching groove in step c does not etch (or corrode) to the active region, then through ion implantation, or depositing a semiconductor or conductive material, a low-resistivity region with a thickness of 50 nm to 200 nm is formed on the inner surface of the groove, so as to increase the pump current provided to the active layer in the groove and reduce the influence of the active region loss in the etching groove on the device performance.

[0069] According to the present invention, if the groove in step c penetrates into the active region, then through depositing a semiconductor or conductive material, a low-resistivity region with a thickness of 50 nm to 200 nm is formed on the inner surface of the groove, so as to increase the pump current provided to the active layer in the groove and reduce the influence of the active region loss in the etching groove on the device performance.

[0070] According to the present invention, if the groove in step c penetrates through the active region, or deposit an insulating layer with a thickness of 50 nm to 400 nm on the inner surface of the groove to adjust the coupling coefficient between each segment of the ridge waveguide, or no deposition treatment is performed.

[0071] According to the present invention, the steps of evaporating and depositing electrodes include: depositing a SiO2 insulating layer on the etched epitaxial wafer, performing photolithography to define the electrode window, etching the SiO2 insulating layer, removing the photoresist, performing photolithography to define the P electrode, depositing the P-side metal, and stripping; further thinning the substrate, depositing the N-side metal, and annealing the alloy.

[0072] For example: deposit a 300-nm SiO2 passivation layer on the chip surface, through photolithography, use RIE to etch the passivation layer in the exposed area, electron beam evaporate Au(20 nm) / Zn(50 nm) / Au(1000 nm) as the P-side metal, thin the chip substrate to a thickness of 110 - 150 μm, electron beam evaporate AuGe(500 nm) / Ni(800 nm) / Au(1000 nm) as the N-side metal, and alloy in a nitrogen atmosphere at 400 - 500 °C for 60 s.

[0073] Beneficial effects

[0074] In the present invention, the ridge waveguide is divided into several segments by a number of etching grooves. The width and / or depth of the etching grooves, and / or the length of the ridge waveguide segments are designed to have an equivalent chirp, apodization or phase shift characteristic distribution, so as to achieve a similar chirp, apodization or phase shift grating effect, realize a narrower linewidth output, and at the same time avoid complex processes such as grating manufacturing and secondary epitaxial growth, and simplify the preparation process of the laser. Further, the pump current is provided to the active layer in the groove by means of leakage current to reduce the influence of the active region loss in the etching groove on the device performance.

[0075] Similar to a chirped grating, the equivalent chirp distribution will not cause an excessive number of photons in the central part of the cavity, resulting in a non-uniform distribution of carriers along the resonant cavity, reducing the occurrence probability of the spatial hole burning phenomenon in the laser, suppressing mode hopping, and making the stability of the single longitudinal mode of the laser reach or even exceed that of other commercial ordinary DFB lasers.

[0076] The apodization distribution structure can suppress the side modes of the reflection spectrum and improve the main side mode gain ratio. In the preparation process, complex processes such as grating manufacturing and secondary epitaxial growth can be avoided, and the preparation process of the laser can be simplified.

[0077] Further, by treating the inner surface of the etching groove, the coupling coefficient between the segments of the ridge waveguide is adjusted, the pump current provided to the active layer in the groove is increased, and the influence of the active region loss in the etching groove on the device performance is reduced. Description of the Drawings

[0078] Figure 1 It is a schematic structural diagram of the epitaxial wafer in the embodiment of the present invention;

[0079] Figure 2 It is a schematic structural diagram of the active layer;

[0080] Figure 3 It is a top view of the epitaxial wafer after etching the ridge waveguide and the etching grooves. Among them, a is the length of the ridge waveguide segment, b is the width of the etching groove, c is the length of the etching groove, X is the equivalent apodization distribution area, and Y is the phase shift or chirp distribution area;

[0081] Figure 4 For Figure 3 A cross-sectional view of, where d is the depth of the side groove and e is the depth of the etching groove;

[0082] Figure 5 For Figure 3 A cross-sectional view of B in, where f is the width of the ridge waveguide, g is the width of the side groove, and h is the height of the ridge waveguide;

[0083] Figure 6 For Figure 3 A cross-sectional view of C in.

[0084] In the figure:

[0085] 1 - Substrate, 2 - Buffer layer, 3 - Lower confinement layer, 4 - Lower waveguide layer, 5 - Active layer, 6 - Upper waveguide layer, 7 - Transition layer, 8 - Upper confinement layer, 9 - Contact layer, 10 - Quantum well layer, 11 - Barrier, 21 - Side trench, 22 - Ridge waveguide, 23 - Etching groove, 24 - Ridge waveguide segment. Detailed implementation manners

[0086] The following will further elaborate on the general formula compound of the present invention, its preparation method and applications in combination with specific embodiments. It should be understood that the following embodiments are only for illustrative explanation of the present invention and should not be construed as limiting the protection scope of the present invention. All technologies implemented based on the above content of the present invention are covered within the scope intended to be protected by the present invention.

[0087] Unless otherwise specified, the raw materials and reagents used in the following embodiments are commercially available products or can be prepared by known methods.

[0088] Example 1

[0089] See Figure 1 As shown, the specific one - step epitaxial growth process is as follows: On the N+-InP substrate 1, at 550 - 650 °C, using MBE (Molecular Beam Epitaxy) or MOCVD (Metal - Organic Chemical Vapor Deposition) epitaxial growth method, sequentially grow an N - InP buffer layer 2 with a doping concentration of 2×10 18 , 1 μm thick; an N - InGaAsP lower confinement layer 3 with a doping concentration of 0.4×10 18 , 0.1 μm thick; an active layer 5 containing multiple layers of InGaAsP quantum wells; a P - InGaAsP upper confinement layer 8 with a doping concentration of 0.4×10 18 , 0.1 μm thick; grow a P - InP lower protection layer with a doping concentration of 0.4×10 18 , 0.12 μm thick; grow a P - InGaAsP etching stop layer with a doping concentration of 0.4×10 18 , 0.015 μm thick; grow a P - InP upper protection layer with a doping concentration of 1×10 18 , 1.6 μm thick; grow a P+-InGaAs contact layer 9 with a doping concentration of 10×10 18 , 0.2 μm thick; Further, the InGaAs contact layer 9 is specifically an In 0.53 Ga 0.47 As capping layer.

[0090] See Figure 2 As shown, the active layer 5 containing multiple layers of InGaAsP quantum wells contains five layers of InGaAsP quantum well layers. The specific growth method of the active layer 5 is as follows: At 550 - 650 °C, first grow a 6 - nm - thick In 0.557 Ga 0.443As 0.95 P 0.05 Quantum well layer 10, and then grow a 10-nm barrier layer 11 of In 0.738 Ga 0.262 As 0.568 P 0.432 , and then repeat the growth of the previous two steps three times, and finally grow a 6-nm layer of In 0.557 Ga 0.443 As 0.95 P 0.05 Quantum well layer 10 to complete the growth of the active layer 5.

[0091] See Figure 3 As shown, the steps when the depths of the formed ridge waveguide 22 and the etched groove 23 are the same are as follows: deposit a 250-nm SiO2 mask layer on the chip surface; perform photolithography to form a ridge pattern including the etched groove 23; perform ICP etching on the SiO2 mask layer; remove the photoresist; select a corrosion solution of H3PO4:H2O2:H2O with a ratio of 1:1:10 for corrosion or dry-etch the contact layer 9, and select a corrosion solution of HCl:H3PO4 with a ratio of 1:3 for corrosion or dry-etch the upper P-InP protection layer at room temperature to form the ridge waveguide 22, with a corrosion depth of 1 - 1.6 μm and a ridge width of 2 μm; the length of the etched groove 23 is the same as the width of the ridge waveguide 22 in size and direction; the width of the etched groove 23 is 0.5 - 2.5 μm; the depth of the etched groove 23 is 1 - 2 μm; the depth-to-width ratio of the etched groove 23 is less than 4; remove the SiO2 mask layer;

[0092] Furthermore, the steps when the depths of the formed ridge waveguide 22 and the etched groove 23 are different, or when the depths of different etched grooves 23 are different are as follows: (1) deposit a 250-nm SiO2 mask layer on the chip surface; perform photolithography to form a ridge pattern; perform ICP etching on the SiO2 mask layer; remove the photoresist; select a corrosion solution of H3PO4:H2O2:H2O with a ratio of 1:1:10 for corrosion or dry-etch the contact layer, and select a corrosion solution of HCl:H3PO4 with a ratio of 1:3 for corrosion or dry-etch the upper P-InP protection layer at room temperature to form the ridge waveguide 22, with a corrosion depth of 1 - 1.6 μm and a ridge width of 2 μm; (2) deposit a 250-nm SiO2 mask layer on the chip surface; perform photolithography to define the etched groove; perform ICP etching on the SiO2 mask layer; remove the photoresist; corrode or etch to the N-InP buffer layer 2, or the upper P-InGaAsP confinement layer 8, or the lower P-InP protection layer; the length of the etched groove 23 is the same as the width of the ridge waveguide 22 in size and direction; the width of the etched groove 23 is 0.5 - 2.5 μm; the depth of the etched groove 23 is 1 - 5 μm; the depth-to-width ratio of the etched groove 23 is less than 4;

[0093] The steps of forming the ridge waveguide and the etching grooves with different depths are as follows: (1) Deposit a 250-nm SiO2 mask layer on the chip surface; perform photolithography to form a ridge pattern; etch the SiO2 mask layer by ICP; remove the photoresist; use a corrosion solution of H3PO4:H2O2:H2O with a ratio of 1:1:10 or dry-etch the contact layer, and use a corrosion solution of HCl:H3PO4 with a ratio of 1:3 or dry-etch the P-InP upper protection layer at room temperature to form the ridge waveguide 22 with a corrosion depth of 1-1.6 μm and a ridge width of 2 μm; (2) Deposit a 250-nm SiO2 mask layer on the chip surface; define the etching grooves by photolithography; etch the SiO2 mask layer by ICP; remove the photoresist; corrode or etch until reaching the N-InP buffer layer 2, or the P-InGaAsP upper confinement layer 8, or the P-InP lower protection layer; the length and width size and direction of the etching groove 23 are the same as those of the ridge waveguide 22; the width of the etching groove 23 is 0.5-2.5 μm; the depth of the etching groove is 1-5 μm; the depth-to-width ratio of the etching groove is less than 4; (3) Repeat step (2) several times according to the required depth value of the etching groove 23.

[0094] If the groove depth does not exceed the P-InP lower protection layer, that is, it does not enter the active region, then through ion implantation, or depositing a semiconductor or conductive material, a low-resistivity region with a thickness of 50 nm to 200 nm is formed on the inner surface of the groove, so as to increase the pump current provided to the active layer in the groove and reduce the influence of the active region loss in the etching groove on the device performance.

[0095] If the groove penetrates into the active region, then through depositing a semiconductor or conductive material, a low-resistivity region with a thickness of 50 nm to 200 nm is formed on the inner surface of the groove, so as to increase the pump current provided to the active layer in the groove and reduce the influence of the active region loss in the etching groove on the device performance.

[0096] If the groove penetrates through the active region, or deposit an insulating layer with a thickness of 50 nm to 400 nm on the inner surface of the groove to adjust the coupling coefficient between the segments of the ridge waveguide 22, or no deposition treatment is performed.

[0097] Furthermore, the cavity length of the ridge waveguide 22 including the etching groove 23 in the chip is 1000 μm; there are side grooves 21 with a width of 10-20 μm on both sides of the ridge waveguide 22.

[0098] See Figure 3 As shown, select the middle 1 / 3 part (part B) of the ridge waveguide. The length of the ridge waveguide segments is a chirped distribution or a phase-shifted distribution structure; the length of the ridge waveguide segments 24 in the remaining parts (part A and part C) is an equivalent apodized distribution structure. The ratio of the length of each segment 24 of this part of the ridge waveguide to the width of the etching groove is symmetrically selected in the range of 2:1 to 10:1, and a cosine apodization function is used.

[0099] Alternatively, further, the ridge waveguide cavity length of the chip including the etching groove 23 is 1000 μm; there are side grooves 21 with a width of 10 - 20 μm on both sides of the ridge waveguide.

[0100] Select the middle 1 / 3 part (part B) of the ridge waveguide 22, and the width of its etching groove 23 is a chirp distribution or a phase shift distribution structure; the width of the etching groove 23 in the remaining parts (part A and part C) is an equivalent apodization distribution structure. The ratio of the length of the ridge waveguide segment 24 in this part to the width of the etching groove 23 is symmetrically selected in the range of 2:1 to 10:1, and a cosine apodization function is adopted.

[0101] Further, the step of evaporating N and P type electrodes is specifically as follows: deposit a 300 nm SiO2 passivation layer on the chip surface, through photolithography, RIE etch the passivation layer in the exposed area, electron beam evaporate Au(20 nm) / Zn(50 nm) / Au(1000 nm) as the P - side metal, thin the chip substrate to a thickness of 110 - 150 μm, electron beam evaporate AuGe(500 nm) / Ni(800 nm) / Au(1000 nm) as the N - side metal, and alloy at 420 °C in a nitrogen atmosphere for 60 s.

[0102] Further, the coating step is specifically as follows: dissociate the sample into bars with a cavity length of 1000 μm, use electron beam evaporation to deposit a single - layer SiO2 high - transmission film on the light - emitting end face of the chip and a high - reflection film on the back - light end face to complete the production of the chip.

[0103] Example 2

[0104] See Figure 1 As shown, the primary epitaxial growth step is specifically as follows. On the N+-GaAs substrate 1, MBE or MOCVD epitaxial growth is carried out at 550 - 750 °C to grow an N+-GaAs buffer layer 2 with a doping concentration of 2×10 18 , 0.3 μm thick; grow an N+-Al 18 , 1.5 μm thick lower confinement layer 3 of Ga 0.3 As; grow a 0.1 μm thick GaAs lower waveguide layer; grow an active layer 5 containing multiple layers of InGaAs / GaAs quantum wells; grow a 0.08 μm thick GaAs upper waveguide layer 6; grow a transition layer 7 with a doping concentration of 0.4×10 0.7 , 0.015 μm thick of P - Al 18 Ga x As, where x gradually changes from 0 to 0.3; grow a P+-Al 1-x Ga 18 , 1.5 μm thick upper confinement layer 8 of As with a doping concentration of 1×10 0.3 Ga 0.7 As; grow a P+-GaAs cap layer 9 with a doping concentration of 20×10 18, a 0.2-μm-thick P++-GaAs contact layer 9; further, the InGaAs contact layer 9 is specifically an In 0.53 Ga 0.47 As cover layer.

[0105] See Figure 2 As shown, the active layer 5 containing multiple InGaAs / GaAs quantum wells is the active layer 5 containing five InGaAs / GaAs quantum well layers 10, and the specific growth method of the active layer 5 is as follows: First, grow a 10-nm In x Ga 1-x As quantum well layer 10 at 550-750 °C, where x is between 0.1 and 0.4, then grow a 25-nm barrier 11 GaAs, repeat the growth of the previous two steps 3 times, and finally grow a 10-nm In x Ga 1-x As quantum well layer 10 to complete the growth of the active layer 5.

[0106] See Figures 3 to 6 As shown, the specific steps when the depths of the formed ridge waveguide 22 and the etched groove 23 are the same are as follows: Deposit a 250-nm SiO2 mask layer on the chip surface; lithographically form a ridge pattern including the etched groove; ICP-etch the SiO2 mask layer; remove the photoresist; select a 1:1:10 H3PO4:H2O2:H2O etching solution to etch or dry-etch the contact layer, and select a dry-etching process to etch the P+-Al 0.3 Ga 0.7 As upper confinement layer to form the ridge waveguide 22 with an etching depth of 1-1.6 μm and a ridge width of 2 μm; the length of the etched groove 23 is the same as the width of the ridge waveguide 22 in size and direction; the width of the etched groove 23 is 0.5-2.5 μm; the depth of the etched groove 23 is 1-2 μm; the depth-to-width ratio of the etched groove 23 is less than 4; remove the SiO2 mask layer;

[0107] Further, the specific steps when the depths of the formed ridge waveguide and the etched groove are different, or when the depths of different etched grooves are different are as follows: (1) Deposit a 250-nm SiO2 mask layer on the chip surface; lithographically form a ridge pattern; ICP-etch the SiO2 mask layer; remove the photoresist; select a 1:1:10 H3PO4:H2O2:H2O etching solution to etch or dry-etch the contact layer, and select a dry-etching process to etch the P+-Al 0.3 Ga 0.7As the upper confinement layer, a ridge waveguide structure is formed with an etching depth of 1 - 1.6 μm and a ridge width of 2 μm; (2) Deposit a 250-nm SiO2 mask layer on the chip surface; Define the etching grooves by photolithography; Etch the SiO2 mask layer by ICP; Remove the photoresist; Etch or corrode until reaching the N+-GaAs buffer layer or the upper confinement layer; The length of the etching groove 23 is the same as the width of the ridge waveguide 22 in size and direction; The width of the etching groove is 0.5 - 2.5 μm; The depth of the etching groove is 1 - 5 μm; The depth-to-width ratio of the etching groove is less than 4;

[0108] Further, the steps of forming the ridge waveguide and the different etching groove depths are as follows: (1) Deposit a 250-nm SiO2 mask layer on the chip surface; Form a ridge pattern by photolithography; Etch the SiO2 mask layer by ICP; Remove the photoresist; Select a corrosion solution of H3PO4:H2O2:H2O with a ratio of 1:1:10 to corrode or dry-etch the contact layer, and use a dry-etching process to etch P+-Al 0.3 Ga 0.7 As the upper confinement layer, a ridge waveguide structure is formed with an etching depth of 1 - 1.6 μm and a ridge width of 2 μm; (2) Deposit a 250-nm SiO2 mask layer on the chip surface; Define the etching grooves by photolithography; Etch the SiO2 mask layer by ICP; Remove the photoresist; Etch or corrode until reaching the N+-GaAs buffer layer or the upper confinement layer; The length of the etching groove 23 is the same as the width of the ridge waveguide 22 in size and direction; The width of the etching groove is 0.5 - 2.5 μm; The depth of the etching groove is 1 - 5 μm; The depth-to-width ratio of the etching groove is less than 4; (3) Repeat step (2) several times according to different values of the etching groove depth;

[0109] Further, the length of the ridge waveguide cavity with etching grooves in the chip is 1000 μm; There are side trench 21 structures with a width of 10 - 20 μm on both sides of the waveguide. Preferably, the coupling coefficient of the middle 1 / 3 part of the ridge waveguide is a chirped distribution or a phase-shift distribution structure, and the coupling coefficient of the remaining part is an equivalent apodized distribution structure. The ratio of the length of each segment of this part of the ridge waveguide 22 to the width of the etching groove 23 is symmetrically selected in the range of 2:1 to 10:1, and a cosine apodization function is used,

[0110] Further, the steps of evaporating the N and P type electrodes are as follows: Deposit a 300-nm SiO2 passivation layer on the chip surface, etch the passivation layer in the exposed area by photolithography and RIE, evaporate Au(20 nm) / Zn(50 nm) / Au(1000 nm) by electron beam evaporation as the P-side metal, thin the chip substrate to a thickness of 110 - 150 μm, evaporate AuGe(500 nm) / Ni(800 nm) / Au(1000 nm) by electron beam evaporation as the N-side metal, and alloy at 420 °C in a nitrogen atmosphere for 60 s.

[0111] Further, the coating step is specifically as follows: The sample is dissociated into a bar with a cavity length of 1000 μm, and a single-layer SiO2 high-transmission film is deposited on the light-emitting end face of the chip and a high-reflection film is deposited on the backlight end face by electron beam evaporation to complete the production of the chip.

[0112] The above describes the embodiments of the present invention. However, the present invention is not limited to the above embodiments. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A semiconductor quantum well laser, characterized in that, It includes an epitaxial structure which includes a substrate, a buffer layer, a lower confinement layer, an active layer, an upper confinement layer and a contact layer arranged successively from bottom to top; The epitaxial structure further includes: a lower waveguide layer, an upper waveguide layer, a transition layer, a lower protective layer, an etch stop layer and an upper protective layer; The lower waveguide layer is located between the lower confinement layer and the active layer, the upper waveguide layer and the transition layer are successively located between the active layer and the upper confinement layer from bottom to top, and the lower protective layer, the etch stop layer and the upper protective layer are arranged successively between the upper confinement layer and the contact layer from bottom to top; There are a ridge waveguide and a plurality of etch grooves on the upper protective layer, the etch grooves are distributed on the ridge waveguide, and the etch grooves divide the ridge waveguide into a plurality of discontinuous ridge waveguide segments; The distribution along the axial direction of the resonator of the coupling coefficient between the segments of the ridge waveguide, and / or the length of the segments of the ridge waveguide, and / or the width of the etch grooves includes at least two of a tapering distribution, a chirp distribution or a phase shift distribution.

2. The semiconductor quantum well laser according to claim 1, wherein The lengths of the segments of the ridge waveguide in the middle region of the ridge waveguide are in a chirp distribution or a phase shift distribution, and the lengths of the segments of the ridge waveguide in the two side regions are in an equivalent tapering distribution.

3. The semiconductor quantum well laser according to claim 1, characterized in that, The lengths of the segments of the ridge waveguide within the middle 1 / 3 range of the ridge waveguide are in a chirp distribution or a phase shift distribution, and the lengths of the segments of the ridge waveguide within the 1 / 3 range on each side are in an equivalent tapering distribution.

4. The semiconductor quantum well laser according to claim 1, wherein The widths of the etch grooves in the middle region of the ridge waveguide are in a chirp distribution or a phase shift distribution, and the widths of the etch grooves in the two side regions are in an equivalent tapering distribution.

5. The semiconductor quantum well laser according to claim 1, characterized in that, The widths of the etch grooves within the middle 1 / 3 range of the ridge waveguide are in a chirp distribution or a phase shift distribution, and the widths of the etch grooves within the 1 / 3 range on each side are in an equivalent tapering distribution.

6. The semiconductor quantum well laser according to claim 1, characterized in that, The coupling coefficients between the segments within the middle region of the ridge waveguide are in a chirp distribution or a phase shift distribution, and the coupling coefficients in the two side regions are in an equivalent tapering distribution.

7. The semiconductor quantum well laser according to claim 1, characterized in that, The coupling coefficients between the segments within the middle 1 / 3 range of the ridge waveguide are in a chirp distribution or a phase shift distribution, and the coupling coefficients within the 1 / 3 range on each side are in an equivalent tapering distribution.

8. The semiconductor quantum well laser according to any one of claims 1-7, characterized in that, The ratio of the length of the ridge waveguide segment to the width of the etch groove is greater than 1, that is, the duty cycle is greater than 0.

5.

9. The semiconductor quantum well laser according to any one of claims 1-7, characterized in that: The segments of the ridge waveguide and the etch grooves are in an equivalent tapering distribution, and the duty cycle varies within 0.75 - 0.

95.

10. The semiconductor quantum well laser according to any one of claims 1-7, characterized in that, The segments of the ridge waveguide and the etch grooves are in an equivalent tapering distribution and are in a cosine distribution.

11. The semiconductor quantum well laser according to claim 1, characterized in that, Grooves are arranged on both sides of the ridge waveguide parallel to the ridge direction, and the width of the grooves is 10 - 20 μm.

12. The semiconductor quantum well laser according to claim 11, wherein, The depth of the grooves is the same as the height of the ridge waveguide, the depth of the ridge waveguide is 1 - 2.6 μm, and the ridge width is 2 - 4 μm.

13. The semiconductor quantum well laser according to claim 1, wherein The width of the etch grooves is in the same direction as the length of the ridge waveguide, and the etch grooves divide the ridge waveguide into a plurality of ridge waveguide segments.

14. The semiconductor quantum well laser according to any one of claims 1 to 7, characterized in that, The active layer includes several layers of In x Ga 1-x As y P 1-y quantum wells, and the number of layers of the quantum wells ≥ 3 layers; The value range of x is 0 - 1, and the value range of y is 0 - 1; the bandgap width E is determined according to the designed wavelength of the laser g , and the values of x and y need to satisfy the formula: E g = 2.75 - 1.33y - 1.4x + 0.33xy - (0.758 - 0.28y)x(1 - x) - (0.21 - 0.109x)y(1 - y).

15. A method for preparing the semiconductor quantum well laser according to any one of claims 1 to 7, characterized in that, It includes the following steps: Preparing an epitaxial wafer, etching a ridge waveguide and etch grooves on the epitaxial wafer, and evaporating electrodes to obtain a chip; After evaporating the electrodes, the following steps are further included: dissociating the chip into bars along the crystal orientation, and evaporating optical films on the light-emitting and backlight end faces of the bars.

16. The manufacturing method of the semiconductor quantum well laser according to claim 15, characterized in that, Specifically, preparing the epitaxial wafer includes the following steps: The first epitaxial structure is grown by MBE or MOCVD, and its structure sequentially includes a substrate, a buffer layer, a lower confinement layer, an active layer, an upper confinement layer, a lower protection layer, an etch stop layer, an upper protection layer, and a contact layer along the crystal orientation.

17. The manufacturing method of the semiconductor quantum well laser according to claim 15, characterized in that, The steps of etching grooves with different etching depths from the height of the ridge waveguide, or grooves with different depths are as follows: Deposit a 250-nm SiO2 mask layer on the chip surface; perform photolithography to form a ridge pattern; perform ICP etching on the SiO2 mask layer; remove the photoresist; Use an etching solution of H3PO4:H2O2:H2O with a ratio of 1:1:10 to etch the contact layer, and use an etching solution of HCl:H3PO4 with a ratio of 1:3 at room temperature to etch the P-InP upper protection layer to form a ridge waveguide structure; deposit a 250-nm SiO2 mask layer on the chip surface; define the etching grooves by photolithography; perform ICP etching on the SiO2 mask layer; remove the photoresist; etch or corrode to a predetermined depth.

18. The method for preparing a semiconductor quantum well laser according to claim 15, characterized in that, The steps of etching grooves with different etching depths from the height of the ridge waveguide, and grooves with different depths are as follows: a. Deposit a 250-nm SiO2 mask layer on the chip surface; perform photolithography to form a ridge pattern; perform ICP etching on the SiO2 mask layer; remove the photoresist; Use an etching solution of H3PO4:H2O2:H2O with a ratio of 1:1:10 to etch the contact layer, and use an etching solution of HCl:H3PO4 with a ratio of 1:3 at room temperature to etch the P-InP upper protection layer to form a ridge waveguide structure; b. Deposit a 250-nm SiO2 mask layer on the chip surface; define the etching grooves by photolithography; perform ICP etching on the SiO2 mask layer; remove the photoresist; etch to a set depth; c. Repeat b several times according to different values of the etching groove depth.

19. The manufacturing method of the semiconductor quantum well laser according to claim 18, characterized in that, In step c, if the groove depth does not exceed the P-InP lower protection layer, through ion implantation, or depositing a semiconductor or conductive material, a low-resistivity region with a thickness of 50 nm to 200 nm is formed on the inner surface of the groove, so as to increase the pump current provided to the active layer in the groove and reduce the influence of the active region loss in the etching groove on the device performance.

20. The manufacturing method of the semiconductor quantum well laser according to claim 18, characterized in that, In step c, if the groove penetrates into the active region, through depositing a semiconductor or conductive material, a low-resistivity region with a thickness of 50 nm to 200 nm is formed on the inner surface of the groove, so as to increase the pump current provided to the active layer in the groove and reduce the influence of the active region loss in the etching groove on the device performance.

21. The method for preparing a semiconductor quantum well laser according to claim 18, wherein, In step c, if the groove penetrates through the active region, or deposit an insulating layer with a thickness of 50 nm to 400 nm on the inner surface of the groove to adjust the coupling coefficient between each segment of the ridge waveguide, or no deposition treatment is performed.

22. The manufacturing method of the semiconductor quantum well laser according to claim 15, characterized in that, The steps of evaporating electrodes include the following: deposit a SiO2 insulating layer on the etched epitaxial wafer, define the electrode window by photolithography, etch the SiO2 insulating layer, remove the photoresist, define the P electrode by photolithography, deposit the P-side metal, and strip; further perform substrate thinning, deposit the N-side metal, and anneal the alloy.

23. The manufacturing method of the semiconductor quantum well laser according to claim 15, characterized in that, Deposit a 300 nm SiO2 passivation layer on the chip surface. Through photolithography, etch the passivation layer in the exposed area by RIE. Electron beam evaporate Au / Zn / Au as the P-side metal. In Au / Zn / Au, the thickness of each layer is as follows: the thickness of Au is 20 nm, the thickness of Zn is 50 nm, and the thickness of Au is 1000 nm. Thin the chip substrate to a thickness of 110 - 150 μm. Electron beam evaporate AuGe / Ni / Au as the N-side metal. In AuGe / Ni / Au, the thickness of each layer is as follows: the thickness of AuGe is 500 nm, the thickness of Ni is 800 nm, and the thickness of Au is 1000 nm. Alloy for 60 s at 400 - 500 °C in a nitrogen atmosphere.

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