Qubit Frequency Tuning Structure and Manufacturing Method for Flip-Chip Quantum Computing Devices

Abstract

A quantum computing device includes a first chip having a first substrate and one or more qubits disposed on the first substrate. Each of the one or more qubits has an associated resonant frequency. The quantum computing device further includes a second chip having a second substrate and at least one conductive surface disposed on the second substrate opposite the one or more qubits. The at least one conductive surface has at least one dimension configured to adjust the resonant frequency associated with at least one of the one or more qubits to a determined frequency adjustment value.

Description

Technical Field

[0001] The present invention generally relates to a superconductor device, a manufacturing method, and a manufacturing system for tuning qubit frequencies in superconducting quantum devices. More specifically, the present invention relates to a device, a method, and a system for a qubit frequency tuning structure and a manufacturing method for a flip-chip quantum computing device. Background Art

[0002] Hereinafter, unless clearly distinguished in use, the prefix "Q" in a word or phrase indicates a reference to that word or phrase in the context of quantum computing.

[0003] Molecules and subatomic particles follow the laws of quantum mechanics, which is a branch of physics that explores how the physical world works at a fundamental level. At this level, particles behave in strange ways, simultaneously presenting more than one state and interacting with other particles that are very far away. Quantum computing utilizes these quantum phenomena to process information.

[0004] The computers we use now are called traditional computers (also referred to as "conventional" computers or traditional nodes, or "CN" here). Traditional computers use traditional processors, which are manufactured using semiconductor materials and technologies, semiconductor memories, and magnetic or solid-state storage devices, which is called the von Neumann architecture. In particular, the processors in traditional computers are binary processors, that is, they operate on binary data represented by 1 and 0.

[0005] A quantum processor (q-processor) uses the peculiarities of entangled qubit devices (abbreviated as "qubits" in this article, multiple "qubits") to perform computational tasks. In a specific field where quantum mechanics works, matter particles can exist in multiple states, such as an "on" state, an "off" state, and an "on" and "off" state simultaneously. While binary calculations using semiconductor processors are limited to only using the ON and OFF states (equivalent to 1 and 0 in binary code), quantum processors utilize these quantum states of matter to output signals that can be used for data calculations.

[0006] Traditional computers encode information in bits. Each bit can take a value of 1 or 0, and these 1s and 0s are used as on / off switches that ultimately drive the functions of the computer. On the other hand, quantum computers are based on qubits, which operate according to two key principles of quantum physics: superposition and entanglement. Superposition means that each qubit can represent 1 and 0 simultaneously.

[0007] Entanglement means that the qubits in superposition can be related to each other in a non-classical way; that is, the state of one (which is 1 or 0 or both) can depend on the state of the other, and more information can be determined when two qubits are entangled than when they are processed separately.

[0008] Using these two principles, qubits operate as more complex information processors, enabling quantum computers to function in ways that allow them to solve difficult problems that are intractable using conventional computers. IBM has successfully built and demonstrated the operability of a quantum processor using superconducting qubits (IBM is a registered trademark of International Business Machines Corporation in the United States and other countries).

[0009] Superconducting qubits include Josephson junctions. A Josephson junction is a superconducting tunnel junction that is formed by separating two thin-film superconducting metal layers with a non-superconducting material. When the metal in the superconducting layer becomes superconducting, for example by lowering the temperature of the metal to a specific cryogenic temperature, electron pairs can tunnel from one superconducting layer through the non-superconducting layer to the other superconducting layer. In a qubit, the Josephson junction - which acts as a dispersive nonlinear inductor - is electrically coupled in parallel with one or more capacitive devices that form a nonlinear microwave oscillator. The oscillator has a resonant / transition frequency that is determined by the values of the inductance and capacitance in the qubit circuit. Any reference to the term "qubit" refers to a superconducting qubit circuit that employs a Josephson junction, unless explicitly distinguished when used.

[0010] In the superconducting state, a material first offers no resistance to the passage of an electric current. When the resistance drops to zero, an electric current can circulate within the material without any energy dissipation. Second, the material exhibits the Meissner effect, i.e., as long as they are weak enough, an external magnetic field will not penetrate the superconductor but will remain on its surface. When a material no longer exhibits one or both of these properties, the material is said to be in the normal state and is no longer superconducting.

[0011] The critical temperature of a superconducting material is the temperature at which the material begins to exhibit the characteristics of superconductivity. Superconducting materials exhibit very low or zero electrical resistivity to an electric current. The critical field is the highest magnetic field for a given temperature at which the material remains superconducting.

[0012] Superconductors are generally classified into one of two types. Type I superconductors exhibit a single transition at the critical field. When the critical field is reached, a Type I superconductor transitions from the non-superconducting state to the superconducting state. Type II superconductors include two critical fields and two transitions. Below or at the lower critical field, a Type II superconductor exhibits the superconducting state. Above the upper critical field, a Type II superconductor does not exhibit superconductivity. Between the upper and lower critical fields, a Type II superconductor exhibits a mixed state. In the mixed state, a Type II superconductor exhibits an incomplete Meissner effect, i.e., an external magnetic field penetrates the superconducting material in quantized packets at specific locations.

[0013] The information processed by qubits is carried or transmitted in the form of microwave signals / photons within the microwave frequency range. The microwave signals are captured, processed, and analyzed to decrypt the quantum information encoded therein. The readout circuit is a circuit coupled to the qubits to capture, read, and measure the quantum state of the qubits. The output of the readout circuit is information that can be used by the Q processor to perform calculations.

[0014] Superconducting qubits have two quantum states - |0> and |1>. These two states can be two energy states of an atom, for example, the ground state (|g>) and the first excited state (|e>) of a superconducting artificial atom (superconducting qubit). Other examples include spin-up and spin-down of nuclear or electron spins, two positions of a crystal defect, and two states of a quantum dot. Since the system has quantum properties, any combination of the two states is allowed and valid.

[0015] In known semiconductor manufacturing technologies, superconducting devices such as qubits are fabricated using superconducting and semiconductor materials. Superconducting devices typically use one or more layers of different materials to achieve the characteristics and functions of the device. The material layers can be superconducting, conductive, semiconductive, insulating, resistive, inductive, capacitive, or have any number of other properties. Given the nature of the materials, the shape, size, or arrangement of the materials, other materials adjacent to the materials, and many other considerations, different methods may have to be used to form the different material layers.

[0016] Superconducting devices are typically planar, i.e., where the superconducting structures are fabricated on a plane. Non-planar devices are three-dimensional (3D) devices where some structures are formed above or below a given fabrication plane.

[0017] Some qubits are fabricated using flip-chip geometry. In flip-chip geometry, the qubit chip (also referred to as the "Qchip") is fabricated to have multiple individual qubits on a substrate, and one or more connected interposer chips are fabricated on a separate substrate. Solder bumps are deposited onto the chip pads on the first surface of the qubit chip and / or the interposer chip, and the qubit chip or the interposer chip is flipped so that its first side faces down. The qubit chip and the interposer chip are aligned and bump-bonded such that the solder of the solder bumps completes the electrical connection between the qubit chip and the interposer chip.

[0018] The readout circuit typically uses a resonator to couple to the qubits through electromagnetic resonance (usually microwave or radio-frequency resonance). The resonator in the readout circuit includes inductive and capacitive elements. Some qubits are fixed-frequency qubits, i.e., their resonance frequencies are unchangeable. Other qubits are frequency-tunable qubits. The Q processor can employ fixed-frequency qubits, frequency-tunable qubits, or a combination thereof.

[0019] Exemplary embodiments recognize that fixed-frequency qubits are designed to be fixed in frequency to improve noise immunity. Exemplary embodiments recognize that when the resonance frequencies of two coupled qubits on a chip are the same or within a threshold frequency band, or when their higher transition frequencies are in resonance or near resonance, negative effects may occur, such as crosstalk, quantum decoherence, energy decay, generation of mixed states, unintentional information transfer, quantum state leakage, etc. Exemplary embodiments also recognize that such qubits can also negatively affect the performance or utility of certain quantum gates, such as cross-resonance gates that have strict requirements on the frequency spectrum of the resonance frequencies of the qubits on which the gates operate. Exemplary embodiments further recognize that one challenge in a quantum processor based on fixed-frequency qubits is frequency crowding or frequency conflict between adjacent qubits.

[0020] Exemplary embodiments recognize that another challenge in a quantum processor based on fixed-frequency qubits is the low on / off ratio between the interaction between coupled qubits when microwave signals are turned on (turning on the interaction strength) and when these signals are disabled (turning off the interaction strength). Exemplary embodiments further recognize that yet another challenge in a quantum processor based on fixed-frequency qubits is enabling a gate of interest without generating unwanted interactions at other sites. Exemplary embodiments also recognize that defects in manufacturing and the materials used in currently available manufacturing methods for fixed-frequency qubits result in deviations from the expected resonance frequencies.

[0021] Accordingly, there is a need in the art to address the above problems. Summary of the Invention

[0022] In a first aspect, the present invention provides a quantum computing device, comprising: a first chip having a first substrate and one or more qubits disposed on the first substrate, each of the one or more qubits having an associated resonance frequency; and a second chip having a second substrate and at least one conductive surface disposed on the second substrate opposite the one or more qubits, the at least one conductive surface having at least one dimension configured to adjust the resonance frequency associated with at least one of the one or more qubits to a determined frequency adjustment value.

[0023] Viewed from another aspect, the present invention provides a method for providing a quantum computing device, the method comprising: forming a first chip having a first substrate and one or more qubits disposed on the first substrate, each of the one or more qubits having an associated resonance frequency; and forming a second chip having a second substrate and at least one conductive surface disposed on the second substrate opposite the one or more qubits, the at least one conductive surface having at least one dimension configured to adjust the resonance frequency associated with at least one of the one or more qubits to a determined frequency adjustment value.

[0024] Viewed from another aspect, the present invention provides a quantum computing device comprising: a first chip having a first substrate and one or more qubits disposed on the first substrate, each of the one or more qubits having an associated resonance frequency; and a second chip having a second substrate, the second substrate having a groove formed therein, wherein the depth of the groove corresponds to a desired resonance frequency associated with at least one of the one or more qubits.

[0025] Viewed from another aspect, the present invention provides a semiconductor manufacturing system including a lithography component, the semiconductor manufacturing system performing operations when operating on at least one die to manufacture a quantum computing device, the operations comprising: forming a first chip having a first substrate and one or more qubits disposed on the first substrate, each of the one or more qubits having an associated resonance frequency; and forming a second chip having a second substrate and at least one conductive surface disposed on the second substrate opposite the one or more qubits, the at least one conductive surface having at least one dimension configured to adjust the resonance frequency associated with at least one of the one or more qubits to a determined frequency adjustment value.

[0026] Exemplary embodiments provide a superconducting device and its manufacturing method and system. An embodiment of a quantum computing device includes a first chip having a first substrate and one or more qubits disposed on the first substrate. In this embodiment, each of the one or more qubits has an associated resonance frequency. This embodiment further includes a second chip having a second substrate and at least one conductive surface disposed on the second substrate opposite the one or more qubits. In this embodiment, the at least one conductive surface has at least one dimension configured to adjust the resonance frequency associated with at least one of the one or more qubits to a determined frequency adjustment value.

[0027] In another embodiment, the at least one dimension of the conductive surface is based on a measurement of a parameter associated with each of the one or more qubits.

[0028] In another embodiment, the resonant frequency associated with a particular qubit is a predicted resonant frequency calculated based on the measured parameter.

[0029] In another embodiment, the parameter includes the resistance associated with the one or more qubits. In another embodiment, the resistance is the normal state resistance of a junction of the qubit. In another embodiment, the junction is a Josephson junction of the qubit.

[0030] In another embodiment, the at least one dimension is determined based on a change in capacitance to achieve a frequency adjustment value. In another embodiment, the at least one dimension includes at least one of the shape or area of the conductive surface.

[0031] In another embodiment, a frequency adjustment value is determined to mitigate a frequency conflict between the resonant frequencies associated with the one or more qubits.

[0032] In another embodiment, the at least one conductive surface includes a ground plane. In another embodiment, the at least one conductive surface is formed of at least one of a superconducting material or a metallic material.

[0033] In another embodiment, the first chip and the second chip are arranged in a flip-chip configuration. In another embodiment, the first chip and the second chip are coupled together at a predetermined distance based on at least one of a frequency tuning range or a tuning sensitivity.

[0034] In another embodiment, the conductive surface is at least one selected from aluminum, niobium, titanium, titanium nitride, palladium silver, copper, platinum, and gold. In another embodiment, the first substrate is at least one member selected from the group including sapphire, silicon, quartz, gallium arsenide, fused quartz, amorphous silicon, and diamond.

[0035] In another embodiment, the second substrate is at least one member selected from the group including sapphire, silicon, quartz, gallium arsenide, fused quartz, amorphous silicon, and diamond. In another embodiment, the conductive surface is a superconducting material. In another embodiment, the at least one dimension includes the depth of a groove formed in the second substrate.

[0036] In another embodiment, a quantum computing device includes a first chip having a first substrate and one or more qubits disposed on the first substrate, each of the one or more qubits having an associated resonant frequency. In this embodiment, the quantum computing device includes a second chip having a second substrate with a groove formed therein, wherein the depth of the groove corresponds to a desired resonant frequency associated with at least one of the one or more qubits. In another embodiment, the first substrate is at least one member selected from the group consisting of sapphire, silicon, quartz, gallium arsenide, fused quartz, amorphous silicon, and diamond.

[0037] Embodiments include a manufacturing method for manufacturing a quantum computing device. In one embodiment, the method includes depositing a first layer, wherein the at least one conductive surface includes the first layer. In one embodiment, the method includes removing a portion of the first layer.

[0038] In one embodiment, the method includes depositing a second layer on the second substrate, wherein the at least one conductive surface includes the second layer. In one embodiment, the first layer and the second layer are connected. In one embodiment, an open space on the second substrate is provided between the first layer and the second layer. In one embodiment, the groove in the second substrate is provided between the first layer and the second layer.

[0039] In one embodiment, the method includes removing a portion of the second substrate. In one embodiment, the at least one dimension is the depth of the groove formed in the second substrate. In one embodiment, the method includes etching a groove in the second substrate.

[0040] Embodiments include a manufacturing system for manufacturing a quantum computing device. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The novel features believed to be characteristic of the invention are set forth in the appended claims. However, the invention itself, as well as its preferred mode of use, further objects and advantages, will best be understood by reference to the following detailed description of an exemplary embodiment in conjunction with the accompanying drawings, in which:

[0042] Figure 1 A cross-sectional view of an exemplary flip-chip quantum computing device is depicted, which shows problems that can be solved using the exemplary embodiment;

[0043] Figure 2 A cross-sectional view of an example qubit frequency tuning structure for a flip-chip quantum computing device according to an exemplary embodiment is depicted;

[0044] Figure 3 A cross-sectional view of another example qubit frequency tuning structure for a flip-chip quantum computing device according to an exemplary embodiment is depicted;

[0045] Figure 4 depicts an exemplary ground plane design for a qubit frequency tuning structure for a flip-chip quantum computing device according to an exemplary embodiment;

[0046] Figure 5 depicts an example graph for calculating the predicted frequency of a qubit based on a measured junction resistance according to an exemplary embodiment;

[0047] Figure 6 depicts a block diagram of an example insert chip manufacturing process step according to an exemplary embodiment;

[0048] Figure 7 depicts a block diagram of another example insert chip manufacturing process step according to an exemplary embodiment;

[0049] Figure 8 depicts a block diagram of another example insert chip manufacturing process step according to an exemplary embodiment;

[0050] Figure 9 depicts a block diagram of another example insert chip manufacturing process step according to an exemplary embodiment;

[0051] Figure 10 depicts an example variable ground plane design for a qubit frequency tuning structure for a flip-chip quantum computing device according to an exemplary embodiment;

[0052] Figure 11 depicts a flowchart of an example process for manufacturing a qubit frequency tuning structure for a flip-chip quantum computing device according to an exemplary embodiment; and

[0053] Figure 12 depicts a cross-sectional view of an example qubit frequency tuning structure for a multi-qubit flip-chip quantum computing device according to an exemplary embodiment. DETAILED DESCRIPTION

[0054] Exemplary embodiments for describing the present invention generally address and solve the above problems and other related problems by providing a qubit frequency tuning structure for a flip-chip quantum computing device. Exemplary embodiments also provide a manufacturing method and system for manufacturing a qubit frequency tuning structure for a flip-chip quantum computing device.

[0055] Figure 1FIG. 0 depicts an example cross-sectional view of a flip-chip quantum computing device 100, which shows problems that can be solved using an exemplary embodiment. The flip-chip quantum computing device 100 includes a qubit chip 102 having a qubit substrate 103. The qubit substrate 103 includes qubits 104 formed on a first surface of the qubit substrate 103. The qubit substrate 103 includes a material having a high thermal conductivity (above a threshold) in a cryogenic temperature range. For example, the qubit substrate 103 can be formed using sapphire, silicon, quartz, gallium arsenide, fused quartz, amorphous silicon, or diamond for operation in a temperature range of 77K to 0.01K. These examples of substrate materials are not limiting. Those of ordinary skill in the art will be able to think of many other materials suitable for forming the substrate and can conceive of such materials within the scope of the exemplary embodiment according to the present disclosure.

[0056] The flip-chip quantum computing device 100 further includes an insert chip 106 including an insert substrate 107. The insert substrate 107 includes a material having a high thermal conductivity (above a threshold) in a cryogenic temperature range. For example, the insert substrate 107 can be made of materials such as sapphire, silicon, quartz, gallium arsenide, fused quartz, amorphous silicon, or diamond for operation in a temperature range of 77K to 0.01K. These examples of substrate materials are not limiting. Those of ordinary skill in the art will be able to think of many other materials suitable for forming the substrate and can conceive of such materials within the scope of the exemplary embodiment according to the present disclosure.

[0057] The insert chip 106 includes a conventional ground plane 108 formed on a first surface of the insert substrate 107. In a specific embodiment, one or more of the qubit substrate 103 and the insert substrate 107 are formed of silicon or other suitable substrate materials. In a particular embodiment, the ground plane 108 is formed of a superconducting material, a plurality of superconducting materials, a metallic material, or a combination thereof. In this embodiment, the qubit 104 has an associated qubit resonance frequency. The ground plane 108 of the insert chip 106 is joined to the qubit chip 102 through a first bump bond 110A and a second bump bond 110B. The joining forms an electrical connection between the insert chip 106 and the qubit chip 102. In one embodiment, the ground plane 108 is formed using at least one of aluminum, niobium, titanium, titanium nitride, palladium, gold, silver, copper, or platinum for operation in a temperature range of 77K to 0.01K. In one embodiment, the bump bonds 110A, 110B are formed using an indium, tin, and bismuth alloy for operation in a temperature range of 77K to 0.01K. These examples of the ground plane and bump bond materials are not limiting. Those of ordinary skill in the art will be able to think of many other materials suitable for forming the first layer and can conceive of such materials within the scope of the exemplary embodiment according to the present disclosure.

[0058] The qubit resonance frequency is difficult to control due to variations in the Josephson junction (JJ) inductance during fabrication. Josephson junctions fabricated by shadow evaporation, such as by Dolan bridge technology, naturally exhibit variations in their Josephson inductance. For single-junction transmon qubits of the same design and fabrication / processing, each qubit can naturally have a different resonance frequency (e.g., with variations of 100 MHz - 2000 MHz). These conditions can lead to frequency conflicts for fixed-frequency qubits using cross-resonance entanglement gates, such as the frequency conflict between qubit 104 and a second, coupled qubit.

[0059] Exemplary embodiments recognize that preventing frequency conflicts is a challenging problem for fixed-frequency superconducting qubits, and it is difficult to change or modify qubit frequencies using conventional methods after chip fabrication. The frequency of a qubit is inversely proportional to the square root of the product of the Josephson inductance and the total capacitance across the Josephson junction. Thus, methods for resolving frequency conflicts include changing the single-junction transmon qubit frequency by modifying the junction inductance or the total capacitance across the junction (e.g., in parallel with the junction).

[0060] Several methods have been proposed to adjust the junction inductance in order to tune the resonance frequency, but each method has limitations and drawbacks. For example, it is difficult to precisely perform the inductance change. Alternatively, frequency tuning can be performed by changing the capacitance, e.g., by etching the substrate (e.g., a silicon (Si) substrate) in the gap of a planar capacitor to change the effective dielectric constant. However, such etching exposes the Josephson junction to significantly more fabrication processes. In addition, the etching and associated processing may introduce additional loss mechanisms. Moreover, etching and associated processing are typically only available for reducing capacitance and increasing qubit frequency, but not for increasing capacitance and correspondingly reducing qubit frequency.

[0061] One embodiment provides a quantum processor in a flip-chip geometry that includes a qubit chip and an insert chip. The qubit chip includes one or more qubits defined on a substrate. The insert chip includes a conductive region formed of a conductive material (e.g., a superconducting material and / or a metallic material), placed opposite the qubit, and the conductive region is capable of having a variable shape and conductive region coverage to change the resonance frequency of one or more qubits. In this embodiment, the size (e.g., the conductive region and / or shape) of the conductive region opposite each qubit is specifically designed for that particular qubit based on one or more measurements of the qubit, such as an electrical probe of the Josephson junction resistance, to change the resonance frequency of that particular qubit and thereby tune the frequency to a desired value (e.g., to avoid frequency conflicts).

[0062] In one or more embodiments, the conductive regions of the insert chip can vary in size, e.g., size, geometry, pattern, and / or ground connection, to tune the frequency of the qubit to an expected value. In one or more embodiments, the tuning range and sensitivity of the frequency tuning of the insert chip depend on the separation distance between the qubit chip and the insert chip.

[0063] One embodiment provides a novel design and manufacturing method to modify the single-junction qubit frequency of qubits in a flip-chip geometry through capacitive tuning. In this embodiment, the design / manufacturing system uses conventional processes to design and manufacture a qubit chip with one or more qubits, and generates an insert chip design template with blank space above the qubits.

[0064] In one embodiment, the design / manufacturing system measures the Josephson junction (JJ) normal resistance of each qubit, e.g., by electrically probing the JJ resistance of each qubit above the superconducting transition temperature. In this embodiment, the design / manufacturing system calculates the predicted frequency of the qubit based on the measured JJ resistance. In a specific embodiment, the design / manufacturing system uses a fitting curve that correlates the JJ resistance with the frequency to calculate the predicted frequency of each qubit. Although various embodiments describe the measurement of the resistance of the qubit, in other embodiments, the measurement of one or more other suitable parameters, such as capacitance or inductance, can be used.

[0065] In one embodiment, the design / manufacturing system determines possible frequency conflicts based on the predicted frequency of each qubit, and calculates the frequency adjustment for each qubit to avoid or mitigate possible frequency conflicts. In this embodiment, the design / manufacturing system uses the equations described herein to calculate the capacitance change required for each qubit to achieve the calculated frequency adjustment, and determines a specific ground plane design corresponding to the calculated capacitance change. In one embodiment, the design / manufacturing system manufactures the insert substrate and manufactures the ground plane corresponding to the design on the insert substrate.

[0066] In one embodiment, the design / manufacturing system determines the separation gap distance between the insert chip and the qubit chip based on the desired frequency adjustment, frequency tuning range, and sensitivity. In this embodiment, the design / manufacturing system bonds the insert chip and the qubit chip at the separation gap distance to achieve the desired qubit frequency in a flip-chip arrangement. In a specific embodiment, the design / manufacturing system bonds the insert chip and the qubit chip. In one embodiment, the bonding is performed using a bump bonding process. In other specific embodiments, other suitable methods can be used to bond the insert chip and the qubit chip.

[0067] Another embodiment provides a method of manufacturing a qubit frequency tuning structure for a flip-chip quantum computing device such that the method can be implemented as a software application. The application implementing the manufacturing method embodiment can be configured to operate in conjunction with an existing superconducting manufacturing system (e.g., a lithography system).

[0068] For clarity of description and without implying any limitation thereto, an example number of qubits disposed on a substrate is used to describe the exemplary embodiments. Within the scope of the exemplary embodiments, the embodiments can be implemented with different numbers of qubits, different arrangements, superconducting devices other than qubits, types of qubits not based on superconductors, or some combination thereof. The embodiments can be implemented to similarly improve other superconducting manufacturing where a frequency tuning structure is desired for a quantum computing device or superconducting element.

[0069] In addition, simplified diagrams of exemplary frequency tuning structures are used in the drawings and exemplary embodiments. In the actual manufacture of the frequency tuning structure, there may be additional structures not shown or described herein, or structures different from those shown and described herein, without departing from the scope of the exemplary embodiments. Similarly, within the scope of the exemplary embodiments, the structures shown or described in the exemplary frequency tuning structure can be manufactured differently to produce similar operations or results as described herein.

[0070] As described herein, the different shaded portions in the two-dimensional diagrams of the example structures, layers, and formations are intended to represent different structures, layers, materials, and formations in the exemplary manufacture. The different structures, layers, materials, and constructs can be manufactured using suitable materials known to those of ordinary skill in the art.

[0071] The specific shapes, positions, orientations, or dimensions of the shapes described herein are not intended to limit the exemplary embodiments, unless such features are explicitly described as features of the embodiments. The selection of a shape, position, orientation, dimension, or some combination thereof is for clarity of the drawings and the specification only and may have been exaggerated, minimized, or otherwise altered relative to the actual shape, position, orientation, or dimension that may be used in actual lithography to achieve an objective response in accordance with the exemplary embodiments.

[0072] In addition, as an example only, these exemplary embodiments are described with respect to a specific actual or hypothetical superconducting device, such as a qubit. The steps described by the various exemplary embodiments can be adapted to manufacture various frequency tuning structures in a similar manner, and such adaptations are within the scope of the exemplary embodiments.

[0073] When implemented in an application, the embodiments cause a manufacturing process to perform certain steps as described herein. The steps of the manufacturing process are depicted in several figures. In a particular manufacturing process, not all steps are required. Some manufacturing processes may implement the steps in a different order, combine certain steps, remove or replace certain steps, or perform some combination of these and other step operations without departing from the scope of the exemplary embodiments.

[0074] By way of example only, the exemplary embodiments are described with respect to certain types of materials, electrical properties, structures, formations, layer orientations, directions, steps, operations, planes, dimensions, quantities, data processing systems, environments, components, and applications. Any particular manifestation of these and other similar artificial factors is not intended to limit the invention. Any suitable manifestation of these and other similar products may be selected within the scope of the exemplary embodiments.

[0075] The exemplary embodiments are described using specific designs, architectures, layouts, diagrams, and tools, which are by way of example only and not a limitation of the exemplary embodiments. The exemplary embodiments may be used in conjunction with other equivalent or similar purpose designs, architectures, layouts, diagrams, and tools.

[0076] One advantage that the embodiments may provide is that the qubit frequency tuning structure allows for an increase and decrease in the qubit resonance frequency. Another advantage that the embodiments may provide is that no additional processing on the qubit chip is required after manufacturing, which presents no risk of junction damage or failure. Another advantage that the embodiments may provide is to provide precise control over frequency variations in the qubits.

[0077] The examples in this disclosure are for clarity of description only and are not limiting of the exemplary embodiments. Any advantages listed herein are only examples and are not intended to limit the exemplary embodiments. Additional or different advantages may be achieved by particular exemplary embodiments. Moreover, a particular exemplary embodiment may have some, all, or none of the advantages listed above.

[0078] Reference Figure 2 , which depicts a cross-sectional view of an example qubit frequency tuning structure for a flip-chip quantum computing device 200 in accordance with an exemplary embodiment. The flip-chip quantum computing device 200 includes a qubit chip 202 having a qubit substrate 203. The qubit substrate 203 includes qubits 204 formed on a first surface of the qubit substrate 203. In this embodiment, the qubits 204 have an associated qubit resonance frequency. The qubit substrate 203 includes a material having a high thermal conductivity (above a threshold) in a cryogenic temperature range. For example, the qubit substrate 203 may be formed using sapphire, silicon, quartz, gallium arsenide, fused quartz, amorphous silicon, or diamond for operation in a temperature range from 77K to 0.01K.

[0079] The flip-chip quantum computing device 200 further includes an insert chip 206 including an insert substrate 207. The insert substrate 207 includes a material having a high thermal conductivity (above a threshold) in a cryogenic temperature range. For example, the insert substrate 207 may employ materials such as sapphire, silicon, quartz, gallium arsenide, fused quartz, amorphous silicon, or diamond for operation in a temperature range from 77K to 0.01K. These examples of qubit and insert substrate materials are not restrictive. According to the present disclosure, those of ordinary skill in the art will be able to conceive of many other materials suitable for forming the substrate, and these materials can be conceived within the scope of the exemplary embodiments.

[0080] The insert chip 206 includes a qubit frequency tuning structure that includes a ground plane including ground plane portions 208A and 208B formed on a surface of the insert substrate 207 and surrounding an open area (e.g., a non-metallic area) shielding the qubit 204. By varying the open area, shape, and superconducting metal coverage, the resonant frequency of the qubit 204 can be adjusted to avoid or mitigate frequency conflicts between the qubit 204 and another qubit.

[0081] The ground plane portions 208A, 208B of the insert chip 206 are joined to the qubit chip 202 at a determined separation gap distance D1 by a first bump bond 210A and a second bump bond 210B based on a desired frequency adjustment, frequency tuning range, and sensitivity. In a specific embodiment, one or more of the qubit substrate 203 and the insert substrate 207 are formed of a silicon material. In a particular embodiment, the ground planes 208A and 208B are formed of a superconducting or metallic material.

[0082] In an embodiment, at least one of aluminum, niobium, titanium, titanium nitride, palladium, gold, silver, copper, or platinum is used to form the ground planes 208A, 208B for operation in a temperature range from 77K to 0.01K. In an embodiment, indium, tin, and bismuth alloys are used to form the bump bonds 210A, 210B for operation in a temperature range from 77K to 0.01K. These examples of ground plane and bump bond materials are not restrictive. According to the present disclosure, those of ordinary skill in the art will be able to conceive of many other materials suitable for forming the first layer, and these materials can be conceived within the scope of the exemplary embodiments.

[0083] In an embodiment, the resonant frequency of the first qubit 204 is predicted based on a measurement (e.g., a probe measurement) of the JJ resistance of the qubit 204, and a possible frequency conflict between the qubit 204 and other qubits is determined. In this embodiment, the frequency adjustment required for the qubit 204 to avoid a possible frequency conflict, and the capacitance change required for the qubit 204 to implement this frequency adjustment are calculated. In one or more embodiments, each qubit of a qubit circuit may have its own associated ground plane, which has been configured to provide the amount required for frequency adjustment of each qubit.

[0084] Reference Figure 3 , which depicts a cross-sectional view of another exemplary qubit frequency tuning structure for a flip-chip quantum computing device 300 according to an exemplary embodiment. The flip-chip quantum computing device 300 includes a qubit chip 302 having a qubit substrate 303. The qubit substrate 303 includes qubits 304 formed on a first surface of the qubit substrate 303. In this embodiment, the qubits 304 have associated qubit resonant frequencies.

[0085] The flip-chip quantum computing device 300 also includes an insert chip 306 that includes an insert substrate 307. In Figure 3 the embodiment, a portion of the insert substrate 307 is etched at a depth D3 and a width w to remove the dielectric material of the insert substrate 307. The insert chip 306 includes a qubit frequency tuning structure that includes a ground plane, which includes ground plane portions 308A and 308B formed on the surface of the insert substrate 307 and surrounding an open region (e.g., a non-metallic region) that shields the qubit 304. By changing the open region, shape, and superconducting metal coverage, the resonant frequency of the qubit 304 can be adjusted to avoid or mitigate a frequency conflict between the qubit 304 and another qubit.

[0086] The ground plane 308 of the insert chip 306 is bonded to the qubit chip 302 at a determined separation gap distance D2 by a first bump bond 310A and a second bump bond 310B based on a desired frequency adjustment, frequency tuning range, and sensitivity. In a specific embodiment, one or more of the qubit substrate 303 and the insert substrate 307 are formed of a silicon material. In a particular embodiment, the ground plane portions 308A and 308B are formed of a superconducting or metallic material.

[0087] In one embodiment, the respective resonant frequencies of qubit 304 and another qubit are predicted based on measurements of the respective JJ resistances of qubit 304 and the other qubit, and a possible frequency conflict between qubit 304 and the other qubit is determined. In this embodiment, a frequency adjustment is calculated for each of qubit 304 and the other qubits to avoid the possible frequency conflict and the capacitance change required for each of qubit 304 and the other qubits to achieve this frequency adjustment. In one or more embodiments, each qubit of a qubit circuit may have its own associated ground plane, which has been configured to provide the desired amount of frequency adjustment for each qubit.

[0088] Reference Figure 4 , which depicts an exemplary ground plane design for a qubit frequency tuning structure for a flip-chip quantum computing device according to an exemplary embodiment. Perspective view 400 includes a first qubit frequency tuning structure 402A and a second qubit frequency tuning structure 402B. The first qubit frequency tuning structure 402A includes a first qubit 404 formed on a qubit substrate of a qubit chip and a first ground plane design 406 formed on an insert substrate of an insert chip. The first ground plane design 406 is formed as a conductive surface of a conductive material such as a superconducting material and / or a metallic material, and includes a void 408 within the first ground plane design 406. In the illustrated embodiment, the first ground plane design 406 and the void 408 are rectangular in shape.

[0089] The second qubit frequency tuning structure 402B includes a second qubit 410 formed on a qubit substrate of a qubit chip and a second ground plane design 412 formed on an insert substrate of the insert chip. The second ground plane design 412 is formed as a conductive surface of a conductive material such as a superconducting material and / or a metallic material, and is rectangular in shape.

[0090] In the illustrated embodiment, the first ground plane design 406 of the first qubit frequency tuning structure 402A includes less conductive material resulting in a reduced capacitance and has a different shape from the second ground plane design 412 of the second qubit frequency tuning structure 402B. Thus, the first ground plane design 406 provides a different frequency adjustment to the resonant frequency of the first qubit 404 than the frequency adjustment provided to the second qubit 410 by the second ground plane design 412.

[0091] Reference Figure 5 , which depicts an exemplary graph 500 for calculating the predicted frequency of a qubit based on measured junction resistance according to an exemplary embodiment. Figure 5A graph showing the predicted qubit frequency f01 versus the Josephson junction resistance R of the qubit is shown, including a first curve 502 and a second curve 504. According to an embodiment, the resistance of the Josephson junction of the qubit is measured (e.g., by electrical detection) to obtain the resistance R. Based on the measured resistance R, the graph 500 can be used to determine the predicted resonant frequency of the qubit.

[0092] Reference Figure 6 , which depicts a block diagram of an exemplary insert chip manufacturing process step according to an exemplary embodiment. The manufacturing system generates or manipulates an insert chip configuration 600 as described herein. An embodiment causes the manufacturing system to deposit a material 604 to form a ground plane 608 on a first surface of an insert substrate 602. In an embodiment, the material 604 is a thin film deposition of particles 606. In another embodiment, the material 604 is deposited by sputtering. These examples of deposition methods are not limiting. According to the present disclosure, one of ordinary skill in the art will be able to conceive of many other methods and processes suitable for forming a ground plane, and these methods and processes can be conceived within the scope of the exemplary embodiments.

[0093] Reference Figure 7 , which depicts a block diagram of an exemplary insert chip manufacturing process step according to an exemplary embodiment. An embodiment causes the manufacturing system to form ground plane portions 704A, 704B from a ground plane 704 on a first surface of an insert substrate 702. For example, a milling device 706 can be configured to remove a portion of the ground plane 704 to form the ground plane portions 704A, 704B. As another example, etching such as reactive ion etching or wet etching can be used to form the ground plane portions 704A, 704B. Removing the ground plane material reduces the capacitor area of the insert chip configuration 700, thereby changing the effective capacitance and resonant frequency of the corresponding qubit.

[0094] In an embodiment, the milling device 706 is a micro-milling device having a diamond milling cutter or a laser milling cutter. These examples of milling devices are not intended to be limiting. According to the present disclosure, one of ordinary skill in the art will be able to conceive of many other milling devices suitable for removing a portion of the ground plane material on the insert substrate, and these are also considered to be within the scope of the exemplary embodiments. Additionally, according to the present disclosure, one of ordinary skill in the art will be able to conceive of many other devices and methods suitable for removing a portion of the ground plane material on the insert substrate, and these devices and methods are conceived within the scope of the exemplary embodiments.

[0095] Reference Figure 8, the figure depicts a block diagram of an exemplary insert chip manufacturing process step according to an exemplary embodiment. The embodiment enables the manufacturing system to form a groove 808 in the first surface of the insert substrate 802. For example, the milling device 804 can be configured to remove a portion of the insert substrate 802 to form the groove 808. As another example, etching (such as reactive ion etching or wet etching) can be used to form the groove 808. Removing the substrate material reduces the effective dielectric constant of the insert chip configuration 800, thereby reducing the effective capacitance and increasing the resonant frequency of the corresponding qubit.

[0096] In an embodiment, the groove 808 includes a rectangular cross-section. In an embodiment, the groove 808 is formed between the ground plane portions 806A, 806B. In an embodiment, the milling device 804 is a micro-milling device with a diamond milling cutter head or a laser milling device. These examples of milling devices are not restrictive. According to the present disclosure, those of ordinary skill in the art will be able to think of many other milling devices suitable for forming a groove in the first surface of the insert substrate, and these devices can be conceived within the scope of the exemplary embodiment. In addition, according to the present disclosure, those of ordinary skill in the art will be able to conceive of many other devices and methods suitable for forming a groove in the first surface of the insert substrate, and these devices and methods are conceived within the scope of the exemplary embodiment.

[0097] Reference Figure 9 , the figure depicts a block diagram of an exemplary insert chip manufacturing process step according to an exemplary embodiment. The manufacturing system generates or manipulates an insert chip configuration 900 as described herein. The embodiment enables the manufacturing system to deposit a material 906 to form a ground plane 910 on the first surface of the insert substrate 902. In an embodiment, the ground plane 910 connects the ground plane portions 904A, 904B. Depositing the ground plane material changes the capacitor area of the insert chip configuration 900, thereby changing the effective capacitance and resonant frequency of the corresponding qubit.

[0098] In an embodiment, the material 906 is a thin film deposition of particles 908. In another embodiment, the material 906 is deposited by sputtering. These examples of deposition methods are not restrictive. According to the present disclosure, those of ordinary skill in the art will be able to think of many other methods and processes suitable for forming a ground plane, and these methods and processes can be conceived within the scope of the exemplary embodiment.

[0099] Reference Figure 10, which depicts an example variable ground plane design of a qubit frequency tuning structure for a flip-chip quantum computing device according to an exemplary embodiment. Perspective view 1000 includes a first qubit frequency tuning structure 1002A, a second qubit frequency tuning structure 1002B, a third qubit frequency tuning structure 1002C, a fourth qubit frequency tuning structure 1004A, a fifth qubit frequency tuning structure 1004B, a sixth qubit frequency tuning structure 1004C, a seventh qubit frequency tuning structure 1006A, an eighth qubit frequency tuning structure 1006B, and a ninth qubit frequency tuning structure 1006C. The process steps in Figures 6 - 9 can be used to form the qubit frequency tuning structure.

[0100] Each of the qubit frequency tuning structures 1002A - 1002C, 1004A - 1004C, and 1006A - 1006C includes a qubit formed on a qubit chip and an associated ground plane design formed on an insert chip. Each of the qubit frequency tuning structures 1002A - 1002C, 1004A - 1004C, and 1006A - 1006C has a different ground plane size and shape, which are configured to have different capacitance values and provide corresponding different amounts of frequency tuning of the associated qubit.

[0101] The qubit frequency tuning structures 1002A - 1002C have a rectangular ground plane design with a central rectangular void.

[0102] The rectangular voids within each of 1002A - 1002C have different sizes and different conductor material areas, resulting in different capacitances and frequency tuning for the associated qubits.

[0103] The quantum frequency tuning structures 1004A - 1004C have an external rectangular ground plane and an internal rectangular ground plane, which is positioned to have a void with respect to the external rectangular ground plane and is not connected to the external rectangular ground plane. The internal ground plane of each of 1004A - 1004C has a different size and different conductor material area, resulting in different capacitances and frequency tuning for the associated qubits.

[0104] The quantum frequency tuning structures 1006A - 1006C have an external rectangular ground plane and an internal rectangular ground plane, which is positioned to have a void with respect to the external rectangular ground plane and is connected to the external rectangular ground plane at each edge. The internal ground plane of each of 1006A - 1006C has different sizes and different conductor material areas, resulting in different capacitances and frequency tuning for the associated qubits.

[0105] Reference Figure 11 This figure depicts a flowchart of an exemplary process 1100 for fabricating a qubit frequency tuning structure for a flip-chip quantum computing device according to an exemplary embodiment. In one or more embodiments, process 1100 is implemented in part by a manufacturing system.

[0106] In block 1102, a user designs a qubit chip having one or more qubits using a known process. In block 1104, the user designs an insert chip template having empty space above the qubits. In block 1106, the manufacturing system fabricates a qubit chip including one or more qubits on a qubit substrate.

[0107] In block 1108, a manufacturing system measures the Josephson junction (JJ) resistance of each qubit, e.g., by electrically probing the JJ resistance of each qubit. In block 1110, the manufacturing system calculates the predicted frequency of each qubit based on the measured JJ resistance. In a particular embodiment, the design / fabrication system uses a fitting curve that correlates JJ resistance with frequency to calculate the predicted frequency of each qubit, e.g., Figure 5 graph 500.

[0108] In block 1112, the manufacturing system determines possible frequency conflicts based on the predicted frequency of each qubit. In block 1114, the manufacturing system calculates a frequency adjustment for each qubit to avoid or mitigate possible frequency conflicts. In block 1116, the manufacturing system calculates the capacitance change required for each qubit to achieve the calculated frequency adjustment. In block 1118, the manufacturing system determines a specific insert ground plane design corresponding to the calculated capacitance change. In a particular embodiment, the manufacturing system selects a predefined ground plane design configured to achieve the desired capacitance change, e.g., Figure 10 one or more of the ground plane designs shown in.

[0109] In block 1120, the manufacturing system fabricates an insert substrate for the insert chip. In block 1122, the manufacturing system fabricates a ground plane on the insert substrate corresponding to the determined ground plane design. In block 1124, the manufacturing system determines a separation gap distance between the insert chip and the qubit chip based on the desired frequency adjustment, frequency tuning range, and sensitivity.

[0110] In block 1126, the manufacturing system joins the insert chip and the qubit chip at the determined separation gap distance to achieve the desired qubit frequency in a flip-chip arrangement. In a particular embodiment, the manufacturing system joins the insert chip and the qubit chip using a bump bonding process. In other specific embodiments, other suitable methods may be used to join the insert chip and the qubit chip. Then, process 1100 ends.

[0111] Reference Figure 12 , which depicts a cross-sectional view of an exemplary qubit frequency tuning structure for a multi-qubit flip-chip quantum computing device 1200 according to an exemplary embodiment. The flip-chip quantum computing device 1200 includes a qubit chip having a qubit substrate 1202. The qubit substrate 1202 includes a first qubit 1204A and a second qubit 1204B formed on a first surface of the qubit substrate 1202. In this embodiment, the first qubit 1204A and the second qubit 1204B each have an associated qubit resonance frequency. A first qubit contact 1208A, a second qubit contact 1208B, and a third qubit contact 1208C are formed on the surface of the qubit substrate 1202. The first qubit 1204A is disposed between the first qubit contact 1208A and the second qubit contact 1208B, and the second qubit 1204B is disposed between the second qubit contact 1208B and the third qubit contact 1208C.

[0112] The flip-chip quantum computing device 1200 further includes an insert chip 1206, which includes an insert substrate 1207. The insert chip 1206 includes a qubit frequency tuning structure, which includes ground plane portions 1210A, 1210B, and 1210C formed on the surface of the insert substrate 1207. The first ground plane portion 1210A and the second ground plane portion 1210B partially cover a portion of the first qubit 1204A, and an open area (e.g., a non-metallic area) between the first ground plane portion 1210A and the second ground plane portion 1210B shields the first qubit 1204A. Similarly, the second ground plane portion 1210B and the third ground plane portion 1210C partially cover a portion of the second qubit 1204B, and an open area (e.g., a non-metallic area) between the second ground plane portion 1210B and the third ground plane portion 1210C shields the second qubit 1204B. By varying the open area, shape, and superconducting metal coverage of each of the ground plane portions 1210A - 1210C, the resonance frequency of each of the first qubit 1204A and the second qubit 1204B can be adjusted to avoid or mitigate frequency conflicts between the first qubit 1204A and the second qubit 1204B.

[0113] The first ground plane portion 1210A of the insert chip 1206 is bonded to the first qubit contact 1208A through the first bump bond 1212A, and the second ground plane portion 1210B is bonded to the second qubit contact 1208B through the second bump bond 1212B and the third bump bond 1212C. The third ground plane portion 1210C is bonded to the third qubit contact 1208C through the fourth bump bond 1212D. In a specific embodiment, one or more of the qubit substrate 1202 and the insert substrate 1207 are formed of a silicon material. In a particular embodiment, the ground plane portions 1210A to 1210C are formed of a superconducting or metallic material.

[0114] In an embodiment, the resonance frequency of each of the first qubit 1204A and the second qubit 1204B is predicted based on the measurement of the JJ resistance of each of the first qubit 1204A and the second qubit 1204B, and a possible frequency conflict between the first qubit 1204A and the second qubit 1204B is determined. In this embodiment, a frequency adjustment for each of the first qubit 1204A and the second qubit 1204B is calculated to avoid a possible frequency conflict and the capacitance change required for each of the first qubit 1204A and the second qubit 1204B to achieve this frequency adjustment. In one or more embodiments, each qubit of the qubit circuit (e.g., the first qubit 1204A and the second qubit 1204B) may have its own associated ground plane, which has been constructed to adjust the frequency of each qubit by the desired amount.

[0115] Various embodiments of the present invention are described herein with reference to the related drawings. Alternative embodiments may be designed without departing from the scope of the present invention. Although various connection and positional relationships between elements (e.g., top, bottom, above, below, adjacent, etc.) are set forth in the following description and drawings, those skilled in the art will recognize that many of the positional relationships described herein are orientation-independent when the described functions are maintained even when the orientation is changed. Unless otherwise stated, these connections and / or positional relationships may be direct or indirect, and the present invention is not intended to be limited in this regard. Thus, the coupling of entities may refer to direct or indirect coupling, and the positional relationship between entities may be direct or indirect positional relationship. As an example of an indirect positional relationship, the formation of layer "A" on layer "B" as mentioned in this specification includes the case where one or more intermediate layers (e.g., layer "C") are between layer "A" and layer "B", as long as the relevant characteristics and functions of layer "A" and layer "B" are not substantially changed by the intermediate layer.

[0116] The following definitions and abbreviations are used to interpret the claims and the specification. As used herein, the terms "comprising", "including", "having", "containing", or any other variation thereof are intended to cover a non-exclusive inclusion. For example, a composition, mixture, process, method, article, or apparatus that comprises a series of elements is not necessarily limited to those elements, but may include other elements not expressly listed or inherent to such composition, mixture, process, method, article, or apparatus.

[0117] Additionally, the term "exemplary" is used herein to mean "serving as an example, instance, or illustration". Any embodiment or design described herein as "exemplary" is not necessarily to be construed as more preferred or advantageous than other embodiments or designs. The terms "at least one" and "one or more" are understood to include any integer greater than or equal to one, i.e., one, two, three, four, etc. The term "plurality" shall be understood to include any integer greater than or equal to two, i.e., two, three, four, five, etc. The term "connected" may include indirect "connection" and direct "connection".

[0118] References in the specification to "embodiments", "example embodiments", etc., indicate that the described embodiments may include a particular feature, structure, or characteristic, but each embodiment may or may not include that particular feature, structure, or characteristic. Moreover, these phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is considered within the knowledge of one of ordinary skill in the art to effect such feature, structure, or characteristic in connection with other embodiments, whether or not expressly described.

[0119] The terms "about", "substantially", "approximately", and variations thereof are intended to include the degree of error associated with a measurement of a particular quantity based on the equipment available at the time of filing the present application. For example, "about" may include a range of ±8% or 5% or 2% of a given value.

[0120] The description of the various embodiments of the present invention has been presented for purposes of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to one of ordinary skill in the art without departing from the scope of the described embodiments. The terms used herein were chosen to best explain the principles of the embodiments, the practical application, or the technical improvement over technologies found in the marketplace, or to enable other ordinary skilled artisans in the art to understand the embodiments described herein.

Claims

1. A quantum computing device, comprising: A first chip having a first substrate and one or more qubits disposed on the first substrate, each of the one or more qubits having an associated resonant frequency; and A second chip having a second substrate and at least one conductive surface disposed on the second substrate opposite the one or more qubits, a groove being formed in the second chip, the groove extending through an open area in the at least one conductive surface at least to the second substrate, the at least one conductive surface having at least one dimension configured to adjust the resonant frequency associated with at least one of the one or more qubits to a determined frequency adjustment value.

2. The quantum computing device according to claim 1, wherein at least one dimension of the conductive surface is based on a measurement of a parameter associated with each of the one or more qubits.

3. The quantum computing device according to claim 2, wherein the resonant frequency associated with a particular qubit is a predicted resonant frequency calculated based on the measured parameter.

4. The quantum computing device according to any one of claims 2 or 3, wherein the parameter includes a resistance associated with the one or more qubits.

5. The quantum computing device according to claim 4, wherein the resistance is the normal state resistance of the junction of the qubit.

6. The quantum computing device according to claim 5, wherein the junction is a Josephson junction of the qubit.

7. The quantum computing device according to any one of claims 1, 2 or 3, wherein the at least one dimension is determined based on a change in capacitance to achieve the frequency adjustment value.

8. The quantum computing device according to any one of claims 1, 2 or 3, wherein the at least one dimension includes at least one of the shape or area of the conductive surface.

9. The quantum computing device according to any one of claims 1, 2 or 3, wherein the frequency adjustment value is determined to mitigate a frequency conflict between the resonant frequencies associated with the one or more qubits.

10. The quantum computing device according to any one of claims 1, 2 or 3, wherein the at least one conductive surface includes a ground plane.

11. The quantum computing device according to any one of claims 1, 2 or 3, wherein the at least one conductive surface is formed of at least one of a superconducting material or a metallic material.

12. The quantum computing device according to any one of claims 1, 2 or 3, wherein the first chip and the second chip are arranged in a flip-chip configuration.

13. The quantum computing device according to any one of claims 1, 2 or 3, wherein the first chip and the second chip are coupled together at a predetermined distance based on at least one of a frequency tuning range or a tuning sensitivity.

14. The quantum computing device according to any one of claims 1, 2 or 3, wherein the conductive surface is at least one member selected from the group consisting of aluminum, niobium, titanium, titanium nitride, palladium, silver, copper, platinum and gold.

15. The quantum computing device according to any one of claims 1, 2, or 3, wherein the first substrate is at least one member selected from the group consisting of sapphire, silicon, quartz, gallium arsenide, fused quartz, amorphous silicon, and diamond.

16. The quantum computing device according to any one of claims 1, 2, or 3, wherein the second substrate is at least one member selected from the group consisting of sapphire, silicon, quartz, gallium arsenide, fused quartz, amorphous silicon, and diamond.

17. The quantum computing device according to any one of claims 1, 2, or 3, wherein the conductive surface is a superconducting material.

18. The quantum computing device according to any one of claims 1, 2, or 3, wherein the at least one dimension includes the depth of the groove formed in the second substrate.

19. The quantum computing device according to any one of claims 1, 2, or 3, wherein the second substrate includes the groove formed therein, and the depth of the groove corresponds to the desired resonance frequency associated with at least one of the one or more qubits.

20. A method for providing a quantum computing device, the method comprising: Form a first chip having a first substrate and one or more qubits disposed on the first substrate, each of the one or more qubits having an associated resonant frequency; and Form a second chip having a second substrate and at least one conductive surface disposed on the second substrate opposite the one or more qubits, the at least one conductive surface including an open area, the at least one conductive surface having at least one dimension of the open area configured to adjust the resonant frequency associated with at least one of the one or more qubits to a determined frequency adjustment value.

21. The method according to claim 20, wherein the at least one dimension of the conductive surface is based on a measurement of a parameter associated with each of the one or more qubits.

22. The method according to claim 21, wherein the resonance frequency associated with a particular qubit is a predicted resonance frequency calculated based on the measured parameter.

23. The method according to claim 21, wherein the parameter includes a resistance associated with the one or more qubits.

24. The method according to claim 23, wherein the resistance is the normal state resistance of the junction of the qubit.

25. The method according to any one of claims 20 to 23, further comprising: Deposit a first layer, wherein the at least one conductive surface includes the first layer.

26. The method according to claim 25, further comprising: Remove a portion of the first layer.

27. The method according to claim 25, further comprising: Deposit a second layer on the second substrate, wherein the at least one conductive surface includes the second layer.

28. The method according to claim 27, wherein the first layer and the second layer are connected.

29. The method according to claim 27, wherein the open space on the second substrate is disposed between the first layer and the second layer.

30. The method according to claim 27, wherein the groove in the second substrate is disposed between the first layer and the second layer.

31. The method according to any one of claims 20 to 23, further comprising: Remove a portion of the second substrate.

32. The method according to any one of claims 20 to 23, wherein the at least one dimension is the depth of the groove formed in the second substrate.

33. The method according to claim 32, further comprising: Etch the groove in the second substrate.

34. A quantum computing device, comprising: A first chip having a first substrate and one or more qubits disposed on the first substrate, each of the one or more qubits having an associated resonant frequency; and A second chip having a second substrate, the second chip having at least one conductive surface disposed on the second substrate opposite the one or more qubits, the second substrate having a groove formed therein, the groove extending through an open area in the at least one conductive surface at least to the second substrate, wherein a depth of the groove corresponds to a desired resonant frequency associated with at least one of the one or more qubits.

35. The quantum computing device according to claim 34, wherein the first substrate is at least one member selected from the group consisting of sapphire, silicon, quartz, gallium arsenide, fused quartz, amorphous silicon, and diamond.

36. A semiconductor manufacturing system including a lithography component, the semiconductor manufacturing system performing operations including the following when operating on at least one die to manufacture a quantum computing device: Forming a first chip having a first substrate and one or more qubits disposed on the first substrate, each qubit of the one or more qubits having an associated resonance frequency; and Forming a second chip having a second substrate and at least one conductive surface disposed on the second substrate opposite the one or more qubits, a groove being formed in the second chip, the groove extending through an open area in the at least one conductive surface at least to the second substrate, the at least one conductive surface having at least one dimension configured to adjust the resonance frequency associated with at least one of the one or more qubits to a determined frequency adjustment value.

37. The semiconductor manufacturing system according to claim 36, wherein the at least one dimension of the conductive surface is based on a measurement of a parameter associated with each of the one or more qubits.

38. The semiconductor manufacturing system according to claim 37, wherein the resonance frequency associated with a particular qubit is a predicted resonance frequency calculated based on the measured parameter.

39. The semiconductor manufacturing system according to any one of claims 37 or 38, wherein the parameter includes a resistance associated with the one or more qubits.

40. The semiconductor manufacturing system according to claim 39, wherein the resistance is a normal state resistance of a junction of the qubit.

41. The semiconductor manufacturing system according to any one of claims 36 to 38, wherein the at least one dimension is determined based on a capacitance change to achieve the frequency adjustment value.

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