Design Methods of Digital Integrated Circuits

Abstract

Disclosed is a digital integrated circuit design method that extracts the timing characteristics of the rising and falling edges of a double-edge dynamic trigger, obtains a first library with relatively large timing characteristic parameters, unifies the first library into a rising-edge trigger type, and obtains a first process library file. The method then executes the design input, logic synthesis, formal verification, layout and routing, timing checking, and physical verification of a traditional design process, as well as the corresponding simulation process, based on the double-edge dynamic trigger functional model and the first process library file. The digital integrated circuit design method of the present invention creates a first process library file based on the relatively large timing characteristic parameters in the timing characteristics of the rising and falling edges, executes the traditional design process based on the first process library file, and simplifies the integration of double-edge dynamic triggers in digital integrated circuit design while ensuring the reliability of the designed circuit, thereby facilitating the application of double-edge dynamic triggers in digital integrated circuits.

Description

Technical Field

[0001] The present invention relates to the technical field of digital integrated circuit design, and in particular to a design method for a digital integrated circuit. Background Art

[0002] With the widespread application of digital signal processing, filter units, convolution operations, etc. are needed in the design of digital signal processing circuits. These operation units consume a lot of triggers.

[0003] According to statistics in chip design, the power consumption of the trigger unit in the digital signal processing design will account for more than 50% of the entire chip.

[0004] Traditional triggers are all single-edge triggers, while double-edge dynamic triggers can trigger data twice in one clock cycle to process different data. Compared with single-edge triggers, double-edge dynamic triggers can reduce the frequency of the clock signal to half, which can effectively reduce the area and power consumption of the clock path and the trigger itself.

[0005] Therefore, applying double-edge dynamic triggers to the design of digital integrated circuits can effectively reduce the overall power consumption of the system and has considerable practical value. Summary of the Invention

[0006] In view of the above problems, the purpose of the present invention is to provide a design method for digital integrated circuits, so as to apply double-edge dynamic triggers to the design of digital integrated circuits, thereby facilitating the reduction of system power consumption of designed chips.

[0007] According to one aspect of the present invention, there is provided a method for designing a digital integrated circuit, comprising:

[0008] Extracting the features of the rising edge and the falling edge of the double-edge dynamic trigger respectively to obtain a first library and a second library, wherein the timing characteristic parameters of the first library are greater than the timing characteristic parameters of the second library;

[0009] Modify the first library to a rising edge trigger type to obtain a first process library file;

[0010] Add the double-edge trigger feature to the double-edge dynamic trigger of the simulation library to obtain a double-edge dynamic trigger functional model with double-edge trigger feature;

[0011] According to the double-edge dynamic trigger functional model and the first process library file, design input, logic synthesis, formal verification, layout and routing, timing check, and physical verification are sequentially performed until the design is completed, and,

[0012] Perform RTL functional simulation according to the RTL level circuit description file obtained in the design input step;

[0013] Performing netlist function simulation based on the first gate-level netlist obtained in the logic synthesis step;

[0014] Netlist timing simulation is performed based on the second gate-level netlist and digital layout obtained in the placement and routing step.

[0015] Optionally, in the step of respectively extracting features of the rising edge and the falling edge of the double-edge dynamic trigger, features of the timing and power consumption of the rising edge and the falling edge of the double-edge dynamic trigger are respectively extracted.

[0016] Optionally, it also includes:

[0017] Modify the second library to a rising edge trigger type to obtain a second process library file,

[0018] Modify the first library and the second library to the falling edge trigger type to obtain the third process library file and the fourth process library file respectively,

[0019] Wherein, the timing check step performs timing check according to the first process library file, the second process library file, the third process library file and the fourth process library file at the same time.

[0020] Optionally, in the steps of logic synthesis, formal verification, and layout and routing, the corresponding double-edge dynamic trigger of the double-edge dynamic trigger functional model is used as a single-edge trigger, and the data trigger frequency is the same as the data trigger frequency of the double-edge dynamic trigger.

[0021] Optionally, in the steps of performing netlist functional simulation according to the first gate-level netlist obtained in the logic synthesis step, and performing netlist timing simulation according to the second gate-level netlist and digital layout obtained in the layout and routing step, the corresponding double-edge dynamic trigger of the double-edge dynamic trigger functional model behaves as a double-edge dynamic trigger.

[0022] Optionally, it also includes:

[0023] Modify the second library to a rising edge trigger type to obtain a second process library file,

[0024] The layout and routing step performs an automatic layout and routing process according to the first process library file and the second process library file at the same time.

[0025] Optionally, the step of adding a double-edge trigger characteristic to the double-edge dynamic trigger of the simulation library further includes performing a timing check on the maximum clock time according to the requirement of the double-edge dynamic trigger on the clock length.

[0026] The digital integrated circuit design method provided by the present invention collects rising edge timing characteristics and falling edge timing characteristics of a double-edge dynamic trigger to obtain a first library with a relatively large timing requirement, and unifies the first library into a rising edge trigger type to obtain a first process library file. Then, based on the double-edge dynamic trigger functional model and the first process library file, the design input, logic synthesis, formal verification, layout and routing, timing check and physical verification of a traditional design process, as well as RTL functional simulation, netlist functional simulation and netlist timing simulation processes are performed. The double-edge dynamic trigger is integrated into the design of the digital integrated circuit, and the first process library file is prepared based on the timing characteristics with relatively large timing requirements among the rising edge timing characteristics and the falling edge timing characteristics. The traditional design process is performed based on the first process library file. While ensuring the reliability of the designed circuit, the integration of the double-edge dynamic trigger in the digital integrated circuit design is simplified, the application of the double-edge dynamic trigger in the digital integrated circuit is facilitated, and the power consumption of the designed digital integrated circuit system is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0028] Figure 1 A schematic structural diagram of a double-edge-edged dynamic trigger according to the prior art is shown;

[0029] Figure 2 A schematic diagram of data triggering of a double-edge dynamic trigger according to the prior art is shown;

[0030] Figure 3 A flow chart of a method for designing a digital integrated circuit according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0031] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, identical elements are represented by identical or similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale.

[0032] The specific implementation of the present invention is further described in detail below with reference to the accompanying drawings and examples.

[0033] Figure 1 A schematic structural diagram of a double-edge-edge dynamic trigger according to the prior art is shown.

[0034] Reference Figure 1The double-edge dynamic trigger includes a transistor MP1, a transistor MP2, a transistor MN1, and a transistor MN2 connected in series between a first reference voltage source and a second reference voltage source. The transistor MP3 and the transistor MN3 are connected in series in parallel with the series structure of the transistor MP2 and the transistor MN1. The gates of the transistor MP1 and the transistor MN2 are connected to the input terminal D of the double-edge dynamic trigger. The gates of the transistor MP2 and the transistor MN3 receive the second clock signal CK2. The gates of the transistor MN1 and the transistor MP3 receive the first clock signal CK1. A first level signal OUT1 is provided at an intermediate node between the transistor MP1 and the transistor MN1, and a second level signal OUT2 is provided at an intermediate node between the transistor MP3 and the transistor MN3.

[0035] In this embodiment, the transistors MP1 , MP2 , and MP3 are PMOS (P-Metal-Oxide-Semiconductor) transistors, and the transistors MN1 , MN2 , and MN3 are NMOS (N-Metal-Oxide-Semiconductor) transistors.

[0036] The clock signal CP received at the clock signal input end is converted into a first clock signal CK1 and a second clock signal CK2 of mutually inverted phases by inverters A1 and A2 connected in series. When the first clock signal CK1 is at a high level and the second clock signal CK2 is at a low level, transistors MP2 and MN1 are turned on, and the first-level signal OUT1 is set to the first level VDD (high-level reference, corresponding to the digital signal 1) or the second level VSS (low-level reference, corresponding to the digital signal 0) according to the state of the input data, thereby realizing rising-edge triggering; when the first clock signal CK1 is at a low level and the second clock signal CK2 is at a high level, transistors MP3 and MN3 are turned on, and the second-level signal OUT2 is set to the first level VDD or the second level VSS according to the state of the input data, thereby realizing falling-edge triggering.

[0037] The first level signal OUT1 is transmitted to the output terminal Q of the double-edge dynamic trigger through latch A3, and the second level signal OUT2 is transmitted to the output terminal Q of the double-edge dynamic trigger through latch A4. Latch A3 and latch A4 are time-sharing opened according to the first clock signal CK1 and the second clock signal CK2. When the first clock signal CK1 is high and the second clock signal CK2 is low, the rising edge is triggered, and latch A3 is turned on at the same time, and the first level signal OUT1 is output to realize rising edge triggered data output; when the first clock signal CK1 is low and the second clock signal CK2 is high, the falling edge is triggered, and latch A4 is turned on at the same time, and the second level signal OUT2 is output to realize falling edge triggered data output.

[0038] Figure 2 A data triggering schematic diagram of a double-edge dynamic trigger according to the prior art is shown.

[0039] Reference Figure 2 When data is input to input terminal D, the corresponding data output is provided at output terminal Q according to the input clock signal CP. When the first rising edge of the clock signal CP is triggered, data A is collected, and output terminal Q outputs data Aq. When the first falling edge is triggered, data B is collected, and output terminal Q outputs data Bq. When the rising edge of the second cycle of the clock signal CP is triggered, data C is collected, and output terminal Q outputs data Cq. Data can be collected twice in one clock cycle, and the clock cycle is equal to twice the unit length of the data. In contrast, a single-edge trigger collects data once in one clock cycle, and the clock cycle is equal to the unit length of the data. That is, the double-edge dynamic trigger has a long clock cycle, low frequency, and low power consumption.

[0040] Among them, the design method of the digital integrated circuit in the embodiment of the present invention mainly adopts the above-mentioned double-edge dynamic trigger, which has a small number of transistors, can reduce the area occupied by the double-edge dynamic trigger on the chip layout, reduce wiring complexity, optimize chip area, and reduce costs.

[0041] Figure 3 A flow chart of a method for designing a digital integrated circuit according to an embodiment of the present invention is shown.

[0042] Reference Figure 3 , the design method of a digital integrated circuit according to an embodiment of the present invention includes:

[0043] In step S11 , timing features are extracted from the double-edge-triggered dynamic trigger circuit to obtain a first library file and a second library file (or simply the first library and the second library).

[0044] The double-edge dynamic trigger circuit in step S11 is: Figure 1 The double-edge dynamic trigger circuit is shown.

[0045] In step S11, the timing characteristics (including timing characteristics and power consumption characteristics) of the rising edge and falling edge of the double-edge dynamic trigger circuit are extracted respectively, that is, two timing characteristic extraction operations are performed, and the extracted library files are classified according to the size of the timing characteristic parameters (delay information, driving capability, etc.). After classification, a first library file and a second library file are obtained, and the timing characteristic parameters of the first library file are greater than the timing characteristic parameters of the second library file.

[0046] The program parameters of the timing characteristic parameters include but are not limited to setuptime, holdtime, risetime, and falltime, i.e., setup time, hold time, rise time (level rise time), and fall time (level fall time). In step S11, the extracted timing characteristic parameters of the double-edge dynamic trigger are, for example:

[0047] The timing characteristic parameters extracted from the simulation of the rising edge trigger timing are: setuptime=0.50, holdtime=0.20, risetime=0.30, falltime=0.25; the timing characteristic parameters extracted from the simulation of the falling edge trigger timing are: setuptime=0.44, holdtime=0.22, risetime=0.31, falltime=0.23, where the unit is nanoseconds (ns).

[0048] Correspondingly, by processing the parameters based on their values, the timing characteristic parameters for the first library file are: setuptime = 0.50, holdtime = 0.22, risetime = 0.31, and falltime = 0.25. The timing characteristic parameters for the second library file are: setuptime = 0.44, holdtime = 0.20, risetime = 0.30, and falltime = 0.23. By unifying the trigger types of the first and second library files to rising edge triggering or falling edge triggering, the corresponding process library files can be obtained.

[0049] In step S12, the timing requirements of the large value and the small value are found, and the process library is uniformly produced according to the rising edge, that is, the first library file and the second library file are modified to the rising edge trigger type, and the first process library file and the second process library file are obtained, and the first process library file is a large value process library, and the second process library file is a small value process library.

[0050] The first process library file and the second process library file correspond to process library files of a model library of a double-edge dynamic trigger.

[0051] Wherein, step S12 further includes making the first library file and the second library file into a process library according to the falling edge to obtain a third process library file and a fourth process library file respectively.

[0052] Step S20: RTL design input (referred to as design input).

[0053] During the design input step, the designer completes the circuit design based on the requirements. This design process can describe the circuit's behavior and / or structure in textual and / or graphical form, forming a circuit description file at the RTL (Register-Transfer Level) level. Textual description languages ​​such as Verilog and VHDL can be used, while graphical description languages ​​such as schematics and state diagrams can be used. Circuit behavior refers to the relationship between a circuit's inputs and outputs and their timing relationships, while circuit structure refers to the various functional modules, blocks, units, gates, and the connections between them.

[0054] In step S13, the double-edge-triggered dynamic trigger in the simulation library is added with double-edge-triggered characteristics to obtain a double-edge-triggered dynamic trigger functional model. In addition, a timing check is performed on the maximum clock time according to the double-edge-triggered dynamic trigger's requirement for clock length.

[0055] Step S21: Logic synthesis: Specifically, the RTL-level circuit description file obtained in the RTL design input step is converted into a gate-level netlist composed of specific logic units, wherein the conversion process is determined by the first process library file.

[0056] In step S21, the descriptions of the double-edge-triggered dynamic triggers in the RTL-level circuit description file are uniformly replaced with single-edge-triggered triggers. The first gate-level netlist file is converted using the first process library file. When conventional logic synthesis tools do not support double-edge-triggered dynamic triggers, the double-edge-triggered dynamic triggers can be integrated into conventional digital integrated circuit designs.

[0057] Step S22: Formal verification, that is, statically determining whether the first gate-level netlist file and the RTL-level circuit description file are functionally consistent based on the circuit structure.

[0058] Among them, in step S21 and step S22, the trigger characteristic of the double-edge dynamic trigger involved is single-edge trigger, corresponding to the first process library file of rising edge trigger.

[0059] Step S23: Layout and routing. In this embodiment, layout and routing are performed according to the first process library file and the second process library file at the same time to obtain a digital layout and a layout corresponding to the digital layout. Figure 1 A corresponding second gate-level netlist has the same logical function as the first gate-level netlist file obtained in step S21, but the driving capability and clock distribution of the second gate-level netlist are different from those in the first gate-level netlist file due to matching the digital layout.

[0060] Step S24: Physical verification, including design rule checking, layout netlist output, electrical rule checking, parasitic parameter extraction, circuit diagram and layout comparison, etc., to verify the validity of the generated digital layout.

[0061] Step S25: Timing Check. In this embodiment, the first, second, third, and fourth process library files are used simultaneously for timing check. That is, both the rising edge oversize library and the falling edge oversize library are used simultaneously for timing check, which can improve the reliability of timing closure verification.

[0062] After passing the physical verification and timing check, the corresponding design is completed and the chip can be taped out.

[0063] Step S30: RTL functional simulation. This involves performing a functional simulation on the RTL-level circuit description file obtained in step S20 to test whether its functionality conforms to the design requirements. RTL functional simulation, also known as function simulation, simulates circuit behavior by interpreting the RTL description file. This simulation typically lacks timing information or includes user-defined delay information.

[0064] Step S31: Netlist function simulation, also known as Pre-Layout Simulation, usually does not have timing information, or simply defines the delay time as a unit time. That is, the first gate-level netlist obtained in step S21 is subjected to netlist function simulation to verify the correctness of the netlist function. In this embodiment, the netlist function simulation uses the simulation library of the double-edge dynamic trigger function model obtained in step S13, and the clock uses the functional clock of the double-edge dynamic trigger, that is, the clock signal used (with Figure 2 The clock period of the clock signal CP shown is consistent with that of the data unit.

[0065] Step S32: Netlist timing simulation, also known as Post-Layout Simulation. That is, the second gate-level netlist obtained in step S23 is simulated. The netlist timing simulation incorporates the timing information corresponding to the second gate-level netlist to determine whether its timing is consistent with the design requirements. In this embodiment, the netlist timing simulation uses the simulation library of the double-edge dynamic trigger functional model obtained in step S13, and the clock uses the functional clock of the double-edge dynamic trigger, that is, the clock signal used (the same as Figure 2 The clock period of the clock signal CP shown is consistent with that of the data unit.

[0066] Among them, in the steps of logic synthesis, formal verification, and layout and routing, the trigger mode of the corresponding double-edge dynamic trigger used is single-edge trigger, and the clock period of the corresponding clock signal is consistent with the unit length of the data, that is, the data trigger frequency of the single-edge trigger is the same as the data trigger frequency of the double-edge dynamic trigger.

[0067] In this embodiment, the double-edge dynamic trigger is a dynamic double-edge dynamic trigger. The dynamic trigger has a small number of transistors and low power consumption. The combination design can effectively reduce the timing deviation between individuals, and the clock triggered by the double-edge can easily achieve timed refresh. The double-edge trigger can reduce the clock frequency, thereby ensuring the timed refresh of data while effectively reducing the power consumption of the data path and the area of ​​the designed chip.

[0068] The digital integrated circuit design method of the present invention collects rising edge timing characteristics and falling edge timing characteristics of a double-edge dynamic trigger to obtain a first library with a relatively large timing requirement, and unifies the first library into a rising edge trigger type to obtain a first process library file. Then, based on the double-edge dynamic trigger functional model and the first process library file, the design input, logic synthesis, formal verification, layout and routing, timing check and physical verification of a traditional design process, as well as RTL functional simulation, netlist functional simulation and netlist timing simulation processes are performed. The double-edge dynamic trigger is integrated into the design of the digital integrated circuit, and a first process library file is prepared based on the timing characteristics with relatively large timing requirements among the rising edge timing characteristics and the falling edge timing characteristics. The traditional design process is performed based on the first process library file. While ensuring the reliability of the designed circuit, the integration of the double-edge dynamic trigger in the digital integrated circuit design is simplified, which facilitates the application of the double-edge dynamic trigger in the digital integrated circuit and reduces the overall power consumption of the designed digital integrated circuit system.

[0069] While embodiments of the present invention have been described above, these embodiments do not exhaustively describe all details and do not limit the invention to the specific embodiments described. Obviously, many modifications and variations are possible based on the above description. These embodiments are selected and described in detail in this specification in order to better explain the principles and practical applications of the present invention, thereby enabling those skilled in the art to better utilize the present invention and its modifications. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A method for designing a digital integrated circuit, characterized in that: include: Extracting timing features of the rising edge and the falling edge of the double-edge dynamic trigger respectively, and classifying the extracted timing features according to the parameter sizes to obtain a first library and a second library, wherein the timing feature parameters of the first library are greater than the timing feature parameters of the second library; Modify the first library to a rising edge trigger type to obtain a first process library file; Modify the second library to a rising edge trigger type to obtain a second process library file; Add the double-edge trigger feature to the double-edge dynamic trigger of the simulation library to obtain a double-edge dynamic trigger functional model with double-edge trigger feature; According to the double-edge dynamic trigger functional model and the first process library file, design input, logic synthesis, formal verification, layout and routing, timing check, and physical verification are performed in sequence until the design is completed. in, The logic synthesis, the formal verification and the layout and routing are performed according to the trigger mode of the single edge trigger of the double edge dynamic trigger, The logic synthesis uses the first process library file to convert and obtain a first gate-level netlist file, and the placement and routing simultaneously obtains a second gate-level netlist file based on the first process library file and the second process library file. The design method of the digital integrated circuit further includes: Perform RTL functional simulation according to the RTL level circuit description file obtained in the design input step; A netlist functional simulation is performed on the first gate-level netlist according to the double-edge triggering behavior of the double-edge dynamic trigger functional model, and a netlist timing simulation is performed on the second gate-level netlist and the digital layout.

2. The design method of a digital integrated circuit according to claim 1, wherein: In the step of respectively extracting the features of the rising edge and the falling edge of the double-edge dynamic trigger, the features of the timing and power consumption of the rising edge and the falling edge of the double-edge dynamic trigger are respectively extracted.

3. The design method of a digital integrated circuit according to claim 1, wherein: Also includes: Modify the first library and the second library to the falling edge trigger type to obtain the third process library file and the fourth process library file respectively, Wherein, the timing check step performs timing check according to the first process library file, the second process library file, the third process library file and the fourth process library file at the same time.

4. The method for designing a digital integrated circuit according to claim 1, wherein: In the steps of logic synthesis, formal verification, and layout and routing, the data trigger frequency is the same as the data trigger frequency of the double-edge dynamic trigger.

5. The design method of a digital integrated circuit according to claim 1, wherein: The placement and routing step simultaneously performs an automatic placement and routing process according to the first process library file and the second process library file.

6. The method for designing a digital integrated circuit according to claim 1, wherein: The step of adding a double-edge trigger characteristic to the double-edge dynamic trigger of the simulation library also includes performing a timing check on the maximum clock time according to the requirements of the double-edge dynamic trigger on the clock length.

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