Scan chain port layout optimization method, apparatus, and electronic device

Abstract

The application relates to the field of integrated circuit design and test technology, and discloses a scan chain port layout optimization method, device and electronic equipment. The core of the method comprises the following steps: an intelligent nearest matching step of a scan chain port and a scan chain, in which a nearest unassigned scan chain is searched as a candidate by sequentially selecting a scan chain port, and it is judged whether the scan chain is matched according to a preset distance constraint threshold, so that a first matching relationship is established; and a step of performing dynamic port rearrangement on the unassigned ports and scan chains that are not successfully matched to generate a second matching relationship. Through a two-stage adaptive matching mechanism, physical perception optimization of the scan chain connection relationship is realized, wiring congestion and interconnection delay are significantly reduced, and the robustness of the design process and the convergence of the test timing are improved.

Description

Technical Field

[0001] This application relates to the field of integrated circuit design and testing technology, and in particular to a scan chain port layout optimization method, apparatus and electronic device. Background Technology

[0002] In the physical design flow of integrated circuits, scan chain design is a core component of Design for Testability (DFT). By inserting scan paths between function registers, it enables the manipulation and observation of the internal state of the integrated circuit, which is the cornerstone of ensuring product yield and reliability. However, traditional scan chain design methods are usually completed during the logic synthesis stage, and their physical connection topology does not fully consider the constraints of the back-end layout. This leads to a large number of long-distance, non-local interconnects during the physical implementation of the scan chain, which not only consumes routing resources and causes routing congestion, but also becomes a timing bottleneck due to significant line delays, severely limiting the operating frequency of the scan chain.

[0003] The congestion and timing issues caused by physical connection mismatches in the scan chain become particularly acute in Hard PHY IP modules. These modules, typically represented by Universal Interconnect PHY for Advanced Packaging (UCIe AP PHY) and High Bandwidth Memory PHY (HBM PHY), are inherently characterized by a completely fixed layout, dense channels, and a large register size, resulting in already highly strained internal routing resources. Under these rigid constraints, the direct matching between "fixed IP boundary ports" and "distributed internal registers" in traditional workflows leads to inefficient use of already scarce routing resources, a sharp increase in critical path latency, and ultimately becomes a rigid bottleneck restricting scan chain performance improvement. Summary of the Invention

[0004] This application provides a scan chain port layout optimization method, device, electronic device, and storage medium. Through a two-stage adaptive matching mechanism, it realizes the physical perception optimization of scan chain connection relationship, significantly reduces wiring congestion and interconnection delay, and improves the robustness of the design process and the convergence of test timing.

[0005] In a first aspect, one embodiment of this application provides a method for optimizing the port layout of a scan chain, including:

[0006] Obtain the scan chain netlist and corresponding physical layout information of the target design. The scan chain netlist contains the established scan chains, and the physical layout information includes at least the physical coordinates of the scan chain registers and scan chain ports.

[0007] Taking the scan chain ports as the processing objects and minimizing the physical distance between each scan chain port and the scan chain as the optimization objective, a scan chain is assigned to each scan chain port to establish a first matching relationship;

[0008] The scan chains that are still not matched after the first matching relationship is established are designated as the remaining scan chains, and the ports of the scan chains that are still not matched are designated as the remaining scan chain ports; a remaining scan chain port is assigned to each of the remaining scan chains, and the physical coordinates of the assigned remaining scan chain ports are adjusted according to the physical location of each of the remaining scan chains, thereby establishing the second matching relationship;

[0009] Based on the first matching relationship, the second matching relationship, and the adjusted physical coordinates of the remaining scan chain ports, update the scan chain netlist and the physical layout information.

[0010] Optionally, allocating a scan chain to each of the scan chain ports specifically includes:

[0011] Iterate through each scan chain port, defining the scan chain port targeted in each iteration as the current port; for each current port, perform the following steps:

[0012] From the currently unassigned scan chains, determine the scan chain that is closest in physical distance to the current port as a candidate scan chain; and

[0013] The candidate scan chain is assigned to the current port only if the physical distance between the candidate scan chain and the current port is less than or equal to a preset distance constraint threshold.

[0014] Optionally, determining the scan chain that is closest in physical distance to the current port as a candidate scan chain specifically includes:

[0015] Using the current port position as the center, and with a preset step distance as the increment, the search range of the physical space is recursively expanded;

[0016] The search is performed within each expanded search range: if at least one unassigned scan chain is found within the current search range, the scan chain with the closest physical distance to the current port is selected as a candidate scan chain, and the search is stopped; if no unassigned scan chain is found within the current search range, the search range is continued to be expanded.

[0017] Optionally, the method further includes:

[0018] For each pair of scan chain ports and scan chains determined by the first and second matching relationships, perform the following steps:

[0019] Determine the end register of the scan chain;

[0020] Calculate the physical distance between the end register and the scan chain port, and use it as the end distance;

[0021] If the end distance is greater than a preset tapping distance threshold, then at least one tapping register is inserted on the scan chain path between the end register and the scan chain port.

[0022] Optionally, the method further includes establishing the scan chain through the following steps:

[0023] Based on the physical coordinates of the scan chain registers, multiple scan chain registers that are physically adjacent are aggregated to form multiple register clusters;

[0024] All scan chain registers within each of the aforementioned register clusters are concatenated to form a scan chain.

[0025] Secondly, one embodiment of this application provides a scan chain port layout optimization device, including:

[0026] The information acquisition module is used to acquire the scan chain netlist of the target design and the corresponding physical layout information. The scan chain netlist contains the established scan chains, and the physical layout information includes at least the physical coordinates of the scan chain registers and scan chain ports.

[0027] The first matching module is used to assign a scanning chain to each scanning chain port and establish a first matching relationship by taking the scanning chain port as the processing object, minimizing the physical distance between each scanning chain port and the scanning chain as the optimization objective;

[0028] The second matching module is used to identify unmatched scan chains after the establishment of the first matching relationship as remaining scan chains, and to identify unmatched scan chain ports as remaining scan chain ports; to assign a remaining scan chain port to each remaining scan chain, and to adjust the physical coordinates of the assigned remaining scan chain ports according to the physical location of each remaining scan chain, thereby establishing the second matching relationship;

[0029] The information update module is used to update the scan chain netlist and the physical layout information based on the first matching relationship, the second matching relationship and the adjusted physical coordinates of the remaining scan chain ports.

[0030] Thirdly, one embodiment of this application provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of any of the above methods.

[0031] Fourthly, one embodiment of this application provides a computer-readable storage medium having computer program instructions stored thereon, which, when executed by a processor, implement the steps of any of the above methods.

[0032] Fifthly, one embodiment of this application provides a computer program product or computer program that includes computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform the methods provided in the various optional implementations of the first aspect described above.

[0033] The scan chain port layout optimization method, apparatus, electronic device, and storage medium provided in this application embodiment can achieve the following significant technical effects:

[0034] (1) Efficient use of physical resources: Through the localized connection strategy, the overall interconnection length and inter-cluster interconnection length of the scanning network are greatly reduced, which effectively alleviates cabling congestion and saves cabling resources;

[0035] (2) Breakthrough in timing performance: On the basis of ensuring physical realizability, through systematic path constraints and optimization, the scanning chain clock frequency has been significantly improved and robustly converged, enabling higher scanning clock frequencies to be supported under a given process node, thereby improving test efficiency and chip testability;

[0036] (3) Enhanced process robustness: It solves the problems of DRC violations and routing failures caused by improper physical planning of the scan chain in large-size multi-channel PHYs in traditional methods, and realizes a high success rate of automated design closed loop. Attached Figure Description

[0037] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1 This is a schematic diagram of the structure of a large-size multi-channel HBM PHY provided in an embodiment of this application.

[0039] Figure 2 This is a flowchart illustrating a scan chain port layout optimization method provided in an embodiment of this application. Detailed Implementation

[0040] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, a detailed description is provided below in conjunction with the accompanying drawings and specific implementation methods. Although the embodiments of this application provide method operation steps as shown in the following embodiments or drawings, the method may include more or fewer operation steps based on conventional or non-inventive effort. For steps that do not logically have a necessary causal relationship, the execution order of these steps is not limited to the execution order provided in the embodiments of this application. Unless otherwise specified, the embodiments and features in the embodiments of this application can be arbitrarily combined with each other.

[0041] For ease of understanding, the terms used in the embodiments of this application are explained below:

[0042] Scan chain: In integrated circuit design for testability, a test path is formed by connecting multiple scan chain registers in series according to a preset logic. It is used to control and observe the internal logic state of the integrated circuit in test mode and is the core carrier for chip test signal transmission.

[0043] Scan chain register: In integrated circuit design, it refers to the sequential logic unit that is selected and connected to form a scan chain. It can transmit test signals in scan mode and implement the normal logic function of the chip in function mode.

[0044] Scan chain port: An input / output interface located at the boundary of the integrated circuit and dedicated to scan chain testing. It is used to realize signal interaction between external test equipment and the scan chain inside the integrated circuit, including the input port of test signal and the output port of test result. Its layout and matching relationship with the scan chain are the core optimization of this application.

[0045] End register: is the scan chain register that is furthest from the scan input direction and closest to the scan chain port in a scan chain.

[0046] Scan chain netlist: refers to circuit design data described in netlist form, which contains the logical connection relationships of the scan chain. It defines the serial connection order between all scan chain registers in the scan chain, as well as the connection relationship between the scan chain ports and the start and end registers of the scan chain. It is the basic data for scan chain physical design and optimization.

[0047] Physical layout information refers to the collection of information describing the precise geometric location of all physical units (including scan chain registers, scan chain ports, standard cells, macro modules, etc.) on the integrated circuit layout. It includes at least the planar coordinates (e.g., X, Y coordinates) of each physical unit. In this application, it specifically refers to information containing the physical coordinates of scan chain registers and scan chain ports, typically derived from layout definition files (e.g., DEF files) or physical design databases, and is the fundamental basis for performing physically-aware optimization.

[0048] DEF file (Design Exchange Format): is a standard format file used in the back-end physical design of integrated circuits to record the physical coordinates, layout information, and routing constraints of all components (registers, ports, etc.).

[0049] refer to Figure 1 The large-size multi-channel HBM PHY structure shown presents particularly significant challenges in scan chain design:

[0050] (1) Complex structure and large size: The HBM PHY (boundary 10) typically contains analog circuit region 11, digital circuit region 12 and multiple parallel channels 13. Its physical size is large (for example, in an example structure, the vertical height can reach 9000μm and the horizontal size can reach 2000μm), and the number of internal logic units (including a large number of scan chain registers 14) is numerous and unevenly distributed.

[0051] (2) Fixed ports, resource mismatch: The scan chain ports 15 used for test access are usually arranged in a fixed manner along the PHY boundary 10. However, due to functional and layout constraints, the internal scan chain registers 14 are distributed non-uniformly and in clusters within the digital circuit area 12 and each channel 13. This leads to a fundamental contradiction between the fixed and uniform supply of port resources and the dynamic and non-uniform distribution of register requirements.

[0052] (3) Disadvantages of traditional methods: If a traditional single long scan chain based solely on the logic level is used, its connection will inevitably ignore the boundaries of the physical channel 13 and the density of its internal layout, resulting in a large number of long-distance, highly congested windings inside the PHY. This will not only severely exacerbate wiring congestion and affect signal integrity, but also introduce unpredictable line delays, making it difficult to converge the timing of the scan mode; and generate huge peak currents in the test mode, putting pressure on the power network.

[0053] Therefore, how to automatically synthesize a physically friendly, timing-reliable, and test-efficient scan chain structure under the complex physical constraints of large size, multiple channels, and fixed port layout has become a technical problem that urgently needs to be solved in this field.

[0054] When performing intelligent matching between scan chain ports and scan chains, a fundamental challenge arises in matching physical resources: the physical locations of scan chain ports on the integrated circuit boundary are typically fixed and relatively evenly distributed; however, the physical locations of the internal registers of the scan chain to be connected are determined by the design logic and prior layout, naturally exhibiting a non-uniform clustering on the layout. This leads to a situation where, during a one-time "nearest matching" process, the port demand in densely populated areas of the scan chain far exceeds the local port supply, easily resulting in matching failure due to "local depletion of port resources"; simultaneously, ports in sparsely populated areas of the scan chain may remain idle due to the lack of suitable nearby connections, resulting in resource waste.

[0055] To systematically resolve the contradiction between "fixed supply and dynamic demand", this embodiment proposes a two-stage adaptive matching process: the first stage performs fast and nearest matching under execution constraints to maximize the use of local resources; the second stage reallocates resources for ports and scan chains that failed to match in the first stage through a global port rearrangement mechanism, thereby achieving efficient adaptation of port resources and scan chain spatial distribution.

[0056] refer to Figure 2 This application provides a method for optimizing the port layout of a scan chain, comprising the following steps:

[0057] S100. Obtain the scan chain netlist and corresponding physical layout information of the target design. The scan chain netlist contains the established scan chains, and the physical layout information includes at least the physical coordinates of the scan chain registers and scan chain ports.

[0058] Among them, target design refers to integrated circuit design projects that are currently undergoing physical design optimization and include scan chains that need to be optimized.

[0059] In practice, the scan chain netlist describes the logical connections of the scan chains established in the design and can be derived from a netlist file (e.g., design_scan.v) generated by a design-for-testability tool (such as Tessent). The physical layout information includes at least the physical coordinates of the scan chain registers and scan chain ports on the integrated circuit layout and can be derived from a layout definition file (e.g., design_placed.def) generated by a physical design tool (such as Innovus).

[0060] It should be noted that the scan chain netlist obtained in step S100 already contains original logical connections established by the front-end tool between scan chains and scan chain ports. These connections are based on logical synthesis and typically do not fully consider physical layout constraints, and are not physically optimal connections. The terms "allocation," "matching," and the "unallocated" state mentioned in subsequent steps refer to the internal logical states during the execution of the optimization method in this application. Before starting the core optimization step (S200), all scan chains are initialized to the "unallocated" state. This state indicates that the scan chain has not yet been reassigned a better scan chain port by the current physical-driven optimization process. The purpose of this application is to generate a new, physically superior connection relationship based on physical coordinates through intelligent optimization, thereby covering the original, non-physically optimized connections in the netlist.

[0061] S200. Taking the scan chain port as the processing object and minimizing the physical distance between each scan chain port and the scan chain as the optimization goal, assign a scan chain to each scan chain port and establish the first matching relationship.

[0062] In practice, based on the physical layout information obtained above, the physical coordinates of all scan chain ports and the position information of the established scan chains are obtained; each scan chain port is treated as an independent processing unit, and the scan chain with the closest physical location is assigned to it first, so as to ensure that the physical distance between each scan chain port and the assigned scan chain is minimized, thereby establishing a first matching relationship between the port and the scan chain.

[0063] The position information of the scan chain can be determined based on the physical coordinates of the scan chain registers it contains. For example, the average value of the physical coordinates of all scan chain registers in the scan chain can be used as the position information of the scan chain; or, the physical coordinates of the end register of the scan chain can be selected as the position information of the scan chain; or, the center coordinates of the region formed by the boundary extreme values ​​of the physical coordinates of all scan chain registers in the scan chain can be selected as the position information of the scan chain.

[0064] The physical distance between a scan chain port and a scan chain can be obtained through a preset distance calculation method. During the allocation process, each scan chain is guaranteed to be assigned to only one scan chain port until all matching ports have completed scan chain allocation, or all assignable scan chains have completed port binding.

[0065] In the specific implementation of step S200, constraints such as distance constraint thresholds can be set to ensure that the physical connection between the port and the scan chain is within a reasonable engineering cost. Based on this, for each scan chain port, the system selects the scan chain with the closest physical distance from the scan chains in its physical neighborhood that meet all constraints, and assigns it to establish the first matching relationship.

[0066] Due to the trade-off between the optimization objective (minimizing distance) and the inherent constraints of the physical layout, after the first matching phase is completed, there are usually two types of unmatched resources: scan chain ports that failed to be assigned to any scan chain, and scan chains that failed to match any ports.

[0067] To clearly describe the subsequent optimization steps, this application defines the scan chains that still fail to match after the first matching stage as "remaining scan chains"; and the scan chain ports that still fail to match after the first matching stage as "remaining scan chain ports". These remaining scan chains and remaining scan chain ports will serve as core inputs to the next stage of the optimization process (i.e., the second matching stage), where the final physical connection optimization will be completed through different strategies (such as port position rearrangement).

[0068] S300. Assign a remaining scan chain port to each remaining scan chain, and adjust the physical coordinates of the assigned remaining scan chain port according to the physical location of each remaining scan chain, thereby establishing a second matching relationship.

[0069] In specific implementation, based on the remaining scan chains and remaining scan chain ports selected after establishing the first matching relationship in step S200, an unmatched remaining scan chain port is assigned to each remaining scan chain to ensure that the remaining scan chains and remaining scan chain ports are assigned in a one-to-one correspondence. After the assignment is completed, for each set of assigned remaining scan chains and remaining scan chain ports, the position information of the remaining scan chain is obtained (the method for determining the position information of the scan chain in step S200 can be used as a reference). Based on the position information of the remaining scan chain, the physical coordinates of the remaining scan chain port assigned to it are adjusted so that the physical distance between the adjusted remaining scan chain port and the corresponding remaining scan chain reaches a reasonable range, adapting to the chip physical design constraints and routing requirements. Finally, the matching and binding of all remaining scan chains and remaining scan chain ports is completed, and the second matching relationship is established.

[0070] refer to Figure 1Taking the HBM PHY scenario adapted by this application as an example, the specific implementation of "adjusting the physical coordinates of the remaining scan chain ports" is explained in detail: If a remaining scan chain uses the physical coordinates (x1, y1) of its end register as its own position information, and the initial physical coordinates of the remaining scan chain ports allocated to it are (x2, y2), then during adjustment, the position information of the remaining scan chain is used as a reference, and the vertical coordinate of the remaining scan chain port is adjusted to be consistent with the vertical coordinate of the corresponding remaining scan chain, that is, the physical coordinates of the remaining scan chain port after adjustment are (x2, y1). Furthermore, if there are already allocated scan chain ports at or near (x2, y1), in order to avoid port layout conflicts and ensure smooth routing, the vertical coordinate y1 can be slightly adjusted so that the remaining scan chain port maintains a preset appropriate interval with other surrounding scan chain ports, ensuring that the adjusted port layout meets the chip physical design constraints and routing requirements.

[0071] It should be noted that the adjustment of the physical coordinates of the scan chain port must be carried out within the preset layout area of ​​the integrated circuit and must not exceed the boundary constraints of the physical design, so as to ensure that the adjusted port layout does not affect the normal operation of other functional modules of the chip.

[0072] S400: Based on the first matching relationship, the second matching relationship, and the physical coordinates of the remaining scan chain ports after adjustment, update the scan chain netlist and physical layout information.

[0073] In practice, firstly, the first matching relationship established in step S200 and the second matching relationship established in step S300 are integrated to form a complete global matching mapping table of scan chain-scan chain port. This mapping table defines the scan chain port that ultimately corresponds to each scan chain and is the sole basis for subsequent data updates.

[0074] Then, based on the global matching mapping table, the logical connection update is performed on the scan chain netlist. This update ensures that the netlist can accurately reflect the scan chain topology optimized based on physical location. The update content mainly includes: (1) Connection redirection: For each scan chain, its logical endpoint (scan input / output) in the scan chain netlist is modified to point to the scan chain port it matches; (2) Redundant information cleanup: Remove the original logical connection records in the scan chain netlist that are inconsistent with the current optimization results.

[0075] Next, based on the global matching mapping table and the port coordinate adjustment results, the physical layout information (such as the DEF file) is updated. This update ensures that the layout information accurately reflects the actual physical location of the ports after optimization. The update mainly includes: writing the new physical coordinates of all remaining scan chain ports from step S300 into the file, overwriting their original coordinates; and adding or updating attributes in the file to indicate the correspondence between the ports and their matching scan chains.

[0076] Before and after the update, perform necessary verifications to ensure the validity of the results. For example, confirm that the coordinate updates of all ports do not violate physical design constraints such as the layout boundaries of the hard core IP and the reserved cabling channels; check whether the updated netlist connections strictly correspond to the port positions in the layout information to ensure that the data of the logical design and physical implementation are consistent.

[0077] Through the above steps, two key data sets are ultimately output: the optimized scan chain netlist and the updated physical layout information. The optimized scan chain netlist contains the optimal connectivity relationships for physical drives, and the updated physical layout information contains the accurate coordinates of the optimized ports. These two sets of data constitute the final deliverables of scan chain port layout optimization and can be directly used in subsequent processes such as timing optimization, clock tree synthesis, and detailed routing.

[0078] Traditional design processes fix scan chain connections during the logic synthesis phase, allowing only localized and passive adjustments in the backend physical design. This fails to address the root cause of scan chain port and scan chain mismatch issues, leading to recurring problems such as wire loop congestion and timing violations, resulting in frequent design iterations and low efficiency. In contrast, the scan chain port layout optimization method provided in this application uses physical layout information as the core basis for driving scan chain port allocation. It employs a two-stage optimization process combining "intelligent proximity matching (corresponding to step S200)" and "dynamic port rearrangement (corresponding to step S300)" to proactively construct the physically optimal connection topology and the physically optimal scan chain and port connection topology. This fundamentally avoids the core pain points of long-line connections and wire loop congestion caused by position mismatch.

[0079] Specifically, the first stage, "intelligent proximity matching," serves as the core of the optimization. Driven by physical layout information, it selects the scan chain with the closest physical distance for each scan chain port for matching and allocation. This design, through the principle of proximity allocation, binds the vast majority of scan chain ports to the scan chain with the closest physical location. On the one hand, this significantly shortens the global interconnect length of the scan chain, reduces internal wiring crossovers, effectively releases valuable wiring resources, and reduces the pressure of local routing resource competition. On the other hand, while shortening the global interconnect length, it also reduces interference during signal transmission, laying the foundation for subsequent timing optimization and reducing timing risks caused by long-line connections from the source.

[0080] The second stage, "Dynamic Port Rearrangement," serves as a supplement and improvement to "Intelligent Proximity Matching." Addressing the remaining scan chains and ports that failed to complete matching in the first stage for various reasons, it optimizes dynamic port rearrangement by assigning corresponding ports to each remaining scan chain and adjusting the port's physical coordinates based on the physical location of the remaining scan chain (e.g., in the HBM PHY scenario, aligning the port's vertical coordinate with the corresponding scan chain's vertical coordinate, making minor adjustments as needed to avoid layout conflicts). This step is not simply about matching remaining cells; it proactively adjusts port positions to build a dynamic port rearrangement mechanism. This effectively addresses the challenges of insufficient or unevenly distributed port resources in local areas, ensuring scan chain connections can still be completed under stringent physical constraints, thus improving the success rate and robustness of the optimization process. Simultaneously, it provides an optimal solution for scan chains that cannot be matched through simple proximity matching, preventing these remaining cells from becoming chip performance bottlenecks or causing repeated design iterations and convergence issues. This significantly enhances the completeness of the scan chain physical design process and further improves the design success rate.

[0081] For design scenarios with extremely tight cabling channels, fixed layouts, and high unit density, such as Hard PHY IP (e.g., HBM, UCIe), the two-stage optimization effect of "intelligent proximity matching + dynamic port rearrangement" is particularly outstanding: intelligent proximity matching significantly shortens the global interconnect length, reduces cabling crossovers, and alleviates congestion hotspots; dynamic port rearrangement specifically addresses the position mismatch problem of remaining units, directly solves the problem of winding congestion caused by scan chains, effectively avoids routing failures caused by unreasonable scan chain layouts, and provides reliable support for the physical design of scan chains in Hard PHY IP.

[0082] Furthermore, the reduction in the physical connection distance between scan chain ports directly reduces the line delay of the scan chain critical path, making it easier for the scan chain setup time and hold time to meet timing convergence requirements. This allows the scan chain operating frequency to converge to a higher level, enabling higher scan clock frequencies to be supported at a given process node. This significantly improves chip test throughput and efficiency, ensures the effectiveness of testability design, and provides strong support for chip yield and reliability.

[0083] Furthermore, the entire scan chain port layout optimization method (including intelligent proximity matching, dynamic port rearrangement, netlist and physical layout information updates) can be automatically executed by EDA tool scripts, completely replacing the cumbersome work of engineers manually adjusting port constraints and optimizing layout in traditional design. This effectively avoids the error-proneness of manual operation, greatly improves the automation level and design efficiency of scan chain physical design, and shortens the design cycle.

[0084] In summary, the scan chain port layout optimization method provided in this application systematically and automatically solves the core challenges of congestion and timing in the physical design of scan chains in high-performance integrated circuits (especially Hard PHYIPs) through an innovative two-stage optimization process of "intelligent proximity matching + dynamic port rearrangement". It not only effectively improves key indicators such as chip routing efficiency and timing convergence, but also revolutionizes the design paradigm of scan chain port layout, shortens the chip design cycle, and improves chip yield and reliability, thus having significant industrial application value.

[0085] In some alternative implementations, the "intelligent nearest matching" process in step S200 is performed according to the following steps:

[0086] S201. Select one scan chain port from all scan chain ports as the current port.

[0087] In practice, the traversal order can be determined based on the physical coordinates of the scan chain ports (e.g., from left to right, from top to bottom), and a port can be selected sequentially as the current port for processing until all ports have been traversed. Figure 1 Taking the HBM PHY shown as an example, the Y-coordinate of the scan chain port is traversed from top to bottom.

[0088] S202. For the current port, determine the scan chain that is closest to the current port in physical distance from the currently unassigned scan chains as a candidate scan chain.

[0089] In practice, based on the physical coordinates of the current port and the position information of each unassigned scan chain, the physical distance between the current port and each unassigned scan chain is calculated. The scan chain with the smallest physical distance is then selected as the candidate scan chain corresponding to the current port. Existing two-dimensional planar distance calculation methods can be used to calculate the physical distance between the current port and each unassigned scan chain; this is not limited here.

[0090] S203. Determine whether the physical distance between the candidate scan chain and the current port is less than or equal to the preset distance constraint threshold; if yes, proceed to step S204; if no, do not assign a scan chain to the current port.

[0091] The distance constraint threshold is not fixed and needs to be scientifically set based on the actual design scenario. The core criteria for its selection include: first, the physical design constraints of the chip; for example, in scenarios with limited routing channels, such as HBM PHYs, the threshold needs to be relatively small to strictly control interconnect lengths and avoid exacerbating routing congestion; second, timing requirements; if the chip has high requirements for scan chain signal transmission delay, the threshold needs to be set strictly to ensure that the matched interconnect length meets timing convergence requirements, otherwise it can be appropriately relaxed to balance efficiency and performance. Furthermore, the distance constraint threshold can also refer to engineering practice experience of similar scenarios for existing chips to ensure its feasibility and compatibility.

[0092] In this embodiment, the maximum physical distance between the scan chain port and the scan chain is limited by a distance constraint threshold to avoid matching scan chains that are too far apart, which would violate the optimization goal of "minimizing physical distance". In addition, the distance constraint threshold can also help filter candidate scan chains that meet the routing and timing constraints. If the physical distance between the candidate scan chain and the current port exceeds the distance constraint threshold, even if no better candidate is found, the candidate scan chain will not be assigned to the current port, but the current port will be directly assigned to the remaining scan chain port, ensuring that the matching result takes into account both efficiency and rationality.

[0093] S204. Assign the candidate scan chain to the current port.

[0094] It should be noted that after assigning a candidate scan chain to the current port, both the current port and the candidate scan chain must be marked as "assigned" and will not be involved in subsequent matching processes. The system can maintain a dynamically updated unassigned list to record scan chain ports and scan chains that have not yet been matched.

[0095] Repeat steps S201 to S204 until all scan chain ports have been traversed, and finally establish the first matching relationship between scan chain ports and scan chains.

[0096] This embodiment introduces a configurable distance constraint threshold as the upper limit of the physical distance for intelligent matching between scan chain ports and scan chains, further improving the controllability, practicality, and design quality of the optimization method. As a rigid constraint, the distance constraint threshold directly prohibits connections where the physical distance between the matching parties is too great. Even if the algorithm fails to find an ideal match within a local range, it will not force a physically unreasonable scan chain connection to "complete the match," thus fundamentally avoiding subsequent problems such as wiring congestion and timing deterioration caused by long-distance connections, ensuring the consistency between the matching result and the initial optimization objective.

[0097] To further improve screening efficiency, a recursive extended search method can be used to efficiently locate the scan chain with the closest physical distance. This involves the following steps:

[0098] S2021. Initialize the search range.

[0099] Using the current port location as the center, and incrementing by a preset step distance, the search range of the physical space is recursively expanded.

[0100] Using the physical coordinates of the current port as the center, set the initial search radius R0 and the preset step distance ΔR. R0 can be set to a small positive value, for example, R0 = 5μm, indicating that the search starts from a small range. ΔR is a preset positive value, which can be set according to the average cell density of the design module; a typical value is 10-50μm.

[0101] In practice, the shape of the search area can be adjusted to a rectangle (aligned with the chip rows and columns) based on the distribution of wiring resources, or customized according to the shape of obstacles. The preset step distance ΔR can be a dynamic value, initially smaller to ensure accuracy, and gradually increased later to accelerate coverage.

[0102] S2022. Perform a scan chain search within the current search range.

[0103] In the current search radius R i Within the defined circular or rectangular region (where i is the expansion index, initially i=0), retrieve all unassigned scan chains:

[0104] If at least one unassigned scan chain is found within the current search range, the physical distance between the current port and all unassigned scan chains within the current search range is calculated. The scan chain with the smallest physical distance is selected as the candidate scan chain, and the search process is terminated immediately, proceeding to the distance threshold judgment in step S203.

[0105] If no unassigned scan chain is found within the current search range, proceed to step S2023.

[0106] S2023, Recursively expand the search scope.

[0107] Expand the search radius in incremental steps: R i+1 =R i +ΔR, then return to step S2022 to continue the search within the expanded search range. This process is executed recursively until the following condition is met:

[0108] (1) Find the candidate scan chain (go to S203); or

[0109] (2) The search radius reaches the preset maximum safe search radius R max .

[0110] R max This is an algorithm efficiency protection parameter used to prevent costly global searches in regions where the scan chain is extremely sparse. Rmax The value can be set to 2-3 times the distance constraint threshold, or reasonably set according to the physical boundary of the current optimization region (e.g., the width or height of the PHY channel). When the search radius reaches the preset maximum safe search radius R... max If no scan chain is found, the current port is determined to have no available match within a reasonable physical range, marked as "unmatched," and the process continues to process the next scan chain port. This is achieved by setting R... max This ensures controllable search boundaries, prevents meaningless global searches in extreme cases, and guarantees deterministic termination of the algorithm.

[0111] It should be noted that in this embodiment, the maximum safe search radius R max The distance constraint threshold and the two parameters are used in a collaborative manner, achieving a balance between algorithm efficiency and matching quality through the "search first, then filter" rule: recursive search only occurs in R... max Within the search range, the algorithm covers a reasonable neighborhood of the current port with controllable computational cost, avoiding missed matches. All candidate scan chains found within the search range must undergo a final verification based on a distance constraint threshold; only candidates with a physical distance ≤ the distance constraint threshold can be matched. Otherwise, the current port is directly assigned to one of the remaining scan chains. In short, R... max By controlling the breadth of the search and the efficiency of the algorithm, and by using distance constraint thresholds to ensure the physical quality of the matching, the two are combined to ensure the feasibility of the algorithm while strictly adhering to the optimization goal of "minimizing physical distance".

[0112] Compared to fixed-range search or global traversal, the above recursive extended search method avoids calculating the global distance for all unassigned scan chains. By dynamically searching from near to far, it terminates once a candidate is found in a relatively close range, greatly reducing unnecessary computational overhead and significantly improving computational efficiency. The search order ensures that the scan chain with the closest physical distance is matched first, which is highly consistent with the optimization objective.

[0113] In some optional implementations, after performing intelligent proximity matching and establishing the matching relationship between the scan chain port and the scan chain (i.e., after obtaining the first matching relationship and the second matching relationship), the following snapshot processing procedure is executed for each pair of scan chain ports and scan chains to ensure the timing reliability of the long-distance scan path. The snapshot processing procedure specifically includes the following steps S501~S504:

[0114] S501, Determine the end register of the scan chain.

[0115] For each matched scan chain port P and scan chain C: determine the end register R of scan chain C. end The terminal register R endIt is a scan chain register in scan chain C that is furthest from the scan input direction and closest to scan chain port P.

[0116] In practice, if the scan chain C is generated by the scan chain register in scan order R1→R2→…→R n The connection is made up of the scan chain port P, which is connected to the scan input of R1. Then the end register is R. n If scan chain port P is connected to the scan output of R1, then the end register is R1. The above identification process can be automatically completed by traversing the scan chain netlist structure.

[0117] S502. Calculate the physical distance between the end register and the scan chain port as the end distance.

[0118] In practice, the physical coordinates of the end register and the scan chain port are obtained. The physical distance between them is calculated using existing two-dimensional distance algorithms (such as Euclidean distance, Manhattan distance, etc.) and denoted as the end distance D. end .

[0119] S503. Determine that the distance to the end is greater than the preset striking distance threshold.

[0120] The end distance D end With the threshold of the striking distance D buffer_th Comparison: If D end >D buffer_th If the physical path between the scan chain port and the end register is too long, the signal propagation delay may not meet the timing requirements of the scan clock cycle, or there may be a risk to signal integrity. Therefore, a beat register needs to be inserted, and the process proceeds to step S504; if D end ≤D buffer_th If the current path length is considered to be within an acceptable range, the original connection is kept unchanged, and the next matching pair is processed.

[0121] Setting the strike distance threshold is a trade-off between performance and overhead, and is mainly based on the following:

[0122] (1) Scanning clock frequency: The higher the frequency, the shorter the allowed signal propagation distance, and the threshold needs to be reduced accordingly.

[0123] (2) Signal transmission characteristics of process nodes: Based on the process library data, calculate the maximum distance that the signal can be reliably transmitted on a unit length interconnect within a scan cycle.

[0124] (3) Engineering experience value: Based on similar designs, the typical value may be between 100μm and 500μm (the specific value decreases as the process progresses).

[0125] (4) Correlation with distance constraint threshold: Usually, the shooting distance threshold is greater than or equal to the distance constraint threshold, because the distance constraint threshold controls the "matching selection", while the shooting distance threshold deals with the long path reinforcement "after matching".

[0126] S504. Insert at least one beat register on the scan chain path between the end register and the scan chain port.

[0127] In practice, depending on the path length and design rules, one or a combination of the following methods should be selected to insert the timing register:

[0128] (1) Single-point stamping: On the line connecting the end register and the scan chain port P, select a legal position that is approximately in the middle and conforms to the layout rules, and insert a stamping register. The original connection R... end →R2→P is split into R end →BUF→P, where BUF is the inserted beat register.

[0129] (2) Equally spaced multi-point tapping: When D end Much larger than D buffer_th Time (e.g., D) end >2×D buffer_th ), can follow the path in no more than D buffer_th Multiple timer registers are inserted at intervals to form R. end The buffer chain is →BUF1→BUF2→…→P.

[0130] (3) Path optimization and timing: Based on the actual wiring channel resources and obstacle distribution, under the premise of satisfying the maximum spacing constraint, the optimal insertion point is selected so that the timing register can also play a role in improving the wiring shape.

[0131] After completing step S504, it is also necessary to update the relevant data in the scan chain netlist and layout definition file according to the inserted stamping register.

[0132] This embodiment fundamentally prevents setup / hold time violations caused by excessive scan signal transmission delay by identifying and strengthening long paths, thus improving timing convergence in test mode. The inserted beat register re-drives the signal, effectively mitigating noise, crosstalk, and attenuation on long interconnects and ensuring the quality of the test signal waveform. This allows the intelligent matching algorithm to pursue the "physical closest" without excessive concern about timing issues on individual long paths, as this strengthening step provides a guarantee. It decouples matching optimization from timing repair, allowing the algorithm to focus more on layout optimization.

[0133] In some alternative implementations, the scan chain can be established through the following steps before performing intelligent matching between the scan chain port and the scan chain:

[0134] S101. Based on the physical coordinates of the scan chain registers, aggregate multiple scan chain registers that are physically adjacent to each other to form multiple register clusters.

[0135] In practice, the estimated or actual physical coordinates of all registers to be inserted into the scan chain in the target design are obtained. These coordinates can come from the output of early placement tools, netlist-based placement estimations, or feedback from the previous physical implementation. Then, a spatial clustering algorithm (such as grid-based clustering or hierarchical clustering) is used to group all scan chain registers, resulting in multiple register clusters, each containing several scan chain registers that are physically adjacent. The clustering operation for scan chain registers can be implemented using existing EDA tools.

[0136] S102. Connect all scan chain registers in each register cluster to form a scan chain.

[0137] In practice, based on the spatial distribution of the scan chain registers within the register cluster on the layout, a sorting strategy (such as Z-order, nearest neighbor greedy algorithm, or time-critical sorting) can be selected to sort the scan chain registers within the cluster. Then, based on the sorting result, all scan chain registers within the register cluster are sequentially connected to form a complete scan chain.

[0138] It should be noted that steps S101-S102 are performed before step S100.

[0139] This embodiment obtains the scan chain through physical clustering, fundamentally ensuring that the registers in the scan chain are physically tightly clustered, minimizing the interconnection segments within the chain, and significantly reducing wiring congestion and line delay. The physical clustering step perceives the register distribution density, forming high-density register clusters. Then, a two-stage intelligent matching process applies differentiated optimization strategies to high- and low-density regions: intelligent proximity matching is implemented for high-density clusters to fully utilize resources, while dynamic port rearrangement actively adapts the layout for matching failures, thereby achieving adaptive scan chain layout optimization based on physical density distribution.

[0140] Furthermore, the high-density register clusters formed by physical clustering in this embodiment result in a highly non-uniform physical aggregation of scan chains on the macroscopic map. While this feature greatly optimizes intra-chain connections, it also exacerbates the "regional supply and demand imbalance of port resources" when connecting fixed-position scan chain ports to these scan chains: the demand for ports is highly concentrated in high-density cluster areas, while the demand is sparse in low-density areas. It is this contradiction, explicitly revealed and reinforced by physical clustering, that makes the two-stage adaptive matching process (first, local intelligent proximity matching, then global dynamic port rearrangement) particularly necessary and effective. The scan chain set generated in this embodiment, with clear physical boundaries and density characteristics, provides structurally regular and feature-defined optimization objects for subsequent intelligent matching algorithms, enabling the overall optimization process to more accurately diagnose resource bottlenecks and perform efficient dynamic resource reallocation.

[0141] Based on the same inventive concept, this application also provides a scan chain port layout optimization device. Since the principle of the above device and apparatus in solving the problem is similar to that of a scan chain port layout optimization method, the implementation of the above device can refer to the implementation of the method, and repeated details will not be elaborated further. This device can be applied to electronic devices; this application does not limit the type of electronic device, which can be any suitable type of device. In some embodiments, the scan chain port layout optimization device exemplified in this application includes:

[0142] The information acquisition module is used to acquire the scan chain netlist of the target design and the corresponding physical layout information. The scan chain netlist contains the established scan chains, and the physical layout information includes at least the physical coordinates of the scan chain registers and scan chain ports.

[0143] The first matching module is used to assign a scanning chain to each scanning chain port and establish a first matching relationship by taking the scanning chain port as the processing object, minimizing the physical distance between each scanning chain port and the scanning chain as the optimization objective;

[0144] The second matching module is used to identify unmatched scan chains after the establishment of the first matching relationship as remaining scan chains, and to identify unmatched scan chain ports as remaining scan chain ports; to assign a remaining scan chain port to each remaining scan chain, and to adjust the physical coordinates of the assigned remaining scan chain ports according to the physical location of each remaining scan chain, thereby establishing the second matching relationship;

[0145] The information update module is used to update the scan chain netlist and the physical layout information based on the first matching relationship, the second matching relationship and the adjusted physical coordinates of the remaining scan chain ports.

[0146] In some optional implementations, the first matching module is used to implement the function of "assigning a scan chain to each of the scan chain ports", specifically including:

[0147] Iterate through each scan chain port, defining the scan chain port targeted in each iteration as the current port; for each current port, perform the following steps:

[0148] From the currently unassigned scan chains, determine the scan chain that is closest in physical distance to the current port as a candidate scan chain; and

[0149] The candidate scan chain is assigned to the current port only if the physical distance between the candidate scan chain and the current port is less than or equal to a preset distance constraint threshold.

[0150] In some optional implementations, the first matching module is used to implement the function of "determining the scan chain that is closest to the current port in physical distance as a candidate scan chain", specifically including:

[0151] Using the current port position as the center, and with a preset step distance as the increment, the search range of the physical space is recursively expanded;

[0152] The search is performed within each expanded search range: if at least one unassigned scan chain is found within the current search range, the scan chain with the closest physical distance to the current port is selected as a candidate scan chain, and the search is stopped; if no unassigned scan chain is found within the current search range, the search range is continued to be expanded.

[0153] In some alternative embodiments, the apparatus further includes a stamp register insertion module for performing the following steps for each pair of scan chain ports and scan chains determined by the first matching relationship and the second matching relationship:

[0154] Determine the end register of the scan chain;

[0155] Calculate the physical distance between the end register and the scan chain port, and use it as the end distance;

[0156] If the end distance is greater than a preset tapping distance threshold, then at least one tapping register is inserted on the scan chain path between the end register and the scan chain port.

[0157] In some alternative embodiments, the apparatus further includes a scan chain establishment module for establishing the scan chain through the following steps:

[0158] Based on the physical coordinates of the scan chain registers, multiple scan chain registers that are physically adjacent are aggregated to form multiple register clusters;

[0159] All scan chain registers within each of the aforementioned register clusters are concatenated to form a scan chain.

[0160] The scan chain port layout optimization device provided in this application embodiment adopts the same inventive concept as the scan chain port layout optimization method described above, and can achieve the same beneficial effects, so it will not be described again here.

[0161] Based on the same inventive concept as the above-described scan chain port layout optimization method, this application also provides an electronic device, which specifically includes a processor and a memory.

[0162] The processor can be a general-purpose processor, such as a central processing unit (CPU), digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component, capable of implementing or executing the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly manifested as being executed by a hardware processor, or executed by a combination of hardware and software modules within the processor.

[0163] Memory, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules. Memory can include at least one type of storage medium, such as flash memory, hard disk, multimedia card, card-type memory, random access memory (RAM), static random access memory (SRAM), programmable read-only memory (PROM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), magnetic memory, magnetic disk, optical disk, etc. Memory is any other medium capable of carrying or storing desired program code in the form of instructions or data structures that can be accessed by a computer, but is not limited to this. The memory in the embodiments of this application can also be a circuit or any other device capable of implementing storage functions for storing program instructions and / or data.

[0164] Those skilled in the art will understand that all or part of the steps of the above method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it performs the steps of the above method embodiments. The aforementioned computer storage medium can be any available medium or data storage device that a computer can access, including but not limited to: mobile storage devices, random access memory (RAM), magnetic storage (e.g., floppy disks, hard disks, magnetic tapes, magneto-optical disks (MO), etc.), optical storage (e.g., CDs, DVDs, BDs, HVDs, etc.), and semiconductor storage (e.g., ROMs, EPROMs, EEPROMs, non-volatile memory (NAND flash), solid-state drives (SSDs)) and other media capable of storing program code.

[0165] Alternatively, if the integrated units described above in this application are implemented as software functional modules and sold or used as independent products, they can also be stored in a computer-readable storage medium. Based on this understanding, the technical solutions of the embodiments of this application, or the parts that contribute to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the methods described in the various embodiments of this application. The aforementioned storage medium includes: mobile storage devices, random access memory (RAM), magnetic memory (e.g., floppy disks, hard disks, magnetic tapes, magneto-optical disks (MO), etc.), optical memory (e.g., CDs, DVDs, BDs, HVDs, etc.), and semiconductor memory (e.g., ROMs, EPROMs, EEPROMs, non-volatile memory (NAND flash), solid-state drives (SSDs), etc.) and other media capable of storing program code.

[0166] The above embodiments are only used to provide a detailed description of the technical solutions of this application. However, the description of the above embodiments is only for the purpose of helping to understand the methods of the embodiments of this application and should not be construed as a limitation on the embodiments of this application. Any changes or substitutions that can be easily conceived by those skilled in the art should be covered within the protection scope of the embodiments of this application.

Claims

1. A method for optimizing the port layout of a scan chain, characterized in that, include: Obtain the scan chain netlist and corresponding physical layout information of the target design. The scan chain netlist contains the established scan chains, and the physical layout information includes at least the physical coordinates of the scan chain registers and scan chain ports. Taking the scan chain ports as the processing objects and minimizing the physical distance between each scan chain port and the scan chain as the optimization objective, a scan chain is assigned to each scan chain port to establish a first matching relationship; The scan chains that are still not matched after the first matching relationship is established are designated as remaining scan chains, and the scan chain ports that are still not matched are designated as remaining scan chain ports. Each remaining scan chain is assigned a remaining scan chain port, and the physical coordinates of the assigned remaining scan chain ports are adjusted according to the physical position of each remaining scan chain. Based on the position information of the remaining scan chains, the physical distance between the adjusted remaining scan chain ports and the corresponding remaining scan chains is made to reach a reasonable range, adapting to chip physical design constraints and routing requirements. Finally, the matching and binding of all remaining scan chains and remaining scan chain ports are completed, thereby establishing the second matching relationship. Based on the first matching relationship, the second matching relationship, and the adjusted physical coordinates of the remaining scan chain ports, update the scan chain netlist and the physical layout information.

2. The method according to claim 1, characterized in that, The allocation of a scan chain to each scan chain port specifically includes: Iterate through each scan chain port, defining the scan chain port targeted in each iteration as the current port; for each current port, perform the following steps: From the currently unassigned scan chains, determine the scan chain that is closest in physical distance to the current port as a candidate scan chain; and The candidate scan chain is assigned to the current port only if the physical distance between the candidate scan chain and the current port is less than or equal to a preset distance constraint threshold.

3. The method according to claim 2, characterized in that, The step of determining the scan chain that is closest in physical distance to the current port as the candidate scan chain specifically includes: Using the current port position as the center, and with a preset step distance as the increment, the search range of the physical space is recursively expanded; The search is performed within each expanded search range: if at least one unassigned scan chain is found within the current search range, the scan chain with the closest physical distance to the current port is selected as a candidate scan chain, and the search is stopped; if no unassigned scan chain is found within the current search range, the search range is continued to be expanded.

4. The method according to any one of claims 1 to 3, characterized in that, The method further includes: For each pair of scan chain ports and scan chains determined by the first and second matching relationships, perform the following steps: Determine the end register of the scan chain; Calculate the physical distance between the end register and the scan chain port, and use it as the end distance; If the end distance is greater than a preset tapping distance threshold, then at least one tapping register is inserted on the scan chain path between the end register and the scan chain port.

5. The method according to any one of claims 1 to 3, characterized in that, The method further includes establishing the scan chain through the following steps: Based on the physical coordinates of the scan chain registers, multiple scan chain registers that are physically adjacent are aggregated to form multiple register clusters; All scan chain registers within each of the aforementioned register clusters are concatenated to form a scan chain.

6. A scanning chain port layout optimization device, characterized in that, include: The information acquisition module is used to acquire the scan chain netlist of the target design and the corresponding physical layout information. The scan chain netlist contains the established scan chains, and the physical layout information includes at least the physical coordinates of the scan chain registers and scan chain ports. The first matching module is used to assign a scanning chain to each scanning chain port and establish a first matching relationship by taking the scanning chain port as the processing object, minimizing the physical distance between each scanning chain port and the scanning chain as the optimization objective; The second matching module is used to identify unmatched scan chains after the establishment of the first matching relationship as remaining scan chains, and to identify unmatched scan chain ports as remaining scan chain ports; to assign a remaining scan chain port to each remaining scan chain, and to adjust the physical coordinates of the assigned remaining scan chain ports according to the physical location of each remaining scan chain, using the position information of the remaining scan chains as a reference, so that the physical distance between the adjusted remaining scan chain port and the corresponding remaining scan chain reaches a reasonable range, adapting to chip physical design constraints and routing requirements, and finally completing the matching and binding of all remaining scan chains and remaining scan chain ports, thereby establishing the second matching relationship; The information update module is used to update the scan chain netlist and the physical layout information based on the first matching relationship, the second matching relationship and the adjusted physical coordinates of the remaining scan chain ports.

7. The apparatus according to claim 6, characterized in that, The first matching module is used to implement the function of "assigning a scan chain to each of the scan chain ports", specifically including: Iterate through each scan chain port, defining the scan chain port targeted in each iteration as the current port; for each current port, perform the following steps: From the currently unassigned scan chains, determine the scan chain that is closest in physical distance to the current port as a candidate scan chain; and The candidate scan chain is assigned to the current port only if the physical distance between the candidate scan chain and the current port is less than or equal to a preset distance constraint threshold.

8. The apparatus according to claim 6 or 7, characterized in that, The device further includes a stamping register insertion module, used to perform the following steps for each pair of scan chain ports and scan chains determined by the first matching relationship and the second matching relationship: Determine the end register of the scan chain; Calculate the physical distance between the end register and the scan chain port, and use it as the end distance; If the end distance is greater than a preset tapping distance threshold, then at least one tapping register is inserted on the scan chain path between the end register and the scan chain port.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method as described in any one of claims 1 to 5.

10. A computer-readable storage medium having computer program instructions stored thereon, characterized in that, When executed by a processor, the computer program instructions implement the steps of the method as described in any one of claims 1 to 5.

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