A method for correcting design errors in a CMOS operational amplifier
By combining simulation and theoretical calculation to correct the error factor of CMOS operational amplifiers, the problem of insufficient accuracy in existing designs is solved, achieving high design accuracy and cost reduction.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- HANGZHOU DIANZI UNIV
- Filing Date
- 2026-02-26
- Publication Date
- 2026-05-26
AI Technical Summary
Existing CMOS operational amplifier designs suffer from performance deviations due to model errors and higher-order effects, resulting in insufficient design accuracy. Relying on manual debugging and simulation optimization is costly and inefficient.
By combining simulation and theoretical calculation, performance error factors are identified and corrected, including error factors in unity-gain bandwidth, phase margin, and slew rate. Initial design parameters such as transconductance and bias current are corrected, and MOSFET dimensions are recalculated to improve design accuracy.
It significantly improves the design accuracy and efficiency of CMOS operational amplifiers, reduces the tedious process of manual debugging, and lowers design costs and resource consumption.
Smart Images
Figure CN121723957B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of analog integrated circuit technology, specifically a method for correcting design errors in a CMOS operational amplifier. Background Technology
[0002] CMOS operational amplifiers, as the core basic unit of analog and mixed-signal integrated circuits, are widely used in various integrated sensors, data converters, power management, and systems-on-a-chip. With the continuous advancement of process nodes, in order to meet design requirements such as low voltage, high gain, and high bandwidth, the structure of operational amplifiers has also evolved from the traditional two-stage Miller compensation to complex structures such as folded cascode, three-stage, and even more-stage nested Miller compensation.
[0003] Regardless of the architecture used, the core of operational amplifier design lies in determining the circuit topology and then calculating the dimensions of each MOSFET and the parameters of passive components based on preset performance specifications (such as unity-gain bandwidth, phase margin, slew rate, and noise). Classical design methods typically derive the calculation formulas from performance specifications to design parameters based on device models (such as the long-channel square-law model or the short-channel gm / ID method) and approximate analytical models of the circuit, thereby completing the initial design.
[0004] However, such methods have inherent design accuracy limitations. The main reasons are: first, the analytical expressions for circuit performance are usually derived from simplified models that ignore higher-order effects (such as higher-order zeros and poles) and various parasitic parameters, resulting in significant deviations from actual systems; second, the device models themselves contain errors due to advanced manufacturing processes. These factors mean that the initial design parameters calculated directly from theoretical formulas often fail to accurately achieve the preset targets in actual circuits, with performance errors typically reaching 20% or even higher.
[0005] To correct these errors, the industry currently relies heavily on manual debugging and iteration. Designers must repeatedly modify transistor dimensions and perform simulations, gradually approaching the target based on experience. This process is not only tedious and time-consuming, but also heavily dependent on the designer's personal experience, making analog circuit design a time-consuming and costly task. Although simulation-based automatic optimization algorithms can replace manual work to some extent, the process is like a "black box," consuming huge computational resources, and the optimization results lack physical intuitiveness, making them difficult for design engineers to understand and accept. Therefore, they have not been widely used in practical engineering design.
[0006] Therefore, there is an urgent need for a correction method that has clear physical meaning, is computationally efficient, and can significantly improve the accuracy of the initial design, in order to overcome the systematic deviations caused by various approximations in the existing design process and fundamentally improve the design efficiency and reliability of CMOS operational amplifiers. Summary of the Invention
[0007] The purpose of this invention is to overcome the shortcomings of the prior art and propose a method for correcting design errors in CMOS operational amplifiers. By combining simulation and theoretical calculation, this method identifies and corrects performance errors caused by model or manual design simplification, thereby ensuring that the final circuit performance meets or exceeds the predetermined specifications.
[0008] To achieve the above objectives, the technical solution specifically adopted by the present invention is as follows:
[0009] A method for correcting design errors in a CMOS operational amplifier includes the following steps:
[0010] S1. According to the predetermined performance indicators, the performance indicators mainly include unity-gain bandwidth, phase margin and slew rate; the CMOS operational amplifier is initially designed using conventional design process to obtain initial circuit parameters; the initial circuit parameters include at least the first stage transconductance, the second stage transconductance (for two-stage amplifiers), the bias current of each stage, the compensation capacitor and the load capacitor;
[0011] S2. Perform circuit simulation on the initial circuit to obtain the actual unity gain frequency, actual phase margin, and actual slew rate obtained from the simulation.
[0012] S3. Calculate the error factors based on the performance indicators and simulation results; the error factors include unity-gain bandwidth error factor, phase error factor, and slew rate error factor;
[0013] S4. Correct the design parameters using the error factor, and correct the first-stage transconductance: the corrected first-stage transconductance is equal to the initial first-stage transconductance divided by the unity-gain bandwidth error factor; correct the second-stage transconductance of the two-stage amplifier: first calculate the corrected pole separation coefficient by subtracting the phase error factor from the predetermined phase margin, and then calculate the corrected second-stage transconductance using the corrected pole separation coefficient, unity-gain frequency, and load capacitance; correct the bias current: the corrected bias current is equal to the corresponding theoretical bias current divided by the slew rate error factor;
[0014] S5. Based on the corrected design parameters, recalculate the dimensions of each MOSFET to complete the design error correction.
[0015] Preferably, the method for calculating the unity-gain bandwidth error factor is as follows:
[0016] Divide the actual unity-gain frequency obtained from the simulation by the initial design gain-bandwidth product; wherein, the gain-bandwidth product is equal to the initial first-stage transconductance divided by the compensation capacitor.
[0017] Preferably, the phase error factor is calculated as follows:
[0018] The actual phase margin obtained from the simulation is subtracted from the theoretical phase margin calculated based on the initial design parameters; wherein, the theoretical phase margin is equal to the arctangent value of the initial pole separation coefficient.
[0019] Preferably, the method for calculating the slewing rate error factor is as follows:
[0020] Divide the actual slewing rate obtained from the simulation by the predetermined target slewing rate value.
[0021] Preferably, the method further includes the following steps before step S1:
[0022] The design target value is increased according to the predetermined performance indicators so that the performance of the corrected circuit fully meets or exceeds the predetermined requirements.
[0023] Preferably, the CMOS operational amplifier is a Miller-compensated two-stage operational amplifier with zero-point elimination, wherein the value of the compensation resistor is equal to the reciprocal of the transconductance of the second stage.
[0024] Preferably, the CMOS operational amplifier is a two-stage operational amplifier with zero-pole cancellation compensation, wherein:
[0025] The value of the compensation resistor is equal to the reciprocal of the second-stage transconductance multiplied by the ratio of the load capacitance to the compensation capacitance plus 1, used to eliminate the original secondary poles; the new secondary pole is equal to the device characteristic frequency divided by the ratio of the load capacitance to the compensation capacitance plus 1; the correction formula for the second-stage transconductance current ratio is: the corrected second-stage transconductance current ratio is determined by interpolation of the corrected characteristic frequency, and the corrected characteristic frequency is equal to the corrected pole separation coefficient multiplied by the unity gain frequency and then multiplied by the ratio of the load capacitance to the compensation capacitance plus 1.
[0026] Preferably, the CMOS operational amplifier is a folded common-source cascode operational amplifier, wherein:
[0027] The unity-gain bandwidth is equal to the first-stage transconductance divided by the load capacitance; the slew rate is equal to the first-stage bias current divided by the load capacitance; the error correction method is the same as that for a two-stage op-amp.
[0028] Preferably, the CMOS operational amplifier is a three-stage nested Miller-compensated operational amplifier, comprising three amplification stages, wherein:
[0029] The unity-gain frequency is equal to the first-stage transconductance divided by the first compensation capacitor; the phase margin depends on the separation coefficient, which is equal to the ratio of the third-stage transconductance to the unity-gain frequency; the slew rate is equal to twice the first-stage bias current divided by the first compensation capacitor, equal to the second-stage bias current divided by the second compensation capacitor, and equal to the third-stage bias current divided by the sum of the load capacitor and the two compensation capacitors.
[0030] The correction method for the first stage transconductance is the same as that for a two-stage op-amp; the second stage transconductance is equal to the first stage transconductance; the correction of the third stage transconductance requires replacing the phase margin with the predetermined phase margin minus the phase error and then resolving the equation for determining the separation coefficient; the correction of the bias current of each stage is equal to the predetermined slew rate multiplied by the corresponding compensation capacitor or load capacitor, and then divided by the slew rate error factor.
[0031] This invention has the following characteristics and beneficial effects:
[0032] For CMOS operational amplifiers, this method can effectively improve design accuracy, quickly obtain designs that meet performance requirements, avoid tedious manual debugging, significantly improve design efficiency, and reduce circuit design and development costs. Improved design accuracy also helps to solve over-design problems, thereby reducing circuit power consumption and / or area consumption. The method is simple and easy to implement, has low computational cost, and is easy to master and apply. Attached Figure Description
[0033] Figure 1 This is a flowchart illustrating a method for correcting design errors in a CMOS operational amplifier according to the present invention.
[0034] Figure 2 This is a circuit diagram of a Miller-compensated two-stage operational amplifier with zero-point elimination and zero-pole cancellation according to the first embodiment of the present invention.
[0035] Figure 3 This is a circuit diagram of a folded common-source cascode operational amplifier according to a second embodiment of the present invention.
[0036] Figure 4 This is a circuit diagram of a three-stage nested Miller compensated operational amplifier according to the third embodiment of the present invention.
[0037] Figure 5 This is a schematic diagram showing the comparison of relative error correction before and after the design of a Miller-compensated two-stage operational amplifier with zero-point elimination in the first embodiment of the present invention.
[0038] Figure 6 A schematic diagram showing the comparison before and after relative error correction in the design of the folded common-source cascode operational amplifier according to the second embodiment of the present invention.
[0039] Figure 7 A schematic diagram showing the comparison before and after relative error correction in the design of a three-stage nested Miller compensated operational amplifier according to the third embodiment of the present invention.
[0040] Figure 8 This is a schematic diagram showing the comparison of relative error correction before and after designing the zero-pole cancellation compensation operational amplifier according to the fourth embodiment of the present invention.
[0041] Figure 9This is a schematic diagram of the design result of the zero-pole cancellation compensation operational amplifier after improving the preset performance in the fourth embodiment of the present invention. Detailed Implementation
[0042] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the following embodiments are for illustrative purposes only and not for limiting the scope of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without inventive effort are within the scope of protection of this invention.
[0043] The core of this invention lies in providing a method for correcting design errors in CMOS operational amplifiers. This method first completes the initial design and simulation using conventional procedures. By comparing the simulation results with the theoretical targets, error factors for key performance indicators (unity-gain bandwidth, phase margin, and slew rate) are calculated. Subsequently, these error factors are used to perform a one-time analytical correction on initial design parameters (such as transconductance and bias current), thereby significantly improving the final circuit performance's fit with the design targets and reducing repeated trial and error.
[0044] Example 1
[0045] This embodiment provides a method for correcting design errors in a CMOS operational amplifier, such as... Figure 1 As shown. Figure 2 Taking a two-stage operational amplifier with Miller compensation and zero-point elimination as an example, the specific method is as follows:
[0046] S1. According to the predetermined performance indicators, the performance indicators include unity-gain bandwidth, phase margin and slew rate; the CMOS operational amplifier is initially designed using a conventional design process to obtain initial circuit parameters; the initial circuit parameters include at least the first-stage transconductance, the second-stage transconductance, the bias current, the compensation capacitor and the load capacitor.
[0047] Specifically, in this embodiment, a conventional design process (e.g., based on the square law model or the gm / ID method) is used for the initial design. The steps are as follows:
[0048] Based on phase margin Calculate the pole separation coefficient Calculate the compensation capacitor based on noise requirements and unity-gain frequency:
[0049] ;
[0050] Calculate the bias current based on the slew rate and compensation capacitor:
[0051] ;
[0052] Calculate the first-stage transconductance and dimensions based on the unity-gain frequency:
[0053] ;
[0054] Calculate the second-stage transconductance and dimensions based on the phase margin:
[0055] , ;
[0056] Determine the dimensions of the tail current source and the current mirror.
[0057] ,in, ;
[0058] , .
[0059] In the above formula, It is thermal noise; (UGB: Unit Gain Bandwidth) is the unity gain bandwidth; (Slewing Rate) is the slewing rate SR. These are the lower limits of the input common-mode voltage.
[0060] It should be noted that the design of the above steps is based on the following: First, the characteristics of the device, namely the square-law model of the MOSFET.
[0061] ;
[0062] and the corresponding transconductance expression ( (It is the overdrive voltage)
[0063] ;
[0064] And unity-gain frequency:
[0065] ;
[0066] Phase margin ( (This is the secondary pole)
[0067] , ;
[0068] With slew rate:
[0069] ;
[0070] Lower limit of the circuit's input common-mode voltage:
[0071] ;
[0072] In addition, there is the equivalent thermal noise spectral density at the input:
[0073]
[0074] For deep submicron and nanometer-scale MOS circuits, since the model relationship is based on the square-law model for long channels, it will cause significant errors in the size calculation. It should be replaced with... Method. To ensure accuracy, a method should be adopted that considers different channel lengths and different V values. ds V bs Multidimensional influence surface.
[0075] The above design process, because the performance indicators are derived from an approximate circuit model of the operational amplifier, often results in design errors exceeding 20% or even higher. Due to the interdependencies between different performance indicators, reducing these errors through manual adjustments is not easy.
[0076] S2. Perform circuit simulation on the initial circuit to obtain the actual unity gain frequency, actual phase margin, and actual slew rate obtained from the simulation.
[0077] The simulation results reveal errors in the initial design. The errors in the design process arise because the performance metrics used are approximate. Both UGB and PM are determined by the frequency characteristics of the small-signal AC voltage transfer function at the circuit's input and output. The accurate transfer function is a higher-order rational function in the complex frequency domain.
[0078]
[0079] in, It is the DC open-loop gain. It is the first One zero point, It is the principal pole. This is the extreme point. ( () is a higher-order pole.
[0080] UGB is Using only the principal pole The phase margin obtained after approximation is based on only considering... , The result at the two poles. Therefore, the accurate UGB should be:
[0081] ;
[0082] in yes Except The product of the factors of the remaining zeros and poles. Ignoring these zeros and poles is equivalent to assuming In this case, UGB is approximately equal to GBW. The accurate phase margin can then be expressed as:
[0083] ;
[0084] Where Δ It is the sum of the contributions of higher-order zeros and poles to the phase.
[0085] S3. Calculate the error factors based on the performance indicators and simulation results; the error factors include unity-gain bandwidth error factor, phase error factor, and slew rate error factor.
[0086] Specifically, this method corrects errors generated in the common design process of operational amplifiers. By analyzing the sources of error, an error factor is defined and estimated based on the initial design results. Then, by re-executing the standard design steps using this error factor, the design can be corrected, yielding a more accurate result. This method is simple and easy to implement, effectively improving design accuracy and efficiency.
[0087] The calculation method for the unity-gain bandwidth error factor is as follows: divide the actual unity-gain frequency obtained from the simulation by the initial design gain-bandwidth product; wherein the gain-bandwidth product is equal to the initial first-stage transconductance divided by the compensation capacitor.
[0088] The phase error factor is calculated by subtracting the theoretical phase margin calculated based on the initial design parameters from the actual phase margin obtained from the simulation; wherein the theoretical phase margin is equal to the arctangent value of the initial pole separation coefficient.
[0089] The calculation method for the slewing rate error factor is as follows: divide the actual slewing rate obtained from the simulation by the predetermined target value of the slewing rate.
[0090] Specifically, neglecting , The two factors are the sources of error in the UGB and PM approximations during design; they are unknown before circuit design. However, after obtaining an initial design circuit by executing step S1, they can be estimated:
[0091] Unity-gain bandwidth error factor:
[0092] ;
[0093] The superscript '0' represents the quantity corresponding to the initial circuit. The actual unity-gain frequency is obtained through circuit simulation. It is the gain-bandwidth product of the initial design.
[0094] Phase error factor:
[0095]
[0096] in, The actual phase margin is obtained through circuit simulation. It is the pole separation coefficient of the initial design.
[0097] Slewing rate error factor:
[0098]
[0099] in, The actual slew rate is obtained through circuit simulation, and SR is the predetermined target value for the slew rate.
[0100] S4. Correct the design parameters using the error factor. Correct the first-stage transconductance: the corrected first-stage transconductance is equal to the initial first-stage transconductance divided by the unity-gain bandwidth error factor. Correct the second-stage transconductance: first calculate the corrected pole separation coefficient by subtracting the phase error factor from the predetermined phase margin, and then calculate the corrected second-stage transconductance using the corrected pole separation coefficient, unity-gain frequency, and load capacitance. Correct the bias current: the corrected bias current is equal to the corresponding theoretical bias current divided by the slew rate error factor.
[0101] The design parameters are corrected using the estimated error factor:
[0102] First-stage transconductance correction, By substituting the accurate UGB, the new gain-bandwidth product and the corresponding... :
[0103] The superscript '1' represents the corrected quantity. This formula indicates that the corrected first-stage transconductance is equal to the initial first-stage transconductance divided by the unity-gain bandwidth error factor.
[0104] The second-stage transconductance correction incorporates estimation errors into the phase margin:
[0105]
[0106] The corrected pole separation coefficient K can be calculated:
[0107]
[0108] Among them, correction factor for:
[0109]
[0110] Therefore, the second-order transconductance is redefined:
[0111]
[0112] in, It is the load capacitor.
[0113] Slew rate (SR) is an indicator of large-signal operating conditions. Common slew rates are approximate expressions under constant current charging and discharging conditions, neglecting parasitic capacitance. An accurate SR can also be expressed as the product of a common slew rate and an error factor:
[0114]
[0115] Similarly, estimates can be made based on the results of the initial design:
[0116]
[0117] Bias current correction: adjusts the slew rate error factor Substituting into the slew rate expression, we obtain the correction value for the bias current:
[0118]
[0119] in, This is the corrected first-stage bias current. It is the corrected second-stage bias current.
[0120] S5. Based on the corrected design parameters, recalculate the dimensions of each MOSFET to complete the design error correction.
[0121] Understandably, correction steps S2-S5 can be repeated to obtain more accurate design results; multiple corrections (such as...) Figure 1 (As shown by the dashed line), the result can be obtained that accurately meets the predetermined requirements, completely avoiding over-design problems.
[0122] It should be noted that, prior to step S1, the following steps may be included: increasing the design target value according to predetermined performance indicators so that the corrected circuit performance fully meets or exceeds the predetermined requirements. For example, UGB (unity-gain bandwidth) and SR (slew rate) are increased by 5% to 10%, and PM (phase margin) is increased by 1° to 2°.
[0123] The above process design example verification: using Process, MOSFET threshold voltage , ±0.9V power supply, load capacitor MOS transistor length , Design specifications: UGB = 10MHz~50MHz, PM = 60°. The result is as follows Figure 5 As shown, the vertical axis of the curve represents the relative errors of UGB, PM, and SR. The solid line represents the result of the commonly used manual design, while the dashed line represents the result after error correction according to the above process. It can be seen that the relative errors of each performance index are significantly reduced after correction.
[0124] The specific implementation methods of the present invention will be described below for three typical CMOS operational amplifier structures.
[0125] Example 2
[0126] The difference between this embodiment and Embodiment 1 is that it employs a two-stage operational amplifier with zero-pole elimination and Miller compensation.
[0127] The circuit remains the same Figure 2 The bandwidth of operational amplifiers using zero-pole cancellation compensation is limited by the location of the secondary poles. To increase the bandwidth, the transconductance of M6 must be increased, which leads to an increase in area or power consumption. However, using zero-pole cancellation compensation can significantly improve the bandwidth without increasing power consumption or area. This can be achieved simply by changing the value of the compensation resistor, such that:
[0128]
[0129] This can eliminate the primary and secondary poles. The new secondary pole is:
[0130]
[0131] in, This is the characteristic frequency of the device. The design steps for this op-amp are basically the same as those for zero-point elimination, except that the dimensional poles change. When determining the size of M6 based on phase requirements, the following relationship must be considered:
[0132]
[0133] The characteristic frequency of the device can be expressed as:
[0134]
[0135] in It is the intrinsic normalized capacitance parameter, whose value depends only on This confirms This allows us to further determine the dimensions of M6; The determination can be made in advance during the generation process. Curves are generated simultaneously Follow Changing curve The design was based on this curve, and the result was given through simple interpolation. Find .
[0136] Similarly, error correction only requires... In Replace with .
[0137] Design example verification: using The process, power supply, load capacitor, and MOSFET length values are the same as in the previous example. Design specifications: UGB = 60MHz~100MHz, PM = 60°. The result is as follows Figure 8 As shown, the relative errors of each performance index are significantly reduced after correction.
[0138] Furthermore, Figure 9 This is the result of design-correction of a two-stage operational amplifier with zero-pole cancellation compensation, where the performance of UGB and SR is increased by 5% and the phase margin is increased by 1° (i.e., PM=61°). After correction, the relative errors of UGB, PM, and SR are all positive, indicating that the predetermined requirements have been fully met or exceeded.
[0139] Example 3
[0140] The difference between this embodiment and Embodiment 1 is that a folded common-source cascode operational amplifier is used. This embodiment is specifically designed for... Figure 3 The single-stage, high-output-impedance folded cascode op-amp shown is also a very common circuit. Because it is a single-stage structure, the circuit does not require frequency compensation. Its unity-gain bandwidth is equal to the first-stage transconductance divided by the load capacitance; its slew rate is equal to the first-stage bias current divided by the load capacitance; the error correction method is the same as that for a two-stage op-amp.
[0141] Specifically, for this amplifier, the expressions for its unity-gain bandwidth and slew rate are similar to those for a two-stage op-amp, as follows:
[0142] ,
[0143] The corresponding error correction formula is the same. Since it is a single-stage structure with only one dominant pole at the output terminal, and the other poles are caused by parasitic parameters and are located far apart, the phase margin is generally above 70 degrees, which can meet the needs of most applications and does not require error correction.
[0144] The design of this op-amp begins with determining the input differential pair based on UGB and SR. and Then, determine the overdrive voltage and current of the remaining transistors, and then the dimensions of each device can be obtained.
[0145] Design example verification: using Process, ±0.6V power supply, load capacitor ; MOS transistor length , Design specifications: UGB = 200MHz~300MHz. The solid and dashed lines in the diagram have the same meaning. Figure 6 .
[0146] Example 4
[0147] The difference between this embodiment and Embodiment 1 is that a three-stage nested Miller compensated operational amplifier is used. The three-stage operational amplifier is a popular operational amplifier structure in low-voltage design under advanced technology in recent years. Figure 4 It is a three-stage op-amp that uses nested Miller compensation.
[0148] The CMOS operational amplifier is a three-stage nested Miller-compensated operational amplifier, comprising three amplification stages, wherein:
[0149] The slew rate is equal to twice the first-stage bias current divided by the first compensation capacitor, equal to the second-stage bias current divided by the second compensation capacitor, and equal to the third-stage bias current divided by the load capacitor.
[0150] The unity-gain frequency is equal to the first-stage transconductance divided by the first compensation capacitor; the second pole is equal to the square root of the product of the second-stage transconductance and the third-stage transconductance divided by the product of the second compensation capacitor and the load capacitor.
[0151] The correction method for the first stage transconductance is the same as that for a two-stage op-amp; the correction of the second stage transconductance requires replacing the phase margin with the predetermined phase margin minus the phase error factor and then solving it again; the correction of the bias current of each stage is equal to the predetermined slew rate multiplied by the corresponding compensation capacitor or load capacitor, and then divided by the slew rate error factor.
[0152] Specifically, for this amplifier, its slew rate expression is similar to that of the aforementioned two-stage amplifier, as follows:
[0153]
[0154] Compensation resistor
[0155] The voltage transfer function is:
[0156]
[0157] in It is the open-loop gain. , , These are the transconductances of the three amplifier transistors M1,2, M6, and M11 in the circuit. The design parameters that need to be determined include the transconductance of each stage. Bias current and compensation capacitor. First, it can be seen from the above formula that the unity-gain bandwidth of the op-amp remains the same as that of the two-stage op-amp; in fact, its noise expression is also the same. Therefore... , The method for determining this is the same as for the two-stage time. Next, it is determined by the phase margin. , and At this point, there is a certain degree of freedom; the method is to make
[0158]
[0159] Simultaneously take The phase margin can then be expressed from the voltage transfer function:
[0160]
[0161] Therefore, we can conclude that:
[0162]
[0163] in Thus, the phase margin can be solved from the above equation. ,get ; then confirm Once the compensation capacitors are determined, the current at each stage can be determined; subsequently, the dimensions of each MOSFET can be calculated.
[0164] Error correction was performed on the operational amplifier design. The correction formula and the new GBW and corresponding The same. The correction needs to be Replace with Then solve the equation again; for:
[0165]
[0166] in It is the phase margin obtained from the initial design through SPICE simulation. , After correction, Update, and then correct the current at each stage:
[0167]
[0168] Design example verification: using Process, ±0.6V power supply, load capacitor ; MOS transistor length , Design specifications: UGB = 30MHz~80MHz, PM = 65°. . Figure 8 The meanings of solid lines and dashed lines are the same as before.
[0169] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely preferred examples and are not intended to limit the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the present invention as claimed. The scope of protection of the present invention is defined by the appended claims and their equivalents.
Claims
1. A method of correcting for design errors in a CMOS operational amplifier, characterized by, Includes the following steps: S1. Based on predetermined performance indicators, including unity-gain bandwidth, phase margin, and slew rate, the CMOS operational amplifier is initially designed using a conventional design process to obtain initial circuit parameters. The initial circuit parameters include at least the first-stage transconductance, the second-stage transconductance, the bias current, the compensation capacitor, and the load capacitor. S2. Perform circuit simulation on the initial circuit to obtain the actual unity-gain bandwidth, actual phase margin, and actual slew rate obtained from the simulation. S3. Calculate the error factor based on the performance indicators and simulation results; The error factors include unity-gain bandwidth error factor, phase error factor, and slew rate error factor. S4. Use the error factor to correct the design parameters and correct the first-stage transconductance: the corrected first-stage transconductance is equal to the initial first-stage transconductance divided by the unity-gain bandwidth error factor. The second-stage transconductance is corrected by first calculating the corrected pole separation coefficient by subtracting the phase error factor from the predetermined phase margin, and then calculating the corrected second-stage transconductance by using the corrected pole separation coefficient, the predetermined unity-gain bandwidth, and the load capacitance. Correcting the bias current: The corrected bias current is equal to the bias current in the initial circuit parameters divided by the slew rate error factor. S5. Based on the corrected design parameters, recalculate the dimensions of each MOSFET to complete the design error correction.
2. The method according to claim 1, characterized in that, The method for calculating the unity-gain bandwidth error factor is as follows: Divide the actual unity-gain bandwidth obtained from the simulation by the initial design gain-bandwidth product; wherein, the gain-bandwidth product is equal to the initial first-stage transconductance divided by the compensation capacitor.
3. The method according to claim 1, characterized in that, The phase error factor is calculated as follows: The actual phase margin obtained from the simulation is subtracted from the theoretical phase margin calculated based on the initial circuit parameters; wherein, the theoretical phase margin is equal to the arctangent value of the initial pole separation coefficient.
4. The method according to claim 1, characterized in that, The calculation method for the slewing rate error factor is as follows: Divide the actual slewing rate obtained from the simulation by the predetermined target slewing rate value.
5. The method according to claim 1, characterized in that, The steps preceding step S1 also include: The design target value is increased according to the predetermined performance indicators so that the performance of the corrected circuit fully meets or exceeds the predetermined requirements.
6. The method according to claim 1, characterized in that, Repeat the correction steps S2-S5 to obtain more accurate design results; by performing multiple corrections, the results that accurately meet the predetermined requirements can be obtained, completely avoiding over-design problems.
7. The method according to claim 1, characterized in that, The CMOS operational amplifier is a two-stage operational amplifier with Miller compensation using zero-point elimination, wherein the value of the compensation resistor is equal to the reciprocal of the transconductance of the second stage.
8. The method according to claim 1, characterized in that, The CMOS operational amplifier is a two-stage operational amplifier with zero-pole cancellation compensation, wherein: The value of the compensation resistor is equal to the reciprocal of the second-stage transconductance multiplied by the ratio of the load capacitance to the compensation capacitance plus 1, used to eliminate the original secondary poles; the new secondary pole is equal to the device characteristic frequency divided by the ratio of the load capacitance to the compensation capacitance plus 1; the second-stage transconductance current ratio is determined by interpolation of the corrected characteristic frequency, and the corrected characteristic frequency is equal to the corrected pole separation coefficient multiplied by the unity gain frequency multiplied by the ratio of the load capacitance to the compensation capacitance plus 1.
9. The method according to claim 1, characterized in that, The CMOS operational amplifier is a folded common-source common-gate operational amplifier, wherein: The unity-gain bandwidth is equal to the first-stage transconductance divided by the load capacitance; the slew rate is equal to the first-stage bias current divided by the load capacitance; the error correction method is the same as that for a two-stage op-amp.
10. The method according to claim 1, characterized in that, The initial circuit parameters of the CMOS operational amplifier include the first-stage transconductance, second-stage transconductance, and third-stage transconductance bias currents, compensation capacitors, and load capacitors. The CMOS operational amplifier is a three-stage nested Miller-compensated operational amplifier, comprising three amplification stages, wherein: The unity-gain frequency is equal to the first-stage transconductance divided by the first compensation capacitor; the phase margin depends on the separation coefficient, which is equal to the ratio of the third-stage transconductance to the unity-gain frequency; the slew rate is equal to twice the first-stage bias current divided by the first compensation capacitor, equal to the second-stage bias current divided by the second compensation capacitor, and equal to the third-stage bias current divided by the sum of the load capacitor and the two compensation capacitors. The unity-gain frequency is equal to the first-stage transconductance divided by the first compensation capacitor; the second pole is equal to the square root of the product of the second-stage transconductance and the third-stage transconductance divided by the product of the second compensation capacitor and the load capacitor. The correction method for the first stage transconductance is the same as that for a two-stage op-amp; the second stage transconductance is equal to the first stage transconductance; the correction of the third stage transconductance requires replacing the phase margin with the predetermined phase margin minus the phase error factor and then resolving the equation for determining the separation coefficient; the correction of the bias current of each stage is equal to the predetermined slew rate multiplied by the corresponding compensation capacitor or load capacitor, and then divided by the slew rate error factor.