Display driver IC and display device including the same

Abstract

Disclosed are a display driver integrated circuit (IC) and a display device including the display driver IC. The display driver IC includes: a logic module that sequentially issues read commands, the read commands including a first read command, a second read command following the first read command, and a third read command following the second read command; and a plurality of memory modules connected in series. The first memory module is connected to the logic module and is the memory module closest to the logic module. The first memory module receives the read command; provides the first read command to a first memory of the first memory module; reads first image data from the first memory in response to the first read command; and provides the first image data and the first remaining read command of the read commands to a second memory module that is connected to the first memory module and is farther from the logic module than the first memory module.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2020-0062415, filed on May 25, 2020, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a display driver integrated circuit (IC) and a display device including the display driver IC, and more particularly, to a display driver IC including a memory module. Background Art

[0004] The display device used in the electronic device of the display image of such as television, notebook computer, monitor and mobile device includes liquid crystal display (LCD) or organic light emitting diode (OLED) display.The display device may include a display panel with multiple pixels and a display driver integrated circuit (IC) for sending an electrical signal to the pixel. The image can be realized by providing an electrical signal to the pixel from the display driver IC (that is, display driver IC). For application to mobile phones, it is desirable that the mobile display driver IC is lighter and smaller.

[0005] Mobile display driver ICs are not square, but rather rectangular with long sides. Therefore, the memory incorporated into these ICs faces the problem of long signal transmission distances. Furthermore, when factors such as product process and size change, the memory must be redesigned taking various factors into consideration. Summary of the Invention

[0006] Some aspects of the present disclosure provide a display driver integrated circuit (IC) including a memory module with reduced bandwidth loss.

[0007] Some aspects of the present disclosure also provide a display driver IC capable of reducing the time required to design a memory module.

[0008] Some aspects of the present disclosure also provide a display device having a display driver IC including a memory module with reduced bandwidth loss.

[0009] Some aspects of the present disclosure also provide a display device including a display driver IC capable of reducing time required to design a memory module.

[0010] However, some aspects of the present disclosure are not limited to the aspects set forth herein. The above and other aspects of the present disclosure will become clear to one of ordinary skill in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure provided below.

[0011] According to an exemplary embodiment of the present invention, a display driver integrated circuit (IC) includes: a logic module that sequentially issues multiple read commands, the multiple read commands including a first read command, a second read command following the first read command, and a third read command following the second read command; and multiple memory modules connected in series. A first memory module is connected to the logic module and is the memory module closest to the logic module. The first memory module receives the multiple read commands; provides the first read command to a first memory of the first memory module; reads first image data from the first memory in response to the first read command; and provides the first image data and a plurality of first remaining read commands of the multiple read commands to a second memory module that is connected to the first memory module and is farther from the logic module than the first memory module.

[0012] According to an exemplary embodiment of the present invention, a display driver IC includes: a logic module configured to sequentially issue multiple read commands for a first channel, the multiple read commands including a first read command, a second read command following the first read command, and a third read command following the second read command; a plurality of first-channel memory modules connected in series with each other in the first channel and including a first memory module, a second memory module, and a third memory module, the first memory module being disposed on a first side of the logic module and connected to the logic module, the first memory module being the memory module closest to the logic module among the plurality of first-channel memory modules; and a termination module connected to the last memory module of the plurality of first-channel memory modules, the last memory module being the farthest from the logic module among the plurality of first-channel memory modules. The first memory module includes a first decoder, a first memory, a first transmitter, a first downstream latch, and a first upstream latch. The first decoder receives the multiple read commands, provides the first read command to a first memory of the first memory module, and provides the first remaining read commands of the multiple read commands to a second memory module connected to the first memory module and further from the logic module than the first memory module via a first downstream latch. The first memory outputs first image data in response to a first read command and provides the first image data to a first transmitter. The first transmitter provides the first image data to a terminal module. A first upstream latch of the first memory receives the first image data from the terminal module and provides the first image data to a logic module.

[0013] According to an exemplary embodiment of the present invention, a display device includes: a display panel including pixels; gate lines electrically connected to the pixels; a gate driver configured to provide gate voltage signals to the pixels via the gate lines; source lines electrically connected to the pixels; a source driver configured to provide drive current to the pixels via the source lines; and a display driver controller that provides control signals to the source driver and the gate driver. The display driver controller includes: a logic module that issues a control signal including a first signal and a second signal subsequent to the first signal; a terminal module; and first, second, and third memory modules configured to store first, second, and third image data, respectively, to drive the gate driver and the source driver, and sequentially connected to each other. The first memory module is connected to the logic module, the third memory module is connected to the terminal module, and the second memory module is disposed between the first and third memory modules. Each of the first, second, and third memory modules includes a decoder, a memory, and a transmitter. The decoder of the first memory module is configured to provide the first signal to a memory of the first memory module and the second signal to a decoder of the second memory module, without providing the second signal to the memory of the first memory module. The second memory module accesses the memory of the second memory module in response to the second signal corresponding to the read command. The memory of the second memory module provides the second image data to the transmitter of the third memory module via the transmitter of the second memory module. The transmitter of the third memory module provides the second image data to the terminal module. The terminal module sequentially provides the second image data to the logic module via the third memory module, the second memory module, and the first memory module. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] These and / or other aspects will become clear and more readily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0015] Figure 1 is a block diagram of an electronic device 1 including a display device according to an embodiment of the present disclosure.

[0016] Figure 2 and Figure 3 is a block diagram of a display device including a display driver integrated circuit (IC) according to an embodiment of the present disclosure.

[0017] Figure 4 A display driver IC according to an embodiment of the present disclosure is shown.

[0018] Figure 5 Shown Figure 4 memory modules.

[0019] Figure 6 yes Figure 4 Magnified view of region R1.

[0020] Figures 7 to 9 is a flowchart illustrating a method of operating a display driver IC according to an embodiment of the present disclosure.

[0021] Figure 10 A display driver IC according to an embodiment of the present disclosure is shown.

[0022] Figure 11 Is shown driving Figure 10 The timing diagram of the display driver IC method.

[0023] Figure 12 A display driver IC according to an embodiment of the present disclosure is shown.

[0024] Figure 13 It shows the operation Figure 12 The timing diagram of the display driver IC method.

[0025] Figure 14 and Figure 15 A display driver IC according to an embodiment of the present disclosure is shown.

[0026] Figure 16 and Figure 17 An electronic device having a display device according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0027] Hereinafter, embodiments according to the technical spirit of the present disclosure will be described with reference to the accompanying drawings.

[0028] Now, refer to Figures 1 to 3 An electronic device 1 including a display device is described.

[0029] Figure 1 is a block diagram of an electronic device 1 including a display device according to an embodiment of the present disclosure. Figure 2 and Figure 3 is a block diagram of a display device including a display driver integrated circuit (IC) according to an embodiment of the present disclosure.

[0030] Reference Figure 1 The electronic device 1 according to the embodiment may include a display device 10, an input / output unit 20, a memory 30, a port 40, and a processor 50. The electronic device 1 may include a television, a desktop computer, or a mobile device such as a smartphone, a tablet personal computer (PC), and a notebook computer. The display device 10, the input / output unit 20, the memory 30, the port 40, and the processor 50 may communicate with each other via a bus 60.

[0031] The display device 10 may include a display driver and a display panel. In some embodiments, the display driver may display image data transmitted by a processor 50 (e.g., an application processor (AP)) via a bus 60 according to an operating mode on the display panel. The display driver may generate a plurality of gamma voltages corresponding to the number of bits of the image data transmitted by the processor 50, select at least some of the gamma voltages according to the image data, and input the selected gamma voltages to the unit buffer.

[0032] In some embodiments, two or more gamma voltages having different amplitudes may be input to an input port of a unit buffer, and the unit buffer outputs a gray voltage in a predetermined range.

[0033] Reference Figure 2 and Figure 3 , the display device 10 according to an embodiment of the present disclosure may include a display driver IC 100 (ie, a display driver IC) and a display panel 200 .

[0034] Reference Figure 2 , the display driver IC 100 can control the display panel 200 .

[0035] The display device 10 according to an embodiment of the present disclosure may be any one of various display devices such as an organic light emitting diode display (OLED), a liquid crystal display (LCD), an electrochromic display (ECD), a digital mirror device (DMD), an actuated mirror device (AMD), a grating light value (GLV), a plasma display panel (PDP), and an electroluminescent display (ELD).

[0036] Reference Figure 3 The display driver IC 100 may include a display driver controller 150 (ie, a display driver controller), a source driver 120 , and a gate driver 130 .

[0037] The display driver controller 150 can receive data DATA and commands CMD from the outside (e.g., from a host (e.g., processor 50) of a system having the display device 10), and provide image data RGB DATA, source driver control signals SDC, and gate driver control signals GDC required for operation to the source driver 120 and the gate driver 130. For example, the memory 300 can be a frame memory. The display driver controller 150 may further include an image processing unit, a memory controller, a command pre-buffer, a command register, and a command synchronization controller.

[0038] The display panel 200 may include a plurality of gate lines 131 transmitting scan signals in a row direction, a plurality of source lines 121 arranged in a direction crossing the gate lines 131 and transmitting data signals in a column direction, and a plurality of pixels PX arranged at intersections of the gate lines 131 and the source lines 121.

[0039] When the gate lines 131 are sequentially selected, a gray voltage may be applied to the pixels PX connected to the selected gate lines 131 through the source lines 121 .

[0040] Each of the pixels PX may include a switching transistor, a driving transistor, a storage capacitor, and an organic light emitting diode. Gate lines 131 and source lines 121 may be connected to the pixels PX.

[0041] The source driver 120 may convert the image data RGB DATA (digital data received from the display driving controller 150) into grayscale voltages and apply the grayscale voltages to the display panel 200 through the source lines 121. The gate driver 130 may sequentially scan the gate lines 131. The gate driver 130 may activate the selected gate lines 131 by applying a gate-on voltage to the selected gate lines 131, and the source driver 120 may output the corresponding grayscale voltages to the pixels PX connected to the activated gate lines 131. Thus, the display panel 200 may display an image horizontally line by horizontal line (that is, row by row).

[0042] The display device 10 can communicate with a host (e.g., a processor 50) through an interface circuit (I / F) 140. The interface circuit 140 receives data DATA and commands CMD transmitted in parallel or serially from the host, and provides the data DATA and commands CMD to the display driver controller 150. The data DATA and commands CMD can be transmitted from a host (e.g., a processor 50) of a system having the display device 10. The interface circuit 140 can receive the data DATA and commands CMD according to an interface method corresponding to a transmission method of the host. For example, the interface method used by the interface circuit 140 can be one of an RGB interface, a central processing unit (CPU) interface, a service provider interface (PSI), a mobile display digital interface (MDDI), and a mobile industry processor interface (MIPI).

[0043] The display driving controller 150 may include a timing controller 110 and a memory 300 .

[0044] The timing controller 110 may generate a source driver control signal SDC for controlling an operation timing of the source driver 120 and a gate driver control signal GDC for controlling an operation timing of the gate driver 130 based on signals such as data DATA and a command CMD.

[0045] The memory 300 can temporarily store one frame of image data RGB DATA to be displayed on the display panel 200, and output the one frame of image data RGB DATA, thereby displaying the image data RGB DATA on the display panel 200. The memory 300 is also called a graphic random access memory (GRAM), and a volatile memory such as a static random access memory (SRAM) can be used. However, the embodiments according to the technical spirit of the present disclosure are not limited thereto, and various memories can be used.

[0046] The display driving controller 150 may control the overall operation of the memory 300 , and specifically, control the address and time at which a write operation and a read operation are performed in the memory 300 .

[0047] Now, refer to Figures 4 to 9 The operation of the display driving IC 100 including the memory module 400 and the operation of the memory module 400 are described.

[0048] Figure 4 A display driver IC according to an embodiment of the present disclosure is shown. Figure 5 Shown Figure 4 memory modules. Figure 6 yes Figure 4 Magnified view of region R1. Figures 7 to 9 is a flowchart illustrating a method of operating a display driver IC according to an embodiment of the present disclosure.

[0049] Reference Figure 4 , the display driver IC 100 may include a logic area 101, a first area 102, and a second area 103. As shown in the figure, the display driver IC 100 may be in a rectangular shape in which one side is longer than the other side. However, the embodiments according to the technical spirit of the present disclosure are not limited thereto, and the display driver IC 100 may have other shapes.

[0050] The rectangular first region 102 may be provided on one side of the logic region 101, and the rectangular second region 103 may be provided on the other side of the logic region 101 opposite to the side where the first region 102 is provided. The logic region 101 may be provided between the first region 102 and the second region 103.

[0051] A logic module may be provided in the logic area 101. In addition, the logic module may include, for example, a timing controller 110 of the display driver IC 100. The logic module may control the source driver 120 and the gate driver 130, and may control the overall operation of the memory 300. In an example embodiment, the display driver IC 100 may have a dual-channel memory architecture having a first channel and a second channel.

[0052] The plurality of memory modules 400 may include a plurality of first channel memory modules for the first channel and disposed in the first area 102, and a plurality of second channel memory modules for the second channel and disposed in the second area 103. The memory 300 of the display driver IC 100 may include the memory modules 400, or may be the same as the memory modules 400. The memory modules 400 may be disposed in series along the sides of the first area 102 and the second area 103. The memory modules 400 may be connected to each other in series. For example, the memory modules 400 may be disposed in series and may be connected to each other. The memory module 400 disposed closest to the logic area 101 among the memory modules 400 may be connected to the logic module of the logic area 101. The logic module of the logic area 101 may control all operations of the memory modules 400. For example, the logic module may control the address and time of performing a write operation or a read operation on the memory module 400.

[0053] Reference Figure 5 , the memory module 400 may include a decoder 410 , a memory 420 , a first latch ( D1 ) 430 , a second latch ( D2 ) 440 , a transmitter 450 , and a third latch ( D3 ) 460 . Figure 4 The memory module 400 may have Figure 5 The memory module 400 has the same structure. However, the embodiment according to the technical spirit of the present disclosure is not limited thereto, and specific elements may be omitted.

[0054] The decoder 410 may be connected to the memory 420 and the first latch 430. The decoder 410 may receive the first signal S1 from the previous memory module 400. Alternatively, when the decoder 410 is connected to the logic module, the decoder 410 may receive the first signal S1 from the logic module. The decoder 410 may provide the second signal S2 to the memory 420. In the case of a write operation, the second signal S2 may include image data and a command, and in the case of a read operation, the second signal S2 may include a command.

[0055] The memory 420 may be connected to the decoder 410 and the transmitter 450. The memory 420 may include a GRAM. In addition, the memory 420 may include an SRAM. However, the embodiments according to the technical spirit of the present disclosure are not limited thereto, and the memory 420 may also include a volatile memory such as a dynamic RAM (DRAM) or a synchronous dynamic RAM (SDRAM). The memory 420 may receive the second signal S2 from the decoder 410 and perform a read operation or a write operation. After the read operation or the write operation, the memory 420 may provide a fourth signal S4 including an access result to the transmitter 450.

[0056] Each of the first latch 430 , the second latch 440 , and the third latch 460 may include a D flip-flop. However, the embodiment according to the technical spirit of the present disclosure is not limited thereto.

[0057] The second latch 440 may receive the third signal S3 from the previous memory module 400. The second latch 440 may receive the third signal S3 and store data. The second latch 440 may output the data and provide the data to the transmitter 450. When the memory module 400 is connected to the logic module, the third signal S3 is not provided to the second latch 440.

[0058] The transmitter 450 may be connected to the memory 420 and the second latch 440. The transmitter 450 may include a multiplexer (MUX). The transmitter 450 may receive the third signal S3 output from the second latch 440 and the fourth signal S4 output from the memory 420. The transmitter 450 may output the third signal S3 and the fourth signal S4 at different times by control. The transmitter 450 may provide the signal to the next memory module 400.

[0059] The first latch 430 may be connected to the decoder 410. The first latch 430 may receive a signal from the decoder 410 and store data. The first latch 430 may output data and provide a signal to the next memory module 400.

[0060] The third latch 460 may receive the fifth signal S5 from the other memory module 400 and store data. The third latch 460 may output data and provide a signal to the other memory module 400.

[0061] The operation of the memory module 400 may include a first operation A1, a second operation A2, and a third operation A3. The first operation A1 may be performed by the decoder 410 and the first latch 430. The second operation A2 may be performed by the memory 420, the second latch 440, and the transmitter 450. The third operation A3 may be performed by the third latch 460. In an example embodiment, the first operation A1 includes: propagating a signal from a logic module along a plurality of first channel memory modules. For example, the signal of the logic module may propagate out from the logic module along the downstream latch and the decoder of each of the plurality of first channel memory modules. In a read operation, the signal may include a plurality of read commands, for example, through the decoder of each first channel memory module, each of the plurality of read commands is delivered to the memory of the corresponding memory module, and the remaining read commands are provided to the next memory module. The second operation A2 and the third operation A3 may include providing the image data read from the corresponding first channel memory module to the logic module. For example, the second operation A2 may include delivering the read image data to the terminal module, which will be referred to later. Figure 12 To illustrate this, the third operation A3 may include returning the read image data from the terminal module to the logic module. The propagation directions in the second operation A2 and the third operation A3 may be opposite to each other. The second operation A2 and the third operation A3 may be collectively referred to as a fourth operation A4.

[0062] In some embodiments, when the operation of the memory module 400 is a read operation, the operation may include a first operation A1 for providing a plurality of read commands to the plurality of memory modules 400 and a fourth operation A4 for receiving image data read from the plurality of memory modules 400 .

[0063] The first operation A1 may include an operation of receiving a first signal S1 from a previous memory module 400 or a logic module. The first operation A1 may also include an operation of providing a second signal S2 to the memory 420 or an operation of providing the second signal S2 to the next memory module 400 through the first latch D1. The second signal S2 may include image data and a write command (in the case of a write operation) and may include a read command (in the case of a read operation).

[0064] The fourth operation A4 may include the second operation A2 and the third operation A3. The fourth operation A4 may include sending a fourth signal S4 including data read from the memory 420 of the memory module 400 to a terminal module 505 (see FIG. 5 ) described later. Figure 12 ), and the terminal module 505 (see Figure 12 ) is sent to the third latch 460 of the memory module 400. In addition, the fourth operation A4 may include: sending the third signal S3 received from the previous memory module 400 to the terminal module 505 (see Figure 12 ), and the terminal module 505 (see Figure 12 ) is transmitted to the third latch 460 of the memory module 400, which is substantially the same as the third signal S3. The fifth signal S5 may include the third signal S3 and the fourth signal S4. For example, in a read operation, the fourth signal S4 may correspond to data read from the memory module 400, and the third signal S3 may correspond to data provided to the memory module 400 from the previous memory module. In an example embodiment, the transmitter 450 may output the third signal S3 and the fourth signal S4 in sequence to form the fifth signal S5. In the fifth signal S5, the third signal S3 may precede the fourth signal S4.

[0065] In some embodiments, the first operation A1 and the fourth operation A4 may be separate operations. For example, when the first operation A1 is executed, the fourth operation A4 is not executed. When the fourth operation A4 is executed, the first operation A1 is not executed. In terms of timing, the first operation A1 and the fourth operation A4 may be separate operations. However, embodiments according to the technical spirit of the present disclosure are not limited thereto, and the first operation A1 and the fourth operation A4 may be executed together.

[0066] Reference Figure 6 , the (N-1)th memory module 401, the Nth memory module 402 and the (N+1)th memory module 403 may be arranged in Figure 4 Here, N may be a natural number of 2 or greater. Although three or more memory modules 400 are provided in the first region 102 in the drawings, embodiments according to the technical spirit of the present disclosure are not limited thereto, and only one memory module or two memory modules may be provided.

[0067] The (N-1)th memory module 401, the Nth memory module 402, and the (N+1)th memory module 403 can be connected to Figure 5 The memory modules 400 have the same structure. Each of the (N-1)th memory module 401, the Nth memory module 402, and the (N+1)th memory module 403 may include a decoder 410, a memory 420, a first latch (D1) 430 (i.e., a downstream latch), a second latch (D2) 440, a transmitter 450, and a third latch (D3) 460 (i.e., an upstream latch). To simplify the drawings, Figure 6 These numbers are omitted.

[0068] The transmitter 450 of the (N-1)th memory module 401 may be connected to the second latch 440 of the Nth memory module 402. The first latch 430 of the (N-1)th memory module 401 may be connected to the decoder 410 of the Nth memory module 402. The third latch 460 of the (N-1)th memory module 401 may be connected to the third latch 460 of the Nth memory module 402.

[0069] The transmitter 450 of the Nth memory module 402 may be connected to the second latch 440 of the (N+1)th memory module 403. The first latch 430 of the Nth memory module 402 may be connected to the decoder 410 of the (N+1)th memory module 403. The third latch 460 of the Nth memory module 402 may be connected to the third latch 460 of the (N+1)th memory module 403.

[0070] In some embodiments, the first operation A1 of each of the (N-1)th memory module 401, the Nth memory module 402 and the (N+1)th memory module 403 may include an operation of receiving a signal from a previous memory module or logic module and providing the signal to the memory 420 or an operation of providing the signal to the next memory module through the first latch 430.

[0071] In some embodiments, the fourth operation A4 of each of the (N-1)th memory module 401, the Nth memory module 402 and the (N+1)th memory module 403 may include: an operation of sending a signal including data read from the memory 420 to a terminal module through the next memory module (for example, the (N-1)th memory module 401, the Nth memory module 402 or the (N+1)th memory module 403), and an operation of sending a signal from the terminal module to the logic module through the memory module (for example, the (N-1)th memory module 401, the Nth memory module 402 or the (N+1)th memory module 403). In addition, the fourth operation A4 may include the operations of sending a signal received from a previous memory module (e.g., the (N-1)th memory module 401, the Nth memory module 402, or the (N+1)th memory module 403) to a terminal module and sending a signal from the terminal module to a logic module through a memory module (e.g., the (N-1)th memory module 401, the Nth memory module 402, or the (N+1)th memory module 403).

[0072] In some embodiments, the first operation A1 and the fourth operation A4 of each of the (N-1)th memory module 401, the Nth memory module 402, and the (N+1)th memory module 403 may be separate operations. In other words, the first operation A1 and the fourth operation A4 may be separate operations in terms of timing. However, embodiments according to the technical spirit of the present disclosure are not limited thereto, and the first operation A1 and the fourth operation A4 may be performed together.

[0073] Now, refer to Figure 7 A first operation A1 in the method of operating the display driver IC 100 is described.

[0074] A signal may be provided from the (N-1)th memory module 401 to the Nth memory module 402 (operation S470). The signal passing through the decoder 410 and the first latch 430 of the (N-1)th memory module 401 is provided to the decoder 410 of the Nth memory module 402. The signal provided to the decoder 410 of the Nth memory module 402 may include a command and image data for the memory 420 of the Nth memory module 402.

[0075] The decoder 410 of the Nth memory module 402 may determine whether to access the memory 420 of the Nth memory module 402 based on a signal received from the (N−1)th memory module 401 (operation S471 ).

[0076] For example, when a signal received from the (N-1)th memory module 401 requires access to the memory 420 of the Nth memory module 402 (operation S471-Yes), the decoder 410 of the Nth memory module 402 may provide a signal to the memory 420 of the Nth memory module 402. In addition, the decoder 410 of the Nth memory module 402 may transmit a signal that does not include a command (that is, a signal that includes null data) to the first latch 430 of the Nth memory module 402 (operation S472). The signal that includes null data and is transmitted to the first latch 430 does not operate the next memory module (e.g., the (N+1)th memory module 403) connected to the memory module (e.g., the Nth memory module 402).

[0077] When the signal received from the (N-1)th memory module 401 does not require access to the memory 420 of the Nth memory module 402 (operation S471-No), the decoder 410 of the Nth memory module 402 may provide the signal to the first latch 430 of the Nth memory module 402 (operation S473). Here, the signal received from the (N-1)th memory module 401 is not sent to the memory 420 of the Nth memory module 402, and the memory 420 of the Nth memory module 402 is not accessed. The first latch 430 of the Nth memory module 402 may store the data of the signal received from the (N-1)th memory module 401.

[0078] The first latch 430 of the Nth memory module 402 may output the stored data and provide the data to the (N+1)th memory module 403 (operation S474). In the process of storing and outputting the data in the first latch 430 of the Nth memory module 402, the signal may be delayed by 1 clock cycle. The decoder 410 of the (N+1)th memory module 403 may receive the delayed signal.

[0079] When the memory 420 of the memory module 400 does not need to be accessed, the operation of another memory module 400 does not occur in one cycle after the memory module 400. Therefore, power consumption of the display driving IC 100 can be prevented.

[0080] Now, refer to Figure 8 A second operation A2 in the method of operating the display driver IC 100 is described.

[0081] The logic module may determine whether to provide a signal from the transmitter 450 of the (N-1)th memory module 401 to the Nth memory module 402 (operation S480). The signal provided from the transmitter 450 of the (N-1)th memory module 401 may be a signal provided from the memory 420 of the (N-1)th memory module 401 or the second latch 440 of the (N-1)th memory module 401.

[0082] When a signal is provided from the transmitter 450 of the (N-1)th memory module 401 to the Nth memory module 402 (operation S480-Yes), the signal may be provided to the transmitter 450 (e.g., a multiplexer) of the Nth memory module 402 through the second latch 440 of the Nth memory module 402 (operation S481). The signal may be stored in the second latch 440 of the Nth memory module 402, may be delayed by 1 clock cycle, and then may be output to the transmitter 450 of the Nth memory module 402.

[0083] When the signal is not provided from the transmitter 450 of the (N-1)th memory module 401 to the Nth memory module 402 (Operation S480-No), for example, when the Nth memory module 402 is connected to the logic module, or when the memory 420 of the (N-1)th memory module 401 is not accessed, it can be determined whether the memory 420 of the Nth memory module 402 has received a read command signal (Operation S482). It can be determined whether the decoder 410 of the Nth memory module 402 has received a signal including read command data and whether the signal has been provided to the memory 420 of the Nth memory module 402.

[0084] When the memory 420 of the Nth memory module 402 has received a read command signal (operation S482-yes), a signal including image data can be output from the memory 420 of the Nth memory module 402 and then provided to the transmitter 450 (e.g., a multiplexer) of the Nth memory module 402 (operation S483).

[0085] When the memory 420 of the Nth memory module 402 does not receive the read command signal (operation S482-No), the logic module may again determine whether to provide a signal from the transmitter 450 of the (N-1)th memory module 401 to the Nth memory module 402 (operation S480).

[0086] A signal provided from the second latch 440 of the Nth memory module 402 to the transmitter 450 of the Nth memory module 402 or a signal provided from the memory 420 of the Nth memory module 402 to the transmitter 450 of the Nth memory module 402 may be provided to the (N+1)th memory module 403 through the transmitter 450 (operation S484). The transmitter 450 may selectively transmit a signal and may sequentially arrange and transmit a signal delayed by one clock cycle and provided from the (N-1)th memory module 401 and a signal output from the memory 420 of the Nth memory module 402. For example, a signal may be transmitted to the transmitter 450 of the (N+1)th memory module 403 via the second latch 440 of the (N+1)th memory module 403.

[0087] Now, refer to Figure 9 A third operation A3 in the method of operating the display driver IC 100 is described.

[0088] A signal may be provided from the (N+1)th memory module 403 to the Nth memory module 402 (operation S490). For example, a signal output from the transmitter 450 of the (N+1)th memory module 403 may be provided back to the (N+1)th memory module 403. The signal output from the transmitter 450 of the (N+1)th memory module 403 may be sent to the third latch 460 of the (N+1)th memory module 403. The third latch 460 of the (N+1)th memory module 403 may store the data of the signal and output a signal delayed by one clock cycle. The signal output from the third latch 460 of the (N+1)th memory module 403 may be sent to the third latch 460 of the Nth memory module 402. The third latch 460 of the Nth memory module 402 may store the data of the signal and output a signal delayed by one clock cycle.

[0089] A signal may be provided from the Nth memory module 402 to the (N-1)th memory module 401 (operation S491). For example, a signal output from the third latch 460 of the Nth memory module 402 may be sent to the third latch 460 of the (N-1)th memory module 401. The third latch 460 of the (N-1)th memory module 401 may store the data of the signal and output a signal delayed by one clock cycle. The signal output from the third latch 460 of the (N-1)th memory module 401 may be sent to, for example, a logic module.

[0090] Since the decoder 410 of each memory module 400 determines whether the memory 420 is accessed, power consumption can be reduced. In addition, since the signal provided by the first latch 430 of each memory module 400 is delayed, the memory modules 400 can be used sequentially. In addition, the signals received by the second latch 440 and the transmitter 450 can be delayed and arranged and transmitted sequentially.

[0091] The memory modules 400 have the same structure, for example, including a decoder 410, a memory 420, a first latch 430, a second latch 440, a transmitter 450, and a third latch 460. Therefore, the memory modules 400 can be cascaded (or connected in series) with each other starting from the logic module. In addition, the signals provided from the logic module can be sequentially transmitted through the memory modules 400, and the access results of the memory 420 can be output to the logic module through the memory modules 400.

[0092] Therefore, by using multiple memories, it is possible to store and output data with a large bandwidth, and to reduce random access constraints. For example, when four memory modules 400 are used and the memory 420 of one memory module 400 stores 2 Mb, the memory 300 can store 8 Mb when the four memory modules 400 are connected. In addition, the time and cost required to design the memory 300 using the same memory modules 400 can be reduced. For example, when a memory capacity greater than the memory capacity of the previously used memory 300 is required, the previously designed memory modules 400 can be connected in series and used.

[0093] Now, refer to Figure 10 and Figure 11 The operation of the display driving IC 100 when reading the memory of the memory module is described.

[0094] Figure 10 A display driver IC according to an embodiment of the present disclosure is shown. Figure 11 Is shown driving Figure 10 The timing diagram of the display driver IC method.

[0095] Reference Figure 10 , the display driver IC 100 may include a first memory module 501 and a second memory module 502. The first memory module 501 may be connected to Figure 4 The second memory module 502 may be connected to the first memory module 501 .

[0096] The first memory module 501 may include a decoder 510, a memory 511, a first latch 512, a second latch 513, and a transmitter 514. The second memory module 502 may include a decoder 520, a memory 521, a first latch 522, a second latch 523, and a transmitter 524.

[0097] The decoder 510 may receive a signal including first input clock data CKI1 (ie, a first input clock signal) and first input command data CMD_IN1. Figure 11 , the first command data CMD1 , the second command data CMD2 , the third command data CMD3 , and the fourth command data CMD4 may be sequentially set in each clock cycle.

[0098] The decoder 510 may transmit the first memory command data MEM CMD1 to the memory 511 . The first memory command data MEM CMD1 may be transmitted in a clock cycle in which the first input command data CMD_IN1 is transmitted. For example, the first command data CMD1 may be transmitted to the memory 511 .

[0099] The memory 511 may provide the first memory output data MEM Q1 to the transmitter 514. The memory 511 may output the first memory output data MEM Q1 based on the first memory command data MEM CMD1 and transmit the first memory output data MEM Q1 in the next clock cycle. For example, the first output data Q1 may be output from the memory 511.

[0100] The first latch 512 may receive a signal from the decoder 510 and output a signal including the first output clock data CK01 and the first output command data CMD_OUT1 . For example, the second command data CMD2 may be output from the first latch 512 .

[0101] When the first command data CMD1 is transmitted to the memory 511 , the first output command data CMD_OUT1 may sequentially include the second command data CMD2 , the third command data CMD3 , and the fourth command data CMD4 in each clock cycle.

[0102] The transmitter 514 may provide the first memory output data MEM Q1 to the second memory module 502 as the first memory module output data MOD Q1. For example, the transmitter 514 may output the first output data Q1 and transmit the first output data Q1 to the second memory module 502.

[0103] A signal including the first output clock data CK01 and the first output command data CMD_OUT1 may be transmitted to the second memory module 502, and a signal including the second input clock data CKI2 and the second input command data CMD_IN2 may be received by the decoder 520. The second input command data CMD_IN2 may sequentially include the second command data CMD2, the third command data CMD3, and the fourth command data CMD4 in each clock cycle.

[0104] The decoder 520 may receive a signal including the second input clock data CKI2 and the second input command data CMD_IN2. Figure 11 , the second command data CMD2 , the third command data CMD3 , and the fourth command data CMD4 may be sequentially provided to the decoder 520 in consecutive clock cycles.

[0105] The decoder 520 may transmit the second memory command data MEM CMD2 to the memory 521 . The second memory command data MEM CMD2 may be transmitted in a clock cycle in which the second input command data CMD_IN2 is transmitted. For example, the decoder 520 may provide the second command data CMD2 to the memory 521 .

[0106] Reference Figure 11 , skew may occur in the first input clock data CKI1 and the second input clock data CKI2. Clock skew may occur while transmitting signals between the first memory module 501 and the second memory module 502. However, the clock can be synchronized with the reference clock through an element such as a clock buffer to be described later.

[0107] Now, refer to Figure 12 and Figure 13 The operation of the display driver IC 500 according to the embodiment of the present disclosure is described when reading the memory of the display driver IC 500. Although the case of reading the memory is described, the operation of the memory is not limited to the read operation, and a write operation may also be performed.

[0108] Figure 12 A display driver IC according to an embodiment of the present disclosure is shown. Figure 13 It shows the operation Figure 12 The timing diagram of the display driver IC method.

[0109] Reference Figure 12 , in the first area 102 , the display driver IC 500 may include first to fourth memory modules 501 to 504 , a terminal module 505 , and a first-in-first-out (FIFO) module 540 (ie, a FIFO buffer).

[0110] The first to fourth memory modules 501 to 504 and the terminal module 505 may be sequentially connected in series. The FIFO module 540 may be provided on one side of the first memory module 501 and between the logic module and the first memory module 501. The FIFO module 540 may receive a signal to be transmitted to the logic module from the first memory module 501, process the signal, and then output and provide the processed signal to the logic module.

[0111] The first memory module 501 may receive first input command data CMD_IN1 from the logic module and output first memory module output data MOD Q1 to the second memory module 502. The second memory module 502 may receive second input command data CMD_IN2 from the first memory module 501 and output second memory module output data MOD Q2 to the third memory module 503. The third memory module 503 may receive third input command data CMD_IN3 from the second memory module 502 and output third memory module output data MOD Q3 to the fourth memory module 504. The fourth memory module 504 may receive fourth input command data CMD_IN4 from the third memory module 503 and output fourth memory module output data MOD Q4 to the terminal module 505.

[0112] The terminal module 505 can be connected to the fourth memory module 504, which is the last memory module in the series connection. The terminal module 505 may include a fourth latch 530. The fourth latch 530 may include a D flip-flop, but embodiments according to the technical spirit of the present disclosure are not limited thereto. The fourth latch 530 of the terminal module 505 can receive the fourth memory module output data MOD Q4 from the fourth memory module 504 and store the fourth memory module output data MOD Q4. The terminal data TERM Q output from the fourth latch 530 can be provided back to the fourth memory module 504.

[0113] The signal including the fourth memory module output data MOD Q4 may be delayed by one clock cycle by the fourth latch 530 of the terminal module 505 and then transmitted. Therefore, even when the data is returned to the fourth memory module 504, the static timing characteristics may be maintained.

[0114] The terminal data TERM Q output from the fourth latch 530 may be sequentially transmitted through the latch of the fourth memory module 504, the latch of the third memory module 503, the latch of the second memory module 502, and the latch of the first memory module 501, and then output as return data RTRN Q.

[0115] The FIFO module 540 may receive the return data RTRN Q output from the latch of the first memory module 501. While signals are being sent through the plurality of memory modules 400, as shown in FIG. Figure 11 As shown, skew may occur between clocks. For example, the clock signal sent from the logic module to the first memory module 501 and the clock signal output from the latch of the first memory module 501 may differ in phase. Therefore, the signal including the return data RTRN Q output from the latch of the first memory module 501 can be synchronized with the reference clock by using the FIFO module 540 and then sent to the logic module. In this example, the FIFO module 540 can receive the return data RTRN Q from the first memory module 501 and provide the return data RTRN Q to the logic module in response to the reference clock.

[0116] Figure 13 1 is a timing diagram illustrating a method of operating the display driver IC 500 assuming that clock skew does not occur. However, the embodiment according to the technical spirit of the present disclosure is not limited thereto, and clock skew may occur in signal transmission.

[0117] Reference Figure 13 , the clock CK_IN may include a first clock cycle t1 to a thirteenth clock cycle t13.

[0118] The first input clock data CMD_IN1 may include first, second, third, and fourth command data CMD1, CMD2, CMD3, and CMD4, which are sequentially input.

[0119] In a first clock cycle t1, first command data CMD1 may be input to the first memory module 501. In a second clock cycle t2, the first memory module 501 may output first output data Q1 and send the output first output data Q1 to the second memory module 502. In a third clock cycle t3, the second memory module 502 may delay the received first output data Q1 by one clock cycle and send the delayed first output data Q1 to the third memory module 503. In a fourth clock cycle t4, the third memory module 503 may delay the received first output data Q1 by one clock cycle and send the delayed first output data Q1 to the fourth memory module 504. In a fifth clock cycle t5, the fourth memory module 504 may delay the received first output data Q1 by one clock cycle and send the delayed first output data Q1 to the terminal module 505. Thus, the first command data CMD1 may be input to the first memory module 501, delayed by four clock cycles (T1), and then sent to the terminal module 505.

[0120] In the sixth clock cycle t6 , the termination module 505 may delay the received first output data Q1 by 1 clock cycle ( T2 ) by using the fourth latch 530 , and transmit the delayed first output data Q1 to the fourth memory module 504 .

[0121] In the seventh to tenth clock cycles t7 to t10 , the first to fourth memory modules 501 to 504 may delay the received first output data Q1 by 4 clock cycles ( T3 ) and transmit the delayed first output data Q1 to the FIFO module 540 .

[0122] In the second clock cycle t2, second command data CMD2 may be input to the first memory module 501. The second command data CMD2 may be delayed by the first memory module 501 and then sent to the second memory module 502. In the third clock cycle t3, the second command data CMD2 may be input to the second memory module 502. In the fourth clock cycle t4, the second memory module 502 may output second output data Q2 and send the output second output data Q2 to the third memory module 503. In the fifth clock cycle t5, the third memory module 503 may delay the received second output data Q2 by one clock cycle and send the delayed second output data Q2 to the fourth memory module 504. In the sixth clock cycle t6, the fourth memory module 504 may delay the received second output data Q2 by one clock cycle and send the delayed second output data Q2 to the terminal module 505.

[0123] In the seventh clock cycle t7 , the termination module 505 may delay the received second output data Q2 by one clock cycle using the fourth latch 530 , and send the delayed second output data Q2 to the fourth memory module 504 .

[0124] In the eighth to eleventh clock cycles t8 to t11 , the first to fourth memory modules 501 to 504 may delay the received second output data Q2 by 4 clock cycles and send the delayed second output data Q2 to the FIFO module 540 .

[0125] In the third clock cycle t3, the third command data CMD3 may be input to the first memory module 501. The third command data CMD3 may be delayed by the first memory module 501 and the second memory module 502, and then sent to the third memory module 503. In the fifth clock cycle t5, the third command data CMD3 may be input to the third memory module 503. In the sixth clock cycle t6, the third memory module 503 may output the third output data Q3 and send the output third output data Q3 to the fourth memory module 504. In the seventh clock cycle t7, the fourth memory module 504 may delay the received third output data Q3 by one clock cycle and send the delayed third output data Q3 to the terminal module 505.

[0126] In the eighth clock cycle t8 , the termination module 505 may delay the received third output data Q3 by one clock cycle using the fourth latch 530 , and send the delayed third output data Q3 to the fourth memory module 504 .

[0127] In the ninth to twelfth clock cycles t9 to twelfth clock cycles t12 , the first to fourth memory modules 501 to 504 may delay the received third output data Q3 by 4 clock cycles and send the delayed third output data Q3 to the FIFO module 540 .

[0128] In the fourth clock cycle t4, the fourth command data CMD4 may be input to the first memory module 501. The fourth command data CMD4 may be delayed by the first memory module 501, the second memory module 502, and the third memory module 503, and then transmitted to the fourth memory module 504. In the seventh clock cycle t7, the fourth command data CMD4 may be input to the fourth memory module 504. In the eighth clock cycle t8, the fourth memory module 504 may output fourth output data Q4, and may transmit the output fourth output data Q4 to the terminal module 505.

[0129] In a ninth clock cycle t9 , the termination module 505 may delay the received fourth output data Q4 by one clock cycle using the fourth latch 530 , and may send the delayed fourth output data Q4 to the fourth memory module 504 .

[0130] In the tenth to thirteenth clock cycles t10 to t13 , the first to fourth memory modules 501 to 504 may delay the received fourth output data Q4 by 4 clock cycles and may transmit the delayed fourth output data Q4 to the FIFO module 540 .

[0131] The first to fourth output data Q1 to Q4 transmitted to the FIFO module 540 may be synchronized with a reference clock by using the FIFO module 540 .

[0132] Now, refer to Figure 14 and Figure 15 A display driver IC according to an embodiment of the present disclosure is described. Hereinafter, differences from the above-described embodiment will be mainly described.

[0133] Figure 14 and Figure 15 A display driver IC according to an embodiment of the present disclosure is shown.

[0134] Reference Figure 14 The display driver IC 160 may include a logic area 101, a first area 102, and a second area 103. The first memory module 501 may be provided in the first area 102, and the memory module 601 may be provided in the second area 103. The first memory module 501 and the memory module 601 may be provided symmetrically with respect to the logic area 101. For example, a signal transmitted from the logic area 101 may be provided to the first memory module 501 and the memory module 601 from the same location, and a signal provided from the first memory module 501 and the memory module 601 to the logic area 101 may be provided to the same location in the logic area 101.

[0135] In some embodiments, the memory 511 of the first memory module 501 and the memory 611 of the memory module 601 may be disposed adjacent to lower ends of the first area 102 and the second area 103 , respectively.

[0136] Reference Figure 15 , the display driver IC 170 may include a logic area 101, a first area 102, and a second area 103. The first memory module 501 may be disposed in the first area 102, and the memory module 602 may be disposed in the second area 103. The first memory module 501 and the memory module 602 may be rotated 180 degrees relative to each other with respect to the logic area 101.

[0137] In some embodiments, the memory 511 of the first memory module 501 may be disposed adjacent to a lower end of the first area 102 , and the memory 611 of the memory module 602 may be disposed adjacent to an upper end of the second area 103 .

[0138] Figure 16 and Figure 17 An electronic device having a display device according to an embodiment of the present disclosure is shown.

[0139] Figure 16There is shown an electronic device 1 having a display device 10. Although a smartphone is shown in the drawings, the electronic device 1 may also be a television or a desktop computer, as well as a mobile device such as a smartphone, a tablet PC, or a notebook computer.

[0140] Figure 17 The electronic device 1 includes a display device 10 and a processor 50 .

[0141] The display device 10 may include a display panel 200, a display driver IC 100, and a printed circuit board substrate PCB. The display panel 200, the display driver IC 100, and the processor 50 may be connected to each other through the printed circuit board substrate PCB.

[0142] In some embodiments, when the electronic device 1 is a mobile device, the printed circuit board substrate PCB may include a flexible printed circuit board substrate. The flexible printed circuit board substrate is foldable, and the display driver IC 100 and the processor 50 may be attached to the flexible printed circuit board substrate. As the flexible printed circuit board substrate is folded, the display driver IC 100 and the processor 50 may be located on the back of the display panel 200. As in the conventional manner in the disclosed technical field, features and embodiments are described and illustrated in the accompanying drawings in the form of functional blocks, units and / or modules. Those skilled in the art will understand that these blocks, units and / or modules are physically implemented by electronic (or optical) circuits such as logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, wiring connections, etc., which can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. In the case of blocks, units and / or modules implemented by microprocessors or the like, they can be programmed using software (e.g., microcode) to perform the various functions discussed herein, and they can optionally be driven by firmware and / or software. Alternatively, each block, unit and / or module can be realized by dedicated hardware, or as a combination of dedicated hardware that performs some functions and a processor (for example, one or more programmed microprocessors and related circuits) that performs other functions. In addition, without departing from the scope of the present invention, each block, unit and / or module of embodiment can be physically separated into two or more interacting and discrete blocks, units and / or modules. In addition, without departing from the scope of the present invention, the block, unit and / or module of embodiment can be physically combined into more complex blocks, units and / or modules. It should be understood that when an element is referred to as "connected to" or "coupled to" another element or "located on" another element, it can be directly connected to or coupled to another element or located on another element, or there can be an intermediate element. On the contrary, when an element is referred to as "directly connected to" or "directly coupled to" another element or "contacting" another element, "contacting" with another element, there is no intermediate element. Other words used to describe the relationship between elements should be interpreted in the same manner (e.g., "between" versus "directly between," "adjacent" versus "directly adjacent," etc.). Ordinal numbers such as "first," "second," "third," etc. may simply be used as labels for specific elements, steps, etc. to distinguish these elements, steps, etc. from each other. Items not described as "first," "second," etc. in the specification may still be referred to as "first" or "second" in the claims. In addition, a term referenced by a specific ordinal number (e.g., "first" in a specific claim) may be described by a different ordinal number in another location (e.g., "second" in the specification or in another claim).

[0143] While the present disclosure has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure as defined in the following claims. The exemplary embodiments are to be regarded in a descriptive sense only and not for purposes of limitation.

Claims

1. A display driver integrated circuit, comprising: a logic module configured to sequentially issue a plurality of read commands, the plurality of read commands comprising a first read command, a second read command following the first read command, and a third read command following the second read command; and multiple memory modules connected in series with each other, wherein a first memory module among the plurality of memory modules is connected to the logic module, and the first memory module is a memory module among the plurality of memory modules that is closest to the logic module, and The first memory module is configured as follows: receiving the plurality of read commands; providing the first read command to the first memory of the first memory module; reading out first image data from the first memory in response to the first read command; and The first image data and a plurality of first remaining read commands of the plurality of read commands are provided to a second memory module, wherein the second memory module is connected to the first memory module and is farther from the logic module than the first memory module.

2. The display driver integrated circuit according to claim 1, in, The second memory module is configured as follows: receiving the plurality of first remaining read commands and the first image data from the first memory module; providing the second read command to the second memory of the second memory module; reading second image data from the second memory in response to the second read command; and providing the first image data, the second image data, and a plurality of second remaining read commands of the plurality of first remaining read commands to a third memory module, wherein the third memory module is connected to the second memory module and is farther from the logic module than the second memory module, and The first image data is output before the second image data.

3. The display driver integrated circuit according to claim 2, further comprising: a terminal module connected to a last memory module of the plurality of memory modules connected in series with each other, The last memory module is the one of the plurality of memory modules farthest from the logic module, and Wherein, the terminal module is configured as follows: sequentially receiving a plurality of image data generated from the plurality of memory modules; and The plurality of image data are sequentially provided to the logic module via the plurality of memory modules.

4. The display driver integrated circuit according to claim 2, in, The third memory module is configured as follows: receiving the first image data, the second image data, and the plurality of second remaining read commands from the second memory module; providing the third read command to a third memory of the third memory module; reading third image data from the third memory in response to the third read command; and The first image data, the second image data, the third image data, and a plurality of third remaining read commands among the plurality of second remaining read commands are provided to a fourth memory module, wherein the fourth memory module is connected to the third memory module and is farther from the logic module than the third memory module.

5. The display driver integrated circuit according to claim 1 , further comprising: a terminal module connected to a last memory module of the plurality of memory modules connected in series with each other and farther from the logic module than the last memory module, Wherein, the terminal module is configured as follows: sequentially receiving a plurality of image data from the last memory module, each of the plurality of image data being generated by a corresponding one of the plurality of memory modules; and The plurality of image data are sequentially provided to the logic module via the plurality of memory modules.

6. The display driver integrated circuit according to claim 5, in, The terminal module includes a latch connected to the last memory module and configured to sequentially provide the plurality of image data received from the last memory module to the logic module.

7. The display driver integrated circuit according to claim 5, in, The first memory module includes a first latch, the second memory module includes a second latch, wherein the second latch of the second memory module is configured to receive the first image data generated from the first memory, and The first latch of the first memory module is configured to sequentially receive the plurality of image data provided from the terminal module and sequentially provide the plurality of image data to the logic module.

8. The display driver integrated circuit according to claim 1, in, The first memory module further includes a latch, and The latch of the first memory module is configured as follows: sequentially receiving the plurality of read commands; delaying the first plurality of remaining read commands; and The delayed plurality of first remaining read commands are sequentially provided to the second memory module.

9. The display driver integrated circuit according to claim 1, in, The logic module is configured to also issue a clock signal to the first memory module, and The plurality of memory modules are configured such that the clock signal propagates from the first memory module to a last memory module of the plurality of memory modules that is farthest from the logic module.

10. A display driver integrated circuit comprising: a logic module configured to sequentially issue a plurality of read commands for a first channel, the plurality of read commands comprising a first read command, a second read command following the first read command, and a third read command following the second read command; a plurality of first channel memory modules connected in series with each other in the first channel and including a first memory module, a second memory module, and a third memory module, wherein the first memory module is disposed on a first side of the logic module and connected to the logic module, and is a memory module closest to the logic module among the plurality of first channel memory modules; and a terminal module connected to a last memory module of the plurality of first channel memory modules, the last memory module being a memory module farthest from the logic module among the plurality of first channel memory modules, The first memory module includes a first decoder, a first memory, a first transmitter, a first downstream latch, and a first upstream latch. The first decoder is configured as follows: receiving the plurality of read commands; providing the first read command to the first memory of the first memory module; and providing a first plurality of remaining read commands of the plurality of read commands to a second memory module via a first downstream latch, wherein the second memory module is connected to the first memory module and is farther from the logic module than the first memory module, wherein the first memory is configured to output first image data in response to the first read command and provide the first image data to the first transmitter; The first transmitter is configured to provide the first image data to the terminal module, and The first upstream latch of the first memory is configured to receive the first image data from the terminal module and provide the first image data to the logic module.

11. The display driver integrated circuit according to claim 10, in, The second memory module includes a second decoder, a second memory, a second transmitter, a second downstream latch, and a second upstream latch, and The second decoder of the second memory module is configured as follows: receiving the plurality of first remaining read commands from the first memory module; sending the second read command to the second memory of the second memory module; and A second plurality of remaining read commands in the first plurality of remaining read commands are provided to a third memory module via the second downstream latch, wherein the third memory module is connected to the second memory module and is farther from the logic module than the second memory module.

12. The display driver integrated circuit according to claim 11, in, the second memory being configured to output second image data in response to the second read command and to provide the second image data to the second transmitter, The second transmitter of the second memory module is configured to sequentially output the first image data received from the first memory module and the second image data received from the second memory module to the terminal module, and The second upstream latch of the second memory module is configured to sequentially receive the first image data and the second image data from the terminal module, and sequentially provide the first image data and the second image data to the logic module.

13. The display driver integrated circuit according to claim 12, in, The third memory module includes a third decoder, a third memory, a third transmitter, a third downstream latch, and a third upstream latch, The third decoder of the third memory module is configured as follows: receiving the second plurality of remaining read commands from the second memory module; providing the third read command to a third memory of the third memory module; and providing a plurality of third remaining read commands of the plurality of second remaining read commands to a fourth memory module, wherein the fourth memory module is connected to the third memory module and is farther from the logic module than the third memory module, and The third memory is configured to output third image data in response to the third read command, and provide the third image data to the third transmitter.

14. The display driver integrated circuit according to claim 13, in, The third transmitter of the third memory module is configured to sequentially output the first image data received from the second memory module, the second image data received from the second memory module, and the third image data received from the third memory module to the terminal module, and The third upstream latch of the third memory module is configured to sequentially receive the first image data, the second image data, and the third image data from the terminal module, and sequentially provide the first image data, the second image data, and the third image data to the logic module.

15. The display driver integrated circuit according to claim 10, in, The first upstream latch includes a D flip-flop.

16. The display driver integrated circuit according to claim 10, in, The logic module is configured to further issue a clock signal to the first memory module, wherein the plurality of first channel memory modules are configured such that the clock signal propagates from the first memory module to the last memory module of the plurality of first channel memory modules that is farthest from the logic module; The display driver integrated circuit further includes a first-in-first-out buffer disposed between the logic module and the first memory module and connected to the first upstream latch of the first memory module, and The first-in-first-out buffer is configured to receive the first image data in response to a reference clock and provide the first image data to the logic module.

17. The display driver integrated circuit according to claim 10, in, The logic module issues a plurality of read commands for the second channel, Wherein, the display driver integrated circuit further includes a plurality of second channel memory modules, wherein a first memory module of the plurality of second channel memory modules is disposed on a second side of the logic module opposite to the first side and is connected to the second side, and Each of the plurality of second channel memory modules includes a decoder, a memory, a transmitter, a downstream latch, and an upstream latch.

18. The display driver integrated circuit according to claim 17, in, The first memory of a first memory module among the plurality of first channel memory modules is disposed adjacent to a lower end of the first memory module, and the memory of a first memory module among the plurality of second channel memory modules is disposed adjacent to an upper end of the first memory module among the plurality of second channel memory modules.

19. A display device comprising: a display panel comprising pixels; a gate line electrically connected to the pixel; a gate driver configured to provide a gate voltage signal to the pixel through the gate line; a source line electrically connected to the pixel; a source driver configured to provide a driving current to the pixel through the source line; as well as a display driver controller configured to provide control signals to the source driver and the gate driver, Wherein, the display driver controller includes: a logic module configured to issue a control signal including a first signal and a second signal subsequent to the first signal; terminal modules; and a first memory module, a second memory module, and a third memory module, wherein the first memory module, the second memory module, and the third memory module are configured to store first image data, second image data, and third image data, respectively, to drive the gate driver and the source driver, and are sequentially connected to each other, The first memory module is connected to the logic module, the third memory module is connected to the terminal module, and the second memory module is arranged between the first memory module and the third memory module. wherein each of the first memory module, the second memory module, and the third memory module comprises a decoder, a memory, and a transmitter; wherein the decoder of the first memory module is configured to provide the first signal to the memory of the first memory module and to provide the second signal to the decoder of the second memory module without providing the second signal to the memory of the first memory module, wherein the second memory module is configured to access the memory of the second memory module in response to a second signal corresponding to a read command, wherein the memory of the second memory module is configured to provide the second image data to the transmitter of the third memory module via the transmitter of the second memory module, The transmitter of the third memory module is configured to provide the second image data to the terminal module, and The terminal module is configured to sequentially provide the second image data to the logic module through the third memory module, the second memory module, and the first memory module.

20. The display device according to claim 19, in, The memory included in each of the first memory module, the second memory module, and the third memory module includes a static random access memory.

Images