Gate driving circuit and display device including the same

Abstract

The present application relates to a gate driving circuit and a display device including the same. The gate driving circuit includes a plurality of driving stages each configured to provide a gate signal to a corresponding gate line of a plurality of gate lines, wherein each of the plurality of driving stages includes a first transistor electrically connected between a first clock terminal and a gate output terminal, the first transistor including a gate electrode electrically connected to a first node, the first clock terminal configured to receive a first clock signal; a second transistor configured to transmit a first carry signal to the first node; and a third transistor electrically connected between the first node and a first voltage terminal, the third transistor including a gate electrode electrically connected to the first voltage terminal, the first voltage terminal configured to receive a first voltage, wherein the gate output terminal is electrically connected to the corresponding gate line.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2020-0063201, filed on May 26, 2020, which is incorporated herein by reference for all purposes as if fully set forth herein. Technical Field

[0003] Exemplary implementations of the present invention generally relate to display devices, and more specifically, to display devices including gate driving circuitry. Background Technology

[0004] Typically, a display device includes a display panel for displaying images and driving circuitry for driving the display panel. The display panel includes multiple gate lines, multiple data lines, and multiple pixels. Each pixel is connected to a corresponding gate line among the multiple gate lines and a corresponding data line among the multiple data lines. The driving circuitry includes a data driving circuit for outputting data signals to the data lines, a gate driving circuit for outputting gate signals for driving the gate lines, a voltage generating circuit for providing a clock signal to the gate driving circuit, and a timing controller for controlling the data driving circuit and the gate driving circuit. The voltage generating circuit can generate the clock signal and voltage according to the control of the timing controller.

[0005] When the drive circuit is powered on, the timing controller performs an initialization operation. In this case, when the gate line is in a floating state, a noisy image may be displayed on the display device.

[0006] The information disclosed in this background section is only for understanding the background technology of the inventive concept, and therefore may include information that does not constitute prior art. Summary of the Invention

[0007] The applicant discovered that when the display device is powered on, it displays a noisy image due to the floating state of the gate lines of the display device.

[0008] A display device constructed according to the principles and exemplary implementations of the present invention can prevent or minimize noisy images caused by the floating state of the gate lines of the display device by discharging the gate lines.

[0009] The display device constructed according to the principles and exemplary implementations of the present invention can operate stably when powered on by providing a gate drive circuit for preventing the gate lines of the display device from floating.

[0010] Additional features of the inventive concept will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the inventive concept.

[0011] According to one or more example embodiments of the present application, a gate drive circuit includes a plurality of drive stages, each of the plurality of drive stages configured to provide a gate signal to a respective gate line of a plurality of gate lines, wherein each of the plurality of drive stages includes a first transistor electrically connected between a first clock terminal and a gate output terminal, the first transistor including a gate electrode electrically connected to a first node, the first clock terminal for receiving a first clock signal; a second transistor configured to transmit a first carry signal to the first node; and a third transistor electrically connected between the first node and a first voltage terminal, the third transistor including a gate electrode electrically connected to the first voltage terminal, the first voltage terminal for receiving a first voltage, wherein the gate output terminal is electrically connected to the respective gate line.

[0012] The first voltage can be changed from a first level to a second level during an initialization mode, the second level being different from the first level.

[0013] The first voltage can be changed to sequentially have the first level, the second level, and the first level during the initialization mode, the second level being different from the first level.

[0014] The first clock signal can have a low level during the initialization mode.

[0015] The third transistor can be configured to transmit the first voltage to the first node when the first voltage has the second level.

[0016] Each of the plurality of drive stages can further include a fourth transistor connected between the gate output terminal and a second voltage terminal for receiving a second voltage, the fourth transistor including a gate electrode connected to a second clock terminal for receiving a second clock signal.

[0017] Each of the plurality of drive stages can further include a fifth transistor connected between the first clock terminal and a carry output terminal, the fifth transistor including a gate electrode connected to the first node, and the carry output terminal can be configured to output the carry signal.

[0018] According to one or more example embodiments of the present application, a display apparatus includes a display panel including a plurality of pixels respectively connected to a plurality of data lines and respectively connected to a plurality of gate lines; a data driving circuit configured to drive the plurality of data lines; a gate driving circuit configured to drive the plurality of gate lines; a timing controller configured to receive an image signal and a control signal, control the data driving circuit and the gate driving circuit to display an image on the display panel, and output a gate pulse signal; and a voltage generating circuit configured to output a first clock signal and a first voltage in response to the gate pulse signal, wherein the voltage generating circuit is configured to change the first voltage such that the first voltage sequentially has a first level and a second level during an initialization mode, the second level is different from the first level, and the gate driving circuit includes a plurality of driving stages, each of the plurality of driving stages is configured to provide a gate signal to a corresponding gate line of the plurality of gate lines, wherein each of the plurality of driving stages is configured to discharge the corresponding gate line in response to the first voltage and the first clock signal during the initialization mode.

[0019] The first voltage can be changed to sequentially have the first level, the second level, and the first level during the initialization mode.

[0020] Each of the plurality of driving stages can include a first transistor connected between a first clock terminal for receiving the first clock signal and a gate output terminal, the first transistor including a gate electrode connected to a first node; a second transistor configured to transmit a first carry signal to the first node; and a third transistor connected between the first node and a first voltage terminal for receiving the first voltage, the third transistor including a gate electrode connected to the first voltage terminal.

[0021] The third transistor can be configured to transmit the first voltage to the first node when the first voltage has the second level.

[0022] The voltage generating circuit can be further configured to generate a second clock signal different from the first clock signal and a second voltage different from the first voltage.

[0023] Each of the plurality of driving stages can further include a fourth transistor connected between the gate output terminal and a second voltage terminal for receiving the second voltage, the fourth transistor including a gate electrode connected to a second clock terminal for receiving the second clock signal.

[0024] The voltage generating circuit can be configured to maintain the first clock signal and the second clock signal at a low level during the initialization mode.

[0025] The voltage generating circuit can be configured to maintain the second voltage at the first level during the initialization mode.

[0026] Each of the multiple driver stages also includes a fifth transistor connected between a first clock terminal and a carry output terminal, the fifth transistor including a gate electrode connected to a first node, and the carry output terminal configured to output a carry signal.

[0027] The carry signal output from the j-th driver stage among multiple driver stages can be provided to the carry input of the (j+1)-th driver stage, where j is a natural number.

[0028] The timing controller can be configured to provide a start signal to the gate drive circuit during drive mode.

[0029] The first of the multiple drive stages in the gate drive circuit can be configured to receive a start signal via a carry input.

[0030] It should be understood that the foregoing general description and the following detailed description are exemplary and illustrative, and are intended to provide further explanation of the claimed invention. Attached Figure Description

[0031] The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the invention and, together with the description, serve to illustrate the concept of the invention.

[0032] Figure 1 This is a block diagram illustrating the configuration of an exemplary embodiment of a display device constructed according to the principles of the present invention.

[0033] Figure 2 yes Figure 1 The equivalent circuit diagram of each representative pixel of the display device.

[0034] Figure 3A and Figure 3B It is used for explanation Figure 1 The timing diagram of the operation of the display device.

[0035] Figure 4 This is an example shown Figure 1 A block diagram of the configuration of the gate drive circuit of the display device.

[0036] Figure 5 This is an example shown Figure 1 The timing diagram shows the operation of the gate drive circuit of the display device.

[0037] Figure 6 yes Figure 4 The circuit diagram of the drive stage in the gate drive circuit.

[0038] Figure 7 It is used to show Figure 6 Timing diagram of driver-level operations. Detailed Implementation

[0039] In the following description, numerous specific details are set forth for illustrative purposes to provide a thorough understanding of various exemplary embodiments or implementations of the invention. As used herein, “implementation” and “method” are interchangeable terms and are non-limiting examples of devices or methods employing one or more of the inventive concepts disclosed herein. However, it will be apparent that various exemplary embodiments can be practiced without these specific details or having one or more common arrangements. In instances, well-known structures and devices are shown in block diagram form to avoid unnecessarily obscuring the various exemplary embodiments. Furthermore, the various exemplary embodiments may be different, but are not necessarily exclusive. For example, a particular shape, configuration, and characteristic of an exemplary embodiment may be used or implemented in another exemplary embodiment without departing from the inventive concept.

[0040] Unless otherwise stated, the exemplary embodiments shown should be understood as exemplary features providing different details of some ways in which the inventive concept can be implemented in practice. Therefore, unless otherwise stated, features, components, modules, layers, films, panels, regions and / or aspects (hereinafter individually or collectively referred to as “elements”) of various embodiments may be combined, separated, interchanged and / or rearranged without departing from the inventive concept.

[0041] In the accompanying drawings, the use of section lines and / or shading is generally used to clarify the boundaries between adjacent elements. Therefore, unless otherwise stated, the presence or absence of section lines or shading does not convey or indicate any preference or requirement for particular materials, material properties, dimensions, scale, commonalities between the shown elements, and / or any other characteristics, properties, etc., of the elements. Furthermore, in the accompanying drawings, the dimensions and relative dimensions of elements may be exaggerated for clarity and / or descriptive purposes. A particular sequence of processes may be performed differently than the sequence described when exemplary embodiments can be implemented differently. For example, two consecutively described processes may be performed substantially simultaneously, or in the reverse order of their description. Furthermore, the same reference numerals denote the same elements.

[0042] When an element or layer is referred to as being "on", "connected to", or "coupled to" another element or layer, it can be directly on, connected, or coupled to the other element or layer, or intervening elements or layers can be present. In contrast, when an element or layer is referred to as being "directly on", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers present. In this regard, the term "connected" can mean physical, electrical, and / or fluidic connection in the presence or absence of intervening elements. Also, the DR1 axis, the DR2 axis, and the DR3 axis are not limited to three axes of a rectangular coordinate system (such as, for example, the x-axis, the y-axis, and the z-axis), and can be interpreted in a broader sense. For example, the DR1 axis, the DR2 axis, and the DR3 axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. For the purposes of the present disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted to include any and all combinations of X, Y, and Z, such as, for example, XYZ, XYY, YZ, and ZZ. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0043] Although the terms "first", "second", etc. can be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, a first element discussed below could be termed a second element without departing from the teachings of the present disclosure.

[0044] Spatially relative terms such as "beneath", "below", "lower", "under", "above", "upper", "on", "over", "side" (as in "sidewall"), and the like, can be used herein for descriptive purposes, and, thereby, to describe one element's relationship to another element(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture in addition to the orientations depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. For example, where an element or feature is said to be "above" another, it is also said, possibly permissively, to be "below" the other. Moreover, the device can be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and, accordingly, the spatially relative descriptors used herein are to be interpreted in the context of such other orientations. The specific spatial and directional descriptions herein are used for the purpose of illustration and do not limit the application.

[0045] The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, to the extent that the terms "including," "includes," "having," "has," "with," or "contains" or variants thereof are used in either the detailed description and / or the claims, such terms are intended to be inclusive in a manner similar to the term "comprising." It is also to be noted that the term "about" and / or "approximately" as used herein when used in connection with a quantity is meant to encompass minor variations (plus or minus ten percent) from the given value, unless otherwise specifically stated.

[0046] In accordance with common practice, some of the examples described herein are illustrated by way of functional blocks, units and / or modules. Those skilled in the art will understand that these blocks, units and / or modules are to be interpreted as physical (e.g., hardware) circuits, or as electronic circuits (e.g., logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, wired connections, etc.) that can be formed using semiconductor-based fabrication techniques or other manufacturing techniques. In cases where the blocks, units and / or modules are implemented by a microprocessor or other similar hardware, software (e.g., microcode) can be used to program and control the blocks, units and / or modules to perform the various functions discussed herein, and they can optionally be driven by firmware and / or software. It is also contemplated that each block, unit and / or module can be implemented by dedicated hardware as is also commonly practiced, or implemented as a combination of dedicated hardware to perform some functions and a processor (e.g., one or more programmed microprocessors and associated circuitry) to perform other functions. In addition, each block, unit and / or module of some of the examples can be physically separated into two or more distinct blocks, units and / or modules without departing from the scope of the inventive concept. Moreover, each block, unit and / or module of some of the examples can be physically combined into a more complex block, unit and / or module without departing from the scope of the inventive concept.

[0047] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. Terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0048] Figure 1is a block diagram showing a configuration of an exemplary embodiment of a display apparatus configured according to the principles of the present invention.

[0049] Referring to Figure 1 , the display apparatus 100 according to the exemplary embodiment includes a display panel 110, a timing controller 120, a voltage generation circuit 130, a gate driving circuit 140, and a data driving circuit 150.

[0050] The display panel 110 is not particularly limited, and can include various display panels such as a liquid crystal display panel, an organic light emitting display panel, an electrophoretic display panel, and an electrowetting display panel. In the case where the display panel 110 is a liquid crystal display panel, the display apparatus 100 can further include a polarizer, a backlight unit, etc.

[0051] The display panel 110 includes pixels PX, a plurality of gate lines GL1 to GLn, and a plurality of data lines DL1 to DLm (where n and m are natural numbers greater than 2) intersecting the gate lines GL1 to GLn. The plurality of gate lines GL1 to GLn are connected to the gate driving circuit 140. The plurality of data lines DL1 to DLm are connected to the data driving circuit 150. In Figure 1 Only some of the plurality of gate lines GL1 to GLn and some of the plurality of data lines DL1 to DLm are shown in

[0052] Although only one of the plurality of pixels PX is shown in Figure 1 , the display panel 110 includes a plurality of pixels PX. Each of the plurality of pixels PX is connected to a corresponding gate line of the plurality of gate lines GL1 to GLn and a corresponding data line of the plurality of data lines DL1 to DLm.

[0053] The timing controller 120 receives image data RGB and a control signal CTRL from an external graphic control unit. The control signal CTRL can include a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and a clock signal.

[0054] The timing controller 120 receives the image data RGB and the control signal CTRL, and outputs a data signal DATA and a data control signal CONT1 to be provided to the data driving circuit 150, a gate control signal CONT2 to be provided to the gate driving circuit 140, and a gate pulse signal CPV to be provided to the voltage generation circuit 130. The timing controller 120 can receive an input voltage VIN from the outside.

[0055] The voltage generation circuit 130 receives the gate pulse signal CPV from the timing controller 120 and generates a first clock signal CKV1 and a second clock signal CKV1B. The first clock signal CKV1 and the second clock signal CKV1B can be signals having the same frequency and different phases. Although the voltage generation circuit 130 is described to output two clock signals CKV1 and CKV1B as an example in the following description, the number of clock signals can be variously changed according to the configuration of the gate driving circuit 140.

[0056] The voltage generation circuit 130 can be implemented with a power management integrated circuit (PMIC). In addition to the first clock signal CKV1 and the second clock signal CKV1B, the voltage generation circuit 130 can further generate a first voltage VSS1 and a second voltage VSS2 for the operation of the gate driving circuit 140. A common voltage, a power supply voltage, a ground voltage, etc. for the operation of the display panel 110 can further be generated by the voltage generation circuit 130.

[0057] The voltage generation circuit 130 can receive an input voltage VIN from the outside. The voltage generation circuit 130 according to an exemplary embodiment can set the first clock signal CKV1, the second clock signal CKV1B, and the first voltage VSS1 to a low level (e.g., about 0 V or less) during an initialization mode after starting to supply the input voltage VIN. The voltage generation circuit 130 can sequentially set the second voltage VSS2 to a first level (e.g., about -7 V), a second level, and the first level during the initialization mode. The operation of the voltage generation circuit 130 will be described in detail later.

[0058] The gate driving circuit 140 generates a gate signal and outputs the gate signal to the plurality of gate lines GL1 to GLn based on the gate control signal CONT2 received from the timing controller 120 and based on the first clock signal CKV1, the second clock signal CKV1B, the first voltage VSS1, and the second voltage VSS2 received from the voltage generation circuit 130.

[0059] The gate driving circuit 140 can be formed at the same time as the pixels PX through a thin film process. For example, the gate driving circuit 140 can be disposed in a predetermined area (e.g., a non-display area in which the pixels PX are not arranged) of the display panel 110. In another exemplary embodiment, the gate driving circuit 140 can include a driving chip and a flexible circuit board on which the driving chip is mounted, and the flexible circuit board can be electrically connected to the display panel 110. In another exemplary embodiment, the gate driving circuit 140 can be mounted on a non-display area of the display panel 110 through a chip on glass (COG) method.

[0060] The data driving circuit 150 generates a gradation voltage from a data signal DATA supplied from the timing controller 120 based on a data control signal CONT1 received from the timing controller 120. The data driving circuit 150 outputs the gradation voltage to the plurality of data lines DL1 to DLm.

[0061] Figure 2 is an equivalent circuit diagram of each of representative pixels of the display device of Figure 1

[0062] As shown in Figure 2 , each of the pixels PX includes a thin film transistor TR (hereinafter referred to as a pixel transistor TR), a liquid crystal capacitor Clc, and a storage capacitor Cst. In another exemplary embodiment, the storage capacitor Cst can be omitted.

[0063] The pixel transistor TR is electrically connected to an i-th gate line GLi and a j-th data line DLj (where i and j are natural numbers). The pixel transistor TR transmits a pixel voltage corresponding to a data signal received from the j-th data line DLj to the liquid crystal capacitor Clc in response to a gate signal received from the i-th gate line GLi.

[0064] The liquid crystal capacitor Clc is charged to the pixel voltage transmitted from the pixel transistor TR. The orientation of liquid crystal directors of a liquid crystal layer of the liquid crystal capacitor Clc can change depending on the amount of charge charged in the liquid crystal capacitor Clc. Depending on the orientation of the liquid crystal directors, light incident on the liquid crystal layer can be transmitted or blocked to display an image.

[0065] The storage capacitor Cst is connected in parallel with the liquid crystal capacitor Clc. The storage capacitor Cst can maintain the orientation of the liquid crystal directors for a period of time.

[0066] Figure 3A and Figure 3B is a timing chart for illustrating an operation of the display device of Figure 1

[0067] Referring to Figure 1 , Figure 3A and Figure 3B , the timing controller 120 performs an initialization operation when starting to supply the input voltage VIN. For example, the timing controller 120 (in Figure 3A and Figure 3B ​​The timing controller 120 can perform a load operation that sets state information such as an operation frequency and an operation voltage level, and sets an interface with the data driving circuit 150 based on a control signal CTRL provided from the outside and state information stored in an internal memory (or a lookup table). The load operation can include a training mode. In the training mode, the timing controller 120 can check the interface with the data driving circuit 150 by transmitting a clock training signal to the data driving circuit 150 and by receiving a lock signal from the data driving circuit 150.

[0068] After the timing controller 120 completes the load operation, when the timing controller 120 transmits a gate pulse signal CPV to the voltage generation circuit 130 (in Figure 3A and Figure 3B (in FIG. 1, denoted as "PMIC"), the voltage generation circuit 130 starts operation. The voltage generation circuit 130 can generate a first clock signal CKV1, a second clock signal CKV1B, a first voltage VSS1, and a second voltage VSS2 in response to the gate pulse signal CPV received from the timing controller 120.

[0069] For example, after completing the load operation, the timing controller 120 outputs a gate control signal CONT2 to the gate driving circuit 140. The gate control signal CONT2 can include a start signal STV indicating the start of a frame.

[0070] The gate driving circuit 140 can output a gate signal to the gate lines GL1 to GLn in response to the start signal STV included in the gate control signal CONT2 from the timing controller 120 and the first clock signal CKV1, the second clock signal CKV1B, the first voltage VSS1, and the second voltage VSS2 from the voltage generation circuit 130.

[0071] As shown in Figure 3A , a time interval between the start of providing the input voltage VIN and the output of the first pulse of the start signal STV is a first time FT1.

[0072] Recently, as the functions of the timing controller 120 become diversified and the size of the lookup table increases, the time required for the load operation of the timing controller 120 increases. Accordingly, as shown in Figure 3B , a time interval between the start of providing the input voltage VIN and the output of the first pulse of the start signal STV is a second time FT2. Figure 3B The second time FT2 shown in Figure 3A is longer than the first time FT1 shown in

[0073] The gate lines GL1 to GLn can be kept in a floating state from after the input voltage VIN is started to be supplied until the first pulse of the output start signal STV. That is, the first time FT1 and the second time FT2 can mean a floating time during which the gate lines GL1 to GLn are kept in a floating state.

[0074] As described with reference to Figure 2 , the gate electrode of the pixel transistor TR is connected to the i-th gate line GLi. When the floating voltage level of the i-th gate line GLi is a predetermined level or a higher level, the pixel transistor TR can be turned on so that an unwanted noise image can be displayed on the display panel 110.

[0075] Figure 4 is a block diagram exemplarily illustrating a configuration of a gate driving circuit of the display apparatus. Figure 1

[0076] With reference to Figure 4 , the gate driving circuit 140 includes a plurality of driving stages SRC1 to SRCn and includes a dummy driving stage SRCn+1. The plurality of driving stages SRC1 to SRCn and the dummy driving stage SRCn+1 have a mutually dependent connection relationship, which operates in response to a carry signal output from a previous stage and a carry signal output from a next stage.

[0077] Each of the plurality of driving stages SRC1 to SRCn and the dummy driving stage SRCn+1 receives a first clock signal CKV1 and a second clock signal CKV1B from the voltage generation circuit 130 illustrated in Figure 1 . The driving stage SRC1 and the dummy driving stage SRCn+1 also receive a start signal STV.

[0078] Although in the example illustrated in Figure 4 , the gate driving circuit 140 receives only two clock signals, for example, the first clock signal CKV1 and the second clock signal CKV1B, the example embodiments are not limited thereto. For example, the voltage generation circuit 130 can generate 4 clock signals, 8 clock signals, 12 clock signals, or 16 clock signals different from each other, and the plurality of driving stages SRC1 to SRCn and the dummy driving stage SRCn+1 in the gate driving circuit 140 can receive some corresponding clock signals among the 4 clock signals, 8 clock signals, 12 clock signals, or 16 clock signals.

[0079] In this example embodiment, the plurality of driving stages SRC1 to SRCn are electrically connected to the plurality of gate lines GL1 to GLn, respectively. The plurality of driving stages SRC1 to SRCn provide gate signals G1 to Gn to the plurality of gate lines GL1 to GLn, respectively.

[0080] ​Each of the driving stages SRC1 to SRCn and the dummy driving stage SRCn+1 includes a first carry-in input terminal IN1, a second carry-in input terminal IN2, a gate output terminal (as an output terminal) OUT, a carry-out terminal CR, a first clock terminal CK1, a second clock terminal CK2, a first voltage terminal V1, and a second voltage terminal V2.

[0081] The gate output terminal OUT of each of the driving stages SRC1 to SRCn is electrically connected to a corresponding gate line among a plurality of gate lines GL1 to GLn. The gate signals G1 to Gn generated from the driving stages SRC1 to SRCn can be supplied to the gate lines GL1 to GLn through the gate output terminals OUT.

[0082] The carry-out terminal CR of each of the driving stages SRC1 to SRCn is electrically connected to the first carry-in input terminal IN1 of the next driving stage of the corresponding driving stage. In addition, the carry-out terminal CR of each of the driving stages SRC2 to SRCn and the dummy driving stage SRCn+1 is electrically connected to the second carry-in input terminal IN2 of the previous driving stage. For example, the carry-out terminal CR of the kth driving stage SRCk among the driving stages SRC1 to SRCn is connected to the second carry-in input terminal IN2 of the (k-1)th driving stage SRCk-1 and the first carry-in input terminal IN1 of the (k+1)th driving stage SRCk+1. In an exemplary embodiment, the carry-out terminal CR of the kth driving stage SRCk among the driving stages SRC1 to SRCn can be connected to the second carry-in input terminal IN2 of the (k-1)th driving stage SRCk-1 and the first carry-in input terminal IN1 of the (k+s)th driving stage SRCk+s (here, each of k and s is a natural number). For example, the carry-out terminal CR of the kth driving stage SRCk among the driving stages SRC1 to SRCn can be connected to the second carry-in input terminal IN2 of the (k-1)th driving stage SRCk-1 and the first carry-in input terminal IN1 of the (k+4)th driving stage SRCk+4.

[0083] The first carry-in input terminal IN1 of each of the driving stages SRC2 to SRCn and the dummy driving stage SRCn+1 receives a carry signal output from the previous driving stage. For example, the first carry-in input terminal IN1 of the kth driving stage SRCk receives a carry signal CRk-1 output from the (k-1)th driving stage SRCk-1. The first carry-in input terminal IN1 of the first driving stage SRC1 among the driving stages SRC1 to SRCn receives a start signal STV included in the gate control signal CONT2 provided by the timing controller 120 shown in FIG. 1. Figure 1 The timing controller 120 shown in FIG. 1 provides a gate control signal CONT2 including a start signal STV.

[0084] The second carry-in input IN2 of each of the drive stages SRC1 to SRCn receives a carry signal from a carry-out terminal CR of a next drive stage. For example, the second carry-in input IN2 of the kth drive stage SRCk receives a carry signal CRk+1 output from the carry-out terminal CR of the (k+1)th drive stage SRCk+1. The second carry-in input IN2 of the dummy drive stage SRCn+1 receives a carry signal CRn+1 included in the start signal STV provided in the gate control signal CONT2 from the timing controller 120 shown in FIG. 6. Figure 1 The start signal STV included in the gate control signal CONT2 provided by the timing controller 120 shown in FIG. 6.

[0085] In another exemplary embodiment, the second carry-in input IN2 of each of the drive stages SRC1 to SRCn-1 can be electrically connected to a gate output terminal OUT of a next drive stage. The second carry-in input IN2 of the nth drive stage SRCn receives a carry signal CRn+1 output from the carry-out terminal CR of the dummy drive stage SRCn+1. The second carry-in input IN2 of the dummy drive stage SRCn+1 receives a carry signal included in the start signal STV provided in the gate control signal CONT2 from the timing controller 120 shown in FIG. 7. Figure 1 The start signal STV included in the gate control signal CONT2 provided by the timing controller 120 shown in FIG. 7.

[0086] The first clock terminal CK1 and the second clock terminal CK2 of each of the drive stages SRC1 to SRCn and the dummy drive stage SRCn+1 receive a first clock signal CKV1 or a second clock signal CKV1B, respectively. The first clock terminal CK1 of the odd-numbered drive stages SRC1, SRC3,..., SRCn+1 can each receive the first clock signal CKV1, and the second clock terminal CK2 of the odd-numbered drive stages SRC1, SRC3,..., SRCn+1 can each receive the second clock signal CKV1B. The first clock terminal CK1 of the even-numbered drive stages SRC2, SRC4,..., SRCn can each receive the second clock signal CKV1B, and the second clock terminal CK2 of the even-numbered drive stages SRC2, SRC4,..., SRCn can each receive the first clock signal CKV1.

[0087] The first voltage terminal V1 of each of the drive stages SRC1 to SRCn and the dummy drive stage SRCn+1 receives a first voltage VSS1. The second voltage terminal V2 of each of the drive stages SRC1 to SRCn and the dummy drive stage SRCn+1 receives a second voltage VSS2. The first voltage VSS1 and the second voltage VSS2 can have different voltage levels, and the second voltage VSS2 can have a lower voltage level than the first voltage VSS1.

[0088] In the exemplary embodiments, each of the drive stages SRC1 to SRCn and the dummy drive stage SRCn+1 can omit any of the first carry-in input IN1, the second carry-in input IN2, the gate output OUT, the carry-out CR, the first clock CK1, the second clock CK2, the first voltage V1, and the second voltage V2 according to its circuit configuration, or can further include other terminals. For example, any of the first voltage V1 and the second voltage V2 can be omitted. In this case, each of the drive stages SRC1 to SRCn and the dummy drive stage SRCn+1 receives only one of the first voltage VSS1 and the second voltage VSS2. Further, the connection relationship between the drive stages SRC1 to SRCn and the dummy drive stage SRCn+1 can also be changed.

[0089] Figure 5 is an exemplary timing diagram illustrating the operation of the gate driving circuit of the display apparatus of Figure 1 .

[0090] Referring to Figure 1 , Figure 4 and Figure 5 , upon the start of the supply of the input voltage VIN, the voltage generation circuit 130 operates in an initialization mode I-M. In the initialization mode I-M, the voltage generation circuit 130 outputs the first voltage VSS1 and the second voltage VSS2 having predetermined levels, respectively. For example, the first voltage VSS1 can have a first low voltage level VL1, and the second voltage VSS2 can have a second low voltage level VL2. In the exemplary embodiments, the first low voltage level VL1 and the second low voltage level VL2 can be identical to each other. In the exemplary embodiments, the second low voltage level VL2 can be lower than the first low voltage level VL1.

[0091] The voltage generation circuit 130 maintains the second voltage VSS2 at the second low voltage level VL2 during a first period P1 of the initialization mode I-M, and changes the second voltage VSS2 to a high voltage level VH higher than the second low voltage level VL2 during a second period P2. The voltage generation circuit 130 can change the second voltage VSS2 to the second low voltage level VL2 after the second period P2 of the initialization mode I-M.

[0092] The drive stages SRC1 to SRCn in the gate driving circuit 140 can maintain the gate signals G1 to Gn to have low levels, respectively, in response to the second voltage VSS2 of the high voltage level VH in the second period P2 of the initialization mode I-M.

[0093] When the initialization mode I-M ends and the driving mode D-M starts, the timing controller 120 can provide a start signal STV to the gate driving circuit 140. Also, when the driving mode D-M starts, the voltage generating circuit 130 can provide the first clock signal CKV1 and the second clock signal CKV1B to the gate driving circuit 140.

[0094] The driving stages SRC1 to SRCn can sequentially activate the gate signals G1 to Gn to high levels, respectively, in response to the start signal STV, the first clock signal CKV1, and the second clock signal CKV1B.

[0095] Figure 6 is Figure 4 A circuit diagram of the k-th driving stage (here, k is a natural number) in the gate driving circuit 140 shown in FIG. 1. Figure 4 Each of the plurality of driving stages SRC1 to SRCn and the dummy driving stage SRCn+1 shown in FIG. 1 can have the same circuit as the k-th driving stage SRCk. Hereinafter, the k-th driving stage SRCk is referred to as the driving stage SRCk.

[0096] Referring to Figure 6 , the driving stage SRCk includes a first carry input end IN1, a second carry input end IN2, a gate output end OUT as an output end, a carry output end CR, a first clock end CK1, a second clock end CK2, a first voltage end V1, a second voltage end V2, first to ninth transistors TR1 to TR9, and a capacitor C1.

[0097] The first transistor TR1 is connected between the first clock end CK1 and the gate output end OUT, and includes a gate electrode connected to the first node N1.

[0098] The second transistor TR2 is connected between the first carry input end IN1 and the first node N1, and includes a gate electrode connected to the first carry input end IN1.

[0099] The third transistor TR3 is connected between the first node N1 and the second voltage end V2, and includes a gate electrode connected to the second voltage end V2.

[0100] The fourth transistor TR4 is connected between the gate output end OUT and the first voltage end V1, and includes a gate electrode connected to the second clock end CK2.

[0101] The fifth transistor TR5 is connected between the first clock end CK1 and the carry output end CR, and includes a gate electrode connected to the first node N1.

[0102] The sixth transistor TR6 is connected between the carry output end CR and the second voltage end V2, and includes a gate electrode connected to the second clock end CK2.

[0103] The seventh transistor TR7 is connected between the first node N1 and the second voltage terminal V2, and includes a gate electrode connected to the second carry-in input terminal IN2.

[0104] The eighth transistor TR8 is connected between the first node N1 and the second voltage terminal V2, and includes a gate electrode connected to the first carry-in input terminal IN1.

[0105] The ninth transistor TR9 is connected between the first node N1 and the carry-out terminal CR, and includes a gate electrode connected to the first clock terminal CK1.

[0106] The capacitor C1 is connected between the first node N1 and the gate output terminal OUT.

[0107] Although the drive stage SRCk including the first to ninth transistors TR1 to TR9 and the one capacitor C1 is shown in Figure 6 , the circuit configuration of the drive stage SRCk can be changed differently. For example, the eighth transistor TR8 can include two transistors connected in series between the first node N1 and the second voltage terminal V2. Each of the two transistors of the eighth transistor TR8 has a gate electrode connected to the first carry-in input terminal IN1. For example, the fourth transistor TR4 can include two transistors connected in parallel between the gate output terminal OUT and the first voltage terminal V1. Each of the two transistors of the fourth transistor TR4 has a gate electrode connected to the second clock terminal CK2.

[0108] Figure 7 is a timing chart for illustrating the operation of the drive stage SRCk shown in Figure 6 .

[0109] Referring to Figure 1 , Figure 6 and Figure 7 , when the input voltage VIN starts to be supplied, the voltage generation circuit 130 does not generate the first clock signal CKV1, the second clock signal CKV1B, the first voltage VSS1, and the second voltage VSS2 yet. Therefore, the first clock signal CKV1, the second clock signal CKV1B, the first voltage VSS1, and the second voltage VSS2 can each be in a floating state. Further, a start signal STV included in the gate control signal CONT2 output from the timing controller 120 can be in a floating state.

[0110] When the input voltage VIN starts to be supplied, the voltage generation circuit 130 operates in an initialization mode I-M. During the initialization mode I-M, the voltage generation circuit 130 sets the first clock signal CKV1, the second clock signal CKV1B, the first voltage VSS1, and the second voltage VSS2 to predetermined levels (e.g., low levels), respectively. For example, the predetermined levels can be voltages of about 0 V or less.

[0111] The voltage generation circuit 130 sets the second voltage VSS2 to a second low voltage level VL2 during a first period P1 in the initialization mode I-M. When the second voltage VSS2 has the second low voltage level VL2, the third transistor TR3 in the drive stage SRCk is turned off.

[0112] The voltage generation circuit 130 sets the second voltage VSS2 to a high voltage level VH during a second period P2 in the initialization mode I-M. When the second voltage VSS2 is at the high voltage level VH, the third transistor TR3 in the drive stage SRCk is turned on. When the third transistor TR3 is turned on, the second voltage VSS2 at the high voltage level VH is transmitted to the first node N1. When the voltage level of the first node N1 rises to the high voltage level VH, the first transistor TR1 is turned on. At this time, because the first clock signal CKV1 is at a low level, the output terminal OUT can be discharged through the first clock terminal CK1. As a result, the gate signal G1 can be maintained at a low level.

[0113] Because the pixel transistor TR (see Figure 2 ) of the pixel PX in the display panel 110 is maintained in an off state when the gate signal G1 is at a low level, it is possible to prevent an undesirable image from being displayed on the display panel 110 during the initialization mode I-M.

[0114] The voltage generation circuit 130 sets the second voltage VSS2 to the high voltage level VH during the second period P2 in the initialization mode I-M, and changes the second voltage VSS2 to the second low voltage level VL2 at the end of the second period P2. For example, the second voltage VSS2 can sequentially have the second low voltage level VL2 (e.g., a first level), the high voltage level VH (e.g., a second level higher than the first level), and the second low voltage level VL2 (e.g., the first level) during the initialization mode I-M. The high voltage level VH can have the same voltage level as the high level voltages of the first clock signal CKV1 and the second clock signal CKV1B. In an exemplary embodiment, the high voltage level VH can have the same voltage level as the input voltage VIN.

[0115] When the loading operation of the timing controller 120 ends and the drive mode D-M starts, the timing controller 120 outputs a start signal STV. The voltage generation circuit 130 generates the first clock signal CKV1, the second clock signal CKV1B, the first voltage VSS1, and the second voltage VSS2 in the drive mode D-M.

[0116] The gate drive circuit 140 can sequentially activate each of the gate signals G1 to Gn to a high level for each of the frames F1 and F2 (see FIG. 2) in response to the start signal STV, the first clock signal CKV1, the second clock signal CKV1B, the first voltage VSS1, and the second voltage VSS2. Figure 5 ) in response to the start signal STV, the first clock signal CKV1, the second clock signal CKV1B, the first voltage VSS1, and the second voltage VSS2.

[0117] During the drive mode D-M, because the second voltage VSS2 remains at the second low voltage level VL2, the third transistor TR3 in the drive stage SRCk is turned off. Thus, the voltage level of the first node N1 can be determined depending on the carry signals CRk-1 and CRk+1. For example, the third transistor TR3 can be turned on only when the second voltage VSS2 is at the high voltage level VH in the second period P2 of the initialization mode I-M. In an exemplary embodiment, the second voltage VSS2 can remain at the high voltage level VH not only during the second period P2 but also during the initialization mode I-M, i.e., until the drive mode D-M starts.

[0118] In an exemplary embodiment, the third transistor TR3 can be connected to a separate initial voltage terminal different from the second voltage terminal V2. The initial voltage terminal can provide a signal having a high level only in the second period P2 of the initialization mode I-M and a signal having a low level in the remaining periods.

[0119] According to the exemplary embodiment as described above, even when the loading time of the timing controller 120 increases, it is possible to prevent a noise image from being displayed on the display panel 110.

[0120] The gate drive circuit in the display apparatus having the above-described configuration can discharge the gate line in a floating state during the initialization mode after power-up. Thus, the switching transistor in the pixel can be maintained to be turned off during the initialization mode, thereby preventing a noise image from being displayed.

[0121] While certain exemplary embodiments and implementations have been described herein, other embodiments and modifications will be apparent from this description. Accordingly, the inventive concept is not limited to these embodiments, but instead has a wider scope as commensurate with the following claims and their equivalents.

Claims

1. A gate driving circuit, comprising: a plurality of driving stages, each of the plurality of driving stages configured to provide a gate signal to a respective gate line of a plurality of gate lines, wherein each of the plurality of driving stages comprises: a first transistor electrically connected between a first clock terminal and a gate output terminal, the first transistor comprising a gate electrode electrically connected to a first node, the first clock terminal configured to receive a first clock signal; a second transistor configured to transmit a first carry signal to the first node; and a third transistor electrically connected between the first node and a first voltage terminal, the third transistor comprising a gate electrode electrically connected to the first voltage terminal, the first voltage terminal configured to receive a first voltage, wherein the gate output terminal is electrically connected to the respective gate line, wherein the first voltage is changed from a first level to a second level during an initialization mode, the second level being different from the first level, and wherein the third transistor and the first transistor are turned on, respectively, when the first voltage is changed to have the second level.

2. The gate drive circuit according to claim 1, wherein the first voltage is changed to sequentially have a first level, a second level, and the first level during the initialization mode, the second level being different from the first level.

3. The gate drive circuit of claim 2, wherein, the first clock signal has a low level during the initialization mode.

4. The gate drive circuit of claim 2, wherein, the third transistor is configured to transmit the first voltage to the first node when the first voltage has the second level.

5. The gate drive circuit of claim 1, wherein, each of the plurality of driving stages further comprises a fourth transistor connected between the gate output terminal and a second voltage terminal configured to receive a second voltage, the fourth transistor comprising a gate electrode connected to a second clock terminal configured to receive a second clock signal.

6. The gate driving circuit of claim 5, wherein: each of the plurality of driving stages further comprises a fifth transistor connected between the first clock terminal and a carry output terminal, the fifth transistor comprising a gate electrode connected to the first node, and the carry output terminal is configured to output a carry signal.

7. A display device, comprising: a display panel comprising a plurality of pixels respectively connected to a plurality of data lines and respectively connected to a plurality of gate lines; a data driving circuit configured to drive the plurality of data lines; a gate driving circuit configured to drive the plurality of gate lines; a timing controller configured to receive an image signal and a control signal, control the data driving circuit and the gate driving circuit to display an image on the display panel, and output a gate pulse signal; and a voltage generation circuit configured to output a first clock signal and a first voltage in response to the gate pulse signal, wherein the voltage generation circuit is configured to change the first voltage such that the first voltage sequentially has a first level and a second level during an initialization mode, the second level being different from the first level, and the gate driving circuit comprises a plurality of driving stages, each of the plurality of driving stages configured to provide a gate signal to a respective gate line of the plurality of gate lines, wherein each of the plurality of drive stages is configured to discharge the respective gate line during the initialization mode in response to the first voltage and the first clock signal, wherein each of the plurality of drive stages comprises: a first transistor connected between a first clock terminal and a gate output terminal, the first clock terminal for receiving the first clock signal, the first transistor including a gate electrode connected to a first node; a second transistor configured to transmit a first carry signal to the first node; and a third transistor connected between the first node and a first voltage terminal for receiving the first voltage, the third transistor including a gate electrode connected to the first voltage terminal, and wherein the third transistor and the first transistor are turned on, respectively, when the first voltage changes to have the second level.

8. The display device of claim 7, wherein, the first voltage is changed to sequentially have the first level, the second level, and the first level during the initialization mode. the first voltage is changed to sequentially have the first level, the second level, and the first level during the initialization mode.

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