Dual-port SRAM memory cell

Abstract

The present invention relates to a storage unit of a dual-port SRAM and to a semiconductor integrated circuit design. By changing the selection tubes corresponding to WLA and WLB from only an N-type standard threshold voltage, i.e., NSVT, to a combination of an N-type standard threshold voltage, i.e., NSVT, and an N-type high threshold voltage, i.e., NHVT, the voltage coupled from BL to a node is suppressed, thereby suppressing read interference and simplifying the process.

Description

Technical Field

[0001] The invention relates to semiconductor integrated circuit design, in particular to a storage unit of a dual-port SRAM. Background Art

[0002] With the development of computers and smart phones, the frequency of their internal core processors is getting higher and higher, and their functions are getting stronger and stronger. Static Random-Access Memory (SRAM) is a type of random access memory. At present, more than half of the area of ​​​​the CPU and system on chip (SoC) is occupied by SRAM. This is mainly due to the fact that SRAM has a higher speed and a smaller leakage current, which can adapt to the CPU / SoC's requirements for cache capacity, bandwidth and speed. There are many performance indicators to measure semiconductor memory, among which the most important are the access speed and stability of the memory. Dual-port SRAM (Dual-port SRAM) is the first-level high-speed cache memory (cache) of the CPU. Its read and write speed and stability are more important parameters, which directly affect the actual operating speed of the CPU. Summary of the invention

[0003] The storage unit of the dual-port SRAM provided by the present invention comprises: a first CMOS inverter composed of a first pull-up tube PU1 and a first pull-down tube PD1; a second CMOS inverter composed of a second pull-up tube PU2 and a second pull-down tube PD2, wherein the output end of the second CMOS inverter and the input end of the first CMOS inverter are connected together to form a first storage node Q, the output end of the first CMOS inverter and the input end of the second CMOS inverter are connected together to form a second storage node Qb, the first storage node Q and the second storage node Qb are mutually inverted and mutually latched; four selection transistors PG1-A, PG1-B, PG2-A and PG2-B, two WLs WLA and WLB, and two groups BL / BLB of BLA / / BLA and BLB / / BLB, wherein the selection tube PG1-B corresponds to / BLA, the selection tube PG2-B corresponds to BLB, the selection tube PG1-A corresponds to BLA, and the selection tube PG2-A corresponds to / BLB, WLA controls the selection tube PG1-B and the selection tube PG1-A, WLB controls the selection tube PG2-B and the selection tube PG2-A, the sources of the first pull-up tube PU1 and the second pull-up tube PU2 are connected to the power supply voltage Vdd, the sources of the first pull-down tube PD1 and the second pull-down tube PD2 are grounded Vss, the selection tube PG1-A and the selection tube PG2-B are also connected to the first storage node Q, the selection tube PG1-B and the selection tube PG2-A are also connected to the second storage node Qb, the metal gate of the selection tube PG1-B and one of the selection tube PG1-A controlled by WLA and the metal gate of the selection tube PG2-B and one of the selection tube PG2-A controlled by WLB has a first work function layer, the first work function layer makes the threshold voltage of the selection tube PG1-B and one of the selection tube PG1-A and one of the selection tube PG2-B and the selection tube PG2-A a first threshold voltage, and the first threshold voltage is an N-type high threshold voltage.

[0004] Furthermore, the four selection transistors PG1-A, PG1-B, PG2-A and PG2-B are all NMOS transistors.

[0005] Furthermore, both the first pull-up tube PU1 and the second pull-up tube PU2 are PMOS tubes.

[0006] Furthermore, both the first pull-down tube PD1 and the second pull-down tube PD2 are NMOS tubes.

[0007] Furthermore, the gate structures of the first pull-up tube PU1, the second pull-up tube PU2, the first pull-down tube PD1, the second pull-down tube PD2, the selection transistor PG1-A, the selection transistor PG1-B, the selection transistor PG2-A and the selection transistor PG2-B all adopt metal gates.

[0008] Furthermore, the metal gates of the selection tube PG1-B and the other of the selection tube PG1-A controlled by WLA and the metal gates of the selection tube PG2-B and the other of the selection tube PG2-A controlled by WLB have a second work function layer, and the second work function layer makes the threshold voltage of the selection tube PG1-B and the other of the selection tube PG1-A and the other of the selection tube PG2-B and the selection tube PG2-A a second threshold voltage, and the second threshold voltage is the standard threshold voltage of the N type.

[0009] Furthermore, the metal gates of the first pull-up tube PU1 and the second pull-up tube PU2 have a third work function layer, which makes the threshold voltage of the first pull-up tube PU1 and the second pull-up tube PU2 a third threshold voltage, and the third threshold voltage is a standard threshold voltage of the P type.

[0010] Furthermore, the metal gates of the first pull-down tube PD1 and the second pull-down tube PD2 have a fourth work function layer, which makes the threshold voltage of the first pull-down tube PD1 and the second pull-down tube PD2 a fourth threshold voltage, and the fourth threshold voltage is a standard threshold voltage of N type.

[0011] Furthermore, a high threshold voltage of the N type is achieved through an implantation process in a well process or a pocket process.

[0012] Furthermore, a high threshold voltage of the N-type is achieved through a work function adjustment process. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 This is the ideal circuit diagram corresponding to a typical 8T dual-port SRAM.

[0014] Figure 2 FIG. 4 is a schematic diagram of a layout of a storage unit of a dual-port SRAM according to an embodiment of the present invention. DETAILED DESCRIPTION

[0015] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0016] See also Figure 1 , Figure 1 This is the ideal circuit diagram corresponding to a typical 8T dual-port SRAM. 8T means there are 8 transistors in the storage unit. Figure 1As shown, the dual-port SRAM is composed of two P-type pull-up tubes PU1 and PU2, two N-type pull-down tubes PD1 and PD2, and four selection transistors PG1-A, PG1-B, PG2-A, and PG2-B. There are two WLs WLA and WLB, and two groups of BL / BLB BLA / / BLA and BLB / / BLB, which can realize the function of simultaneous reading. In the unit design of the dual-port SRAM, the selection tube PG1-B corresponds to / BLA, the selection tube PG2-A corresponds to / BLB, the selection tube PG1-A corresponds to BLA, and the selection tube PG2-B corresponds to BLB. WLA controls the selection tube PG1-B and the selection tube PG1-A, and WLB controls the selection tube PG2-B and the selection tube PG2-A. The P-type pull-up tube PU1 and the N-type pull-down tube PD1 form a CMOS inverter, and the P-type pull-up tube PU2 and the N-type pull-down tube PD2 also form a CMOS inverter. The two CMOS inverters are connected end to end to form a latch, and the latch includes two mutually inverted and interlocked first storage nodes Q and the second storage node Qb. The sources of the P-type pull-up tubes PU1 and PU2 are both connected to the power supply voltage Vdd, and the sources of the N-type pull-down tubes PD1 and PD2 are both grounded Vss.

[0017] For example, when Q=”0”, Qb=”1”, the read current Iread of the BLA terminal reaches Vss through PG1-A and PD1, and the read current Iread of the / BLB terminal reaches Vss through PG2-B and PD1, thereby realizing readout.

[0018] Of course, during the read operation, WLA or WLB will be turned on, and the BL voltage will be coupled to the node, which will cause the node voltage to increase. If the node voltage changes too much, it will cause the bit unit to reverse and cause a fatal error. Therefore, read disturbance is an important issue that needs to be considered for dual-port SRAM.

[0019] An embodiment of the present invention provides a dual-port SRAM storage unit, see Figure 1 , and see Figure 2 The schematic diagram of the layout of the storage unit of the dual-port SRAM of one embodiment of the present invention is shown. The storage unit of the dual-port SRAM of the present invention comprises:

[0020] The first CMOS inverter is composed of a first pull-up tube PU1 and a first pull-down tube PD1;

[0021] The second CMOS inverter is composed of a second pull-up tube PU2 and a second pull-down tube PD2, the output end of the second CMOS inverter and the input end of the first CMOS inverter are connected together to form a first storage node Q, the output end of the first CMOS inverter and the input end of the second CMOS inverter are connected together to form a second storage node Qb, and the first storage node Q and the second storage node Qb are inverted and mutually latched;

[0022] Four selection transistors PG1-A, PG1-B, PG2-A and PG2-B, two WLs WLA and WLB, and two groups of BL / BLB BLA / / BLA and BLB / / BLB realize the function of simultaneous reading, wherein the selection tube PG1-B corresponds to / BLA, the selection tube PG2-B corresponds to BLB, the selection tube PG1-A corresponds to BLA, the selection tube PG2-A corresponds to / BLB, WLA controls the selection tube PG1-B and the selection tube PG1-A, WLB controls the selection tube PG2-B and the selection tube PG2-A, the sources of the first pull-up tube PU1 and the second pull-up tube PU2 are connected to the power supply voltage Vdd, the first pull-down tube PD1 and the second pull-down tube PD2 are connected to the power supply voltage Vdd, The source of the pull-down tube PD2 is grounded to Vss, the selection tube PG1-A and the selection tube PG2-B are also connected to the first storage node Q, the selection tube PG1-B and the selection tube PG2-A are also connected to the second storage node Qb, and the metal gates of the selection tubes PG1-B and PG1-A controlled by WLA and the selection tubes PG2-B and PG2-A controlled by WLB have a first work function layer, and the first work function layer makes the threshold voltage of the selection tubes PG1-B and PG1-A and the threshold voltage of the selection tubes PG2-B and PG2-A be the first threshold voltage, and the first threshold voltage is the high threshold voltage of N type, namely NHVT.

[0023] In one embodiment, the four selection transistors PG1-A, PG1-B, PG2-A and PG2-B are all NMOS transistors.

[0024] In one embodiment, the first pull-up tube PU1 and the second pull-up tube PU2 are both PMOS tubes.

[0025] In one embodiment, both the first pull-down tube PD1 and the second pull-down tube PD2 are NMOS tubes.

[0026] In one embodiment, the gate structures of the first pull-up tube PU1, the second pull-up tube PU2, the first pull-down tube PD1, the second pull-down tube PD2, the selection transistor PG1-A, the selection transistor PG1-B, the selection transistor PG2-A and the selection transistor PG2-B all use metal gates and are all FinFETs.

[0027] In one embodiment, the metal gates of the selection tube PG1-B and the other of the selection tube PG1-A controlled by WLA and the metal gates of the selection tube PG2-B and the other of the selection tube PG2-A controlled by WLB have a second work function layer, and the second work function layer makes the threshold voltage of the selection tube PG1-B and the other of the selection tube PG1-A and the other of the selection tube PG2-B and the selection tube PG2-A a second threshold voltage, and the second threshold voltage is the standard threshold voltage of the N type, namely, NSVT.

[0028] In one embodiment, the metal gates of the first pull-up tube PU1 and the second pull-up tube PU2 have a third work function layer, and the third work function layer makes the threshold voltage of the first pull-up tube PU1 and the second pull-up tube PU2 a third threshold voltage, and the third threshold voltage is the standard threshold voltage of the P type, namely PSVT.

[0029] In one embodiment, the metal gates of the first pull-down tube PD1 and the second pull-down tube PD2 have a fourth work function layer, which makes the threshold voltage of the first pull-down tube PD1 and the second pull-down tube PD2 a fourth threshold voltage, and the fourth threshold voltage is the standard threshold voltage of N type, namely NSVT.

[0030] In one embodiment, the N-type high threshold voltage, ie, NHVT, may be achieved through an implantation process in a well process or a pocket process.

[0031] In one embodiment, the above-mentioned N-type high threshold voltage, ie, NHVT, may be achieved through a work function adjustment process.

[0032] like Figure 2 As shown, BLA and / BLA are both represented by BLA, BLB and / BLB are both represented by BLB, and the layout of the storage unit of the dual-port SRAM includes: multiple fin bodies 102, each of the fin bodies 202 is arranged in parallel with each other, and the gate structures of the first pull-up tube PU1, the second pull-up tube PU2, the first pull-down tube PD1, the second pull-down tube PD2, the selection transistor PG1-A, the selection transistor PG1-B, the selection transistor PG2-A and the selection transistor PG2-B cover the side and top surfaces of the fin body 102. In addition, there are areas on the layout structure where the gate structure does not need to be formed, so part of the fin body 102 will be truncated, such as Figure 2 The mark 102a in the figure corresponds to the area where the fin is cut off. A plurality of metal gates 103 are arranged in parallel with each other and cross-arranged on the fin 102. The intersection area of ​​the metal gate 103 and the fin 102 forms a metal gate, which includes a work function layer and a metal conductive material layer. A through hole 104, which is usually a zero-layer through hole and is represented by M0PO. A metal layer 105, which is usually a zero-layer metal layer and is represented by M0D.

[0033] like Figure 2 As shown, the pull-up tube is formed on one fin 202, such as the area shown by the label 106, which is the standard threshold voltage of the P type, namely PSVT. The pull-down tube is formed on six fins 202, such as the area shown by the label 107, which is the standard threshold voltage of the N type, namely NSVT. The selection tube PG1-B and one of the selection tube PG1-A controlled by WLA and the selection tube PG2-B and one of the selection tube PG2-A controlled by WLB are formed on two fins 202, such as the area shown by the label 108, which is the high threshold voltage of the N type, namely NHVT. The selection tube PG1-B and the other of the selection tube PG1-A controlled by WLA and the selection tube PG2-B and the other of the selection tube PG2-A controlled by WLB are formed on three fins 202, such as the areas shown by the labels 109 and 110, which are the standard threshold voltage of the N type, namely NSVT.

[0034] In this way, by changing the selection tubes corresponding to WLA and WLB from only the N-type standard threshold voltage, i.e., NSVT, to a combination of the N-type standard threshold voltage, i.e., NSVT, and the N-type high threshold voltage, NHVT, the voltage coupled from BL to the node is suppressed, thereby suppressing read interference and simplifying the process.

[0035] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A dual-port SRAM storage unit, characterized in that: include: A first CMOS inverter composed of a first pull-up tube PU1 and a first pull-down tube PD1; A second CMOS inverter composed of a second pull-up tube PU2 and a second pull-down tube PD2, wherein the output end of the second CMOS inverter and the input end of the first CMOS inverter are connected together to form a first storage node Q, the output end of the first CMOS inverter and the input end of the second CMOS inverter are connected together to form a second storage node Qb, and the first storage node Q and the second storage node Qb are inverted and mutually latched; There are four selection transistors PG1-A, PG1-B, PG2-A and PG2-B, two WLs WLA and WLB, and two groups of BL / BLB BLA / / BLA and BLB / / BLB, wherein the selection tube PG1-B corresponds to / BLA, the selection tube PG2-B corresponds to BLB, the selection tube PG1-A corresponds to BLA, the selection tube PG2-A corresponds to / BLB, WLA controls the selection tube PG1-B and the selection tube PG1-A, WLB controls the selection tube PG2-B and the selection tube PG2-A, the sources of the first pull-up tube PU1 and the second pull-up tube PU2 are connected to the power supply voltage Vdd, the first pull-down tube PD1 and the second pull-down tube PD2 are connected to the power supply voltage Vdd, The source of the transistor PD2 is grounded to Vss, the selection transistor PG1-A and the selection transistor PG2-B are also connected to the first storage node Q, the selection transistor PG1-B and the selection transistor PG2-A are also connected to the second storage node Qb, and the metal gates of the selection transistors PG1-B and PG1-A controlled by WLA and the selection transistors PG2-B and PG2-A controlled by WLB have a first work function layer, and the first work function layer makes the threshold voltage of the selection transistors PG1-B and PG1-A and the threshold voltage of the selection transistors PG2-B and PG2-A be the first threshold voltage, and the first threshold voltage is the high threshold voltage of the N type; The metal gates of the selection tube PG1-B and the other of the selection tube PG1-A controlled by WLA and the selection tube PG2-B and the other of the selection tube PG2-A controlled by WLB have a second work function layer, and the second work function layer makes the threshold voltage of the selection tube PG1-B and the other of the selection tube PG1-A and the other of the selection tube PG2-B and the selection tube PG2-A a second threshold voltage, and the second threshold voltage is the standard threshold voltage of the N type.

2. The storage unit of the dual-port SRAM according to claim 1, characterized in that: The four selection transistors PG1-A, PG1-B, PG2-A and PG2-B are all NMOS transistors.

3. The storage unit of the dual-port SRAM according to claim 1, characterized in that: The first pull-up tube PU1 and the second pull-up tube PU2 are both PMOS tubes.

4. The storage unit of the dual-port SRAM according to claim 1, characterized in that: The first pull-down tube PD1 and the second pull-down tube PD2 are both NMOS tubes.

5. The storage unit of the dual-port SRAM according to claim 1, characterized in that: The gate structures of the first pull-up tube PU1, the second pull-up tube PU2, the first pull-down tube PD1, the second pull-down tube PD2, the selection transistor PG1-A, the selection transistor PG1-B, the selection transistor PG2-A and the selection transistor PG2-B all adopt metal gates.

6. The storage unit of the dual-port SRAM according to claim 1, characterized in that: The metal gates of the first pull-up tube PU1 and the second pull-up tube PU2 have a third work function layer, and the third work function layer makes the threshold voltage of the first pull-up tube PU1 and the second pull-up tube PU2 a third threshold voltage, and the third threshold voltage is a standard threshold voltage of the P type.

7. The storage unit of the dual-port SRAM according to claim 1, characterized in that: The metal gates of the first pull-down tube PD1 and the second pull-down tube PD2 have a fourth work function layer, which makes the threshold voltage of the first pull-down tube PD1 and the second pull-down tube PD2 a fourth threshold voltage, and the fourth threshold voltage is a standard threshold voltage of an N type.

8. The storage unit of the dual-port SRAM according to claim 1, characterized in that: The high threshold voltage of the N-type is achieved by an implantation process in a well process or a pocket process.

9. The dual-port SRAM storage unit according to claim 1, characterized in that: The high threshold voltage of N-type is achieved through work function adjustment process.

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