Apparatus, computer-implemented method, and program product for compiling instructions for at least one time slice in a one-dimensional quantum computing environment

Abstract

The present invention is entitled "Apparatus, Computer-Implemented Method, and Computer Program Product for Instruction Compilation for At Least One Time Slice in a One-Dimensional Quantum Computing Environment." Various embodiments of the present disclosure provide for instruction compilation for at least one time slice in a one-dimensional quantum computing environment. In this regard, embodiments generate an algorithmic swap command set by performing an even-odd permutation ordering based on at least an initial set of qubit positions and a target set of qubit positions for one or more time slices. The algorithmic swap command set may correspond to a qubit manipulation instruction set that can be used to generate a hardware instruction set that, when executed, efficiently repositions any number of qubits to the target positions for gating.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Provisional Application No. 63 / 031,410, filed on May 28, 2020, entitled “APPARATUSES, COMPUTER-IMPLEMENTED METHODS, AND COMPUTER PROGRAM PRODUCTS FOR INSTRUCTION COMPILATION FOR ATLEAST ONE TIME SLICE IN A ONE-DIMENSIONAL QUANTUM COMPUTING ENVIRONMENT,” the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] Embodiments of the present disclosure generally relate to qubit manipulation in a quantum computing environment, and particularly relate to instruction compilation for at least one time slice in a one-dimensional quantum computing environment to reposition qubits for gating at one or more time slices. Background Art

[0004] A general-purpose quantum computer must compile user programs into machine instructions specific to the underlying hardware embodying the quantum computer. Typically, implementations of such quantum computers require that qubits be repositioned for use in performing one or more logical operations, such as one or more logic gates. However, the transmission sequence for repositioning qubits can be expensive, error-prone, and otherwise resource-intensive. Therefore, it is desirable to efficiently compile user programs into instructions that effectively transmit qubits within a quantum system at different times as needed. Applicants have identified problems with current implementations of instruction compilation in a one-dimensional quantum computing environment. Through expended effort, ingenuity, and innovation, Applicants have addressed many of these recognized problems by developing solutions embodied in the present disclosure, which are described in detail below. Summary of the Invention

[0005] Generally speaking, embodiments of the present disclosure provided herein provide instruction compilation for at least one time slice in a one-dimensional quantum computing environment. Other specific implementations of instruction compilation for at least one time slice in a one-dimensional quantum computing environment will be or will become apparent to those skilled in the art upon examination of the following figures and detailed description. All such additional implementations are intended to be within the scope of this disclosure and protected by the following claims.

[0006] According to at least one aspect of the present disclosure, a computer-implemented method for compiling instructions for at least one time slice in a one-dimensional quantum computing environment is provided. The computer-implemented method can be performed by any of the computing entities, apparatuses, and / or other devices described herein, embodied in hardware, software, firmware, and / or combinations thereof. In at least one exemplary embodiment, the computer-implemented method includes identifying an initial set of qubit positions associated with a set of qubits, the qubit set associated with a set of qubit pairings for gating at a first time slice, the qubit pairing set including at least one qubit pair, each qubit pair having a first qubit and a second qubit. The exemplary computer-implemented method also includes identifying a set of target qubit positions associated with the set of qubits and the initial set of qubit positions at the first time slice, wherein for each qubit pair, the first qubit is associated with a first target position index in the set of target qubit positions, and the second qubit is associated with a second target position index in the set of target qubit positions, and wherein the first target position index is adjacent to the second target position index. The exemplary computer-implemented method also includes generating an algorithmic swap command set by performing an even-odd permutation sort based at least on the set of target qubit positions.

[0007] Additionally or alternatively, in some exemplary embodiments of the exemplary computer-implemented method, generating the algorithmic exchange command set includes storing a first exchange indicator for each even exchange determined according to the even-odd transposition order in a data object representing the algorithmic exchange command set, and storing a second exchange indicator for each odd exchange determined according to the even-odd transposition order to the data object representing the algorithmic exchange command set.

[0008] Additionally or alternatively, in some exemplary embodiments of the exemplary computer-implemented method, generating the algorithmic swap command set includes: determining, while performing the even-odd transposition ordering, that a second qubit pair for gating at a first time slice is associated with a first position index and a second position index, the first position index and the second position index representing adjacent position indexes; storing at least one command to perform a logical operation based on at least the second qubit pair; and determining a first updated target qubit position index and a second updated target qubit position index for the second qubit pair, wherein the first updated target qubit position index and the second updated target qubit position index are determined based on the second time slice.

[0009] Additionally or alternatively, in some exemplary embodiments of the exemplary computer-implemented method, the set of target qubit positions represents a second set of initial qubit positions, and the computer-implemented method further comprises: identifying a second set of initial qubit positions at a second time slice based on the set of target qubit positions for the first time slice; identifying a second set of target qubit positions associated with the set of qubits at the second time slice based on the initial set of qubit positions at the second time slice; and generating a second set of algorithmic swap commands by performing a second even-odd transposition ordering based on at least the second set of target qubit positions.

[0010] Additionally or alternatively, in some exemplary embodiments of the exemplary computer-implemented method, identifying the set of target qubit positions includes receiving a qubit program, the qubit program including a set of qubit pairings associated with the set of qubits, the qubit pairing set representing at least one qubit pair for gating at the first time slice; and generating the set of target qubit positions based on the set of qubit pairings.

[0011] Additionally or alternatively, in some such exemplary embodiments of the exemplary computer-implemented method, for each qubit pair of the at least one qubit pair for gating, the first qubit is associated with a first initial position index of the set of initial qubit positions, and the second qubit is associated with a second initial position index of the set of initial qubit positions, and generating the set of target qubit positions includes: for each qubit pair of the at least one qubit pair for gating at the first time slice and starting with the qubit pair having a maximum position distance based on at least the first initial position index and the second initial position index, determining a near-midpoint open index pair based on at least the first initial position index and the second initial position index, wherein the near-midpoint open index pair includes a first target position index and a second target position index; and assigning the first target position index and the second target position index in the set of target qubit positions based on at least the near-midpoint open index pair.

[0012] Additionally or alternatively, in some exemplary embodiments of the exemplary computer-implemented method, the computer-implemented method further comprises generating a qubit manipulation instruction set based at least on the algorithmic exchange command set, the qubit manipulation instruction set comprising any number of qubit swap instructions, any number of qubit split instructions, any number of qubit merge instructions, and any number of qubit shift instructions.

[0013] Additionally or alternatively, in some such exemplary embodiments of the exemplary computer-implemented method, the computer-implemented method further comprises generating a hardware instruction set based at least on the qubit manipulation instruction set, wherein the hardware instruction set comprises at least one action to be performed by qubit manipulation hardware to position the set of qubits based on the qubit manipulation instruction set; and executing the hardware instruction set using the qubit manipulation hardware.

[0014] Additionally or alternatively, in some exemplary embodiments of the exemplary computer-implemented method, identifying the target set of qubit positions includes identifying a starting set of position pairings corresponding to the set of qubit pairings; generating a target slot vector based at least in part on the starting set of position pairings; determining a target slot midpoint vector by sorting the target slot vector using an even-odd transposition ordering; and generating the target set of qubit positions based at least in part on the target slot midpoint vector.

[0015] Additionally or alternatively, in some such exemplary embodiments of the exemplary computer-implemented method, the computer-implemented method further comprises determining that the set of starting position pairs satisfies a first constraint, the first constraint indicating that each starting position pair in the set of starting position pairs includes: a first position that exists in a first subset of an equal dual partition of all positions, and a second position that exists in a second subset of an equal dual partition of all positions, wherein each position in the first subset of the equal dual partition is associated with a unique position in the second subset of the dual partition. The association between the positions in the first subset and the unique positions in the second subset may be used to generate the target time slot vector.

[0016] Additionally or alternatively, in some such exemplary embodiments of the exemplary computer-implemented method, each first position in the first subset of the equal bipartition is adjacent to a unique position associated with the first position in the second subset of the equal bipartition.

[0017] Additionally or alternatively, in some exemplary embodiments of the exemplary computer-implemented method, the first subset of equal dual partitions of all positions includes the set of even positions, and the second subset of equal dual partitions of all positions includes the set of odd positions.

[0018] Additionally or alternatively, in some such exemplary embodiments of the exemplary computer-implemented method, generating the target time slot vector includes assigning a fixed time slot from the set of available time slots to each position in the first subset of equal dual partitions, and generating the target time slot vector includes, for each starting position pair including a first position from the first subset of equal dual partitions of all positions and a second position from the second subset of equal dual partitions of all positions, the target time slot vector including a second time slot representing the second position, the second time slot generated at an index of the target time slot vector corresponding to the fixed time slot from the set of available time slots assigned to the first position. Generating the target time slot vector including the second time slot representing the second position for each starting position pair including a first position from the first subset of equal dual partitions of all positions and a second position from the second subset of equal dual partitions of all positions, the second time slot generated at an index of the target time slot vector corresponding to the fixed time slot from the set of available time slots assigned to the first position.

[0019] Additionally or alternatively, in some such exemplary embodiments of the exemplary computer-implemented method, determining the target time slot midpoint vector by sorting the target time slot vector using an even-odd transposition order includes: for each starting position pair in the set of starting position pairings, sorting the target time slot vector to achieve a parity check between a second time slot representing the second position and a fixed time slot assigned to the first position.

[0020] Additionally or alternatively, in some such exemplary embodiments of the exemplary computer-implemented method, the set of starting position pairings includes a plurality of even-odd position pairs, each even-odd position pair including an even position and an odd position associated with the even position, wherein the target time slot vector is generated based on assigning a fixed time slot from the set of available time slots to the even positions of the plurality of even-odd position pairs, and the target time slot vector is generated based on each odd position of the plurality of even-odd position pairs.

[0021] Additionally or alternatively, in some such exemplary embodiments of the exemplary computer-implemented method, the computer-implemented method further comprises identifying an original starting position pairing set corresponding to the set of qubit pairings; determining that the original starting position pairing set does not satisfy the first constraint; and transforming the original starting position pairing set to the starting position pairing set to satisfy the first constraint by: generating a directed graph based on the initial starting position pairing set; and applying the path selection algorithm to the graph.

[0022] Additionally or alternatively, in some such exemplary embodiments of the exemplary computer-implemented method, a directed graph is generated: a first set of nodes is generated, the first set of nodes representing a first subset of pairs from the original starting position pairing set, the first subset of pairs including a subset of ee pairs or a subset of oo pairs from the original starting position pairing set; a second set of nodes is generated, the second set of nodes representing a second subset of pairs from the original starting position pairing set, the second subset of pairs including the other of the subset of ee pairs or oo pairs from the original starting position pairing set; a third set of nodes is generated, the third set of nodes representing a third subset of pairs from the original starting position pairing set, the third subset of pairs including the third subset of pairs from the original starting position pairing set. a subset of the eo pairs of the pairing set, where the third set may be an empty set if no eo pairs exist; generating a first set of directed edges, the directed edges emanating from each first node associated with the first node set to a second node associated with the second node set, wherein the first node is associated with a starting position pair including at least one position adjacent to at least one position of a second starting position pair, the second starting position pair being associated with a second node conforming to the first sorting phase; generating a single source node and a second set of directed edges from the single source node to each node in the first node set; and generating a single target node and a third set of directed edges from each node in the second node set to the single target node.

[0023] Additionally or alternatively, in some such exemplary embodiments of the exemplary computer-implemented method, the path selection algorithm includes a specific implementation of the Suurballe algorithm for finding a set of node-disjoint paths from a single source node to a single destination node, the set of node-disjoint paths representing a path from the ee pair to the oo pair in one parallel exchange command.

[0024] Additionally or alternatively, in some such exemplary embodiments of the exemplary computer-implemented method, the Suurballe algorithm implementation includes a modified Suurballe algorithm that includes generating edge weights representing a difference distance histogram for one or more of the first set of directed edges, the second set of directed edges, and the third set of directed edges.

[0025] Additionally or alternatively, in some such exemplary embodiments of the exemplary computer-implemented method, the computer-implemented method further comprises determining that the original set of starting position pairings does not satisfy at least one additional constraint; and updating the original set of starting position pairings to satisfy the at least one additional constraint.

[0026] According to another aspect of the present disclosure, an apparatus for compiling instructions for at least one time slice in a one-dimensional quantum computing environment is provided. In at least one exemplary embodiment, the apparatus includes at least one processor and at least one memory having computer-coded instructions stored thereon. When executed by the at least one processor, the computer-coded instructions configure the apparatus to perform any of the exemplary computer-implemented methods described herein. In at least one other exemplary embodiment, the apparatus includes means for performing each step of any of the exemplary computer-implemented methods described herein.

[0027] According to another aspect of the present disclosure, a computer program product is provided for compiling instructions for at least one time slice in a one-dimensional quantum computing environment. In at least one exemplary embodiment, the computer program product includes at least one non-transitory computer-readable storage medium having computer program code stored thereon. When executed by at least one processor, the computer program code configures an apparatus to perform any of the exemplary computer-implemented methods described herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Having thus generally described embodiments of the present disclosure, reference will now be made to the accompanying drawings, which are not necessarily drawn to scale, and in which:

[0029] Figure 1 shows a block diagram of a system that may be specially configured, in which embodiments of the present disclosure may operate;

[0030] Figure 2 A block diagram illustrating an exemplary apparatus that may be specifically configured according to an exemplary embodiment of the present disclosure;

[0031] Figure 3 An exemplary computing environment for compiling at least one time slice of a quantum program in a one-dimensional quantum computing environment according to at least one exemplary embodiment of the present disclosure is shown;

[0032] Figure 4 Another exemplary computing environment for performing instruction compilation for at least one time slice in a one-dimensional quantum computing environment according to at least one exemplary embodiment of the present disclosure is shown;

[0033] Figure 5 illustrates exemplary operations of an even-odd transposition sort and a corresponding algorithmic swap command set according to at least one exemplary embodiment of the present disclosure;

[0034] Figure 6 shows various configurations of an algorithm exchange command set according to an exemplary embodiment of the present disclosure;

[0035] Figure 7A An exemplary data flow diagram illustrating an exemplary process for performing instruction compilation for at least one time slice in a one-dimensional quantum computing environment according to at least one exemplary embodiment of the present disclosure is shown;

[0036] Figure 7B An exemplary process of compiling instructions for at least one time slice in a one-dimensional quantum computing environment according to at least one exemplary embodiment of the present disclosure is shown (eg, Figure 7A An exemplary flow chart of the data flow operation in FIG.

[0037] Figure 8 Additional operations are shown for an exemplary process for compiling instructions for at least one time slice in a one-dimensional quantum computing environment, specifically for generating an algorithmic exchange command set by performing an even-odd transposition ordering based on at least an initial set of qubit positions and a target set of qubit positions, according to at least one exemplary embodiment of the present disclosure;

[0038] Figure 9 Additional operations are shown for an exemplary process for compiling instructions for at least one time slice in a one-dimensional quantum computing environment, specifically for generating an algorithmic exchange command set by performing an even-odd transposition ordering based on at least an initial set of qubit positions and a target set of qubit positions, according to at least one exemplary embodiment of the present disclosure;

[0039] Figure 10 Additional operations of an exemplary process for performing instruction compilation for at least one time slice in a one-dimensional quantum computing environment, specifically for generating a second algorithm exchange command set by performing a second even-odd transposition sort, are shown according to at least one exemplary embodiment of the present disclosure;

[0040] Figure 11 Additional operations are shown for an exemplary process for compiling instructions for at least one time slice in a one-dimensional quantum computing environment, specifically for identifying a set of target qubit positions associated with a set of qubits, according to at least one exemplary embodiment of the present disclosure;

[0041] Figure 12 shows an exemplary visualization of a target set of qubit positions for identifying a particular set of qubits according to at least one exemplary embodiment of the present disclosure;

[0042] Figure 13 shows exemplary data associated with manipulating an exemplary quantum computing environment according to at least some exemplary embodiments of the present disclosure;

[0043] Figure 14An exemplary algorithm transformation for determining a time slot corresponding to each location of a set of locations is shown in accordance with at least one exemplary embodiment of the present disclosure;

[0044] Figure 15A shows a visualization of operations for performing an even-odd transposition ordering of an exemplary set of even-odd starting position pairs starting from an even phase and generating a target position vector therefrom, in accordance with at least one exemplary embodiment of the present disclosure;

[0045] Figure 15B An exemplary process for target assignment of a target vector based on a target slot midpoint vector, the target vector embodying a target qubit position vector, according to at least one exemplary embodiment of the present disclosure is shown;

[0046] Figure 16A shows a visualization of operations for performing an even-odd transposed ordering of an exemplary set of even-odd starting position pairs starting from an odd phase, in accordance with at least one exemplary embodiment of the present disclosure;

[0047] Figure 16B An exemplary process for target assignment of another target vector based on another target time slot midpoint vector, the other target vector embodying another target qubit position vector, according to at least one exemplary embodiment of the present disclosure is shown;

[0048] Figure 17A A data visualization illustrating partitioning of a position pairing set for conversion into an even-odd position pairing set according to at least one exemplary embodiment of the present disclosure is shown;

[0049] Figure 17B shows an exemplary visualization of a weighted directed graph generated corresponding to an example set of starting position pairings according to at least one exemplary embodiment of the present disclosure;

[0050] Figure 18 illustrates an exemplary distance histogram weight calculation for an exemplary path traversing an exemplary directed weighted graph in accordance with at least one exemplary embodiment of the present disclosure;

[0051] Figure 19 shows a visualization of a first identified shortest path as part of a shortest path graph algorithm according to at least one exemplary embodiment of the present disclosure;

[0052] Figure 20 shows a visualization of a processed portion of an exemplary directed weighted graph with updated weights based on identified shortest path trees and shortest paths according to at least one exemplary embodiment of the present disclosure;

[0053] Figure 21A visualization showing a processed portion of an exemplary directed weighted graph with an identified shortest path in reverse according to at least one exemplary embodiment of the present disclosure;

[0054] Figure 22 showing a visualization of a second identified shortest path as part of a shortest path graph algorithm according to at least one exemplary embodiment of the present disclosure;

[0055] Figure 23A showing a visualization of a third identified shortest path as part of a shortest path graph algorithm according to at least one exemplary embodiment of the present disclosure;

[0056] Figure 23B showing a visualization of merged paths of an exemplary graph according to at least one exemplary embodiment of the present disclosure;

[0057] Figure 24 shows an exemplary visualization of operations for processing closed loop paths of a weighted directed graph in accordance with at least one exemplary embodiment of the present disclosure;

[0058] Figure 25 An exemplary visualization of an original starting position pairing set and corresponding initial swap commands and converted even-odd starting position pairing sets according to at least one exemplary embodiment of the present disclosure is shown;

[0059] Figure 26 An exemplary flow chart including exemplary operations for target allocation as part of an exemplary process for instruction compilation for at least one time slice in accordance with at least one exemplary embodiment of the present disclosure is shown;

[0060] Figure 27 An exemplary flow chart including exemplary operations for target allocation as part of an exemplary process for instruction compilation for at least one time slice in accordance with at least one exemplary embodiment of the present disclosure is shown;

[0061] Figure 28 An exemplary flow chart including exemplary operations for target allocation as part of an exemplary process for instruction compilation for at least one time slice in accordance with at least one exemplary embodiment of the present disclosure is shown;

[0062] Figure 29 An exemplary flow chart including exemplary operations for target allocation as part of an exemplary process for instruction compilation for at least one time slice according to at least one exemplary embodiment of the present disclosure is shown; and

[0063] Figure 30An exemplary flow chart including exemplary operations for target allocation as part of an exemplary process for instruction compilation for at least one time slice is shown in accordance with at least one exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0064] Embodiments of the present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which some, but not all, embodiments of the present disclosure are shown. Indeed, embodiments of the present disclosure can be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will satisfy applicable legal requirements. Throughout, like reference numerals refer to like elements.

[0065] Overview

[0066] Quantum computers manipulate qubits (qubits) for various computational actions. In one such context, a quantum computer utilizes qubits as input to one or more logic gates configured to perform logical operations based on the states of the input qubits. Logic gate configurations can be combined in various ways within a quantum program, for example, where the program is specifically configured to achieve a desired result.

[0067] One such environment in which qubits are manipulated is a one-dimensional quantum computing environment. In a one-dimensional quantum computing environment, qubit movement is constrained to a single dimension, meaning that the qubit can move forward or backward along that dimension. An example of a one-dimensional quantum computing environment is one in which qubits are linearly arranged within a confinement device of a quantum computer, such as at one or more predefined regions of an ion trap, while maintaining the ion positions in a well-defined order. In some such contexts, a quantum computer is configured to perform logic operations (e.g., logic gates) using input qubits that are adjacent to each other. Thus, in a one-dimensional arrangement of qubits, only those qubits that are positioned at adjacent positions within the qubit ordering can be input to the same logic gate. Additionally, in some such implementations, each region can be configured to enable one or more qubits to be located at that region while maintaining well-defined positions within the qubit ordering such that no two qubits within the ordering can share a single position. Non-limiting examples of such implementations include transport-capable trapped-ion quantum computers such as quantum charge-coupled devices that require physically adjacent pairs of qubits within the same gating region (e.g., adjacent locations within a computing environment) for gating at appropriate time slices.

[0068] The present disclosure includes embodiments for all one-dimensional quantum computing environments, regardless of the various factors associated with such quantum computing environments. For example, the present disclosure includes embodiments for all one-dimensional quantum computing environments, regardless of the qubit type and the specific exchange operations available, as long as the exchange operation occurs between nearest neighboring sites (e.g., adjacent qubit positions in a qubit ordering) in the one-dimensional quantum computing environment. Non-limiting examples include: superconducting qubits, quantum dot qubits, neutral atom qubits, photon qubits, one-dimensional arrays of any qubit type where the neighbor exchange is a quantum exchange gate; one-dimensional arrays of logical qubits formed from a collection of any physical qubit type, where the exchange operation is a logical exchange gate or an exchange of batches of physical qubits between neighboring blocks of nearest qubits; one-dimensional arrays of qubits within a larger and / or higher dimensional arrangement of qubits, regardless of the qubit type and exchange operation implementation, and the like. Therefore, it should be understood that the present disclosure should not be limited to any particular quantum computing environment, any particular one-dimensional quantum computing environment implementation, qubit implementation, exchange operation implementation, and / or any combination thereof.

[0069] Additionally, in some implementations, the physical structure of a quantum computer minimizes the ability of qubits to easily move across long distances. For example, in a one-dimensional arrangement, a qubit may be constrained to move only to a region adjacent to the qubit's current region, or to the next occupied region (e.g., the next region in which another qubit is located), or to the next unoccupied region (e.g., the next region in which no qubit is located). In this regard, qubits may be swapped with qubits in a well-defined order to a higher position or a lower position in the order, such that, regardless of the distance between qubits, the qubits remain within the one-dimensional environment in the desired well-defined order. It will be appreciated that such contexts may involve multiple qubit swaps to facilitate movement of each qubit from a starting position within the well-defined order of qubits to a desired position. Similarly, it may be desirable to perform such moves on multiple qubits, for example, to organize the qubits for executing a desired set of logic gates within a particular time slice. For example, a quantum program may include multiple logic gates to be executed within one or more time slices.

[0070] However, managing and moving qubits is a resource-intensive task. Each repositioning action requires time and energy to achieve the desired movement. Furthermore, the precise nature of qubit management increases the likelihood of errors caused by qubit movement (e.g., qubit memory errors, which accumulate as the movement takes longer). Therefore, to conserve computing resources and minimize errors, it is desirable to efficiently perform qubit repositioning within a quantum computing environment. Furthermore, conventional non-quantum computing system implementations configured to manipulate qubit positions are often significantly resource-intensive, difficult to maintain, and / or otherwise inappropriate based on limitations in the operation of a quantum computer (e.g., manipulating qubits to move a region in either direction). Improved methods for generating a reduced number of elementary operations performed by a non-quantum computer offer corresponding advantages in both the operation of the non-quantum computer and the operation of the quantum computer. For example, such improved methods reduce the use of conventional computing resources (e.g., processing resources, memory resources, networking resources, etc.) compared to conventional implementations known in the art for generating such instructions for controlling a quantum computer to achieve a desired result. Therefore, it is desirable to achieve efficient qubit repositioning that meets the limitations of modern quantum computing implementations.

[0071] Embodiments of the present disclosure provide instruction compilation for at least one time slice in a one-dimensional quantum computing environment, for example, by automatically generating an algorithmic exchange command set. The algorithmic exchange command set can be efficiently generated using a sorting algorithm, wherein data movement is constrained to exchanging and / or otherwise manipulating data elements between adjacent data storage sites within a one-dimensional array, and a manipulation indicator, such as a swap indicator, is stored for determining each manipulation to be performed. A sorting algorithm that generates a set of exchange commands in which exchanges can be performed in parallel reduces the total time for qubit repositioning. One such sorting algorithm is an even-odd transposition sort. For a one-dimensional quantum computing environment constrained to reposition only to adjacent regions, the algorithmic exchange command set represents a move that can be implemented by a quantum computer to reposition qubits to a desired position that conforms to the constraints of the quantum computer. The algorithmic exchange command set includes a set of parallel exchange commands, each parallel exchange command representing a set of exchanges that can be applied simultaneously and in parallel to a set of adjacent qubit pairs, wherein for a single parallel exchange command, all sets of qubits in the set of adjacent qubit pairs are unique (i.e., a qubit is included in at most one exchange within the parallel exchange command). Furthermore, in some contexts, the set of target qubit positions can be identified in a particular manner, such as based on a near-midpoint qubit open index pair for each qubit pair, to reduce the number of resulting parallel swap commands. Thus, an even-odd transposition sort can be performed to reduce the number of required parallel swap commands to at most N, where N represents the number of qubits in the qubit set that may need to be repositioned in a quantum computing environment. Furthermore, by assigning target qubit positions close to a near-midpoint qubit open index pair for each qubit pair and / or a single qubit gated as a single input (which may not need to be repositioned and / or can be otherwise manipulated to any position), the number of parallel swap commands can be further reduced to less than N in many cases. Additionally or alternatively, in some embodiments, a slot-based target assignment is performed, resulting in a set of target qubit positions with a further reduced worst-case scenario, as described herein. By generating an algorithmic swap command set and / or any corresponding instruction set therefrom using an even-odd transposition sort or other sorting algorithm that satisfies the constraints, complexity is reduced due to the simplified nature of generating such instructions for implementing such repositioning. Additionally or alternatively, by reducing the number of parallel exchange commands to be executed, some exemplary embodiments of the present disclosure conserve computing resources and / or reduce expected errors that may occur in a quantum computing environment. Furthermore, in some exemplary embodiments, look-ahead processing of subsequent time slices can enable further reduction in the number of operations to be performed, for example, by identifying when a pair of qubits at a first (e.g., current) time slice are adjacent during repositioning. In this regard, the adjacent qubits can be gated in an earlier operation before continuing to other qubits at the first time slice that become adjacent.Additionally or alternatively, in some embodiments, look-ahead processing optimization may be performed to select new target locations for the qubits that are gated ahead of time based on the qubits to be gated at the second or other subsequent time slices, such as to minimize the number of parallel exchange commands at the second time slice. It will be appreciated that such embodiments enable the repositioning of any number of qubits.

[0072] definition

[0073] In some embodiments, some of the operations described above may be modified or further amplified. In addition, in some embodiments, additional optional operations may also be included. Modifications, amplifications, or additions to the operations described above may be performed in any order and in any combination.

[0074] Those skilled in the art to which the present disclosure pertains will appreciate many modifications and other embodiments of the present disclosure as set forth herein, having benefited from the teachings presented in the foregoing description and the associated drawings. It will be appreciated, therefore, that the embodiments are not limited to the specific embodiments disclosed, and that modifications and other embodiments are intended to be included within the scope of the appended claims. In addition, although the foregoing description and the associated drawings have described exemplary embodiments in the context of certain exemplary combinations of elements and / or functions, it will be understood that different combinations of elements and / or functions may be provided by alternative embodiments without departing from the scope of the appended claims. In this regard, for example, it is also conceivable to combine elements and / or functions that are different from those explicitly described above, as may be shown in some of the appended claims. Although specific terms are employed herein, they are used only in a general and descriptive sense, and not for the purpose of limitation.

[0075] The term "one-dimensional quantum computing environment" refers to quantum computing hardware, software, middleware, firmware and / or a combination thereof, wherein qubits are positioned in a one-dimensional space. In some exemplary embodiments, the one-dimensional space can be a linear arrangement of positions. In some exemplary embodiments, the one-dimensional quantum computing environment includes an ion trap, which includes a plurality of one-dimensionally arranged regions (such as a longitudinal axis parallel to the ion trap) for capturing qubits in various regions along a linear arrangement of regions within the ion trap. For example, a region can be defined so that a qubit at a specific index is located within a specific space associated with one or more other qubits (e.g., a first qubit is positioned in front of all other qubits, a second qubit is positioned anywhere between the first and third qubits, and so on). The position of the qubits within the one-dimensional quantum computing environment can be controlled using one or more electrodes positioned along the length of the ion trap (e.g., by adjusting the voltage applied to one or more of the electrodes to move the ions along the one-dimensional space). In some exemplary embodiments, the one-dimensional quantum computing environment includes a one-dimensional arrangement of logical qubits formed by a set of physical qubits.

[0076] The term "qubit set" refers to a representation of a plurality of qubits within a one-dimensional quantum computing environment. In at least one exemplary embodiment, the qubit set corresponds to a plurality of qubits trapped within an ion trap and / or other quantum computing hardware for storing qubits within the one-dimensional quantum computing environment. In one exemplary embodiment, the qubit set corresponds to a plurality of logical qubits formed from a set of physical qubits.

[0077] The term "time slice" refers to a specific instance or interval of time during which one or more computational operations will occur within a computing environment. In at least one exemplary embodiment, a time slice represents a time interval during which a set of quantum gates are to be executed. The set of quantum gates may be executed serially, in parallel, or substantially in parallel.

[0078] The term "circuit depth" refers to the number of time slices that embody the execution of a particular quantum circuit. It should be understood that a quantum circuit embodying a quantum program can include any number of time slices, depending on the operations to be performed. The term "depth-1 circuit" refers to a quantum circuit with a single time slice. In this context, the terms "time slice" and "depth-1 circuit" are used interchangeably as synonyms.

[0079] The terms "position index" and "position" refer to electronically managed data that represents the position of a qubit within a one-dimensional ordering of qubits within a one-dimensional quantum computing environment at a particular time slice. In this regard, the position index "P" represents the qubit position within the range [0,Q), where Q represents the number of positions within the one-dimensional quantum computing environment. The term "position vector" refers to any vector having a vector length "L" with a unique position, where the vector length L is less than or equal to the number of positions within the one-dimensional quantum computing environment. For example, given a particular position vector "v" having a length "L" and a vector index "i" within the range [0,L), v[i] represents a unique position within the range of positions [0,Q). In some contexts, the position vector includes the same number Q of qubit positions (e.g., L = Q) for processing all positions within the one-dimensional quantum computing environment, and in some other contexts, the position vector includes a lesser number of qubit positions (e.g., L < Q) for processing a subset of all positions within the one-dimensional quantum computing environment. It should be understood that the one-dimensional quantum computing environment may include any number of positions for processing qubits within a set of qubits.

[0080] The terms "complete position set" and "all positions" refer to one or more data structures that represent all positions within a one-dimensional quantum computing environment. For example, in an exemplary context having 12 positions, "all positions" would refer to a list, set, or other data structure (e.g., a list of indices 0 to 11 corresponding to positions 1 to 12) that includes data values corresponding to each of the 12 positions.

[0081] The term "initial position index" refers to the particular position index of a qubit at the start of a time slice. The term "starting position pair set" refers to electronically managed data that represents the set of all starting position pairs within a particular time slice. In some embodiments, the starting position pair set includes paired initial pairing indices.

[0082] The term "target position index" refers to the particular position index of a qubit that is located at the corresponding position index at the end of a time slice.

[0083] The term "initial qubit position set" refers to electronically managed data that represents a set of initial position indices that embody all or a subset of the qubits within a set of qubits. In some embodiments, the initial qubit position set is embodied by a vector having a length equal to the number of qubits within the set of qubits, where the value at each index of the vector represents the initial position index of the qubit represented by the index of the vector.

[0084] The term "target qubit position set" refers to electronic management data representing the target position for each current position of a qubit indexed by the current position. In some embodiments, the target qubit position set is represented by a vector ("target") indexed by the current position. For example, given a current position set ("current") and a particular indexed qubit ("q"), p1 = current[q], where p1 represents the current position index of qubit q, and further t1 = target[p1], where t1 represents the target position that includes the current position p1 of qubit q during a particular time period. The target qubit position set includes the target qubit position indices for all qubits or a subset of qubits in the qubit set. In some embodiments, the target qubit position set is represented by a vector of length equal to the number of qubits in the qubit set, where the value at each index of the vector represents the target position index for the qubit represented by the index of the vector. In at least some embodiments, the target qubit position set includes the target position index for each qubit in the initial qubit position set that corresponds to the initial position index.

[0085] The term "double partition" with respect to a particular source set refers to identifying two subsets of the source set based on one or more criteria, wherein the two subsets are disjoint and the union of the two subsets is equivalent to the source set. The term "equal-sized subsets of a double partition" refers to two subsets of a double partition, wherein each subset includes an equal number of elements from the source set. Non-limiting examples of equal-sized subsets of a double partition of a complete set of positions include, for example, a first position subset having all even positions and a second position subset having all odd positions, the first subset containing the elements {0, 3, 4, 7, 8, 11, 12, ..., N-4, N-1} and the second subset containing the elements in N positions {1, 2, 5, 6, 9, 10, ..., N-3, N-2}, the first subset containing the first position of all starting position pairs and the second subset containing the second position of all starting position pairs, and so on.

[0086] The term "gating" refers to the physical positioning of one or more qubits, and / or the pairing of two qubits within a defined proximity, to enable the execution of logic gates based on the state of the one or more qubits. In this regard, multiple qubits may be gated in order to execute multiple logic gates in parallel and / or to implement quantum circuits based on various gating operations performed within a series of time slices.

[0087] The term "qubit pair" refers to an unordered pair of unique qubit indices comprising a first qubit "q1" and a second qubit "q2," wherein the first qubit q1 and the second qubit q2 are each in the range [0, Q), and wherein q1 is not equal to q2, and Q represents the total number of qubits in a one-dimensional quantum computing environment. Unless otherwise specified elsewhere in this specification, the order of the qubits in a qubit pair is insignificant, such that for processing purposes, the qubit pair (q1, q2) can be determined to be equivalent to the qubit pair (q2, q1). In some embodiments, the first qubit and the second qubit in a qubit pair are associated with each other to be gated at a defined time slice. In some embodiments, a logic gate within a designed circuit identifies the qubit pair to be used to perform the logic gate. Generally, any consistency in the storage and / or display of qubit pairs and / or qubit position indices throughout is provided for convenience and to enhance the understandability of the present disclosure and is not intended to limit the scope or spirit of the present disclosure.

[0088] The terms "qubit pairing set" and "position pairing set" refer to electronically managed data objects that include paired qubit sets and / or position sets representing qubit pairs that are marked for gating at a particular time slice or multiple time slices. For example, in at least one exemplary embodiment, based on a designed quantum computing circuit for one or more logic gates to be executed, the qubit pairing set includes position pairs corresponding to qubit pairs for each of a plurality of time slices.

[0089] The term "start," when used relative to a particular time slice, refers to a Q-length position vector, where Q is the number of qubits in the set of qubits maintained in a one-dimensional quantum computing environment indexed by the qubit representing the starting positions of all qubits at the beginning of the particular time slice. For example, given the vector "start" and a particular index "q," start[q] represents the starting position of qubit q within the particular time slice, where q falls within the range [0, Q) and Q represents the number of positions within the one-dimensional quantum computing environment. The term "start position" of a particular qubit refers to the position index of the particular qubit identified by the start vector, the starting position index p of the start vector v, and the qubit q defined by start[q] within the particular time slice.

[0090] The term "current" refers to a Q-length vector, where Q is the number of qubits in a qubit set held in a one-dimensional quantum computing environment, indexed by a qubit representing the current position of each qubit in the qubit set at a particular step in an algorithm for assigning and / or manipulating qubit positions as described herein. In one exemplary context, "current" refers to a vector of the current positions of all qubits at a particular step in the process for assigning a target qubit position set. For example, in some embodiments, current[q] defines the current position of qubit q from a particular qubit set. At the beginning of a particular time slice, "current" is initialized to be equal to the "start" vector. During the rearrangement sequence used to assign a target qubit position set, "current" may be updated to reflect the current positions of qubits as they are swapped through positions in the one-dimensional quantum computing environment on their way to the assigned target position for the particular time slice. In some such contexts, the "current" value is unique within the index range [0, N).

[0091] The term "position pair" refers to electronically managed data representing a unique position pair comprising a first position p1 and a second position p2, wherein the first position and the second position fall within the range [0, N), where N represents the number of positions, and p1 is different from p2. Unless otherwise specified herein, the position pairs are unordered such that the position pair (p1, p2) is equivalent to the position pair (p2, p1).

[0092] The term "starting position pair," when used with respect to a particular time slice, refers to electronic management data representing a position pair (p1, p2) corresponding to a particular qubit pair (q1, q2), the position pair identifying a starting position index for each of qubits q1 and q2. The position pair (p1, p2) includes a first position p1 representing a first starting position corresponding to the first qubit q1 of the particular qubit pair in the set of qubit pairs, and includes a second position p2 representing a second starting position corresponding to the second qubit q2 of the particular qubit pair. The starting position pair (p1, p2) corresponding to the particular qubit pair (q1, q2) can be determined from a starting vector ("start") such that p1 is defined by start[q1] and p2 is defined by start[q2]. Unless otherwise specified herein, the starting position pairs are unordered such that the starting position pair (p1, p2) is equivalent to the starting position pair (p2, p1).

[0093] The terms "even-even pair" and "ee pair" refer to a position pair (p1, p2), where both p1 and p2 represent even position indices. In some cases, an even-even pair represents a starting position pair representing two even position indices, which may be referred to as an "even-even starting position pair."

[0094] The terms "odd-odd pair" and "odd pair" refer to a position pair (p1, p2) where both p1 and p2 represent odd position indices. In some cases, an odd pair represents a starting position pair representing two odd position indices, which may be referred to as an "odd-odd starting position pair."

[0095] The terms "even-odd pair," "odd-even pair," "eo pair," and "oe pair" refer to a position pair (p1, p2) where p1 is odd and p2 is even, or p1 is even and p2 is odd. In some cases, the even-odd pair represents a starting position pair representing one even position index and one odd position index in any order, which may be referred to as an "even-odd starting position pair."

[0096] The term "even-odd starting position pairing set" refers to a starting position pairing set comprising any number of starting position pairs, wherein each position pair comprises an even-odd starting position pair.

[0097] The term "time slot" refers to an index representation corresponding to two position indices in a one-dimensional quantum computing environment. The correlation between the position and the time slot can be determined based on a specific algorithm. In some embodiments, the two positions of the time slot are adjacent, and the two qubits occupying the same time slot meet the adjacent requirement. For example, integer division is performed on a specific position to divide it by a division factor that can be determined to determine the time slot ("s") of a specific position ("p"), such as p / / 2==s, where " / / " represents integer division that discards the remainder. In this regard, a specific time slot can be mapped to two different positions (e.g., p1==(s*2), and p2==(s*2)+1).

[0098] The term "near-midpoint open index pair" refers to one or more data objects representing unassigned target position indices of a set of target qubit positions to be assigned to a first qubit and a second qubit of a qubit pair. In some embodiments, a near-midpoint open index pair represents two target position indices that are located at a near-midpoint index and / or closest to a midpoint index based on initial position indices of the first qubit and the second qubit of the qubit pair.

[0099] The term "even-odd transposition sort" refers to a computational algorithm for sorting data values ​​within a vector (having any number of indices) by performing a swap of data values ​​at adjacent indices in alternating even and odd cycles, where for a number of iterations, the even cycles have lower indices even and the odd cycles have lower indices odd. It will be appreciated that even-odd transposition sort relies on comparing data values ​​at adjacent indices of a vector and swapping the data values ​​if the order of the data values ​​does not satisfy the desired value order (e.g., swapping the data values ​​if they are to be in ascending order but are not). Even-odd transposition sort is also known as: even-odd sort, odd-even sort, odd-even transposition sort, bricksort, paritysort, or parallel bubble sort.

[0100] The term "even swap" as part of an even-odd transposition sort refers to determining a swap to be performed between data values ​​residing at adjacent positions in a data vector where the lower index is an even number. In some embodiments, one or more even swaps are performed during even cycles of the even-odd transposition sort.

[0101] The term "odd swap" as part of an even-odd transposition sort refers to determining a swap to be performed between data values ​​residing at adjacent positions in a data vector where the lower index is an odd number. In some embodiments, one or more odd swaps are performed during odd cycles of the even-odd transposition sort.

[0102] The term "swap indicator" refers to an electronically managed data value that indicates a determination of a swap to be performed. In some embodiments, the swap indicator indicates a first data value that indicates a determination of an even swap to be performed, and a second value that indicates a determination of an odd swap to be performed. In other embodiments, for example where the determination of whether a swap is an even or odd swap can be derived in another manner, the swap indicator indicates a first value that indicates a determination of a swap to be performed, and a second value that indicates a determination that no swap is to be performed.

[0103] The term "algorithmic swap command set" refers to one or more electronic management data objects representing all swaps determined to be performed based on the even-odd transposition ordering or one or more steps thereof. In some embodiments, for example, the algorithmic swap command set includes any number of swap indicators determined to be performed to order the initial set of qubit positions to reflect the target set of qubit positions.

[0104] The term "parallel swap command" refers to one or more electronic management data objects representing a set of swaps to be performed simultaneously in parallel. In some embodiments, a parallel swap command may refer to a set of swap indicators generated according to an even-numbered cycle of an even-odd transposition ordering. In some embodiments, a parallel swap command may refer to a set of swap indicators generated according to an odd-numbered cycle of an even-odd transposition ordering.

[0105] The term "qubit manipulation instruction set" refers to one or more electronically managed data objects representing instructions for manipulating qubits based on an associated algorithmic exchange command set. In this regard, in some embodiments, the qubit manipulation instruction set represents one or more qubit energy-level operations to be performed to represent the actions embodied in the corresponding algorithmic exchange command set.

[0106] The term "qubit swap instruction" refers to electronically managed data representing a swap of at least a first qubit and a second qubit. In this regard, the positions of the swapped qubit pair are interchanged such that the final position of the first qubit after the swap is the initial position of the second qubit before the swap, and the final position of the second qubit after the swap is the initial position of the first qubit before the swap.

[0107] The term "qubit split instruction" refers to electronic management data representing the splitting of at least a first qubit and a second qubit that are associated with a well-defined order and that initially reside in a common region into two separate adjacent regions, wherein after the splitting, the first qubit resides in a first of the two separate regions and the second qubit resides in a second of the two separate regions, and the order of the qubits remains in their initial well-defined order.

[0108] The term "qubit merge instruction" refers to electronic management data that causes at least a first qubit initially residing in a first region and a second qubit initially residing in a second, separate, adjacent region to be finally merged into a common region while maintaining the initial well-defined order of the two qubits. The term "qubit merge instruction" may also be referred to as a "qubit merge instruction" and a "qubit reshuffle instruction."

[0109] The term "qubit shift instruction" refers to electronically managed data representing a shift that causes one or more qubits initially residing in a first region to ultimately be in a second region without changing the well-defined order of the qubits in a one-dimensional quantum computing environment.

[0110] The term "hardware instruction set" refers to one or more hardware instructions that are executed to physically manipulate qubits to perform the actions represented by the qubit manipulation instruction set. Non-limiting examples of a hardware instruction set include applying a time-varying potential to control electrodes of an ion trap and / or associated hardware to cause the hardware to perform the desired action represented by the qubit manipulation instruction set.

[0111] The term "qubit manipulation hardware" refers to computing hardware, firmware, and / or software for configuring the hardware that is configured to execute one or more hardware instructions for manipulating the position of one or more qubits, or regions containing the one or more qubits, in a quantum computing environment. Non-limiting examples of qubit manipulation hardware include: an ion trap; electrodes connected to interact with one or more qubits positioned at one or more regions of the ion trap along a quantum computer; voltage and / or waveform generators for providing voltage signals to the electrodes; lasers and corresponding beam delivery paths for performing gating, cooling, and / or measurement functions on the one or more qubits; and the like.

[0112] The term "adjacent," when used with respect to a position index and / or a qubit at a position index, refers to two positions whose indices differ by 1. For the example of two positions p1 and p2, p1 is adjacent to p2 if and only if abs(p1-p2) == 1, where abs(x) of some value x is defined as the absolute value of x, which represents x if x is greater than or equal to zero (0) and -x (negative x) if x is less than zero. Qubits that are in adjacent positions at a particular time slice can be gated.

[0113] Exemplary Computing Systems and Environments

[0114] Figure 1A block diagram of a system that can be specially configured according to at least one exemplary embodiment of the present disclosure is shown, within which embodiments of the present disclosure can operate. The block diagram provides a schematic diagram of an exemplary quantum computer system 100 including an ion trap device and / or package 150 according to an exemplary embodiment. In various embodiments, the quantum computer system 100 includes a computing entity 10 and a quantum computer 102. In various embodiments, the quantum computer 102 includes a controller 30, a cryostat and / or vacuum chamber 40 enclosing the ion trap device and / or package 150, one or more manipulation sources 60, and one or more voltage sources 50. In an exemplary embodiment, the one or more manipulation sources 60 may include one or more lasers (e.g., optical lasers, microwave sources, etc.). In various embodiments, the one or more manipulation sources 60 are configured to manipulate and / or cause the controlled quantum state evolution of one or more ions in the ion trap of the ion trap device and / or package 150. For example, in an exemplary embodiment, where the one or more manipulation sources 60 include one or more lasers, the lasers can provide one or more laser beams to the cryostat and / or ion trap within the vacuum chamber 40 via corresponding beam paths 66 (e.g., 66A, 66B, 66C). In various embodiments, the quantum computer 102 includes one or more voltage sources 50. For example, the voltage sources 50 can include a plurality of transmission and / or trapping (TT) voltage drivers and / or voltage sources and / or at least one radio frequency (RF) driver and / or voltage source. The voltage sources 50 can be electrically coupled to corresponding TT electrodes and / or RF rails for generating a trapping potential configured to trap one or more ions within an ion trap of the ion trap device and / or package 150 via corresponding electrical leads.

[0115] In some such embodiments, the ion trap includes and / or otherwise defines one or more physical regions at which qubits may be located or otherwise positioned within the ion trap. In various embodiments, these regions are arranged in a linear and / or one-dimensional arrangement along the longitudinal axis of the ion trap (e.g., defined by the RF rails of the ion trap). In at least one exemplary context, each physical region is configured to enable one or more qubits to be stored at that region while maintaining a well-defined order of qubit positions across all regions in the ion trap. Alternatively or additionally, in some embodiments, the ion trap is configured to enable movement of regions and movement of qubits within those regions along the ion trap. In some such embodiments, adjacent qubits within a qubit ordering may swap their positions to enable repositioning of the qubits in a one-dimensional quantum computing environment. In this regard, a qubit located at a first position (e.g., position 0) may only be exchanged with a second position (e.g., position 1) located in a first direction along the ion trap. A qubit located at a second position (e.g., position 1 between positions 0 and 2) may be capable of being swapped with position 2 (in a first direction) or position 0 (in another direction, e.g., opposite to the first direction). In some embodiments, for example, a voltage signal may be applied to an electrode of an ion trap (e.g., a TT electrode) to induce a potential experienced by ions within the ion trap that induces one or more actions for swapping adjacent qubits to allow such repositioning (e.g., in an exchange between position 1 and position 2 in the qubit ordering, the qubit initially at position 1 becomes positioned at position 2, and the qubit at position 2 concurrently and / or otherwise substantially simultaneously becomes positioned at position 1).

[0116] In various embodiments, computing entity 10 is configured to allow a user to provide input to quantum computer 102 (e.g., via a user interface of computing entity 10) and receive output from quantum computer 102, view output, etc. The computing entity 10 may communicate with a controller 30 of quantum computer 102 via one or more wired or wireless networks 20 and / or via direct wired and / or wireless communications. In an exemplary embodiment, computing entity 10 may convert, configure, format, etc. information / data, quantum computing algorithms, etc. into a computing language, executable instructions, command set, etc. that controller 30 may understand and / or implement.

[0117] In various embodiments, controller 30 is configured to control voltage source 50, a cryogenic system and / or vacuum system that controls the temperature and pressure within cryogenic chamber and / or vacuum chamber 40, a manipulation source 60, and / or other systems that control various environmental conditions (e.g., temperature, pressure, etc.) within cryogenic chamber and / or vacuum chamber 40 and / or are configured to manipulate and / or cause a controlled evolution of the quantum state of one or more ions within the ion trap. In various embodiments, some or all of the ions trapped within the ion trap serve as qubits for quantum computer 102.

[0118] In some embodiments, the controller 30 is embodied by a non-quantum computer configured to perform an even-odd transposition sort, as described herein. Additionally or alternatively, in some embodiments, the controller 30 is configured to generate a swap command set, a qubit manipulation instruction set, and / or a hardware instruction set associated with the performed even-odd transposition sort. In this regard, the controller 30 can be configured to generate appropriate instructions for controlling the quantum computer 102 in a desired manner (e.g., repositioning individual qubits to desired locations). Alternatively or additionally, in some embodiments, the computing entity 10 is configured to perform an even-odd transposition sort and / or to generate a swap command set, a qubit manipulation instruction set, and / or a hardware instruction set associated with the performed even-odd transposition sort. In some such embodiments, the computing entity 10 is configured to transmit some or all of the generated data (such as the swap command set, the qubit manipulation instruction set, and / or the hardware instruction set). In this regard, data generated via computing entity 10 may be used by controller 30 to control quantum computer 102 in a desired manner (e.g., to reposition individual qubits to desired locations), such that computing entity 10 indirectly controls at least one aspect of quantum computer 102.

[0119] Exemplary devices of the present disclosure

[0120] The methods, apparatuses, systems, and computer program products of the present disclosure may be implemented by any of a variety of devices. For example, the methods, apparatuses, systems, and computer program products of the exemplary embodiments may be implemented by a fixed computing device such as a personal computer, a computing server, a computing workstation, or a combination thereof. Additionally, the exemplary embodiments may be implemented by any of a variety of mobile terminals, mobile phones, smartphones, laptop computers, tablet computers, or any combination thereof.

[0121] In at least one exemplary embodiment, the controller 30 is comprised of one or more computing systems such as Figure 2 In other embodiments, the computing entity 10 is implemented by the apparatus 200 shown in FIG. Figure 22. The apparatus 200 may include a processor 202, a memory 204, an input / output module 206, a communication module 208, and / or a qubit instruction processing module 210. In some embodiments, the qubit instruction processing module 210 is optional and may be embodied by one or more of the other modules and / or may be embodied by another system associated with the apparatus 200.

[0122] Although the components are described with respect to functional limitations, it should be understood that a particular implementation necessarily includes the use of specific hardware. It should also be understood that certain components described herein may include similar or common hardware. For example, two modules may use the same processor, network interface, storage medium, etc. to perform their associated functions, such that each module does not require duplicate hardware. Therefore, it should be understood that the use of the term "module" and / or the term "circuitry" as used herein with respect to components of device 200 includes specific hardware configured to perform the functions associated with the specific module described herein.

[0123] Additionally or alternatively, the terms "module" and "circuit" should be broadly understood to include hardware and, in some embodiments, software and / or firmware used to configure the hardware. For example, in some embodiments, a "module" and "circuit" may include processing circuitry, storage media, network interfaces, input / output devices, and the like. In some embodiments, other components of the apparatus 200 may provide or supplement the functionality of a particular module. For example, for one or more of the other modules, the processor 202 may provide processing functionality, the memory 204 may provide storage functionality, the communication module 208 may provide network interface functionality, and the like.

[0124] In some embodiments, the processor 202 (and / or a coprocessor or any other processing circuitry that assists the processor or is otherwise associated with the processor) may communicate with the memory 204 via a bus for transferring information between components of the device. The memory 204 may be non-transitory and may include, for example, one or more volatile and / or non-volatile memories. In other words, the memory may be an electronic storage device (e.g., a computer-readable storage medium). The memory 204 may be configured to store information, data, content, applications, instructions, etc. for enabling the device 200 to perform various functions according to the exemplary embodiments of the present disclosure.

[0125] The processor 202 may be embodied in any of a variety of ways and may, for example, include one or more processing devices configured to execute independently. Additionally or alternatively, the processor 202 may include one or more processors configured in series via a bus to enable independent execution of instructions, pipelining, and / or multithreading. The use of the terms "processor," "processing module," or "processing circuitry" may be understood to include single-core processors, multi-core processors, multiple processors within a device, other central processing units ("CPUs"), microprocessors, integrated circuits, and / or remote or "cloud" processors.

[0126] In an exemplary embodiment, the processor 202 may be configured to execute computer-coded instructions stored in the memory 204 or otherwise accessible to the processor. Alternatively or in addition, the processor 202 may be configured to perform hard-coded functions. Thus, whether configured by hardware or software methods, or by a combination thereof, the processor 202 may represent an entity (e.g., physically embodied in circuit form) capable of performing operations according to embodiments of the present disclosure while being configured accordingly. Alternatively, for example, when the processor is embodied as an executor of software instructions, the instructions may specifically configure the processor to perform the algorithms and / or operations described herein when executing the instructions.

[0127] As an exemplary context, processor 202 may be configured to provide instruction compilation functionality for at least one time slice in a one-dimensional quantum computing environment. In this regard, processor 202 may be specifically configured to support the functionality of controller 30. In some such embodiments, processor 202 includes hardware, software, firmware, etc. configured to generate an algorithmic exchange command set for gating qubits in a qubit set in appropriate positions at a given time slice. The algorithmic exchange command set may also be used to generate one or more intermediate instruction sets and / or reposition qubits in a qubit set, such as using qubit manipulation hardware (e.g., one or more electrodes), according to the algorithmic exchange command set. It should be understood that processor 202 may be configured to perform such functionality over any number of time slices.

[0128] Device 200 also includes an input / output module 206. The input / output module 206 can then communicate with the processor 202 to provide output to the user, and in some embodiments, to receive instructions to user input. The input / output module 206 may include one or more user interfaces and / or may include a display that can present a user interface to it. In some embodiments, the input / output module 206 includes a web user interface, a mobile application, a desktop application, a linked or networked client device, etc. In some embodiments, the input / output module 206 may also include a keyboard, a mouse, a joystick, a touch screen, a touch area, soft keys, a microphone, a speaker, or other input / output mechanisms. In some such embodiments, the input / output mechanism is configured to enable the user to provide data representing one or more user interactions for device 200 to process. The processor and / or a user interface module including a processor such as processor 202 may be configured to control one or more functions of one or more user interface elements by computer program instructions (e.g., software and / or firmware) stored in a memory accessible to the processor (e.g., memory 204, etc.).

[0129] The communication module 208 may be any device, such as a device or circuit embodied in hardware or a combination of hardware and software, configured to receive and / or transmit data from and / or to a network and / or any other device, circuit, or module in communication with the device 200. In this regard, the communication module 208 may, for example, include at least a network interface for enabling communication with a wired or wireless communication network. For example, the communication module 208 may include one or more network interface cards, antennas, buses, switches, routers, modems, and supporting hardware and / or software, or any other device suitable for enabling communication via a network. Additionally or alternatively, the communication interface may include circuitry for interacting with one or more antennas to facilitate transmission of signals via the one or more antennas or to process signals received via the one or more antennas.

[0130] Qubit instruction processing module 210 includes hardware, software, firmware, and / or combinations thereof configured to support instruction compilation functionality and / or corresponding qubit manipulation functionality in a one-dimensional quantum computing environment associated with controller 30. In some embodiments, qubit instruction processing module 210 may utilize processing circuitry, such as processor 202, to at least partially or fully perform these actions. In some such embodiments, qubit instruction processing module 210 includes hardware, software, firmware, and / or combinations thereof for at least identifying an initial set of qubit positions associated with a qubit set, identifying a target set of qubit positions associated with the qubit set, and generating an algorithmic swap command set by performing an even-odd permutation ordering based at least on the target set of qubit positions. In some embodiments, qubit instruction processing module 210 is further configured to receive a quantum program including a set of qubit pairings associated with the qubit set, and / or determine near-midpoint open index pairs for the set of qubit pairings, and / or assign target position indices in the set of target positions based at least on the near-midpoint open index pairs. In some embodiments, qubit instruction processing module 210 is further configured to identify a second set of target qubit positions associated with the set of qubits at a second time slice, and to generate a second set of algorithmic swap commands by performing an even-odd transposition ordering based on at least the second set of target qubit positions.

[0131] In some embodiments, qubit instruction processing module 210 is further configured to perform target allocation (e.g., identify a set of target qubit positions) based on a particular starting position for a particular set of qubits. In some such embodiments, qubit instruction processing module 210 may be configured to perform near-midpoint target allocation, slot-based target allocation, etc., as described herein. Additionally or alternatively, in some embodiments, qubit instruction processing module 210 is configured to perform one or more pre-processing algorithms on the set of starting position pairings prior to performing such target allocation.

[0132] It should be understood that in some embodiments, qubit instruction processing module 210 may include a separate processor, a specially configured field programmable gate array (FPGA), or a specially configured application specific integrated circuit (ASIC).

[0133] In some embodiments, one or more of the aforementioned components are combined to form a single module. The single combined module can be configured to perform some or all of the functions described above with respect to the individual modules. For example, in at least one embodiment, qubit instruction processing module 210 can be combined with processor 202. Additionally or alternatively, in some embodiments, one or more of the modules described above can be configured to perform one or more of the actions described with respect to one or more of the other modules.

[0134] Exemplary computing environment of the present disclosure

[0135] Figure 3 An exemplary quantum program according to at least one exemplary embodiment of the present disclosure is shown, compiled in an exemplary computing environment, for example, for at least one time slice in a one-dimensional quantum computing environment. In some embodiments, one or more of the illustrated elements are embodied by one or more data objects and / or other data values ​​maintained by a computing system (such as a controller 30 embodied by a specially configured device 200). In this regard, each illustrated element can be embodied and / or manipulated using hardware, software, firmware, and / or a combination thereof.

[0136] In some embodiments, a computing entity may be used to generate a quantum program 302 and / or submit the quantum program 302 for compilation and / or execution. The quantum program 302 may be written in any of a variety of quantum computing programming languages ​​and embody any number of commands to be executed via a quantum computing system. In this regard, the quantum program 302 may embody user-submitted instructions to be executed via a quantum computing system, for example, by first compiling the quantum program into one or more executable instruction sets that the quantum computing system can process and / or execute. In this regard, the quantum computing system may implement the quantum program by initializing any number of qubits managed by the quantum computing system and / or performing operations using the qubits, such as performing logic gate operations using associated qubit pairs and / or individual qubits as inputs to the logic gate operations.

[0137] In some such embodiments, quantum program 302 includes and / or is embodied by one or more qubit pair sets to be executed at various time slices. An exemplary quantum program 302 is depicted, wherein quantum program 302 is embodied by one or more qubit pair sets, each qubit pair set including qubit pairs of qubits of qubit set 304 to be executed at multiple time slices. As shown, quantum program 302 is associated with qubit set 304. Qubit set 304 includes 8 qubits, each identified by a zero-based qubit index ranging from 0 to 7. Each qubit represented in qubit set 304 may correspond to a qubit physically maintained in a corresponding quantum computing environment. Thus, the depicted qubit set 304 may correspond to an 8-qubit quantum computing system. It should be understood that in other embodiments, any number of qubits may be utilized.

[0138] The quantum program 302 is decomposed into multiple time slices, specifically time slices T k 、T k+1 and Tk+2 Each of these time slices is associated with a set of qubit pairs that include the qubit pairs to be gated at the corresponding time slice. For example, as shown in the figure, at time slice T k At qubit 0, qubit 7 is represented by qubit pair 306A, which pairs qubit 1 with qubit 2; qubit pair 306B, which pairs qubit 3 with qubit 4; and qubit pair 306D, which pairs qubit 5 with qubit 6 (qubit pairs 306A through 306D are collectively referred to as "qubit pairing set 306"). In this regard, each qubit pair may be associated with one or more logic gates to be executed at a time slice. For example, as shown, qubit pair 306C may represent qubits 3 and qubit 4 as gates to be executed at time slice T. k As inputs to a particular logic gate executed during the time period, qubit pair 306D may represent qubit 5 and qubit 6 as the inputs to a particular logic gate executed during the time period T. k+1 302. In this regard, the plurality of qubit pairing sets for each time slice may represent all qubit pairings that represent quantum program 302. Although not depicted, it should be understood that in some embodiments, one or more qubits are not associated with a qubit pair, such that the qubits need not be positioned adjacent to any particular qubit within the associated time slice.

[0139] The execution of a logic gate may require that a pair of qubits representing the inputs of the logic gate be located at adjacent locations within the quantum computing environment during a corresponding time slice to enable execution of the logic gate. In this regard, qubits may need to be repositioned within the quantum computing system to position the qubits of a particular qubit pair adjacent to each other for execution of the corresponding logic gate. It should be understood that other logic gates may only require a single qubit, and thus do not require that the qubits be located in any particular region or at any particular index in a well-defined order.

[0140] In this regard, Figure 4 Another exemplary computing environment for performing instruction compilation for at least one time slice in a one-dimensional quantum computing environment according to at least one exemplary embodiment of the present disclosure is shown. Specifically, the exemplary computing environment includes a plurality of data objects that can be identified, maintained, and / or used to locate qubits based on a set of qubit pairs for a particular time slice. The data objects can also be maintained by a computing system (such as a controller 30 embodied by a specially configured device 200). In this regard, each of the illustrated elements can be embodied and / or manipulated using hardware, software, firmware, and / or a combination thereof.

[0141] Figure 4Specifically illustrated for qubit set 304 are exemplary initial qubit position sets 402 and target qubit position sets 404 for time slice k. In this regard, initial qubit position set 402 includes an initial position index for each qubit in the qubit set. Such initial qubit position indices may correspond to the physical ordering of the qubits along the ion trap in the quantum computing system at the beginning of the time slice. In this regard, for example, data value 402A represents the initial position index of the qubit at index 0 (e.g., qubit 0 in qubit set 304), data value 402B represents the initial position index of the qubit at index 1 (e.g., qubit 1 in qubit set 304), data value 402C represents the initial position index of the qubit at index 2 (e.g., qubit 2 in qubit set 304), data value 402D represents the initial position index of the qubit at index 3 (e.g., qubit 3 in qubit set 304), and so on. In some embodiments, each qubit may be located at a default initial position index, for example, the initial position index being defaulted to be within the index range {0:7} associated with the qubit. In other contexts, the set of initial qubit positions may be optimized such that the initial qubit positions are assigned to qubits that are already adjacent to each other and that will be gated in the current time slice. Additionally or alternatively, the set of initial qubit positions may be generated such that the number of parallel swap commands required to reposition from the initial qubit position set to the target qubit position set in one or more subsequent time slices is reduced and / or otherwise minimized. For example, the set of initial qubit positions for a first time slice may be generated such that a second time slice has the fewest parallel swap commands required to reposition from the initial qubit position set to the target qubit position set in the second time slice. It should be understood that embodiments may determine and / or otherwise generate the default initial position index for each qubit in any manner such that one or more time slices are optimized to reduce, minimize, and / or otherwise eliminate swap operations between one or more qubits for repositioning based on the target qubit position set.

[0142] Thus, target qubit position set 404 includes a target position index for each qubit in the qubit set. Such target qubit position indices may correspond to the physical ordering of the qubits along an ion trap in a quantum computing system during and / or at the end of a time slice, e.g., to execute one or more logic gates. In this regard, for example, data value 404A represents the target position index for the qubit at index 0 (e.g., qubit 0 in qubit set 304), data value 404B represents the target position index for the qubit at index 1 (e.g., qubit 1 in qubit set 304), data value 404C represents the target position index for the qubit at index 2 (e.g., qubit 2 in qubit set 304), data value 404D represents the target position index for the qubit at index 3 (e.g., qubit 3 in qubit set 304), and so on. Thus, for a particular qubit, the target position indices in target qubit position set 404 correspond to the position to which the qubit must be moved within the ordering of the qubits along the ion trap. It will be understood that in some cases one or more qubits may not be moved such that the initial position index of the qubit matches the target position index of the qubit.

[0143] In some embodiments, for example, by apparatus 200 based on a set of qubit pairings for time slice k (such as, for example, Figure 3 qubit pairings 306 as depicted and described above) to determine a set of target qubit positions 404. In this regard, each qubit pair may be positioned such that the target position indexes associated with each of the qubits in the qubit pair are adjacent to one another. In other words, for example, in some contexts, a data value for a first target position index corresponding to a first qubit of a qubit pair may be adjacent to a data value for a second target position index corresponding to a second qubit of the qubit pair, where these data values ​​are at most one position away from one another. In this regard, a target position index for a value of "X" is adjacent to target position indexes for values ​​of "X+1" and / or "X-1" if each of such values ​​represents a valid index.

[0144] As depicted, target qubit position set 404 positions each qubit adjacent to a corresponding qubit of a qubit pair in qubit pairing set 306 at time slice k, as relative to Figure 3 For example, Figure 3 As depicted by qubit pair 306A, qubit 0 is paired with qubit 7, and accordingly qubit 0 is associated with a target qubit position index 404A having a value of "2," while qubit 7 is associated with a target qubit position index 404H having a value of "3," such that the target position indices of the qubit pair are adjacent. Similarly, Figure 3As depicted by qubit pair 306B, qubit 1 is paired with qubit 2, and accordingly qubit 1 is associated with a target qubit position index 404B having a value of "0," while qubit 2 is associated with a target qubit position index 404C having a value of "1," such that the target position indices of the qubit pair are adjacent. Similarly, Figure 3 As depicted by qubit pair 306C, qubit 3 is paired with qubit 4, and accordingly qubit 3 is associated with a target qubit position index 404D having a value of "4," while qubit 4 is associated with a target qubit position index 404E having a value of "5," such that the target position indices of the qubit pair are adjacent. Similarly, Figure 3 As depicted by qubit pair 306D, qubit 5 is paired with qubit 6, and accordingly, qubit 5 is associated with a target qubit position index 404F having a value of "6," while qubit 6 is associated with a target qubit position index 404G having a value of "7," such that the target position indices of the qubit pairs are adjacent. Thus, where each qubit pair in qubit pairing set 306 is located in adjacent indices (e.g., corresponding to adjacent positions in the ordering of qubits along the ion trap), each qubit pair can be used as an input to perform a desired logic gate.

[0145] Figure 5 504 and 505. In this regard, the algorithm exchange command set 504 is used to reposition a qubit from an initial position to a target position. Specifically, Figure 5 An even-odd transposition ordering is depicted for repositioning qubit set 304 based on target qubit position set 404, specifically for repositioning qubit set 304 from initial qubit position set 402 to the target qubit position set. Utilizing the even-odd transposition ordering, it will be appreciated that qubits can be ordered in up to Q parallel swap operations, where Q represents the number of qubits in the qubit set. Furthermore, as described herein, the determination and utilization of near-midpoint indices for qubit pairs can be used to reduce the number of parallel swap operations required to achieve the target qubit position set. In this regard, utilizing near-midpoint indices can reduce the number of parallel swaps by approximately half (Q / 2 swaps), regardless of the initial position of each qubit.

[0146] The even-odd transposition sort includes a plurality of operational steps 502A through 502E (collectively referred to as "step 502"). Specifically, the algorithm operates on a data vector and begins at step 502A (where the data vector is loaded with an array of values ​​having the same ordering as the target qubit position set 404) and ends at step 502E (where the data vector is sorted). In some embodiments, the data vector may be loaded with the target qubit position set itself. As shown, step 502 includes a plurality of swap operations for swapping qubits at adjacent position indices. As shown, dashed lines (or "dotted lines") are used to indicate the qubits being swapped at a particular step.

[0147] The algorithm swap command set 504 includes a swap indicator for each swap determined to be performed during the even-odd transposition sort. It should be understood that the steps of the even-odd transposition sort alternately determine the swaps to be performed on even indices (e.g., 0, 2, 4, and 6 as shown) and odd indices starting with even indices (e.g., 1, 3, and 5 as shown). It should be noted that in some embodiments, the algorithm can start with odd indices and achieve the same results. Each data value at an index in the data vector is compared with the data value at the next index (e.g., each data value at index "X" is compared with the data value at index "X+1"). In the exemplary context shown, the data vector is first loaded with the target qubit position set 404 and used as a starting point for performing the even-odd transposition sort, for example, at step 502A. Subsequently, at step 502B, a swap operation is determined for each of the even indices 0, 2, 4, and 6. In this regard, a swap operation may be determined for a given index when the data value at the lower index is determined to be in an unsorted order relative to the data value at the next index. For example, a swap operation may be determined for an even index X (e.g., an "even swap") when the data value at index X+1 is less than the data value at index X.

[0148] As shown in the figure, in the first step 502B, the data vector values ​​at index 0 and index 1 are exchanged. In this regard, the data value at index 0 (value "2") is determined to be in an unsorted order relative to the data value at the subsequent index 1 (value "0"). In this regard, the value "0" is less than the value "2", and the order (e.g., ascending order in the context) is incorrect, so an exchange is required to correctly sort the values. Therefore, the data values ​​of the two indexes are exchanged at the first step 502B. Similarly, the data value at index 6 (value "7") is determined to be in an unsorted order relative to the data value at the subsequent index 7 (value "3"). In this regard, the value "3" is less than the value "7", but the order is incorrect, so an exchange is required. Therefore, the data values ​​of the two indexes are exchanged at the first step 502B. These exchanges are recorded as exchange indicators in the corresponding indexes in the algorithm exchange command set 504. Specifically, for each determined exchange, the left index of the exchange is represented as "L" and the right index of the exchange is represented as "R". Such a swap concludes the even-indexed first step 502B.

[0149] In this regard, the data vector may represent data values ​​indexed by the qubit positions as they are manipulated by performing the even-odd transposition sort. It should be understood that, as described, the data vector may be loaded based on the target qubit position set and thereby manipulated (e.g., based on a swap command) until the data vector is correctly sorted. Once the data vector is correctly sorted, the even-odd transposition sort may be terminated and processing for a new time slice may begin, as described herein. Additionally or alternatively, the data vector may be processed during intermediate steps for any of a number of purposes, such as to optimize based on a look-ahead analysis of individual qubits as described herein. For subsequent time slices, it should be understood that upon completion of the slice, e.g., at time slice k, the qubits in the qubit set have specific current positions. In this regard, such current positions at the end of the time slice may be used as initial qubit position indices for the subsequent (k+1) time slice and, in some embodiments, may be used to derive the target qubit position set for the subsequent (k+1) time slice in order to optimize the number of required swap operations. In this regard, the algorithm may continue in this manner for any number of time slices (eg, up to K time slices, where K is the circuit depth).

[0150] For odd-numbered indices of the data vector, the process continues in a similar manner. For example, when the data value at index X+1 is less than the data value at index X, a swap operation (e.g., an "odd swap") may be determined for the odd-numbered index X. For example, in a second step 502C, the data value at index 1 (value "2") is determined to be unsorted relative to the subsequent data value at index 2 (value "1"). In this regard, value "1" is less than value "2," but is not in the correct order, and therefore requires a swap. Therefore, in a second step 502C, the data values ​​of these two indices are swapped. Similarly, the data value at index 5 (value "6") is determined to be unsorted relative to the position index value at index 6 (value "3"). In this regard, value "3" is less than value "6," but is not in the correct order, and therefore requires another swap. Therefore, in a second step 502C, the data values ​​at these two indices are swapped. For each swap determined, a corresponding swap indicator is stored at the corresponding index in the algorithmic swap command set. This type of swap concludes the second step 502C for odd-numbered indices.

[0151] The process continues to a third step 502D, where the data value at index 4 (value "5") is swapped with the data value at index 5 (value "3"). The corresponding swap indicator is then stored in the algorithmic swap command set 504. The process then continues to a fourth step 502E, where the data value at index 3 (value "4") is swapped with the data value at index 4 (value "3"). The corresponding swap indicator is then stored in the algorithmic swap command set 504. After fourth step 502E, the data values ​​are in the correct order and the even-odd transposition order is complete. Thus, the algorithmic swap command set 504 represents the swaps required to reposition the qubits according to the target qubit position set 404. In this regard, the algorithmic swap command indicators can be processed to perform the corresponding swaps associated with the swap indicators therein, for example, by generating one or more intermediate instruction sets and / or executing such instructions.

[0152] Figure 6 Various configurations of an algorithmic swap command set according to exemplary embodiments of the present disclosure are shown. Such configurations include an algorithmic swap command set 504 that utilizes a first swap indicator to indicate a left index to swap and a second swap indicator to indicate a right index to swap. In this regard, the swap indicator may be processed to determine whether the qubits are to be swapped left or right.

[0153] Figure 6Also included is a first alternative algorithm swap command set 602. The algorithm swap command set indicates the lower index of each swap where the swap indicator is equal to 1. In this regard, a corresponding system may process the first alternative algorithm swap command set 602 to identify each swap based on the swap indicator and perform the swap for the index at which the swap indicator is located and subsequent indices. In doing so, there is no need to store the right swap indicator within the first alternative algorithm swap command set 602. In other embodiments, it should be understood that an algorithm swap command set may be generated that includes a swap indicator at the right index of each swap, such that the swap can be performed for the index at which the swap indicator is located and the previous index (e.g., index "X" and index "X-1").

[0154] Figure 6 A second alternative algorithm swap command set 604 is also included. The algorithm swap command set 604 utilizes knowledge of the even-odd transposition sorting algorithm to reduce the amount of data that needs to be stored. Specifically, in this regard, the algorithm swap command set 604 stores a swap indicator at a corresponding location based on whether the row represents an even index phase or an odd index phase. Figure 5In the exemplary context depicted, for example, the first step 502B is performed for even indices, so that the first row of the algorithm exchange command set 604 corresponds to an even index in the set of position indices being processed. Thus, index 0 of the first row of the algorithm exchange command set 604 corresponds to the first even index in the set of position indices being processed (e.g., index 0), wherein index 1 of the first row of the algorithm exchange command set 604 corresponds to the second even index in the set of position indices being processed (e.g., index 2), wherein index 2 of the first row of the algorithm exchange command set 604 corresponds to the third even index in the set of position indices being processed (e.g., index 4), and wherein index 3 of the first row of the algorithm exchange command set 604 corresponds to the fourth even index in the set of position indices being processed (e.g., index 6). Subsequently, the second step 502C is performed for odd indices, so that the second row of the algorithm exchange command set 604 corresponds to an odd index in the set of position indices being processed. Thus, the index 0 of the second row of the algorithm exchange command set 604 corresponds to the first odd index (e.g., index 1) in the position index set being processed, the index 1 of the second row of the algorithm exchange command set 604 corresponds to the second odd index (e.g., index 3) in the position index set being processed, and so on. This process can continue when executing subsequent steps, wherein the stored exchange indicator alternates between representing an exchange for an even index and representing an exchange for an odd index. Therefore, based at least on a determined and / or predetermined starting value (e.g., the first step performed for, for example, an even index), the value of the row of the algorithm exchange command set 604 being processed can be used to determine whether the row corresponds to an exchange indicator for an even index or to an exchange indicator for an odd index. In this regard, the data size of the algorithm exchange command set 604 can be reduced.

[0155] Exemplary Data Flow and Process of the Disclosure

[0156] Having described the exemplary systems, devices and computing environments associated with the embodiments of the present disclosure, the data flows and corresponding flow charts including the various operations performed by the above-mentioned devices and / or systems will now be discussed. It should be understood that each flow chart in the flow chart depicts an exemplary computer-implemented process that can be performed by one or more of the above-mentioned devices, systems and / or equipment, for example, using one or more of the components described herein to perform. The frames of each process can be arranged in any of a variety of ways, as described and described herein. In some such embodiments, one or more frames of a first process may occur between one or more frames of a second process, or otherwise operate as a subprocess of a second process. Additionally or alternatively, the process may include some or all of the operations described and / or depicted, including one or more optional frames in some embodiments. With regard to the following flow charts, in some or all of the embodiments of the present disclosure, one or more frames in the frame depicted may be optional. Optional frames are shown with dotted lines (or "dash-dot lines"). Similarly, it should be understood that one or more of the operations of each flow diagram may be combined, replaced, and / or otherwise varied as described herein.

[0157] Figure 7A An exemplary data flow diagram of an exemplary process for performing instruction compilation for at least one time slice in a one-dimensional quantum computing environment according to at least one exemplary embodiment of the present disclosure is shown. Specifically, as shown in the figure, Figure 7A The operational data flow between various devices and / or systems is depicted, specifically, the controller 30, the computing entity 10, and the remaining components of the quantum computer 102 (e.g., the manipulation source 60 and / or the voltage source 50). It should be understood that the operation can be described from the perspective of any of the depicted devices and / or systems.

[0158] Figure 7B An exemplary process of compiling instructions for at least one time slice in a one-dimensional quantum computing environment according to at least one exemplary embodiment of the present disclosure is shown (eg, Figure 7A In this regard, the exemplary operations are depicted and described from the perspective of the controller 30. In this regard, the controller 30 may be implemented by any number of computing devices (e.g., as described herein with respect to Figure 2 The apparatus 200 is embodied in the apparatus 200 depicted and described herein. The apparatus 200 may be configured to communicate with any number of other devices and / or systems (e.g., computing entity 10 and / or other components of quantum computer 102). In this regard, each operation will be described from the perspective of controller 30 embodied by the specifically configured apparatus 200.

[0159] At optional operation 702, apparatus 200 receives a quantum program comprising at least one set of qubit pairings associated with a set of qubits. For example, apparatus 200 includes means for receiving a quantum program, such as qubit instruction processing module 210, input / output module 206, communication module 208, processor 202, or the like, or a combination thereof, comprising at least one set of qubit pairings associated with a set of qubits. In some such embodiments, apparatus 200 receives the qubit program from a computational entity, such as computational entity 10. In this regard, computational entity 10 may be operable to input and / or generate the quantum program, for example, using one or more programming languages ​​configured for compilation and / or implementation via a quantum computer. In this regard, the quantum program may comprise and / or be embodied by one or more sets of qubit pairings to be executed via the quantum computer, for example, at various time slices. In some such embodiments, the qubit pairing sets correspond to individual qubit pairs to be used as inputs to one or more logic gates at a particular time slice. In this regard, all qubits in a qubit set (e.g., having a predetermined number of qubits held by a quantum computer) may be associated with a qubit pair in a qubit pairing set at each time slice to associate the two qubits so as to position the two qubits at adjacent locations within the quantum computer, for example, by moving the paired qubits to adjacent regions within an ion trap of the quantum computer.

[0160] At operation 704, apparatus 200 identifies an initial set of qubit positions associated with the set of qubits. For example, apparatus 200 includes means for identifying an initial set of qubit positions associated with the set of qubits and initializing the current set of positions with the initial set of qubit positions, such as qubit instruction processing module 210, input / output module 206, communication module 208, processor 202, or the like, or a combination thereof. In some embodiments, apparatus 200 identifies an initial set of qubit positions that has qubit pairings that are adjacent to each other for a first time slice, such that no qubit repositioning is required for the first time slice. Furthermore, the initial set of qubit positions may be selected to minimize the number of parallel swap commands required to reposition qubits for a second time slice. In other embodiments, the initial set of qubit positions may be identified based on one or more previously performed qubit repositionings. For example, in at least one context, the initial set of qubit positions corresponds to a target set of qubit positions for a previous time slice. In this regard, the current set of positions may be represented as a well-defined order of qubits that are currently positioned based on initialization of the device and / or based on repositioning of the qubits during one or more previous time slices.

[0161] At operation 706, apparatus 200 identifies a set of target qubit positions associated with the set of qubits. For example, apparatus 200 includes means for identifying a set of target qubit positions associated with the set of qubits, such as qubit instruction processing module 210, input / output module 206, communication module 208, processor 202, or the like, or a combination thereof. In some embodiments, the set of target qubit positions corresponds to a target position index for each qubit in the set of qubits during a particular time slice. In this regard, the qubits may each need to be relocated from an initial position index associated with the qubit in the initial qubit position set to a target position index associated with the qubit in the target qubit position set to enable execution of one or more logic gates based on a qubit pair (e.g., a qubit pair in the qubit pairing set for the time slice). In this regard, the set of target qubit positions may include adjacent target position indices for qubits to be input to a single logic gate. In some embodiments, the set of target qubit positions is based on the initial qubit position set for the current time slice. In this regard, apparatus 200 processes an initial set of qubit positions to optimize a target set of qubit positions in order to reduce the number of required parallel exchange commands. One exemplary context for such optimization is using near-midpoint open-index pairing of qubit pairs as described herein. In other embodiments, the target set of qubit positions is generated a priori relative to the initial set of qubit positions.

[0162] In some embodiments, a data vector is initialized based on an index into a set of target qubit positions. In this regard, the data vector can be manipulated as each step of the even-odd transposition order is performed, such that an intermediate index can be determined at each step and reflected as an update in the data vector. In some embodiments, the set of target qubit positions embodies the data vector.

[0163] At operation 708, apparatus 200 generates an algorithmic swap command set by performing an even-odd permutation sort based on at least the set of target qubit positions. For example, apparatus 200 includes means for generating the algorithmic swap command set by performing an even-odd permutation sort based on at least the set of target qubit positions, such as qubit instruction processing module 210, input / output module 206, communication module 208, processor 202, or the like, or a combination thereof. For example, the even-odd permutation sort may be performed to generate swap indicators for repositioning qubits from positions indicated by the initial set of qubit positions to positions indicated by the set of target qubit positions. For example, each swap determined in the even-odd permutation sort may result in a swap indicator being generated for inclusion in the algorithmic swap command set. Thus, the algorithmic swap command set may be processed to generate corresponding instructions for repositioning qubits in the set of qubits for executing corresponding logic gates, such as logic gates embodying a quantum program and represented in the set of qubit pairs for the current time slice.

[0164] In this regard, in some embodiments, an even-odd transposition ordering manipulates the data vector to reposition it from the target set of qubit positions to which it was initialized until the data vector is correctly ordered. As the transposition operations are performed and labeled as described herein, the data vector may embody each intermediate step. In some such embodiments, the data vector may be processed as described herein at each transposition for optimization, look-ahead determinations, and the like. It will be appreciated that once the data vector is correctly ordered from the target set of qubit positions, the apparatus may determine that processing for the current time slice is complete.

[0165] In some embodiments, a loop may be formed for multiple time slices based on operations 704, 706, and 708, as described herein. In this regard, the generated swap commands indicated by executing the even-odd transposition ordering for a particular time slice may represent a subset of algorithmic swap commands for that particular time slice, where the full set of algorithmic swap commands represents swap operations for all time slices of the quantum program. In this regard, for subsequent iterations, identifying an initial set of qubit positions for a subsequent time slice may include updating a current set of positions based on the swap operations represented in the subset of algorithmic swap commands for the previous time slice. Thus, the qubits are indicated to start from the positions to which they were relocated during the previous time slice. Subsequently, a set of target qubit positions for a subsequent time slice may be determined based on the initial set of qubit positions in some embodiments and, in other embodiments, using any of a variety of target position assignment algorithms as described herein. Thus, each iteration of the even-odd transposition ordering may be used to generate a subset of algorithmic swap commands based on at least the set of target qubit positions for each time slice. At the completion of each iteration of the even-odd transposition ordering, the resulting algorithmic exchange command subset for the time slice can be added to a data object embodying the algorithmic exchange command set for the full quantum circuit. Thus, upon completion of processing for all time slices (e.g., {0:(K-1)} time slices, where K is the total number of time slices), each algorithmic exchange command subset corresponding to each time slice will have been added to the full algorithmic exchange command set, such that the full algorithmic exchange command set embodies all exchange operations required for the quantum circuit.

[0166] At optional operation 710, apparatus 200 generates a qubit manipulation instruction set based on at least the algorithmic exchange command set. For example, apparatus 200 includes means for generating the qubit manipulation instruction set based on at least the algorithmic exchange command set, such as qubit instruction processing module 210, input / output module 206, communication module 208, processor 202, or the like, or a combination thereof. In this regard, the qubit manipulation instruction set may correspond to a series of actions that can be compiled for execution via one or more components of a quantum computer to perform an exchange corresponding to an exchange indicator of the algorithmic exchange command set. For example, the qubit manipulation instruction set may include one or more qubit swap instructions, qubit split instructions, qubit merge instructions, qubit shift instructions, and / or any combination thereof. It should be understood that in some embodiments, a subset of instructions may additionally or alternatively be included in the qubit manipulation instruction set.

[0167] At optional operation 712, the apparatus generates a hardware instruction set based on at least the qubit manipulation instruction set. For example, apparatus 200 includes means for generating the hardware instruction set based on at least the qubit manipulation instruction set, such as qubit instruction processing module 210, input / output module 206, communication module 208, processor 202, or the like, or a combination thereof. In this regard, the hardware instruction set may correspond to one or more physical manipulations of components of a quantum computer (e.g., quantum computer 102) to implement the actions represented by the qubit manipulation instruction set. For example, the hardware instruction set may represent one or more voltages to be applied to various electrodes for affecting the ion trap and / or the qubits stored in its region. It should be understood that the hardware instruction set may include predetermined voltages to be applied corresponding to each of a qubit swap instruction, a qubit split instruction, a qubit merge instruction, and / or a qubit shift instruction.

[0168] At optional operation 714, apparatus 200 executes the hardware instruction set using qubit manipulation hardware, and includes means for executing the hardware instruction set using the qubit manipulation hardware, such as qubit instruction processing module 210, input / output module 206, communication module 208, processor 202, or the like, or a combination thereof. In some such embodiments, the qubit manipulation hardware may include any number of hardware components configured to implement the repositioning of qubits in a quantum computer, such as one or more electrodes. For example, in some embodiments, the qubit manipulation hardware includes a voltage source 50 and electrodes of an ion trap. By executing the hardware instruction set, apparatus 200 is configured to reposition the set of qubits to positions represented in the set of target qubit positions by physically performing the swaps represented in the algorithmic swap command set via any number of hardware-level operations.

[0169] Figure 8Additional operations are shown for an exemplary process for compiling instructions for at least one time slice in a one-dimensional quantum computing environment, specifically for generating an algorithmic exchange command set by performing an even-odd permutation ordering based on at least an initial set of qubit positions and a target set of qubit positions, according to at least one exemplary embodiment of the present disclosure. In this regard, the exemplary method shown in the figure can be performed by one or more specially configured systems such as, for example, a controller 30 embodied by a specially configured device 200. In this regard, in some such embodiments, the device 200 is specially configured by computer program instructions stored therein, for example, in a memory 204 and / or another component depicted and / or described, and / or otherwise accessible to the device 200, for performing the depicted and described operations. In some embodiments, the specially configured device includes and / or otherwise communicates with one or more other devices, systems, equipment, etc. to perform one or more of the depicted and described operations. For example, the device 200 may include one or more components and / or computing entities of a quantum computer and / or communicate with one or more components and / or computing entities of a quantum computer to facilitate Figure 8 One or more of the operations of the process depicted in .

[0170] The illustrated process begins at operation 802. In some embodiments, the process begins after one or more of the operations depicted and / or described with respect to a process in other processes described herein. For example, in some of the embodiments described, the process begins after performing operation 706. In this regard, the process may replace or supplement one or more of the blocks depicted and / or described with respect to a process in other processes described herein. For example, in some of the embodiments depicted, the process begins after performing operation 706. Figure 8 The illustrated process replaces, supplements, and / or otherwise substitutes the operations depicted and described with respect to operation 708. Additionally or alternatively, as depicted, Figure 8 Upon completion of the depicted process and / or one or more operations associated therewith, flow may return to one or more operations of another process, such as to optional operation 710 as depicted.

[0171] At operation 802, the apparatus 200 stores, in a data object representing an algorithmic swap command set, a first swap indicator for each even-numbered swap determined according to the even-odd transposition ordering, and stores, in the data object representing the algorithmic swap command set, a second swap indicator for each odd-numbered swap determined according to the even-odd transposition ordering. For example, the apparatus 200 includes means, such as the qubit instruction processing module 210, the input / output module 206, the communication module 208, the processor 202, or the like, or a combination thereof, for performing the following operations: storing, in the data object representing the algorithmic swap command set, a first swap indicator for each even-numbered swap determined according to the even-odd transposition ordering, and storing, in the data object representing the algorithmic swap command set, a second swap indicator for each odd-numbered swap determined according to the even-odd transposition ordering. In this regard, the data object stores indicators for all swaps performed as part of the even-odd transposition ordering. By storing a first swap indicator for even swaps and a second swap indicator for odd swaps, the generated data object can be parsed to distinguish between even and odd phases without storing additional data and / or without prior knowledge of even-odd transposition ordering.

[0172] Figure 9 Additional operations of an exemplary process for compiling instructions for at least one time slice in a one-dimensional quantum computing environment, specifically for optimizing the timing of gating operations of qubits positioned adjacent to each other before even-odd transposition ordering is completed, are shown in accordance with at least one exemplary embodiment of the present disclosure. In this regard, the exemplary method shown in the figure may be performed by one or more specially configured systems such as, for example, a controller 30 embodied by a specially configured device 200. In this regard, in some such embodiments, the device 200 is specially configured by computer program instructions stored therein, for example, in a memory 204 and / or another component depicted and / or described and / or otherwise accessible to the device 200, for performing the depicted and described operations. In some embodiments, the specially configured device includes and / or otherwise communicates with one or more other devices, systems, equipment, etc., to perform one or more of the depicted and described operations. For example, the device 200 may include one or more components and / or computing entities of a quantum computer and / or communicate with one or more components and / or computing entities of a quantum computer to facilitate Figure 9 One or more of the operations of the process depicted in .

[0173] The process shown begins at operation 902. In some embodiments, the process begins after one or more of the blocks depicted and / or described with respect to one of the other processes described herein. For example, in some of the embodiments described, the process begins after performing operation 706. In this regard, the process may replace or supplement one or more of the blocks depicted and / or described with respect to one of the other processes described herein. For example, in some of the embodiments depicted, the process begins after performing operation 706. Figure 9 The illustrated process replaces, supplements, and / or otherwise substitutes the operations depicted and described with respect to operation 708. Additionally or alternatively, as depicted, Figure 9 Upon completion of the depicted process and / or one or more operations associated therewith, flow may return to one or more operations of another process, such as to optional operation 710 as depicted.

[0174] At operation 902, while performing an even-odd transposition sort, apparatus 200 determines that a second qubit pair for gating at a first time slice is associated with a first position index and a second position index, the first position index and the second position index representing adjacent position indexes. For example, apparatus 200 includes means, such as qubit instruction processing module 210, input / output module 206, communication module 208, processor 202, or the like, or a combination thereof, for performing the following operations: while performing an even-odd transposition sort, determining that the second qubit pair for gating at a current time slice is located at the adjacent index before the even-odd transposition sort is completed (e.g., before the qubits are placed in a final desired order). In this regard, the second qubit pair may represent a first qubit in a set of qubits and a second qubit in the set of qubits, with these two qubits, as well as other qubit pairs (and / or individual qubits) for gating, similarly serving as inputs to a logic gate to be executed at a first time slice (e.g., the current time slice). In this regard, the first position index and the second position index may indicate that the qubits of the second qubit pair will be adjacent during an intermediate stage of repositioning from the initial set of qubit positions to the target set of qubit positions. It should be understood that such intermediate determinations may be identified for any number of qubit pairs, such that execution of logic gates using qubit pairs that are adjacent before they reach their target qubit position indexes may be identified for any number of qubit pairs, such that instructions may be generated to execute those logic gates in advance (e.g., before the even-odd transposition ordering is complete).

[0175] At operation 904, apparatus 200 stores at least one command to perform a logic operation based on at least the second qubit pair. For example, apparatus 200 includes means for storing at least one command to perform a logic operation based on at least the second qubit pair, such as qubit instruction processing module 210, input / output module 206, communication module 208, processor 202, or the like, or a combination thereof. In this regard, apparatus 200 may store a first command to perform a logic operation. In at least one exemplary context, apparatus 200 performs the logic operation by executing a logic gate that utilizes qubits of the second qubit pair as inputs. Additionally or alternatively, apparatus 200 may store the same command. In this regard, by performing the logic operation in advance, apparatus 200 may not be required to re-perform the logic operation upon completion of the even-odd transposition sorting, and / or may not be required to continue relocating qubits of the second qubit pair to adjacent locations for such purposes during the current time slice. Thus, such early execution may save execution power, processing power, and / or both, which may be further improved based on whether this situation is determined for multiple qubit pairs.

[0176] At optional operation 906, apparatus 200 includes means for determining a first updated target qubit position index for a first qubit of a second qubit pair, such as qubit instruction processing module 210, input / output module 206, communication module 208, processor 202, and / or a combination thereof. In some such embodiments, the first updated target qubit position index for a first qubit is determined based on a third qubit pair, the third qubit pair including at least the first qubit for gating at a second time slice. In this regard, because the logic operation may be performed when the second qubit pair becomes adjacent before the even-odd transposition ordering for the current time slice terminates, the target qubit position index for the first qubit of the second qubit pair may be updated. For example, because the qubit no longer needs to be positioned adjacent to the second qubit of the second qubit pair at the end of the current time slice, the target qubit position index associated with the first qubit of the second qubit pair may be updated (e.g., to the first updated target qubit position index) such that the qubit is closer to and / or otherwise adjacent to another qubit for gating during execution of the next time slice. It should be understood that apparatus 200 can similarly process data associated with the second time slice to determine a qubit pair including the first qubit at the second time slice, such that the first qubit can be positioned closer to another qubit to be gated in the second time slice. In some embodiments, apparatus 200 can regenerate the entire set of target qubit positions for all qubits to further reduce the number of exchanges required for the current time slice and future time slices (e.g., subsequent time slices).

[0177] At optional operation 908, apparatus 200 includes means for determining a second updated target qubit position index for a second qubit of a second qubit pair, such as qubit instruction processing module 210, input / output module 206, communication module 208, processor 202, and / or a combination thereof. In some such embodiments, the second updated target qubit position index for the second qubit is determined based on a fourth qubit pair, the fourth qubit pair including at least a second qubit for gating at a second time slice. It should be understood that, in some contexts, the fourth qubit pair may be the same as the third qubit pair. It should be understood that the second updated target qubit position index associated with the second qubit of the second qubit pair may be determined in a manner similar to that described with respect to the first qubit of the second qubit pair in operation 906. For example, the target qubit position index for the second qubit of the second qubit pair may be updated because a logical operation (e.g., a logic gate) utilizing the second qubit pair may be performed when the qubit pair becomes adjacent before the even-odd transposition ordering for the current time slice terminates. Similarly, the target qubit position index associated with the second qubit of the second qubit pair may be updated (e.g., to a second updated target qubit position index) such that the second qubit is closer to and / or otherwise adjacent to the other qubit for gating during execution of the next time slice. It should be understood that apparatus 200 may similarly process data associated with the second time slice to determine a qubit pair including the second qubit at the second time slice such that the second qubit can be positioned closer to the other qubit to be gated in the second time slice.

[0178] It should be understood that relative to Figure 9 The described process can be repeated for any number of qubit pairs for a given time slice. For example, in some embodiments, only one qubit pair becomes adjacent before the even-odd transposition sorting terminates. In other embodiments, no qubit pairs may become adjacent before the even-odd transposition sorting terminates. In other embodiments, all qubit pairs may become adjacent before the even-odd transposition sorting terminates. It will also be understood that in situations where all qubit pairs may be executed before the even-odd transposition sorting terminates (e.g., due to adjacent positioning between two qubits of a qubit pair during an intermediate step of the even-odd transposition sorting), the apparatus 200 can be configured to terminate the even-odd transposition sorting and / or begin execution processing earlier relative to a subsequent time slice.

[0179] Figure 10Additional operations are shown for an exemplary process for compiling instructions for at least one time slice in a one-dimensional quantum computing environment, specifically for generating a second algorithmic exchange command set by performing a second even-odd transposition ordering, in accordance with at least one exemplary embodiment of the present disclosure. In this regard, the exemplary method shown in the figure may be performed by one or more specially configured systems such as, for example, a controller 30 embodied by a specially configured device 200. In this regard, in some such embodiments, the device 200 is specially configured by computer program instructions stored therein, for example, in a memory 204 and / or another component depicted and / or described and / or otherwise accessible to the device 200, for performing the depicted and described operations. In some embodiments, the specially configured device includes and / or otherwise communicates with one or more other devices, systems, equipment, etc., to perform one or more of the depicted and described operations. For example, the device 200 may include one or more components and / or computing entities of a quantum computer and / or communicate with one or more components and / or computing entities of a quantum computer to facilitate Figure 10 One or more of the operations of the process depicted in .

[0180] The process shown begins at operation 1002. In some embodiments, the process begins after one or more of the operations depicted and / or described with respect to one of the other processes described herein. For example, in some of the embodiments described, the process begins after performing operation 714. In this regard, the process may replace or supplement one or more of the operations depicted and / or described with respect to one of the other processes described herein. For example, in some of the embodiments depicted, the process begins after performing operation 714. Figure 10 The illustrated process replaces, supplements, and / or otherwise substitutes the operations depicted and described with respect to FIG7. Additionally or alternatively, as depicted, upon completion of Figure 10 When the process and / or one or more operations associated therewith are described, the process may end or return to one or more operations of another process. Figure 10 The depicted process occurs after operation 708 is performed, and the flow is in the Figure 10 The depicted process returns to optional operation 710 upon completion.

[0181] At operation 1002, apparatus 200 identifies a second set of target qubit positions associated with a set of qubits at a second time slice. For example, apparatus 200 includes means for identifying the second set of target qubit positions associated with the set of qubits at the second time slice, such as qubit instruction processing module 210, input / output module 206, communication module 208, processor 202, or the like, or a combination thereof. In some embodiments, the second set of target qubit positions is identified based on a current set of qubit positions that is updated from a set of target qubit positions for a previous time slice. In other words, when a time slice advances to a subsequent time slice, a position index for a qubit can be determined based on the position where such qubit ends up and is located from the previous time slice. In a manner similar to the first time slice, the second time slice can be associated with the execution of one or more logic gates used to implement a quantum program. Such logic gates can each utilize a qubit pair as input, for example, where all qubit pairs for a time slice are represented by the second set of qubit pairings. The second set of target qubit positions can be based on such qubit pairs. For example, in some such embodiments, the second set of target qubit positions represents a determined set of target position indices, where each qubit in the set of qubits is assigned a target position index that is adjacent to the second target position index of the second qubit with which the qubit is paired. Thus, when repositioned based on the second set of target qubit positions, each qubit pair can be located at adjacent locations for input to a single logic gate. It should be understood that in some embodiments, one or more qubits are not associated with a pair and can be used as a single input to a logic operation at one or more time slices.

[0182] At operation 1004, apparatus 200 generates a second set of algorithmic exchange commands by, for example, performing a second even-odd transposition ordering based on at least a second set of target qubit positions. In this regard, the second even-odd transposition ordering may reposition the qubits to their target qubit position indexes as indicated for performing the logic operation during the second time slice. For example, apparatus 200 includes means for generating the second set of algorithmic exchange commands by performing the second even-odd transposition ordering based on at least a second set of initial qubit positions and a second set of target qubit positions, such as qubit instruction processing module 210, input / output module 206, communication module 208, processor 202, or the like, or a combination thereof. In some such embodiments, the second set of initial qubit positions is embodied by the first set of target qubit positions for the first time slice and / or a previous (e.g., immediately preceding) time slice. In this regard, the second set of algorithmic exchange commands may include a swap indicator for repositioning the set of qubits from the second set of initial qubit positions to the second set of target qubit positions. For example, the second algorithmic swap command set may represent swap indicators for relocating qubits from a region associated with the first set of target qubit positions (e.g., during a first time slice) to an adjacent region so that qubit pairs can be input to at least one corresponding logic gate.

[0183] In some embodiments, apparatus 200 is configured to perform one or more additional actions based on at least the second algorithmic exchange command set. For example, in some embodiments, apparatus 200 includes means for generating a second set of qubit manipulation instructions based on at least the second algorithmic exchange command set, such as qubit instruction processing module 210, input / output module 206, communication module 208, processor 202, or the like, or a combination thereof. Apparatus 200 may perform such actions in a manner similar to that described above with respect to optional operation 710. In this regard, the second set of qubit manipulation instructions may include one or more qubit swap instructions, qubit split instructions, qubit merge instructions, qubit shift instructions, or the like, or any combination thereof, which may be compiled for execution to reposition the set of qubits according to the second algorithmic exchange command set. Additionally or alternatively, in some embodiments, apparatus 200 includes means for generating a second set of hardware instructions based on at least the second set of qubit manipulation instructions, such as qubit instruction processing module 210, input / output module 206, communication module 208, processor 202, or the like, or a combination thereof. The apparatus 200 may perform such actions in a manner similar to that described above with respect to optional operation 712. In this regard, the second set of hardware instructions may represent one or more voltages to be applied to qubit manipulation hardware (e.g., various electrodes) to effectuate the repositioning of the set of qubits within the ion trap. Additionally or alternatively, in some embodiments, the apparatus 200 includes means for executing the second set of hardware instructions using the qubit manipulation hardware, such as the qubit instruction processing module 210, the input / output module 206, the communication module 208, the processor 202, or the like, or a combination thereof. The apparatus 200 may perform such actions in a manner similar to that described above with respect to operation 714. In this regard, by executing the second set of hardware instructions, the apparatus 200 may reposition the set of qubits to positions corresponding to the second set of target qubit positions by performing the swaps represented in the second set of algorithmic swap commands.

[0184] Figure 11Additional operations are shown for an exemplary process for compiling instructions for at least one time slice in a one-dimensional quantum computing environment, specifically for identifying a target set of qubit positions associated with a set of qubits, in accordance with at least one exemplary embodiment of the present disclosure. In this regard, the exemplary method as shown may be performed by one or more specially configured systems such as, for example, a controller 30 embodied by a specially configured apparatus 200. In this regard, in some such embodiments, the apparatus 200 is specially configured by computer program instructions stored therein, for example, in a memory 204 and / or another component depicted and / or described and / or otherwise accessible to the apparatus 200, for performing the depicted and described operations. In some embodiments, the specially configured apparatus includes and / or otherwise communicates with one or more other apparatuses, systems, devices, etc., to perform one or more of the depicted and described operations. For example, the apparatus 200 may include one or more components and / or computing entities of a quantum computer and / or communicate with one or more components and / or computing entities of a quantum computer to facilitate Figure 11 One or more of the operations of the process depicted in .

[0185] Relative to Figure 11 The depicted and described process provides an optimization for assigning target qubit position indices in a manner that reduces or minimizes the number of parallel exchange commands required to reposition qubits adjacent to each other as needed for gating. It should be understood that this particular process defines a specific exemplary target qubit position index assignment algorithm. In other embodiments, one or more alternative and / or additional target qubit position index assignment algorithms may be implemented. Indeed, it should be understood that such algorithms may vary with respect to complexity level without departing from the scope and spirit of the present disclosure.

[0186] The process shown begins at operation 1102. In some embodiments, the process begins after one or more of the operations depicted and / or described with respect to one of the other processes described herein. For example, in some of the embodiments described, the process begins after performing operation 704. In this regard, the process may replace or supplement one or more of the operations depicted and / or described with respect to one of the other processes described herein. For example, in some of the embodiments depicted, the process begins after performing operation 704. Figure 11 The illustrated process replaces, supplements, and / or otherwise substitutes the operations depicted and described with respect to FIG. 7 . Additionally or alternatively, as depicted, in Figure 11 Upon completion of the depicted process and / or one or more operations associated therewith, flow may end or return to one or more operations of another process, such as returning to optional operation 708 as depicted.

[0187] At operation 1102, apparatus 200 determines a near-midpoint open index pair for each qubit pair in the at least one qubit pair used for gating at a first time slice and starting with a qubit pair having a maximum position distance based on at least a first initial position index for a first qubit of the qubit pair and a second initial position index for a second qubit of the qubit pair. For example, apparatus 200 includes means, such as qubit instruction processing module 210, input / output module 206, communication module 208, processor 202, or the like, or a combination thereof, for determining a near-midpoint open index pair for each qubit pair in the at least one qubit pair used for gating at a first time slice and starting with a qubit pair having a maximum position distance based on at least a first initial position index for a first qubit of the qubit pair and a second initial position index for a second qubit of the qubit pair. In at least some such embodiments, the near-midpoint open index pair for a particular qubit pair is based on at least the first initial position index and the second initial position index for the qubits of the qubit pair. In some such embodiments, apparatus 200 may be configured to determine the position distance of the qubits of each qubit pair at a particular time slice. In this regard, the position distance of each qubit pair may be determined based on the difference between a first initial position index for a first qubit of the qubit pair and a second qubit of the qubit pair, such as represented in the identified set of initial qubit positions for the time slice. For example, if the first qubit of the qubit pair is associated with a first initial position index having a value of "1," and the second qubit of the qubit pair is associated with a second initial position index having a value of "7," the position distance may be determined to be "6" (e.g., 7 minus 1). Similarly, if the second qubit pair includes a first qubit associated with a first initial position index having a value of "2," and a second qubit associated with a second initial position index having a value of "4," the position distance may be determined to be "2" (e.g., 4 minus 2).

[0188] In some embodiments, apparatus 200 is configured to determine the positional distances of all qubit pairs at a particular time slice, e.g., as indicated by a set of qubit pairings. Thus, the apparatus may subsequently assign target position indices to qubit pairs in descending order, such that at each step, the qubit pair associated with the largest positional distance is assigned. If no qubit pair has the largest positional distance (e.g., there is a peer relationship between one or more qubit pairs with equal positional distances), apparatus 200 may continue to assign positions to qubit pairs sequentially, randomly, and / or using any other selection algorithm. See, e.g., Figure 3As shown, qubit pairs in qubit pairing set 306, for example, qubit pair 306A is associated with a position distance having a value of "7" (e.g., 7 minus 0), qubit pair 306B is associated with a position distance having a value of "1" (e.g., 2 minus 1), and so are each of qubit pair 306C (e.g., 4 minus 3 equals 1) and qubit pair 306D (6 minus 5 equals 1). Thus, device 200 can determine that qubit pair 306A is associated with the largest position distance and, therefore, assign a target qubit position index to qubit pair 306A first. Device 200 can then determine that each of the remaining qubit pairs 306B through 306D is associated with the same position distance and, therefore, assign target position indices in any order (e.g., in descending order and / or ascending order based on the initial qubit position index, etc.).

[0189] In some such embodiments, apparatus 200 is configured to determine a near midpoint open index pair for each qubit pair associated with a given time slice. For a given qubit pair, the near midpoint open index pair may represent a first target position index for a first qubit of the qubit pair, and a second target position index for a second target position index of the qubit pair. At the previous step, the target position index for each qubit may not be assigned to another qubit (e.g., "open" for assignment). In this regard, apparatus 200 may determine the midpoint between the initial position indices for the qubit pair, and determine the nearest neighbor target position index for the set of target qubit positions that remain unassigned. Return to the Figure 3 In the illustrated exemplary qubit pairing set 306, starting with qubit pair 306A, apparatus 200 may determine indices with values ​​of "3" and "4" as possible midpoint indices. In some embodiments, apparatus 200 may shift each qubit pair to be indexed so that near-midpoint open index pairs begin at even-numbered indices, e.g., to enable the maximum number of qubit pairs to be located when necessary. In some such embodiments, apparatus 200 is configured to attempt to shift indices to lower indices first, and then determine whether such lower indices remain unassigned (e.g., by searching for such indices in the set of target qubit positions) before attempting to shift indices to immediately higher indices. In this regard, apparatus 200 may determine a near-midpoint open index pair with values ​​of "2" and "3," e.g., as depicted. In other embodiments, apparatus 200 is configured to attempt to shift indices to higher indices first, and then determine whether such higher indices remain unassigned before attempting to shift indices to immediately lower indices. In some such implementations, device 200 may determine a near-midpoint open index pair having values ​​"4" and "5."

[0190] At operation 1104, apparatus 200 determines a first target position index and a second target position index based on at least the near-midpoint open index pair for allocation within the set of target qubit positions. For example, apparatus 200 includes means, such as qubit instruction processing module 210, input / output module 206, communication module 208, processor 202, or the like, or a combination thereof, for determining the first target position index and the second target position index based on at least the near-midpoint open index pair for allocation within the set of target qubit positions. For example, apparatus 200 may associate a first target position index of the near-midpoint open index pair with a first qubit of the qubit pair within the set of target qubit positions. Additionally, apparatus 200 may associate a second target position index of the near-midpoint open index pair with a second qubit of the qubit pair within the set of target qubit positions. By assigning such indices within the set of target qubit positions, apparatus 200 may perform subsequent checks on the set of target qubit positions to prevent these indices from being assigned to another qubit at a future step.

[0191] When assigning target position index "2" and target position index "3," such indices may not subsequently be assigned to another qubit. Thus, in some embodiments, apparatus 200 may continue to perform operations 1102 and / or 1104 for any number of qubit pairs. For example, apparatus 200 may continue to determine another near-midpoint open index pair for the next qubit pair in the set of qubit pairings. In some embodiments, when all remaining qubit pairs have the same position distance, the apparatus next selects qubit pair 306B, and in some such embodiments, apparatus 200 may continue in ascending order for the qubits in the set of qubit pairs.

[0192] Figure 12 For example, based on Figure 3 The depicted and described set of qubit pairings depicts, for example, an exemplary visualization of a target qubit position set 404 for identifying a qubit set 304 in accordance with at least one exemplary embodiment of the present disclosure. Figure 11 Each iteration of the depicted process may result in another assignment of target position indices in target qubit position set 404, as relative to Figure 12 As depicted, qubit pair 306B includes qubit 1 and qubit 2 associated with initial position indices "1" and "2" that are already adjacent. However, target position index "2" has already been assigned as described. Therefore, device 200 may attempt to shift the index to a lower and / or higher index while minimizing the required distance that the qubits need to move. In this regard, device 200 may determine that the lower indices "0" and "1" remain unassigned, and therefore may continue to assign such indices as target position indices for qubit pair 306B.

[0193] Similarly, for qubit pair 306C, the qubits of the qubit pair are assigned initial qubit position indices having values ​​of "3" and "4," and apparatus 200 may determine that such qubits are already adjacent (e.g., having a position distance of "1"). Apparatus 200 may attempt to position the qubit at a near-midpoint open index pair starting from the nearest unassigned even-number index (e.g., at "2" and "3"). However, apparatus 200 may subsequently determine that such indices are already assigned, for example, by searching for such indices in the set of target qubit positions and identifying that such indices are already associated with qubits 0 and 7 (e.g., qubit pair 306A). Apparatus 200 may then attempt to shift the near-midpoint open index pair to a higher index (e.g., having values ​​of "4" and "5") and determine that such indices remain unassigned. Thus, apparatus 200 may then assign a first target position index having a value of "4" to qubit 3 and a second target qubit position index having a value of "5" to qubit 4 in the target qubit position set based at least on the near-midpoint open index pair and the assigned indices in the target qubit position set. Similar actions may be performed for qubit pair 306D relative to the already assigned indices "4" and "5" (as lower indices than the initial position indices for qubits 5 and 6). Thus, apparatus 200 may then assign a first target position index having a value of "6" to qubit 5 and a second target qubit position index having a value of "7" to qubit 6 in the target qubit position set based at least on the near-midpoint open index pair. After completing the assignment of target position indices within the target qubit position set, apparatus 200 may continue processing the target qubit position set as described.

[0194] Exemplary Alternative Process for Target Qubit Location Assignment

[0195] Some embodiments implement one or more alternative processes for assigning target positions, such as those embodied in a set of target qubit positions. In this regard, in some embodiments, near-midpoint open index pairs may be utilized, in whole or in part. In other embodiments, one or more alternative algorithms are implemented to identify and / or otherwise generate a set of target qubit positions. Non-limiting examples of such alternative embodiments are provided with respect to the remaining Figures 13 to 25 In some embodiments, apparatus 200 is configured to perform the various operations of the processes described herein with respect to the remaining figures of this type.

[0196] In some embodiments, target allocation is performed based on two equally sized subsets of an equal dual partition of a complete set of positions. In this regard, the complete set may include elements of a first subset and elements of a second subset, wherein the number of elements in each subset is equal, the two subsets are disjoint, and the union of the two subsets is the complete set. Elements of a given starting position pairing set (e.g., representing elements to be gated at a particular time slice) may be paired from each dual partition subset such that the first element of a given starting position pair from the starting position pairing set is present in the first dual partition subset, and the second element of the given starting position pair from the starting position pairing set is present in the second dual partition subset. For example, the first position may be present in the first dual partition subset, and the second position may be present in the second dual partition subset. One such example of equally sized dual partitioned subsets includes a first subset containing the first position of all starting position pairs and a second subset containing the second position of all starting position pairs. The two dual partitioned subsets may further satisfy a contiguity requirement. In this regard, adjacent position pairs form time slots (i.e., a time slot within [0, N / 2) contains adjacent positions {2*s, 2*s+1}) and may have one position of a time slot in the first subset and another position of a time slot in the second subset. One such example of a dual partition of equal-sized subsets that satisfies the contiguity requirement includes partitioning a set of positions into an even position set and an odd position set, wherein each starting position pair includes an even position and an odd position. It should be understood that any of a variety of alternative algorithms for partitioning the full set of positions into two equal-sized subsets (which may or may not satisfy the contiguity requirement) based on a particular classification, feature, or other determination may be implemented to generate the dual partition of equal-sized subsets of the full set. It should be understood that in some embodiments, any valid mapping from a first position in the first dual partition subset to any unique second position in the second dual partition subset is valid. In other embodiments, a mapping is considered valid only if the contiguity requirement is also satisfied, which requires that each position in the first dual partition subset have at least one adjacent position in the second dual partition subset.

[0197] A vector of target slot assignments for such dual-partitioned subsets (target_slots vector) can then be generated. In some embodiments, each position in one of the subsets (e.g., the first dual-partitioned subset or the second dual-partitioned subset) is assigned a fixed time slot from the set of available time slots. The target_slots vector can then be assigned time slots corresponding to other positions in the second dual-partitioned subset. The target_slots vector can then be sorted to achieve parity between the time slot value for each position in the second dual-partitioned subset and the corresponding time slot for the first position in the first dual-partitioned subset. An exemplary embodiment is provided herein that dual-partitions the starting position into a first subset comprising even positions and a second subset comprising odd positions, the odd positions having a time slot formed by a pair of adjacent positions (one from the even subset and one from the odd subset). However, it should be understood that other methods of partitioning the set of positions into subsets of equal size can be utilized without departing from the scope and spirit of the present disclosure.

[0198] Figure 13 Depicts exemplary data associated with manipulating an exemplary quantum computing environment according to at least some exemplary embodiments of the present disclosure. Figure 14 、 Figure 15A 、 Figure 15B , Figure 16A and Figure 16B The exemplary implementation depicted in Figure 13 . As depicted, for purposes of explanation and understanding, exemplary qubit set 1302 is processed. Exemplary qubit set 1302 includes a qubit count ("Q") of 12 qubits. In this regard, qubit set 1302 includes qubits indexed from 0 to 11, which represents a total of 12 qubits. Qubit set 1302 may be associated with a set of positions corresponding to positions indexed by the integer range [0, 1, ... Q-1] (which corresponds to 12 positions) in which the qubits in qubit set 1302 may be arranged. It should be understood that qubit set 1302, as described herein, is exemplary and that in other embodiments, qubit set 1302 may include any number of qubits.

[0199] Figure 13Also depicted is an exemplary position vector 1304. The position vector includes 12 positions, which match the number of qubits in qubit set 1302. In this regard, each qubit from qubit set 1302 can be located at any one of the position indices depicted as part of position vector 1304. For example, in some embodiments, at a first time slice, each qubit can be located at the position corresponding to the qubit depicted by the numerical index (e.g., qubit 1 is located at position 1, qubit 2 is located at position 2, qubit 3 is located at position 3, etc.). As time slices are processed, qubits can be repositioned among the various positions in position set 1304. In this regard, position vector 1304 can represent a current vector representing the position of each qubit in qubit set 1302 as such qubits are processed within a particular time slice.

[0200] Figure 13Also depicted is an exemplary even-odd starting position pairing set 1306 based on the starting positions of the individual qubits in qubit set 1302. In some exemplary contexts, even-odd starting position pairing set 1306 includes a number of position pairs that represent pairs between the current position indices of the particular qubits to be gated at the particular time slice to be processed. The position pairs are subject to at least one constraint requiring that the two elements of each position pair be in different subsets of two equally sized subsets of a dual partition of the set of all positions (e.g., into even and odd positions). In the depicted example, such a dual partition imposes an even-odd constraint such that even-odd starting position pairing set 1306 produces an even-odd starting position pairing set that includes every even-odd pair of two starting positions to be gated at the next time slice. In this regard, each even-odd position pair in even-odd starting position pairing set 1306 includes an even starting position index paired with an odd starting position index such that each qubit position pair satisfies the even-odd constraint. In other contexts, even-odd starting position pairing set 1306 may not satisfy the even-odd constraint, e.g., where starting position pairing set 1306 includes one or more even-even position pairs including a first even position index paired with a second even position index, or where even-odd starting position pairing set 1306 includes one or more odd-odd position pairs including a first odd position index paired with a second odd position index. In some such cases, a qubit pairing set including at least one even-even position pair or at least one odd-odd position pair may be converted to include all even-odd position pairs that satisfy the even-odd constraint. The conversion to a position pairing set that satisfies the even-odd constraint may be performed using one or more pairing set conversion algorithms as described herein, e.g., as described herein with respect to Figure 17A 、 Figure 17B and Figures 18 to 25 As stated.

[0201] Figure 14 Depicts an exemplary algorithmic transformation for determining a time slot corresponding to each location in a set of locations. As shown, Figure 14 The method includes determining a time slot assigned to each of the positions in the position set 1402. The position set 1402 includes a total of twelve positions indexed by the integer range [0, 12) (e.g., where the integer range [X, Y) embodies the integer set {X, X+1, ..., Y-1}, such as {0, 1, ..., N-1}). In this regard, the positions may correspond to positions with respect to Figure 13 The available locations are described in an exemplary computing environment.

[0202] Each position in the set of positions 1402 is mapped to a corresponding time slot based on a particular time slot determination algorithm. As depicted, the time slot determination algorithm includes integer division by 2, such that a time slot ("s") is defined by p / / 2, where p / / 2 represents the integer division of the position ("p") by 2 (e.g., discarding the remainder). In this regard, position index 0 maps to time slot index 0 because 0 / / 2=0, and position index 1 similarly maps to time slot index 0 because 1 / / 2=0. Similarly, position index 2 maps to time slot index 1 (because 2 / / 2=1), and position index 3 similarly maps to time slot index 1 (because 3 / / 2=1). Such time slot allocation continues for the remaining positions, such that each even position 2n is mapped to a time slot to which a subsequent odd position 2n+1 is similarly mapped. In this regard, adjacent index pairs are mapped to the same shared time slot. The qubit indices and / or position indices for such qubits may be assigned to specific slot indices, and such slot indices may be similarly rearranged as described herein for the purpose of target position assignment as described herein, for example, with respect to Figures 15-16. The resulting target assignment produces all starting position pairs in each slot such that each starting position pair becomes adjacent and thus gateable.

[0203] Figure 15A An exemplary visualization is depicted of an exemplary process for performing target assignment of a starting position pair by determining a target position vector for a particular time slice. The exemplary process may be performed according to any of the embodiments described herein. For example, in some embodiments, the apparatus 200 is configured to perform the operations of the process before generating an algorithm exchange command set as described herein, such as described herein with respect to Figures 5 to 11 described.

[0204] For relative to Figure 15A 、 Figure 15B 、 Figure 16A and Figure 16B The exemplary process described for target allocation relies on one or more basic assumptions. Figure 15A Figure 15B Figure 16A and Figure 16B The exemplary process described for target allocation relies on the basic assumption that the set of starting position pairs to be processed is even. Additionally or alternatively, for example, for Figure 15A 、 Figure 15B 、 Figure 16A and Figure 16B The exemplary process described for target allocation relies on the basic assumption that the set of starting position pairs to be processed is complete (because the starting position pair set includes all positions). Additionally or alternatively, for example, for Figure 15A 、 Figure 15B 、 Figure 16A and Figure 16B The exemplary process described for target allocation relies on the basic assumption that the starting position pairing set reflects the even-odd starting position pairing set (e.g., only includes eo pairs). Some embodiments may perform one or more processes to check whether the starting position pairing set meets each basic assumption and then calculate the target allocation target by comparing the starting position pairing set to the even-odd starting position pairing set. Figure 15A 、 Figure 15B 、 Figure 16A and Figure 16B The process described initiates processing of the starting position pairing set. In some embodiments, if an embodiment (e.g., device 200) determines that one or more base assumptions are not satisfied, the embodiment may initiate one or more pre-processing algorithms to update the starting position pairing set to satisfy each base assumption. Non-limiting examples of pre-processing algorithms for updating the starting position pairing set to satisfy these base assumptions are described in the next section and with respect to Figure 17A 、 Figure 17B 、 Figure 18 and Figures 19 to 25 Provide a description.

[0205] The target position vector is derived from a starting position pairing set, which can be determined, for example, based on a set of qubit pairings derived for a particular time slice and the current positions of such qubits at the beginning of the particular time slice. In this regard, the starting position pairing set can represent a pair of current position indices at the beginning of a time slot that includes the qubits to be gated during the particular time slice. In this regard, embodiments of the present disclosure process the starting position pairing set to generate target positions for positioning the qubits such that each first qubit is relocated from its starting position to a new position adjacent to a corresponding position that includes the second qubit with which the first qubit is paired for gating.

[0206] The exemplary process is performed on a starting position pairing set that includes all positions in [0, N), where N is the number of starting positions and N is an even number. The exemplary process is further performed on the starting position pairing set, where each position pair satisfies the even-odd constraint. For example, the even-odd starting position pairing set 1302 can represent a position pairing set for the next time slice to be processed and satisfies the following two assumptions: all positions are included (e.g., [0, N), where N is 12), N is an even number, and all position pairs are o-pairs. As shown, the even-odd starting position pairing set 1302 includes a complete set of even-odd starting position pairings sorted in increasing order of the even starting positions of each pair, where each even starting position is the first starting position in the pair, so that the resulting even-odd starting position pairing set 1302 has the form {(0, o0), (2, o1), (4, o2), ..., (N- 2, oN / 2-1 )}, where o k is an odd starting position paired with an even position 2k of k in the range [0, N / 2). In some cases where one or more of these assumptions are not met, for example where the starting position paired set includes ee pairs or oo pairs, the starting position paired set may be pre-processed to meet such assumptions before the process for determining the target position vector for a particular time slice begins, as described herein.

[0207] The exemplary process for determining the target position vector for a particular time slice is similar to the problem of utilizing two rows of target assignments. The even position resides in the descending row (for example, the second row), and the odd position resides in the upper row (for example, the first row). Target is to manipulate the row under the situation of finding the shared target column for each starting position in the even-odd starting position pairing set 1302. In order to achieve this target, it can be fixing any row, and another row can be manipulated to be in the same column with the corresponding pairing even starting position in the fixed row. For exemplary purposes, depict and describe Figure 15 from the angle of the even starting position that keeps being fixed in the descending row and manipulating the odd starting position in the upper row. Should be understood that this process can similarly be performed by odd position being set to fixing and manipulating even position.

[0208] Each odd starting position o k In the upper row, it is assigned to column k among the N / 2 columns. Next, an even-odd transposition sort is performed on the upper row to generate a set of parallel swap commands for the upper row. The generated set of parallel swap commands rearranges the upper row so that all odd starting positions reside in the same column as their fixed even-numbered counterparts in the lower row. Taking advantage of the even-odd transposition sort, this operation can be completed within N / 2 parallel swap commands for the N / 2 positions in the row.

[0209] Once the qubits are rearranged so that qubit pairs are in common columns across two rows, performing the same swap operation on both rows will preserve the common column property, satisfying the constraint that qubit pairs remain in common columns with the qubits in their fixed pair positions. Reversing the swap commands applied to the upper row, for example by moving the upper row back along the path it followed (e.g., toward its starting position), simply undoes its rearrangement, while applying the swap commands to the lower row will also cause the lower row to move in the same manner to preserve the common column property. In this regard, from the outset (e.g., without ordered position assignments), a particular implementation may apply the first half of the parallel swap commands to the upper row and reverse the second half of these parallel swap commands to the lower row, so that the qubit pairs arrive at the same target column in no more than (N / / 2 + 1) / / 2 parallel swap commands. Therefore, by assigning target positions to the uplink based on the downlink starting position, performing an even-odd transposition sort on the uplink target vector, and finding the positions of the target vector values ​​at the midpoints of the sort, these midpoint positions can be used as target positions for both the uplink and the downlink to reduce the total number of parallel transposition commands used to locate the qubit to be gated.

[0210] The depicted and described operations perform a similar process for a linear array of positions by treating even positions as downstream and odd positions as upstream. An embodiment constructs a target vector comprising slots of length N / 2, which may be referred to as a "target_slots" vector indexed by slot "s". Each slot "s" is associated with a pair of adjacent positions {2s, 2s+1}, where the lower position 2s represents the even position of the even-odd starting position pair. Given a position p, the corresponding slot may be determined by a slot determination algorithm, such as relative to Figure 14 The time slot determination algorithm 1404 is depicted and described where s=p / / 2.

[0211] Some such implementations initialize the vector "target_slots" such that:

[0212] target_slots[o s / / 2]=s, all s are in the range [0,N / 2).

[0213] With this initialization, each odd starting position is assigned the time slot that its paired even starting position resides in. Thus, the resulting target_slots vector is initialized in a way that pairs each position identified in the set of corresponding even-odd starting position pairs by positioning the odd positions to the time slots of their fixed even counterparts for the time slice being processed.

[0214] Such embodiments also perform an even-odd transposition sort on the target_slots vector to generate a parallel swap command sequence of length M, where M <= N / 2. The parallel swap command sequence is embodied by a parallel swap command set that represents each swap performed when performing the even-odd transposition sort. It should be understood that the parallel swap command set representing the swap commands used to sort the target_slots vector can be embodied in any of a variety of ways to indicate the left swap and / or right swap performed, as described herein.

[0215] The resulting target_slots vector may be used to generate a new vector "target_slots_mid" that represents the position of each position at the midpoint to complete the even-odd transposition order. In this regard, an embodiment may apply a first (M+1) / / 2 parallel swap command to the target_slots vector to generate a target_slots_mid vector, where target_slots_mid[o s / / 2] is the odd starting position at the midpoint of the even-odd transposition sort s Then, the implementation will be, for example, to start from the sorted (2s,o s ) the sorted starting position pairs represented by the vector obtained are assigned to the target position pairs (2* target_slots_mid[o s / / 2],2*target_slots_mid[o s / / 2]+1). Under the request that odd positions be sorted separately, such assignments represent the time slots in which the odd positions will reside. Next, embodiments perform an even-odd permutation sort on the target vector representing the set of target qubit pairs for all positions, generating a step that sorts the qubits into their correct positions for the purpose of processing a particular time slice.

[0216] For the purpose of determining a target vector for determining a parallel swap command set, the target_slots vector may be sorted starting with either an even phase or an odd phase as the first phase. It should be understood that in some embodiments, the even-odd transposition sort is performed using each of the even and odd phases as the starting phase. The target vector generated by sorting the target_slots vector starting with an even phase may be different from the target vector generated by sorting the target_slots vector starting with an odd phase. However, in a specific implementation, one of the resulting target vectors may be computationally more efficient than the other target vector in a one-dimensional quantum computing environment (e.g., when sorted as described herein as a set of target qubit positions for instruction compilation via a subsequent even-odd transposition sort) in a specific embodiment. In this regard, embodiments may perform a first subsequent even-odd transposition sort on a first target vector generated from a first target_slots_mid vector in phase with the first sort phase (e.g., associated with starting with an even sort phase) and execute a first number of steps in the determined first resulting algorithmic swap command set. Similarly, embodiments may perform a second subsequent even-odd transposition sort on a second target vector, generated from a second target_slots_mid vector in phase with a second sorting phase (e.g., associated with starting with an odd sorting phase), and execute a second number of steps in the determined second resulting algorithmic swap command set. The number of steps associated with each resulting algorithmic swap command set (e.g., corresponding to sorting the target_slots vector starting with a different sorting phase) may be compared to determine which resulting algorithmic swap command set includes fewer steps. Embodiments may select a resulting target vector for sorting using the fewest steps, thereby reducing the computational resources required to perform qubit sorting in a one-dimensional quantum computing environment, because the consumption of conventional computational resources to generate an efficient swap algorithm is preferred over the consumption of quantum computational resources in a one-dimensional quantum computing environment because it is less time-consuming, less expensive, and less prone to errors.

[0217] like Figure 15A As shown, the described algorithm is performed on the exemplary even-odd starting position pairing set 1302 as depicted and described herein. Even positions are assigned to time slots in the downlink, represented by even time slot vector 1502. Even time slot vector 1502 corresponds to the six time slots depicted and described with respect to time slot vector 1406, which correspond to the six time slots with respect to Figure 13 and Figure 14The 12 positions of the depicted and described one-dimensional quantum computing environment. For purposes of understanding, vectors for even positions 1506 are depicted, corresponding to even time slot vectors 1502.

[0218] The embodiment initializes the target_slots vector to a starting configuration 1504a. For example, based on a time slot determination algorithm s=p / / 2, odd positions are assigned time slots from time slot vector 1406 to generate a starting configuration for the target_slots vector for the uplinks associated with the odd positions. The resulting starting configuration is then used to initiate an even-odd transposition sorting of the target_slots vector, for example, starting from an even phase as depicted. For purposes of understanding, a vector of starting configuration positions 1508A is depicted, representing the starting configuration of the time slot assignments in target_slots vector 1504A. Similarly, for purposes of understanding, each of the steps of performing the even-odd transposition sorting on the target_slots vector is depicted in steps 1504B through 1504E, and the corresponding steps of the even-odd transposition sorting for positions corresponding to such time slots are depicted in steps 1508B through 1508E.

[0219] The embodiment utilizes an even-odd transposition sort to rearrange the target_slots vector. As depicted, the target_slots vector is fully sorted in four steps. At step 1504B, the target_slots vector is swapped based on the even phase to swap the slots assigned to the targets_vector at indexes 2 and 3, and to swap indexes 4 and 5. As described, these indices are swapped because the higher-order index includes a first value that is lower than the second value at the lower-order index. At step 1504C, the embodiment continues the even-odd transposition sort at an odd phase, swapping indexes 1 and 2 of the target_slots vector and 3 and 4 of the target_slots vector. Then, at step 1504D, the embodiment continues the even-odd transposition sort at another even phase, swapping indexes 0 and 1 of the target_slots vector and 2 and 3 of the target_slots vector. Then, at step 1504E, the algorithm completes at the next odd phase, where index 1 and index 2 of the target_slots vector are swapped, and index 3 and index 4 of the target_slots vector are swapped, thereby producing a fully sorted target_slots vector. The fully sorted target_slots vector depicted at step 1504E is arranged so that the common column property applies to each slot of the target_slots vector for each qubit pair in the even-odd starting position pairing set 1302. An embodiment can generate a swap command set representing the swap commands resulting from the even-odd transposition sorting operation.

[0220] In this regard, the value of target_slots[s] before the sort begins represents the destination of slot s (e.g., the odd position represented by slot s in an embodiment where the even position is fixed), such that it arrives at the slot occupied by its even position counterpart specified in the even-odd starting position pairing set 1302. Similarly, upon completion of the even-odd transposition sort for sorting the target_slots vector based on rearranging the odd positions, the resulting set of swap commands can be applied to the even positions in reverse order to cause the qubits residing at the even positions to arrive at the slots where the corresponding paired odd positions were originally located. In this regard, the midpoint step of the even-odd transposition sort can be identified by applying only the first (M+1) / / 2 parallel swap commands to generate the target_slots vector, where M is the length of the sequence of parallel swap commands generated based on the completed even-odd transposition sort. The midpoint step in Figure 15 includes step 1504C, as indicated by the asterisk (*), which corresponds to a target_slots_mid vector having the value [2, 0, 4, 1, 3, 5]. The target_slots_mid vector corresponds to the position at the midpoint step indicated by 1508C, and the corresponding even position corresponds to the position indicated by the corresponding time slot in the even position vector 1506. Then, by sorting the starting position pair (2s, o s ) are assigned to the target position pairs represented by the slots where the odd positions would reside if the odd positions were sorted separately (2*target_slots_mid[o s / / 2],2*target_slots_mid[o s / / 2]+1), the target_slots_mid vector associated with the midpoint step can be used to generate the final target vector for all positions.

[0221] As shown in the figure, similar to Figure 16A 1406, and even slot vector 1502 are associated with even-odd transposition sorting. Thus, for the purpose of starting the even-odd transposition sorting, the starting configuration 1504A and even slot vector 1502 remain the same. However, the first step begins with an odd phase at step 1604B of the even-odd transposition sorting.

[0222] like Figure 16AAs shown, the target_slots vector is fully sorted in five steps starting from an odd phase. At step 1604B, the target_slots vector is swapped based on the odd phase to swap the slots assigned to the targets_vector at indexes 1 and 2, thereby generating an updated targets_vector [2, 3, 4, 0, 5, 1]. As described, such indices are swapped because the higher-order index includes a first value that is lower than the second value at the lower-order index. At step 1604C, the embodiment continues the even-odd transposition sorting at an even phase, where indexes 2 and 3 of the target_slots vector are swapped, and indexes 4 and 5 of the target_slots vector are swapped, thereby generating an updated targets_vector [2, 3, 0, 4, 1, 5]. Then, at step 1604D, the embodiment continues the even-odd transposition sorting at another odd phase, where index 1 and index 2 of the target_slots vector are swapped, and index 3 and index 4 of the target_slots vector are swapped, thereby generating an updated target_vector [2, 0, 3, 1, 4, 5]. Then, at step 1604E, the embodiment continues the even-odd transposition sorting at another even phase, where index 0 and index 1 of the target_slots vector are swapped, and index 2 and index 3 of the target_slots vector are swapped, thereby generating an updated target_vector [0, 2, 1, 3, 4, 5]. Then, at step 1604F, the algorithm completes at the next odd phase, where index 1 and index 2 of the target_slots vector are swapped, thereby generating a fully sorted target_slots vector.

[0223] Figure 15B Depicts the Figure 15A 15. Example generation of a target vector corresponding to the target_slots_mid vector resulting from the depicted and described operations. For purposes of illustration, the slot vector 1406 is vertically aligned with the corresponding index of the even slot vector 1502 and the target_slots_mid vector 1552. Further as depicted, the target vector 1554 is generated based on the target_slots vector 1552, which reflects the Figure 15A1504C. For purposes of explanation and understanding, target allocation is described sequentially based on the order of the slot indices at each index of target_slots_mid vector 1552. It should be understood that in some implementations, target allocation is performed in any order, sequentially, in parallel, simultaneously, etc.

[0224] At index 0, the target_slots_mid vector 1552 refers to slot 2 of the corresponding position pair (e.g., target_slots_mid[0] == 2). The position pair leading to the second slot can be identified from the set of even-odd starting position pairs 1302, which can be identified, for example, via a lookup or calculation. For example, since we have fixed the even index, an embodiment may identify the pair including the even position corresponding to the identified slot 2 as pair (4, 1), since slot s == 2 maps to the even position 2s == 4. Some such embodiments may perform one or more lookups to determine that the even position 2s == 4 resides in the starting position pair (4, 1). Therefore, the target vector indices at 4 and 1 are assigned the values ​​corresponding to the positions of slot 0 (e.g., positions 0 and 1). In some embodiments, as described herein, the order of the pairs is not restrictive, such that pair (4, 1) is equivalent to pair (1, 4). This flexibility allows the target positions corresponding to slot 0 (e.g., positions 0 and 1) to be assigned to the corresponding indices 1 and 4 in any order. To reduce the worst-case scenario of the number of swaps to be performed in the subsequent even-odd transposition ordering of the target vector 1554, the lower index of the pair (4, 1) in the target vector is assigned a lower index position corresponding to slot 0, and the higher index of the pair (4, 1) is assigned a higher index position corresponding to slot 0. For example, in the depicted embodiment, the target vector at index 1 is assigned a lower position of slot 0 (e.g., target[1]=0), and the target vector at index 4 is assigned a higher position of slot 0 (e.g., target[4]=1).

[0225] Similarly, this process is performed for each index of the target_slots_mid vector 1552 to complete the target allocation in the resulting target vector 1554. For example, at index 1, the target_slots_mid vector 1552 refers to the time slot 0 of the corresponding position pair corresponding to the position pair (0,7) (e.g., target_slots_mid[1]==0). The indices 0 and 7 of the target vector 1554 are assigned the values ​​corresponding to the position of time slot 1, so that the lower index of the position pair is assigned the lower position represented by time slot 1. Therefore, when time slot 1 indexes positions 2 and 3, the lower target index 0 is assigned the value 2 (e.g., target[0]=2), and the higher target index 7 is assigned the value 3 (e.g., target[7]=3). For the purpose of brevity, the subsequent allocation of time slots 2, 3, 4, and 5 follows the same operation, so repeated descriptions are omitted.

[0226] In some embodiments, the even-odd transposition sorting of the target_slots vector is performed starting from the even phase and the odd phase to determine which of the starting phases results in completing the even-odd transposition sorting in fewer steps. Figure 16A Depicted are steps for performing an even-odd transposition sort of an exemplary set of even-odd starting position pairs starting from an odd phase according to at least one exemplary embodiment of the present disclosure. The even-odd transposition sort is performed similarly to that described herein, but instead of starting with the transposition pair with the lower odd index. Steps 1602B through 1602F are performed, resulting in a second midpoint vector generated at the third step 1604C of [2, 0, 3, 1, 4, 5]. As shown, the vector is generated by starting from the phase at Figure 15B The target_slots_mid vector generated by the even-odd transposition sequence starting from the odd phase is different from the target_slots_mid vector generated by the even-odd transposition sequence starting from the odd phase Figure 15A The target_slots_mid vector is generated by sorting the even-odd positions starting from the even phase.

[0227] It will be appreciated that different target_slots_mid vectors generated by the even-odd permutation order starting from the odd phase similarly generate different target vectors embodying the target qubit position set for further processing. For example, Figure 16B Describes how Figure 16A An exemplary visualization of the target allocation of the target_slots_mid vector generated at the midpoint step of the even-odd transposition sequence starting from the odd phase is depicted and described.

[0228] like Figure 16B As shown, the target_slots_mid vector 1652 is generated relative to Figure 16AThe target_slots_midpoint vector 1652 is at the midpoint of the even-odd transposition order of the target_slots vector depicted and described. Figure 15A 1554 begins in the same manner as the target_slots_midpoint vector 1552 depicted and described above, where the target_slots_midpoint vector at index 0 refers to slot 2 and at index 1 refers to slot 0. Thus, both target vector 1554 and target vector 1654 are assigned positions 0, 1, 2, and 3 at the same index. However, at index 2, target_slots_midpoint vector 1552 differs from target_slots_midpoint vector 1652 because target_slots_midpoint vector 1552 refers to slot 4 and target_slots_midpoint vector 1652 refers to slot 3. Thus, as Figure 15B As shown, the index of the target vector 1554 assigned target positions 4 and 5 (which corresponds to time slot 2) is the index of the position in the pair (8, 3), which corresponds to time slot 4 referred to in the target_slots_mid vector 1552 at index 2. Specifically, the lower index of the pair is assigned the lower position corresponding to time slot 2, so target vector index 3 is assigned 4, and target vector index 8 is assigned 5. Alternatively, as Figure 16B As shown, the indices of the target vectors 1654 assigned target positions 4 and 5 are indices of positions in (6, 5), which corresponds to slot 3 referenced in the target_slots_mid vector 1652 at index 2. Specifically, the lower index of the pair is assigned the lower position corresponding to slot 2, so target vector index 5 is assigned 4, and target vector index 6 is assigned 5. In this regard, the resulting target vectors 1654 corresponding to odd phases differ from the resulting target vectors 1554 corresponding to even phases.

[0229] Such target vectors may similarly take different numbers of steps to be sorted via the even-odd permutation sorting. Thus, embodiments of the present disclosure may perform a subsequent even-odd permutation sorting on each of target vectors 1554 and target vector 1654, and for each determined swap, execute a corresponding set of algorithmic swap commands, where each new sorting phase in the set of algorithmic swap commands represents a step for comparison. Such embodiments may then compare the number of steps required to sort each of the target vectors and select the target vector corresponding to the fewer number of steps to sort into a set of target qubit positions for further processing, e.g., as compared to Figures 3 to 11Fewer ordering steps are selected to reduce the time and amount of quantum computing resources required to perform the swaps required to position the qubits from their initial positions to their target positions.

[0230] In the completion of the relative Figure 15A and Figure 15B After the even-odd transposition sorting starting from the even phase, the embodiment may perform an even-odd transposition sorting of the target_slots vector starting from the odd phase. Alternatively or additionally, in some embodiments, the even-odd transposition sorting starting from the odd phase is performed first, and then the even-odd transposition sorting starting from the even phase is performed, such as with respect to Figure 15A and Figure 15B As stated.

[0231] Implementations can compare the number of steps for an even-odd transposition sort starting with an even phase to the number of steps for an even-odd transposition sort starting with an odd phase. An implementation that results in a smaller number of steps can be selected, and the target_slots_mid vector for the selected implementation can be determined and / or further processed as described herein. In the depicted example, the sort starting with an even phase results in four steps to fully sort the target_slots vector, while the sort starting with an even phase results in five steps to fully sort the target_slots vector. In this exemplary context, such implementations select the even-odd transposition sort starting with an even phase for further processing, and therefore will determine the target_slots_mid vector based on the swap commands generated from performing the even-odd transposition sort starting with an even phase. In the case where the even-odd transposition ordering results in fewer steps (e.g., where six steps are obtained starting with an even phase, e.g., based on a different set of even-odd starting position pairings), as depicted in FIG16 , the target_slots_mid vector is determined from the midpoint step represented by step 1604D of the even-odd transposition ordering starting with an odd phase. The target_slots_mid vector determined from the selected specific implementation of the even-odd transposition ordering can then be used to determine the target vector corresponding to the final target position for each starting position, as described herein with respect to FIG15 , and then processed as described herein with respect to Figures 5 to 11 Selecting an implementation corresponding to a smaller number of steps minimizes the amount of computational resources required to complete the exchange of qubits to their target positions in a one-dimensional quantum computing environment.

[0232] Example Operations for Preprocessing a Set of Starting Position Pairs for Target Assignment

[0233] As described herein, a set of starting position pairings may satisfy various basic assumptions and then be processed to perform a target assignment among a set of target qubit positions. It should be understood that each of these basic assumptions embodies constraints that must be satisfied before further target assignments can be performed for a particular set of starting positions. In this regard, apparatus 200 may, for example, retrieve, receive, or otherwise identify a set of starting positions and perform one or more checks and / or initiate preprocessing for such assumptions to ensure that such assumptions are satisfied, either serially or in parallel with checks and / or preprocessing for other assumptions.

[0234] In some embodiments, the starting position pairing set to be processed for target allocation is subject to an even-number constraint, which requires that the number of positions in the starting position pairing set be even. In some such embodiments, the starting position pairing set is processed to convert it to include an even number of positions. If the original starting position pairing set includes an odd number of positions, such embodiments generate a new arbitrary position to serve as the empty position. The new arbitrary position can be sorted in the same manner as the other positions, and the resulting target vector will have an allocation for the empty position and provide the empty position as a usable target for other starting positions or itself. In some embodiments, the new arbitrary position is appended to the available position list. In other embodiments, the new arbitrary position is pre-entered into the available position list, and the position list is shifted to have a minimum index of 0. In other embodiments, the new arbitrary position is inserted into the middle of the available starting position list, shifting the portion of the starting position to the right of the insertion point so that the starting position list occupies the index range [0, N), where N is an even number. In some embodiments, the target vector can remove the new arbitrary position associated with the empty position to generate a target vector valid for the odd-numbered position set. In other embodiments, the target vector can accept the empty position without removing it. Any and all combinations generated and / or otherwise performed by such embodiments result in an updated set of starting position pairings that is a valid representation that overcomes the evenness constraint on the total number of positions.

[0235] In some embodiments, the starting position pairing set to be processed for target allocation is subject to an integrity constraint, which requires that these pairs include all positions in the available position set. The integrity constraint further requires evenness as described above, so the starting position pairing set can be processed to first solve the evenness constraint and then solve the integrity constraint. In some embodiments, an unused position set is identified from the starting position pairing set, which includes all positions not represented in the starting position pairing set. The unused position set is sorted so that the positions therein are ordered. Subsequently, the unused positions are paired in sorted order (for example, so that the first unused position at index 0 in the unused position of the sort is paired with the second unused position at index 1 in the unused position of the sort, the third unused position at index 2 in the unused position of the sort is paired with the fourth unused position at index 3 in the unused position of the sort, and so on) to generate a new position pair set based on the ordered unused positions. The new position pair set includes the position pair utilizing the unused position, which ensures that the required travel distance of each position pair is minimized. The new set of position pairs is added to the original set of starting position pairs to generate an updated set of starting position pairs, and the updated set of starting position pairs is then processed regardless of which pairs were previously considered unused.

[0236] In some embodiments, the starting position pairing set can be similarly preprocessed to ensure that the even-odd constraint that only even-odd position pairs are present in the starting position pairing set is satisfied. In this regard, some embodiments (e.g., apparatus 200) initiate such preprocessing operations in response to determining that the starting position pairing set includes at least one ee pair and / or oo pair. Figure 17A 、 Figure 17B and Figures 18 to Figure 25 Depicted are exemplary data and operations associated with preprocessing a set of starting position pairs to satisfy the only-even-odd-number constraint. The only-even-odd-number constraint can rely on the underlying assumptions embodied by the evenness constraint and the completeness constraint described herein. Therefore, starting position pair sets that do not satisfy these two constraints can be further preprocessed to ensure that such constraints are satisfied before further preprocessing to satisfy the only-even-odd-number constraint.

[0237] Figure 17A An exemplary process for partitioning a position pairing set (e.g., a starting position pairing set) into an even-odd position pairing set (e.g., an even-odd starting position pairing set) according to at least one exemplary embodiment of the present disclosure is depicted. An exemplary starting position pairing set 1752 is depicted. The exemplary starting position pairing set 1752 satisfies other basic assumptions (e.g., the set is complete and even), however, it includes multiple ee pairs and oo pairs.

[0238] In some embodiments, such as apparatus 200, starting position pair set 1752 is divided into ee pair set 1754A, oo pair set 1754B, and eo pair set 1754C. Such embodiments generate ee pair set 1754A, which includes only ee pairs from starting position pair set 1752. Similarly, such embodiments generate oo pair set 1754B, which includes only oo pairs from starting position pair set 1752. Similarly, such embodiments generate eo pair set 1754C, which includes only eo pairs from starting position pair set 1752. Some embodiments perform a check on each position in each position pair in starting position pair set 1752 to determine whether the position pair represents an ee pair, an oo pair, or an eo pair. Based on the check results (e.g., the ee pairs in ee pair set 1754A), such embodiments classify the position pair into the correct set: ee pair set 1754A, oo pair set 1754B, or eo pair set 1754C. When such a partitioning is performed on each pair in the starting position pairing set 1752, the ee pair set 1754A, the oo pair set 1754B, and the eo pair set 1754C include all position pairs to be further processed. It should be understood that the starting position pair set 1752 that satisfies other basic assumptions (such as the integrity constraint and the evenness constraint) will include the same number of ee pairs and oo pairs, so that the ee pair set 1754A and the oo pair set 1754B will include the same number of position pairs therein.

[0239] Each ee pair has a path to the oo pair formed by adjacent oe pairs, where the sequence of oe pairs reaching the oo pair may have zero length. Generally speaking, the path has the form 1756, which may include any number of adjacent eo pairs from the ee pair to the oo pair. In the depicted format, the second element of each pair is an even number and is adjacent to the first element of the subsequent pair. The ee pair may be directly adjacent to the oo pair, and in this case, the sequence of oe pairs has zero length. An exemplary path with an oe pair is (2,6) → (7, 24) → (25,4) → (5,12) → (13,10) → (11,3). In this example, the first pair (2,6) is an ee pair; the second element (6) of the first pair is an even number and is adjacent to the first element (7) of the second pair, which is an odd number. Next, the second element (24) of the pair (7,24) is adjacent to the first element 25 of the following pair (25,4), and the second element (4) of the pair (25,4) is adjacent to the first element (5) of the following pair (5,12), and so on. The last pair (3,11) is an oo pair, so swapping the even positions with the previous pair yields a new oe pair. In this regard, performing a parallel swap of the second element of each pair with the first element of its following pair in the path yields the set of transition pairs {(2,7), (6,25), (24,5), (4,13), (12,11), (10,3)}, which completely includes eo pairs. Examples of Ee pairs directly adjacent to oo pairs include the path (6,2) → (3,11). Such paths do not include oe pairs and therefore have zero-length oe pair paths. In this regard, exchanging the second element (2) of the first pair with the first element (3) of the adjacent second pair results in a set of transformation pairs {(6,3), (2,11)|, which completely includes the eo pair.

[0240] Such paths are formed by adjacent pairs. In some embodiments, adjacent pairs are constrained to coincide with the first phase of an even-odd transposition sort to be used to generate an algorithmic swap command set, the algorithmic swap command set comprising parallel swap commands for the set of target qubit positions to be processed. For example, an embodiment may determine the first phase of an even-odd transposition sort to be used to generate an algorithmic swap command set (e.g., based on user input, hardware configuration of a one-dimensional quantum computing environment, etc.). The first sorting phase is even, corresponding to parallel swap commands that swap adjacent positions whose lower indices are even. In such cases where the first phase of the even-odd transposition sort is even, an even position (e) may only be swapped with an odd position o, where o=e+1. Similarly, in the case where the first sorting phase is odd, an even position e may only be swapped with an odd position o, where o=e-1.

[0241] Some such embodiments construct paths (e.g., from ee pairs to oo pairs) from each pair of positions from the dual partitioned subset that are consistent with the constraints based on the first sorting phase. In this regard, it should be understood that when the first sorting phase is even, the pairs adjacent to the ee pair (e1, e2) that satisfy the constraints imposed by the first sorting phase are pairs with odd elements e1+1 and e2+1, and accordingly, there are only two such pairs. Similarly, it should be understood that when the first sorting phase is odd, the allowed pairs adjacent to the ee pair (e1, e2) are pairs with odd elements e1-1 and e2-1. In such cases, if both e1 and e2 are non-zero, there are two such pairs that satisfy the constraints. However, when either e1 or e2 is zero, there is only one such pair that satisfies the applicable constraints. Thus, when the first sorting phase is even, there are two paths from each ee pair to the corresponding oo pair, and when the first sorting phase is odd, there are one or two paths. Similarly, it should be understood that if the first sorting phase is even, there are two pairs to each oo pair, and if the first sorting phase is odd, there are one path or two paths. Each intermediate oe pair in the path from an ee pair to an oo pair has only a single input and a single output (e.g., the previous adjacent pair of the first element and the subsequent adjacent pair of the second element).

[0242] In addition to the oe pair used as an intermediate pair in any path from the ee pair to the oo pair, one or more eo pairs may form oe1→oe2→oe N A closed loop of the form, where oe N Adjacent to oe1. In the case where the first sorting phase is odd, then oe pairs that contain even positions (e) where e=0, or contain odd positions (o) where o=Q-1, where Q is the number of positions, are excluded from the closed loop of ee to oo paths or oe pairs.

[0243] ee pair set 1754A is used to determine a set of pair-disjoint paths from such ee pairs to oo pairs present in oo pair set 1754B. Given ee pair set 1754A, which includes a total of N ee pairs, the embodiment determines a set of N pair-disjoint paths from such ee pairs to oo pairs in oo pair set 1754B. These paths are used to form a single-step parallel swap command by swapping the second element of each pair in the path with the first element of the subsequent pair, as long as there is a path. By forming a single-step parallel swap command that implements such a transformation, the starting position pairing set 1752 can be transformed to completely include eo pairs in the minimum number of algorithmic steps, thereby reducing the time, amount of quantum computing resources, and cost of performing such a transformation in a one-dimensional quantum computing environment.

[0244] In some embodiments, a graph is formed to identify and / or analyze paths between positions of a first bipartition subset and positions of a second bipartition subset (e.g., ee pairs and oo pairs). In this regard, embodiments may identify paths between ee pairs and oo pairs via the graph and select any such paths to generate parallel swap commands that transform a set of starting position pairs to satisfy the constraint that each starting position pair has a first element from the first bipartition subset of all positions and a second element from the second bipartition subset of all positions. In some embodiments, such paths may be selected arbitrarily, randomly, etc. using any of a variety of path analysis and / or selection algorithms. Additionally or alternatively, some such embodiments identify and / or process the paths in the generated graph to determine the resource cost and / or efficiency advantage of each path for converting from ee pairs and oo pairs to eo pairs, such that the paths achieve efficiency improvements (e.g., minimization of the worst-case scenario or any reduction in the worst-case or average scenario).

[0245] Based on a set of starting position pairs, which may include all adjacent and interchangeable ee pairs, all oo pairs, and zero or more eo pairs, embodiments can convert any set of pairs into a set that satisfies the following constraints: each element of the starting position pair comes from a different subset of the bipartition, such as an even-odd constraint (e.g., a set consisting only of eo pairs). For example, some such embodiments utilize an efficient shortest path algorithm (such as a modified version of Suurballe's node-disjoint total shortest path algorithm and / or similar algorithms) to process various paths to identify the worst-case path that reduces the conversion from ee pairs and oo pairs to all eo pairs when considering all ee pairs. It should be understood that the modified Suurballe algorithm represents one exemplary implementation of such a method for identifying chains (e.g., paths) of starting position pairs, and that the distance histogram described herein is one of many cost metrics that can be used. Other embodiments implement other graph theoretic algorithms and / or modified versions of graph theoretic algorithms to identify paths from the constructed graph. In some cases, the modified Suurballe algorithm can be utilized to minimize the worst-case distance associated with such path traversal. In other cases, alternative path analysis and / or path selection algorithms may be implemented, such as selecting the first identified path, selecting an arbitrary or otherwise random path, selecting the identified shortest path based on another weighted metric, etc. For example, in some embodiments, ease of implementation while reducing the overall worst case may be prioritized over minimizing the worst case, and thus an alternative algorithm for analyzing paths may be selected.

[0246] Figure 17BDepicted is an exemplary weighted directed graph generated corresponding to an exemplary starting position pairing set according to at least one exemplary embodiment of the present disclosure, specifically, Figure 17B Depicts the corresponding Figure 17A An exemplary weighted directed graph 1700 is depicted and described for generating a set of starting position pairings 1752. In some such embodiments, embodiments utilize a set of ee pairs 1754A, a set of oo pairs 1754B, and a set of eo pairs 1754C to generate the weighted directed graph 1700 ("graph 1700").

[0247] Graph 1700 includes two nodes for each ee pair in ee pair set 1754A, specifically an input node and an output node. As shown, for example, ee pair (2, 6) is associated with ee input node 1704A and ee output node 1704B, ee pair (8, 22) is associated with ee input node 1704C and ee output node 1704D, and ee pair (14, 20) is associated with ee input node 1704E and ee output node 1704F. Similarly, graph 1700 includes two nodes for each oo pair in oo pair set 1754B. As shown, for example, oo pair (1, 9) is associated with oo input node 1706A and oo output node 1706B, oo pair (3, 11) is associated with oo input node 1706C and oo output node 1706D, and oo pair (21, 23) is associated with oo input node 1706E and oo output node 1706F.

[0248] The embodiment generates a graph 1700 including zero-weight directed edges from each input node to a corresponding output node (e.g., from input node 1704A to corresponding output node 1704B, from 1706A to 1706B, from 1704C to 1704D, from 1706C to 1706D, etc.). Graph 1700 is also generated to include a single source node, depicted as SRC node 1702A ("src1702A"), and a single target node, depicted as TAR node 1702B ("tar1702B"). src1702A is associated with a zero-weight directed edge to each of the ee input nodes 1704A, 1704C, and 1704E corresponding to each of the ee pairs. Similarly, each oo output node 1706B, 1706D, and 1706F corresponding to one of the oo pairs is associated with a zero-weight directed edge to tar1702B. For each ee output node 1704B, 1704D, and 1704F, there are one to two paths to the oo node. Similarly, for each oo input node 1706A, 1706C, and 1706E, there are one to two incoming paths from each ee output node 1704B, 1704D, and 1704F.

[0249] In some embodiments, for a path with zero eo nodes between an ee pair and an oo pair, a single weighted directed edge is generated from the ee output node to the oo input node, representing the total cost of traversing the path from the ee pair to the oo pair. For example, the ee output node 1704B associated with the ee pair (2, 6) is directly connected to the oo input node 1706A associated with the oo pair (3, 11) via a single weighted edge because such pairs include adjacent indices. Alternatively or additionally, in some embodiments, for a path with one or more oe nodes between an ee pair and an oo pair, a weighted directed edge is created from the ee output node to the oe node associated with the first oe pair in the chain of one or more oe pairs, wherein a weight is assigned to the weighted edge for all nodes traversed in the chain of one or more oe pairs to reach the corresponding oe pair. Then, a zero-weight edge is created from the oe node associated with the first oe pair to the oo input node corresponding to the oo pair that can be exchanged with the initial ee pair. For example, node 1704B associated with ee pair (2,6) is connected to node 1708A associated with oe pair (7,24). In this path, subsequent intermediate oe nodes must be traversed until the corresponding oo node is reached. For example, an embodiment may determine that intermediate node 1710A corresponding to swapping oe pair (25,4) with (7,24) must be traversed, then intermediate node 1710B corresponding to swapping oe pair (5,12) with oe pair (25,4) must be traversed, then intermediate node 1710C corresponding to swapping oe pair (13,10) with oe pair (5,12) must be traversed until we reach an oe pair that can be swapped with one of the oo pairs, namely oo pair (3, 11) corresponding to oo input node 1706C. In this regard, in some such embodiments, intermediate nodes 1710A-1710C may be optional, and instead, the weighted edge between ee-output node 1704B and intermediate node 1708A corresponding to the first oe pair may be weighted as w1, where w1 includes the weight of each subsequent portion of the path, thereby further allowing intermediate node 1708A to be directly connected to oo-input node 1706C. In other embodiments, individual intermediate nodes 1710A-1710C are maintained independently in the graph, and their individual weights are similarly maintained independently.

[0250] In some embodiments, for a path having a sequence of one or more intermediate oe pairs, the first oe pair is included in a path having a weighted directed edge from the ee output node to the oe node, where the corresponding weight represents the total path weight from the ee to oo pair. In this regard, the weight from the ee node to the eo node can be generated based on the weights of all subsequent eo nodes. In other embodiments, the graph includes the complete full path, including all intermediate nodes connected by weighted edges, and these weighted edges include weights for each individual node, as described herein.

[0251] Graph 1700 also includes a subgraph that includes nodes that form a closed loop path. As shown, graph 1700 includes node 1712A corresponding to oe pair (27, 16), node 1712B corresponding to oe pair (17, 18), and node 1712C corresponding to oe pair (19, 26), each of which is associated with a directed edge that connects the node to the node associated with the adjacent position in the exchange sequence. Some embodiments process such closed loop paths independently of the rest of graph 1700, for example, as described herein with respect to Figure 24 and Figure 25 In this regard, it should be understood that pairs of nodes corresponding to closed loop paths are not used in a path from any given ee pair to any given oo pair.

[0252] In some embodiments, the non-zero weight from the ee node to the first path node represents the total cost of swapping the even positions of all pairs along the path with their adjacent odd positions in the next pair in the path. The total cost is measured as a histogram of the difference distances of the pairs after the swap is initiated relative to the pairs before the swap is initiated. In this regard, given the set of pairs {(p a,1 ,p b,1 ),(p a,2 ,p b,2 ),…,(p a,N , p b,N )}, the implementation scheme determines the distance histogram as each distance abs(p a-,k -p b,k ) occurs, where each k is in the range {1,2,…,N}.

[0253] Figure 18 Depicted is an exemplary distance histogram weight calculation for an exemplary path traversing an exemplary graph according to at least one exemplary embodiment of the present disclosure. Specifically, Figure 18Depicted is the calculation of a distance histogram representing the weights of an exemplary path 1800 of graph 1700. The path includes nodes 1702A, 1704A, 1704B, 1708A, 1710A, 1710B, 1710C, 1706C, 1706D, and 1702B, which correspond to a set of pairs 1802A comprising {(2,6), (7,24), (25,4), (5,12), (13,10), (11,3)}. The distance of each segment of the path is determined by the absolute value of the difference between the two positions in the pair, or in other words, the distance is abs(p1–p2), where p1 is the first position in the pair and p2 is the second position in the pair. Thus, for the set of pairs 1802, the corresponding distance calculations are indicated as original sw1 to original sw6 in distance calculation set 1804A, respectively. As shown, pair set 1802A is associated with distance calculation set 1804A, which includes {abs(2-6), abs(7-24), abs(25-4), abs(5-12), abs(13-10), abs(11-3)}, resulting in values ​​{4, 17, 21, 7, 3, 8}. A corresponding distance histogram 1806A is generated by mapping each occurrence of a particular value in distance calculation set 1804A to a histogram, resulting in {3:1, 4:1, 7:1, 8:1, 17:1, 21:1}, where each element "x:y" indicates that value x occurs y times in distance calculation set 1806A (e.g., value 3 occurs once, value 4 occurs once, value 7 occurs once, value 8 occurs once, value 17 occurs once, and value 21 occurs once). Distance histogram 1806A embodies the distance histogram of the original pairs in set 1802A and may be referred to as h0.

[0254] Some embodiments then generate a distance histogram of position pairs representing the path after the swaps have been performed. As depicted, the swap pair set is represented as 1802 and includes {(2, 7), (6, 25), (24, 5), (4, 13), (12, 11), 10, 3)}. The absolute value of the difference between the two positions in the swap pair is again used to determine the distance of each segment of the swap path. Therefore, for swap pair set 1802B, the corresponding distance calculations are indicated as swap sw1 through swap sw6 in distance calculation set 1804B for swap pair set 1802B, respectively. As shown, swap pair set 1802B is associated with distance calculation set 1804B, which includes {abs(2-7), abs(6-25), abs(24-5), abs(4-13), abs(12-11), abs(10-3)}, resulting in the values ​​{5, 19, 19, 9, 1, 7}. A corresponding distance histogram 1806B is generated by mapping each occurrence of a particular value in the distance calculation set 1804B of the exchange pair set 1802B to a histogram, resulting in {19:2, 9:1, 7:1, 5:1, 1:1} (e.g., the value 19 occurs 2 times, the value 9 occurs 1 time, the value 7 occurs 1 time, the value 5 occurs 1 time, and the value 1 occurs 1 time).

[0255] Using the distance histograms for each pair in the pair sets 1802A and 1802B, the resulting distances between the original position pair set 1802A and the swapped position pair set 1802B can be compared. Each distance represents a worst-case measure of the efficiency of swapping the positions of these pairs to adjacent positions. By comparing the distance histograms for a given path, the worst-case scenario for each path can be directly identified and / or compared. For example, distance histogram 1806A includes a maximum (e.g., worst-case) distance of 21 and a second worst-case scenario of 17, while distance histogram 1806B includes a maximum (e.g., worst-case) distance of 19 and a reproduced second worst-case scenario of 19. In this regard, the original position pair set 1802A presents a worst-case scenario that is worse than the corresponding worst-case scenario for the swapped position pair set 1802B.

[0256] The distance histogram 1806A of the set of original position pairs 1802A (e.g., before any swaps) and the distance histogram 1806B of the set of swapped position pairs 1802B (e.g., after the swaps) can be used for the differential distance histogram with respect to the transformation from the original position pairs to the swapped position pairs. For example, the differential distance histogram 1808 corresponding to the path 1800 can be determined by subtracting h0 from h1 (e.g., differential distance histogram 1808 = distance histogram 1806B corresponding to the set of swapped position pairs 1802B - distance histogram 1806A corresponding to the set of original position pairs 1802A). As depicted, the resulting differential distance histogram 1808 includes {21: -1, 19: 2, 17: -1, 9: 1, 8: -1, 5: 1, 4: -1, 3: -1, 1: 1}.

[0257] The differential distance histogram represents the relative improvement in the worst case of performing even-odd transposition sort by swapping the original position pairs in the manner described by the path (in the case where the differential distance histogram includes the maximum distance value with a negative count), or represents the relative cost of the worst case of performing even-odd transposition sort (in the case where the differential distance histogram includes the maximum distance value with a positive count). In this regard, histograms of positive integer values (e.g., positive distances) are comparable and can be sorted by first comparing the maximum values using the following procedure. Given a histogram h, the number of times the value v is counted is given by h[v]. If v does not exist in the histogram (e.g., including the mapping diagram), then h[v] == 0. The value v does not exist in the mapping diagram with h[v] == 0, and in some embodiments, such values are removed from the mapping diagram. Subsequently, in some embodiments, a sorting operator < ("less than") is defined on two histograms h1 and h2 such that h_{1}<h_{2} is true if and only if the following procedure yields true:

[0258] 1. Determine the maximum values v1 and v2 such that h1[v1]!= 0 and h2[v2]!= 0 (a!= b means a is not equal to b)

[0259] 2. If v1 does not exist and v2 does not exist, return false

[0260] 3. If v2 does not exist, then return true if h1[v1] < 0, otherwise return false

[0261] 4. If v1 does not exist, then return true if h2[v2] > 0, otherwise return false

[0262] 5. If v1 < v2, then return true if h2[v2] > 0, otherwise return false

[0263] 6. If v1 > v2, then return true if h1[v1] < 0, otherwise return false

[0264] 7. If v1 == v2, then return true if h1[v1] < h2[v2], and return false if h1[v1] > h2[v2].

[0265] 8. If v1 == v2 == 0, then return false.

[0266] 9. Update v1 and v2 to values such that h1[v1] != 0 and h2[v2] != 0, and v1 is strictly less than its previous value and v2 is strictly less than its previous value, and repeat steps 2 - 9 until termination.

[0267] In addition to the above process, in some embodiments, a histogram may be compared to zero. In the case where the maximum value vmax = max(v | v > 0 and h[v] != 0) in the histogram is not zero, then the histogram h > 0 if and only if h[vmax] > 0, and h < 0 if and only if h[vmax] < 0. A histogram with no positive zero values is considered zero, which may be equivalent to an empty map.

[0268] In some embodiments, histograms may be added. For example, given two histograms h1 and h2, then for all v in h1 or h2, h = h1 + h2 has elements h[v] = h1[v] + h2[v].

[0269] Additionally or alternatively, it should be understood that in some embodiments, histograms may be subtracted. For example, given two histograms h1 and h2, then for all v in h1 or h2, h = h1 - h2 has elements h[v] = h1[v] - h2[v].[[]END]

[0270] Additionally or alternatively, in some embodiments, histograms may be negated. For example, given h1, for all v in h1, h = -h1 has elements h[v] = -h1[v].[[]END]

[0271] Histograms having each of such properties can be used in various graph theory algorithms. For example, histograms having each of the above properties enable such histograms to be used as weights in a directed graph as described herein, such as with respect to directed graph 1700, and such properties are exploited to enable the graph to be processed via the Suurballe algorithm as described herein.

[0272] In this regard, the difference distance histogram 1808 is designated as the weight w1 in graph 1700 of the depicted path. Embodiments may similarly determine the weights w2, w3, w4, w5, and w6 of the remaining paths, as depicted. Using the same method for calculating w1, the following weights may be determined:

[0273] w1: {21:-1,19:2,17:-1,9:1,8:-1,5:1,4:-1,3:-1,1:1};

[0274] w2: {9:1,8:-1,4:-1,3:1};

[0275] w3:{14:-1,13:1,8:-1,7:1};

[0276] w4:{15:1,14:-1,2:-1,1:1};

[0277] w5: {15:-1,13:1,9:1,8:-1,6:-1,5:1};

[0278] w6:{7:1,6:-1,3:1,2:-1}.

[0279] In some embodiments, the weights are reweighted to eliminate negative weights from consideration. In some such embodiments, to reweight the graph, the minimum value of the determined weights emanating from any of the ee output nodes is subtracted from each weight (e.g., the minimum value of w1 to w6 is subtracted from each of the weights w1 to w6). Such reweighting does not affect the relative total weight across all paths, and thus maintains the priority of each path relative to each other. Additionally, by reweighting to ensure that weights reflect only positive weights, additional shortest path algorithms (such as Dijkstra's efficient shortest path algorithm) that require conditions such as basic properties can be used as part of an algorithm for determining the total minimum weight for multiple paths across graph 1700, for example, as a subroutine in a specific implementation of the Suurballe algorithm for processing graph 1700.

[0280] As shown in the figure, for example, the minimum weight (w min ) is w1. Therefore, after reweighting, such embodiments determine the modified weights as:

[0281] w1=w1– wmin :{}

[0282] w2=w2–w min :{21:1,19:-2,17:1,5:-1,3:2,1:-1}

[0283] w3=w3–w min :{21:1,19:-2,17:1,14:-1,13:1,9:-1,7:1,5:-1,4:1,3: 1,1:-1}

[0284] w4=w4–w min:{21:1,19:-2,17:1,15:1,14:-1,9:-1,8:1,5:-1,4:1,3: 1,2:-1}

[0285] w5=w5–w min :{21:1,19:-2,17:1,15:-1,13:1,6:-1,4:1,3:1,1:-1}

[0286] w6=w6–w min :{21:1,19:-2,17:1,9:-1,8:1,7:1,6:-1,5:-1,4:1,3:2, 2:-1,1:-1}

[0287] The fully weighted and constructed graph 1700 can then be processed using one or more graph theory algorithms to determine the shortest total path. In some embodiments, as described herein, the Suurballe multiple-path shortest total path algorithm is modified to be implemented based on weights represented by a difference distance histogram, and is utilized to find paths from ee pairs in the ee pair set 1754A to oo pairs in the oo pair set 1754B. In this regard, using the difference distance histogram as weights, a specific implementation of the Suurballe algorithm will find a set of paths from ee to oo that minimizes the worst-case distance during a single step of the parallel swap commands generated by these paths. In other words, in some embodiments, the modified Suurballe algorithm is executed to generate a single-step algorithm swap command (e.g., which can be performed in one phase of an even-odd transposition order) that tends to reduce the distance of the modified pairs it generates, starting with the worst-case distance as its highest priority.

[0288] It should be understood that some embodiments utilize a histogram of distances to minimize the worst-case total number of parallel exchange commands. As described, a distance histogram enables determination of the worst-case cost (or benefit) of a particular path and / or otherwise execution of a particular exchange path. In the event that the worst-case scenario between two paths is tied, the impact on the next worst-case scenario can be determined to continue attempting to identify whether the exchange achieves a reduction in the overall worst-case total number of parallel exchange commands. However, without departing from the scope and essence of this disclosure, other embodiments may utilize other metrics for weighted edges as depicted in Figure 1700. For example, in other embodiments, ease of implementation may be a preferred factor for the weight of a given edge, so as to favor simplicity of implementation rather than the most efficient. In this regard, a simple average, sum, or other calculation can be utilized to generate weights, rather than a distance histogram as depicted. Alternatively, even without minimization, a value representing only the worst-case scenario (e.g., without a value corresponding to the next worst-case scenario) can be used as an edge weight to attempt to reduce the worst-case total number of exchanges without incurring additional complexity when implementing a distance histogram.

[0289] Figure 19 to Figure 2 3 depicts an exemplary visualization of the intermediate steps of performing a modified Suurballe algorithm based on a distance histogram. In this regard, the modified Suurballe algorithm begins with the first operation: finding a shortest path tree from the src node 1702A to all nodes in the graph 1700. Since all weights in the graph 1700 are non-negative, a Dijkstra algorithm (or a similar shortest path algorithm) can be implemented for this purpose. In this regard, the Dijkstra algorithm returns a shortest path tree from the src node 1702A to all graph nodes, as well as the distances from the source node to all graph nodes along the tree path (i.e., the sum of all weights along the path). In some embodiments, the edges traversed from the src node 1702A to the tar node 1702B are recorded for subsequent processing. As shown, the path from src node 1702A to tar node 1702B is embodied as a traversal from src 1702A to ee input node 1704A to ee output node 1704B to intermediate node 1708A to oo input node 1706C (optionally through intermediate eo nodes 1710A-1710C) to oo output node 1706D and finally to tar 1702B. Figure 19 A visualization of the first identified shortest path tree is depicted, with the shortest path src 1702A to tar 1702B identified in bold.

[0290] Each graph node is associated with a particular distance (eg, the shortest distance) from the src node 1702A to the particular node. For example, distance d1 is 0 (e.g., empty mapping), which is the distance from src node 1702A to pair node (7, 24) 1708A; distance d2 is {21:1, 19:-2, 17:1, 15:-1, 13:1, 6:-1, 4:1, 3:1, 1:-1}, which is equivalent to w5, which is the distance from src node 1702A to pair node (15, 0) 1708B; and distance d3 is {21:1, 19:-2, 17:1, 9:-1, 8:1, 7:1, 6:-1, 5: -1, 4:1, 3:2, 2:-1, 1:-1}, which is equivalent to w6, which is the distance from src node 1702A to pair node (21, 23) 1706E. Because other weights are zero after these particular nodes, d1 represents the distance to nodes 1710A, 1710B, 1710C, 1706C, 1706D, and 1702B. Similarly, d2 represents the distance to nodes 1706A and 1706B, and d3 represents the distance to node 1706F. As further described herein, such distances to all nodes in the graph (of which d1, d2, and d3 are examples) are utilized when reweighting the edges of graph 1700.

[0291] In the second operation, after identifying the shortest path tree, the graph weight from each node (u) to the subsequent node (v) is updated according to the following formula:

[0292] weight(u→v)=weight(u→v)+dist(u)–dist(v),

[0293] Where dist(x) is the distance from the src node 1702A to the node x in the shortest path tree. Figure 20 Depicted is a diagram having a structure based on the above with respect to Figure 19 A visualization of the processed portion of the diagram 1700 depicting the identified shortest path tree and updated weights for the shortest paths as depicted and described. As depicted, all weights included in the shortest paths are updated to have zero weight. Edges that are not in the shortest path tree ( Figure 20 ), including edges that previously had zero weights being updated accordingly. For example, as depicted, weights w7 and w8 become non-zero and have the following values. Similarly, w2, w3, and w4 are updated to have the following values:

[0294] w2: {21:1,19:-2,17:1,5:-1,3:2,1:-1}

[0295] w3: {15:1,14:-1,9:-1,7:1,6:1,5:-1}

[0296] w4: {15:1,14:-1,7:-1,6:1,3:-1,1:1}

[0297] w7=d2-d1:{21:1,19:-2,17:1,15:-1,13:1,6:-1,4:1,3:1,1:-1}

[0298] w8=d3-d1: {21:1,19:-2,17:1,9:-1,8:1,7:1,6:-1,5:-1,4:1,3:2,2:-1, 1:-1}

[0299] In a third operation, after completing the reweighting of the edges in the graph 1700, the embodiment makes the edges found in the most recently performed operation for finding the shortest path tree as relative to Figure 18 and Figure 19 The directions of the depicted and described shortest paths are opposite. Figure 21 Describes the Figure 18 A visualization of the processed portion of the graph 1700 of the first identified shortest path for the depicted and described path reversal. As depicted, the new reverse edges are depicted in bold. Based on the previously performed reweighting, the weights of all edges along the reverse path remain zero.

[0300] The algorithm then completes this iteration and continues by finding the next shortest path tree in the modified graph 1700, recording the edge of the shortest path from src 1702A to tar 1702B, reweighting the graph, and reversing the shortest path for the newly found shortest path until the desired number of shortest paths (e.g., the number of ee pairs in ee pair set 1754A) is determined. In the final iteration, it should be understood that some embodiments may not reweight the graph or reverse the shortest path.

[0301] Relative to the ongoing example, as in Figure 17A and Figure 17B As depicted and described, FIG. 22 depicts the next shortest path tree identified during the second iteration of the Suurballe algorithm. The shortest path from src 1702A to tar 1702B is similarly depicted in bold. In addition, as Figure 22 As depicted, the shortest path is associated with a distance d4, which is {21:1, 19:-2, 17:1, 15:-1, 13:1, 6:-1, 4:1, 3:1, 1:-1}. This distance d4 is similarly used to update the edges of the previously updated graph 1700 in the manner described herein. Subsequently, Figure 22The edges of the depicted path are also reversed in the manner described herein, and the final iteration begins. For brevity, the intermediate steps of reweighting the graph and reversing the path are omitted, as they follow the path relative to Figure 20 and Figure 21 Same process as depicted and described.

[0302] Figure 23A The final shortest path tree identified during the third and final iteration of the Suurballe algorithm, given an ee-pair set 1704A having three ee-pairs, is depicted. The shortest path from source 1702A to target 1702B is similarly depicted in bold. The depicted shortest path traverses the edges in the reverse direction of the path traversed in the previous iteration, specifically, the path between oo input node 1706A associated with oo pair (1,9) and intermediate node 1708B associated with oe pair (15,0), and the path between intermediate node 1708B associated with oe pair (15,0) and ee output node 1704F associated with ee pair (14,20).

[0303] After completing all iterations and finding all shortest path trees, the implementation scheme merges the paths by removing all edges that were traversed the same number of times in both directions from the set of all edges traversed in all paths. As described in the example being used herein, edges are traversed in the reverse direction in the identified third path and were previously traversed in the forward direction in the identified second path. These edges are associated with traversing from the oo input node 1706A associated with the oo pair (1,9) to the intermediate node 1708B associated with the oe pair (15,0), and from the intermediate node 1708B associated with the oe pair (15,0) to the ee output node 1704F associated with the ee pair (14,20). Therefore, such edges are removed from the set of edges. The remaining set of edges forms a set of node-disjoint paths from src to tar, whose characteristic is that the sum of the weights along all paths is the minimum weight. For processing at this stage, the implementation scheme ignores src node 1702A and tar node 1702B. The result is a unique pair-disjoint path from every ee pair to an oo pair.

[0304] Figure 23B A visualization of merged paths is shown in an exemplary graph 1700 according to at least one exemplary embodiment of the present disclosure. For example, with respect to an ongoing example for processing a starting location pairing set 1752, the path set includes:

[0305] {Path 1: (2,6)→(7,24)→(25,4)→(5,12)→(13,10)→(3,11),

[0306] Path 2: (8,22)→(1,9)

[0307] Path 3: (14,20) → (21,23)

[0308] The swaps indicated in each path form a set of swap commands that can be executed within a single phase of the even-odd transposition order.

[0309] In some embodiments, to further improve the worst-case scenario, the embodiments further process each closed loop path individually to determine whether swapping the pairs represented in the closed loop path reduces the delta cost of the newly formed pairs relative to the original pairs (e.g., thereby improving the overall worst-case efficiency of such ordering).

[0310] Figure 24 An exemplary visualization of a processing closed loop path according to at least one exemplary embodiment of the present disclosure is depicted. As described herein, the closed loop path includes nodes 1712A, 1712B, and 1712C corresponding to the oe pairs (27, 16), (17, 18), and (19, 26), respectively, representing the original pair set 2402A. In this regard, the closed loop path is formed so that each pair is adjacent to each other, and the last element of the last pair is also adjacent to the first element of the first pair and coincides with the sorting phase to be performed (e.g., an even phase as depicted, but in other specific implementations, the odd phase is the first sorting phase). In this regard, if the embodiment determines that the correspondence in the closed loop path is swapped, each even position is swapped with its next adjacent odd position in the loop, including the last pair looping back to the first pair. In this regard, the original pair set 2402A can be swapped to generate a corresponding swapped pair set 2402B.

[0311] The weights associated with the elements of the closed loop path may be determined in the same manner as those discussed above with respect to the remainder of Figure 1700. As depicted, the original pair set 2402A of closed loop paths is associated with a set of distance calculations (e.g., weights) including {abs(27-16), abs(17-18), abs(19-26)}, respectively, resulting in the values ​​{11, 1, 7}. A corresponding distance histogram 2406A is generated by mapping each occurrence of a particular value in the distance calculation set 2404A to a histogram, resulting in {11:1, 7:1, 1:1}. The distance histogram 2406A of the original pair set 2402A may be referred to as h0 in the context of this figure.

[0312] After performing the swaps (e.g., for swap pair set 2402B), a distance histogram is similarly determined. As depicted, the swap pair set is represented as 2402B and includes {(26, 17), (16, 19), (18, 17)}. The absolute value of the difference between the two positions in the swap pair is again used to determine the distance of each segment of the swap path. Thus, the corresponding distance calculation set 2406B for swap pair set 2402B is indicated as swap sw1 to swap sw3, respectively, and includes {abs(26-17), abs(16, 19), abs(18-27)}, resulting in the values ​​{9, 3, 9}. The corresponding distance histogram 2406B is generated by mapping each occurrence of a particular value in the distance calculation set 2404B for swap pair set 2402B to a histogram, resulting in {9:2, 3:1} (e.g., the value 9 appears twice and the value 3 appears once). The histogram corresponding to the swap pair set 2402B may be referred to as h1.

[0313] Using the distance histograms for each of sets 2402A and 2402B, a resulting difference distance histogram 2408 corresponding to a closed loop path can be determined by subtracting histogram h0 from h1 (e.g., difference distance histogram 2408 = distance histogram 2406B - distance histogram 2406A). As depicted, the resulting difference distance histogram 2408 includes {11:-1, 9:2, 7:-1, 3:1, 1:-1}.

[0314] From this difference distance histogram 2408, an embodiment may determine that h < 0 because the maximum value (11) has a negative count, making the path beneficial for the overall improvement of the worst case. Therefore, some such embodiments determine that performing such a swap is beneficial and will include such a swap command in the single-step parallel swap commands generated thereby.

[0315] It should be understood that each closed loop path can be processed separately. In this regard, where multiple independent closed loop paths are identified, some such embodiments may process each closed loop path to determine whether the closed loop path results in an improvement (e.g., negative h) or a cost. Each closed loop path that results in an improvement over the worst case can be processed as part of a generated single-stage parallel exchange command.

[0316] Figure 25 Depicted is an exemplary visualization of an original starting position pairing set, a corresponding initial swap command, and a converted even-odd starting position pairing set. Specifically, Figure 25 Describes the relative Figure 17A 、 Figure 17B and Figures 18 to 24The depicted and described process is for the initial exchange commands generated by the original starting position pairing set 1702 .

[0317] The initial swap command set 2504 includes all swaps included in the identified merged graph of the shortest path determined using the modified Suurballe algorithm implementation described herein. As depicted and described, such a path includes single-phase swap commands consistent with an even-odd transposition order (e.g., {(4,5),(6,7),(8,9),(10,11),(12,13),(20,21),(24,25)}. Further determination is made with respect to Figure 24 The closed loop path depicted and described to produce an improvement over the worst case scenario further includes {(16, 17), (18, 19), (26, 27)} swaps in the set, resulting in {(4, 5), (6, 7), (8, 9), (10, 11), (12, 13), (16, 17), (18, 19), (20, 21), (24, 25), (26, 27)}. In this regard, the initial swap command set 2504 includes all single-phase swaps that minimize the worst-case distance. Some embodiments herein may generate an algorithmic swap command set that performs the swaps indicated in the initial swap command set 2504 in a first step and then sorts the starting position pairing set 1702.

[0318] For example, the initial swap command converts the original starting position pair set 1702 to the even-odd starting position pair set 2506. Thus, the even-odd pair set is converted to the even-odd starting position pair set 2506 via the present disclosure, for example, with respect to FIG. Figure 15B 、 Figure 16A and Figure 16B Any of the processes described satisfies all requirements for target allocation.In this regard, the even-odd starting position pairing set 2506 can therefore be subsequently used for target allocation.

[0319] In some embodiments, an initial swap command is applied to a target vector (e.g., a target set of qubit positions) resulting from a target assignment to undo the initial swap command required to convert from an arbitrary set of starting position pairings (which includes any number of ee pairs and oo pairs) to an even-odd set of starting position pairings. The resulting target vector after reapplying the initial swap command is then sorted using an even-odd permutation sort as described herein to identify a set of algorithmic swap commands representing the steps for sorting the target vector.

[0320] In some embodiments, as described herein, this process can be performed twice, once using the even phase as the even-odd transposition to sort only the first phase in the odd positions (e.g., as reflected in the target_slots vector), and once using the odd phase as the even-odd transposition to sort only the first phase in the odd positions (as reflected in only the odd positions in the target_slots vector). As described, the two target vectors are sorted to obtain the sorting steps, and the target vector with the fewer sorting steps can be selected.

[0321] Figure 26 An exemplary flow chart of operations for target allocation, for example, in an exemplary process of compiling instructions for at least one time slice, according to at least one exemplary embodiment of the present disclosure is shown. In this regard, the exemplary operations are depicted and described from the perspective of the controller 30. In this regard, the controller 30 may be comprised of any number of computing devices (e.g., as described herein with respect to Figure 2 The apparatus 200 is embodied in the apparatus 200 depicted and described herein. The apparatus 200 may be configured to communicate with any number of other devices and / or systems (e.g., computing entity 10 and / or other components of quantum computer 102). In this regard, each operation will be described from the perspective of controller 30 embodied by the specifically configured apparatus 200.

[0322] The illustrated process begins at operation 2602. In some embodiments, the process begins as the first operation of any process. In other embodiments, the process begins after one or more of the operations depicted and / or described with respect to a process in other processes described herein. For example, in some of the embodiments described, the process begins after performing operation 704. In this regard, the process may replace or supplement one or more of the blocks depicted and / or described with respect to a process in other processes described herein. Additionally or alternatively, in some embodiments, after completing Figure 26 After the process described in , the process ends. Alternatively, in other embodiments, the process can return to one or more operations in the operations of another process, such as operation 706.

[0323] At operation 2602, apparatus 200 identifies a starting position pairing set. For example, apparatus 200 includes means for identifying a starting position pairing set, such as qubit instruction processing module 210, input / output module 206, communication module 208, processor 202, or the like, or a combination thereof. The starting position pairing set may include pairs of qubit positions to be gated at a particular time slice, such as pairs of positions determined from a quantum circuit. The starting position pairing set may be in any of a variety of formats, such as an eo-specific format, an arbitrary format (which may include ee pairs or oo pairs), or the like.

[0324] At operation 2604, apparatus 200 determines whether the starting position pairing set satisfies the only-even-odd constraint. For example, apparatus 200 includes means for determining whether the starting position pairing set satisfies the only-even-odd constraint, such as qubit instruction processing module 210, input / output module 206, communication module 208, processor 202, or the like, or a combination thereof. In some embodiments, apparatus 200 iterates through the starting position pairing set and tests whether each position pair includes an even position and an odd position, thereby representing an eo pair.

[0325] At operation 2606, the apparatus 200 generates a target time slot vector based at least in part on the starting position pairing set. For example, the apparatus 200 includes means for generating the target time slot vector based at least in part on the starting position pairing set, such as the qubit instruction processing module 210, the input / output module 206, the communication module 208, the processor 202, or the like, or a combination thereof. In some embodiments, the apparatus 200 generates the target time slot vector using a specific time slot determination algorithm, as described herein. In some embodiments, the apparatus 200 fixes even time slots (and / or even positions) and assigns the target time slot vector to odd time slots and / or positions. In other embodiments, the apparatus 200 fixes odd time slots (and / or odd positions) and assigns the target time slot vector to even time slots and / or positions.

[0326] At operation 2608, the apparatus 200 determines a target time slot midpoint vector by sorting the target time slot vector using an even-odd permutation order. For example, the apparatus 200 includes means for sorting the target time slot vector using an even-odd permutation order to determine the target time slot midpoint vector, such as the qubit instruction processing module 210, the input / output module 206, the communication module 208, the processor 202, or the like, or a combination thereof. In some embodiments, the target time slot vector is sorted using an even-odd permutation order, and the target time slot vector is sorted using an even-odd permutation order as described herein with respect to Figure 13 、 Figure 14 、 Figure 15A 、 Figure 15B , Figure 16A and Figure 16B The target time slot midpoint vector is identified in the manner described.

[0327] At operation 2610, apparatus 200 generates a target set of qubit positions based at least in part on the target time slot midpoint vector. For example, apparatus 200 includes means for generating a target set of qubit positions based at least in part on the target time slot midpoint vector, such as qubit instruction processing module 210, input / output module 206, communication module 208, processor 202, or the like, or a combination thereof. For example, in some embodiments, apparatus 200 assigns values ​​in the target time slot midpoint vector to indices of the target set of qubit positions that represent the target vector based on the values ​​in the target time slot midpoint vector. Figure 15A Figure 15B Figure 16A and Figure 16B Non-limiting examples of such target qubit position set generation are described.

[0328] Figure 27 An exemplary flow chart of operations for target allocation, for example, in an exemplary process of compiling instructions for at least one time slice, according to at least one exemplary embodiment of the present disclosure is shown. In this regard, the exemplary operations are depicted and described from the perspective of the controller 30. In this regard, the controller 30 may be comprised of any number of computing devices (e.g., as described herein with respect to Figure 2 The apparatus 200 is embodied in the apparatus 200 depicted and described herein. The apparatus 200 may be configured to communicate with any number of other devices and / or systems (e.g., computing entity 10 and / or other components of quantum computer 102). In this regard, each operation will be described from the perspective of controller 30 embodied by the specifically configured apparatus 200.

[0329] The process shown begins at operation 2702. In some embodiments, the process begins as the first operation of any process. In other embodiments, the process begins after one or more of the operations depicted and / or described with respect to a process in other processes described herein. For example, in some of the embodiments described, the process begins after performing operation 2606. In this regard, the process may replace or supplement one or more of the blocks depicted and / or described with respect to a process in other processes described herein. Additionally or alternatively, in some embodiments, after completing Figure 27 After the process described in , the process ends. Alternatively, in other embodiments, the process can return to one or more operations in the operations of another process, such as operation 2610.

[0330] At operation 2702, the apparatus 200 assigns a fixed time slot from the set of available time slots to each even position in the set of starting position pairings. For example, the apparatus 200 includes a device for assigning a fixed time slot from the set of available time slots to each even position in the set of starting position pairings, such as the qubit instruction processing module 210, the input / output module 206, the communication module 208, the processor 202, or the like, or a combination thereof. The time slots may be assigned using a specific time slot determination algorithm. Alternatively, in some embodiments, the apparatus 200 assigns a fixed time slot from the set of available time slots to each odd position in the set of starting position pairings. Figure 14 、 Figure 15A and Figure 16A Non-limiting examples of time slot allocation are described.

[0331] At operation 2704, the apparatus 200 sorts the target time slot vector to achieve parity between the time slot value of each odd position and the fixed time slot of the even position associated with the odd position. For example, the apparatus 200 includes a means for sorting the target time slot vector to achieve parity between the time slot value of each odd position and the fixed time slot of the even position associated with the odd position, such as the qubit instruction processing module 210, the input / output module 206, the communication module 208, the processor 202, etc. or a combination thereof. In some embodiments, the apparatus 200 sorts the target time slot vector using an even-odd transposition sort, as described herein. Figure 15A and Figure 16A A non-limiting example of ordering target slot vectors to achieve parity (eg, equivalent to a common column property) is described.

[0332] Figure 28 An exemplary flow chart of operations for target allocation, for example, in an exemplary process of compiling instructions for at least one time slice, according to at least one exemplary embodiment of the present disclosure is shown. In this regard, the exemplary operations are depicted and described from the perspective of the controller 30. In this regard, the controller 30 may be comprised of any number of computing devices (e.g., as described herein with respect to Figure 2 The apparatus 200 is embodied in the apparatus 200 depicted and described herein. The apparatus 200 may be configured to communicate with any number of other devices and / or systems (e.g., computing entity 10 and / or other components of quantum computer 102). In this regard, each operation will be described from the perspective of controller 30 embodied by the specifically configured apparatus 200.

[0333] The illustrated process begins at operation 2802. In some embodiments, the process begins as the first operation of any process. In other embodiments, the process begins after one or more of the operations depicted and / or described with respect to a process in other processes described herein. For example, in some of the embodiments described, the process begins after performing operation 2610. In this regard, the process may replace or supplement one or more of the blocks depicted and / or described with respect to a process in other processes described herein. Additionally or alternatively, in some embodiments, after completing Figure 28 After the process described in , the process ends. Alternatively, in other embodiments, the process can return to one or more operations in the operations of another process, such as operation 2610.

[0334] At operation 2802, apparatus 200 identifies an original starting position pairing set corresponding to a set of qubit pairings. For example, apparatus 200 includes means for identifying the original starting position pairing set corresponding to the set of qubit pairings, such as qubit instruction processing module 210, input / output module 206, communication module 208, processor 202, or the like, or a combination thereof. The original starting position pairing set may not satisfy one or more applicable constraints, for example, because it may be based solely on qubits to be paired at the time slice to be processed. The original starting position pairing set may be parsed and / or otherwise extracted from the quantum circuit, as described herein. In some embodiments, the original starting position pairing set is embodied by the set of qubit pairings.

[0335] At operation 2804, the apparatus 200 determines that the original starting position pairing set does not satisfy the only even-odd constraint. For example, the apparatus 200 includes means for determining that the original starting position pairing set does not satisfy the only even-odd constraint, such as the qubit instruction processing module 210, the input / output module 206, the communication module 208, the processor 202, or the like, or a combination thereof. The apparatus 200 may examine each position pair in the original starting position pairing set to identify one or more ee pairs and / or oo pairs. Alternatively or additionally, in some embodiments, the apparatus 200 processes the original starting position pairing set to determine that the original starting position pairing set does not satisfy one or more prerequisite (e.g., additional prerequisite) constraints, such as an evenness constraint or a completeness constraint as described herein.

[0336] At operation 2806, the apparatus 200 converts the original starting position pairing set into a starting position pairing set that satisfies only the even-odd constraint by applying the original starting position pairing set to the modified Suurballe algorithm. For example, the apparatus 200 includes a device for converting the original starting position pairing set into a starting position pairing set that satisfies only the even-odd constraint by applying the original starting position pairing set to the modified Suurballe algorithm, such as the qubit instruction processing module 210, the input / output module 206, the communication module 208, the processor 202, etc. or a combination thereof. In some embodiments, the modified Suurballe algorithm includes or is otherwise configured to generate a plurality of difference distance histograms. Additionally or alternatively, in some embodiments, the modified Suurballe algorithm includes or is configured to convert the original starting position pairing set based on the plurality of difference distance histograms. In this document relative to Figure 17A 、 Figure 17B and Figures 18 to 25 A non-limiting example of utilizing a modified Suurballe algorithm to transform a raw set of starting position pairs is described.

[0337] Figure 29 An exemplary flow chart of operations for target allocation, for example, in an exemplary process of compiling instructions for at least one time slice, according to at least one exemplary embodiment of the present disclosure is shown. In this regard, the exemplary operations are depicted and described from the perspective of the controller 30. In this regard, the controller 30 may be comprised of any number of computing devices (e.g., as described herein with respect to Figure 2 The apparatus 200 is embodied in the apparatus 200 depicted and described herein. The apparatus 200 may be configured to communicate with any number of other devices and / or systems (e.g., computing entity 10 and / or other components of quantum computer 102). In this regard, each operation will be described from the perspective of controller 30 embodied by the specifically configured apparatus 200.

[0338] The process shown begins at operation 2902. In some embodiments, the process begins as the first operation of any process. In other embodiments, the process begins after one or more of the operations depicted and / or described with respect to a process in other processes described herein. For example, in some of the embodiments described, the process begins after performing operation 2602. In this regard, the process may replace or supplement one or more of the blocks depicted and / or described with respect to a process in other processes described herein. Additionally or alternatively, in some embodiments, after completing Figure 29After the process described in , the process ends. Alternatively, in other embodiments, the process can return to one or more operations in the operation of another process, such as operation 2604.

[0339] At operation 2902, the apparatus 200 determines that the original starting position pairing set does not satisfy at least one additional constraint. For example, the apparatus 200 includes means for determining that the original starting position pairing set does not satisfy at least one additional constraint, such as the qubit instruction processing module 210, the input / output module 206, the communication module 208, the processor 202, or the like, or a combination thereof. In some embodiments, the apparatus 200 performs one or more algorithmic processes to check whether the original starting position pairing set satisfies the evenness constraint and / or the completeness constraint, as described herein. If the apparatus 200 determines that the original starting position pairing set satisfies both additional constraints (and / or any other constraints required by the apparatus 200), the apparatus 200 may continue processing the original starting position pairing set to determine whether the set satisfies only the even-odd constraint and / or proceed with the target allocation.

[0340] At operation 2904, apparatus 200 updates the original starting position pairing set to satisfy the at least one additional constraint. For example, apparatus 200 includes means for updating the original starting position pairing set to satisfy the at least one additional constraint, such as qubit instruction processing module 210, input / output module 206, communication module 208, processor 202, or the like, or a combination thereof. In some embodiments, for example, apparatus 200 allocates one or more new positions to pair with in the original starting position pairing set. Such new positions may be used to satisfy the integrity constraint. Additionally or alternatively, in some embodiments, the original starting position pairing set is updated with the new position pairs. For example, apparatus 200 may generate new position pairs for unused positions that were not previously in the original starting position pairing set to satisfy the integrity constraint. Alternatively or additionally, in some embodiments, vacant positions may be created to satisfy the evenness constraint.

[0341] Figure 30 An exemplary flow chart of operations for target allocation, for example, in an exemplary process of compiling instructions for at least one time slice, according to at least one exemplary embodiment of the present disclosure is shown. In this regard, the exemplary operations are depicted and described from the perspective of the controller 30. In this regard, the controller 30 may be comprised of any number of computing devices (e.g., as described herein with respect to Figure 2The apparatus 200 is embodied in the apparatus 200 depicted and described herein. The apparatus 200 may be configured to communicate with any number of other devices and / or systems (e.g., computing entity 10 and / or other components of quantum computer 102). In this regard, each operation will be described from the perspective of controller 30 embodied by the specifically configured apparatus 200.

[0342] The illustrated process begins at operation 3002. In some embodiments, the process begins as the first operation of any process. In other embodiments, the process begins after one or more of the operations depicted and / or described with respect to a process in other processes described herein. For example, in some of the embodiments described, the process begins after performing operation 2610. In this regard, the process may replace or supplement one or more of the blocks depicted and / or described with respect to a process in other processes described herein. Additionally or alternatively, in some embodiments, after completing Figure 30 After the process described in , the process ends. Alternatively, in other embodiments, the process can return to one or more operations in the operations of another process, such as operation 2610.

[0343] At operation 3002, the apparatus 200 determines a second target time slot midpoint vector by sorting the target time slot vector starting with a second phase. For example, the apparatus 200 includes means for determining the second target time slot midpoint vector by sorting the target time slot vector starting with a second phase, such as the qubit instruction processing module 210, the input / output module 206, the communication module 208, the processor 202, or the like, or a combination thereof. The second phase can be opposite to the first phase used to generate the first target qubit position set. For example, in some embodiments, the apparatus 200 generates the first target qubit position set by sorting the target time slot vector starting with an even phase, and then performs sorting starting with an odd-numbered sorting phase. Alternatively, in other embodiments, the apparatus 200 generates the first target qubit position set by sorting the target time slot vector starting with an odd phase, and then performs sorting starting with an even-numbered sorting phase.

[0344] At operation 3004, apparatus 200 generates a second set of target qubit positions based at least in part on the target time slot midpoint vector, the second set of target qubit positions being in addition to the previously generated first set of target qubit positions. For example, apparatus 200 includes means, such as qubit instruction processing module 210, input / output module 206, communication module 208, processor 202, or the like, or a combination thereof, for generating the second set of target qubit positions based at least in part on the target time slot midpoint vector, the second set of target qubit positions being in addition to the previously generated first set of target qubit positions. The first set of target qubit positions may have been previously generated at an ordering phase that is opposite to the second phase. It will be appreciated that the second set of target qubit positions is generated using the second target time slot midpoint vector in a manner similar to that described with respect to block 2610. Figure 15A 、 Figure 15B 、 Figure 16A and Figure 16B Non-limiting examples of these two target slot vectors are described.

[0345] At operation 3006, apparatus 200 sorts the first set of target qubit positions using an even-odd transposition ordering to generate a first set of algorithmic exchange commands. For example, apparatus 200 includes means for sorting the first set of target qubit positions using an even-odd transposition ordering to generate a first set of algorithmic exchange commands, such as qubit instruction processing module 210, input / output module 206, communication module 208, processor 202, or the like, or a combination thereof. The first set of algorithmic exchange commands identifies all parallel exchanges to be performed based on the even-odd transposition ordering. Figures 4 to 12 Non-limiting examples of such ordering are described.

[0346] At operation 3008, apparatus 200 sorts the second set of target qubit positions using an even-odd permutation ordering to generate a second set of algorithmic exchange commands. For example, apparatus 200 includes means for sorting the second set of target qubit positions using an even-odd permutation ordering to generate a second set of algorithmic exchange commands, such as qubit instruction processing module 210, input / output module 206, communication module 208, processor 202, or the like, or a combination thereof. It should be understood that the second set of target qubit positions is generated in a manner similar to that generated at block 3008. However, based on the difference between the first set of target qubit positions and the second set of target qubit positions, the resulting first and second sets of algorithmic exchange commands differ in the required number of parallel exchanges. In this regard, each set of algorithmic exchange commands may include a different number of steps, as described herein.

[0347] At operation 3010, the apparatus 200 compares the first number of steps represented by the first algorithm exchange command set and the second number of steps represented by the second exchange command set. For example, the apparatus 200 includes a device for comparing the first number of steps represented by the first algorithm exchange command set and the second number of steps represented by the second exchange command set, such as the qubit instruction processing module 210, the input / output module 206, the communication module 208, the processor 202, etc., or a combination thereof. In this regard, the apparatus 200 may determine which algorithm exchange command set includes fewer steps (e.g., fewer algorithm exchange commands including parallel exchanges). Figures 5 to 12 、 Figure 15A and Figure 15B A non-limiting example of the stages of even-odd transposition sorting is described.

[0348] At operation 3012, apparatus 200 selects a first set of target qubit positions or a second set of target qubit positions based on a comparison between the first number of steps and the second number of steps. For example, apparatus 200 includes means for selecting the first set of target qubit positions or the second set of target qubit positions based on a comparison between the first number of steps and the second number of steps, such as qubit instruction processing module 210, input / output module 206, communication module 208, processor 202, etc., or a combination thereof. In some embodiments, apparatus 200 selects a set of target qubit positions that results in a smaller number of steps (e.g., a stage of an even-odd transposition ordering). Apparatus 200 may then implement instructions for performing the parallel swaps represented by the set of target qubit positions associated with the smaller number of steps. Figure 15A 、 Figure 15B 、 Figure 16A and Figure 16B Non-limiting examples of selecting a target set of qubit positions based on a small number of steps are described.

[0349] in conclusion

[0350] Although an exemplary processing system has been described above, specific implementations of the subject matter and functional operations described herein may be realized in other types of digital electronic circuitry, or in computer software, firmware, or hardware (including the structures disclosed in this specification and their structural equivalents), or in combinations of one or more of them.

[0351] The embodiments of the subject matter and operations described herein may be implemented in digital electronic circuits, or in computer software, firmware, or hardware (including the structures disclosed in this specification and their structural equivalents), or in a combination of one or more thereof. The embodiments of the subject matter described herein may be implemented as one or more computer programs (i.e., one or more modules of computer program instructions) encoded on a computer storage medium for execution by an information / data processing device or for controlling the operation of an information / data processing device. Alternatively or in addition, program instructions may be encoded on an artificially generated propagated signal (e.g., a machine-generated electrical, optical, or electromagnetic signal) that is generated to encode information / data for transmission to a suitable receiver device for execution by the information / data processing device. The computer storage medium may be a computer-readable storage device, a computer-readable storage substrate, a random or serial access memory array or device, or a combination of one or more thereof, or may be included in a computer-readable storage device, a computer-readable storage substrate, a random or serial access memory array or device, or a combination of one or more thereof. Furthermore, although a computer storage medium is not a propagated signal, a computer storage medium may be a source or destination of computer program instructions encoded in an artificially generated propagated signal. The computer storage medium can also be, or be included in, one or more separate physical components or media (eg, multiple CDs, disks, or other storage devices).

[0352] The operations described herein may be implemented as operations performed by an information / data processing apparatus on information / data stored on one or more computer-readable storage devices or received from other sources.

[0353] The term "data processing apparatus" encompasses all types of apparatus, equipment, and machines for processing data, including, for example, a programmable processor, a computer, a system on a chip, or a plurality of the foregoing or a combination thereof. The apparatus may include dedicated logic circuitry (e.g., an FPGA (field programmable gate array) or an ASIC (application-specific integrated circuit)). In addition to hardware, the apparatus may also include code that creates an execution environment for the computer program in question (e.g., code constituting processor firmware, a protocol stack, a repository management system, an operating system, a cross-platform runtime environment, a virtual machine, or a combination of one or more thereof). The apparatus and execution environment may implement a variety of different computing model infrastructures, such as web services, distributed computing infrastructures, and grid computing infrastructures.

[0354] A computer program (also referred to as a program, software, software application, script, or code) may be written in any form of programming language (including compiled or interpreted languages, declarative languages, or procedural languages) and may be deployed in any form, including as a stand-alone program or as a module, component, subroutine, object, or other unit suitable for use in a computing environment. A computer program may, but need not, correspond to a file in a file system. A program may be stored in a portion of a file that holds other programs or information / data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program in question, or in multiple coordinated files (e.g., files that store portions of one or more modules, subroutines, or code). A computer program may be deployed to execute on one computer or multiple computers located at one site or distributed across multiple sites and interconnected by a communications network.

[0355] The processes and logic flows described herein can be performed by one or more programmable processors executing one or more computer programs to perform actions by operating on input information / data and generating output. By way of example, processors suitable for executing computer programs include both general-purpose microprocessors and special-purpose microprocessors and any one or more processors of any type of digital computer. Generally speaking, the processor will receive instructions and information / data from a read-only memory or a random access memory or both. The basic elements of a computer are a processor for performing actions according to instructions and one or more memories for storing instructions and data. Generally speaking, a computer will also include one or more mass storage devices (e.g., magnetic disks, magneto-optical disks, or optical disks) for storing data, or be operably connected to the one or more mass storage devices to receive information / data from the one or more mass storage devices or to transfer information / data to the one or more mass storage devices, or both. However, a computer does not need to have such devices. Devices suitable for storing computer program instructions and information / data include all forms of non-volatile memory, media, and storage devices, including, by way of example, semiconductor memory devices such as EPROM, EEPROM, and flash memory devices; magnetic disks, such as internal hard disks or removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks. The processor and memory can be supplemented by, or incorporated in, special purpose logic circuitry.

[0356] To provide for interaction with a user, embodiments of the subject matter described herein may be implemented on a computer having a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information / data to the user, as well as a keyboard and pointing device (e.g., a mouse or trackball through which the user can provide input to the computer). Other types of devices may also be used to provide for interaction with the user; for example, the feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form, including sound, voice, or tactile input. Furthermore, the computer may interact with the user by sending data, files, documents, etc. to and receiving data, files, documents, etc. from a device used by the user; for example, by sending a web page to a web browser in response to a request received from a web browser on the user's client device.

[0357] Embodiments of the subject matter described herein may be implemented in a computing system that includes a back-end component (e.g., as an information / data server), or includes a middleware component (e.g., an application server), or includes a front-end component (e.g., a client computer with a graphical user interface or web browser through which a user can interact with a specific implementation of the subject matter described herein), or any combination of one or more such back-end components, middleware components, or front-end components. The components of the system may be interconnected by any form or medium of digital information / data communication (e.g., a communication network). Examples of communication networks include local area networks ("LANs") and wide area networks ("WANs"), internetworks (e.g., the Internet), and peer-to-peer networks (e.g., ad hoc peer-to-peer networks).

[0358] The computing system may include a client and a server. The client and the server are generally remote from each other and typically interact via a communication network. The relationship between the client and the server is obtained by means of computer programs running on respective computers that have a client-server relationship with each other. In some embodiments, the server transmits information / data (e.g., an HTML page) to a client device (e.g., for displaying information / data to a user interacting with the client device and receiving user input from the user interacting with the client device). Information / data (e.g., results of user interactions) generated at the client device can be received at the server from the client device.

[0359] Although this specification includes many specific implementation details, these details should not be interpreted as limiting the scope of any disclosure or claimable content, but should be interpreted as descriptions of features that are specific to a particular disclosed embodiment. Certain features described herein in the context of a separate embodiment may also be implemented in combination in a single embodiment. On the contrary, the various features described in the context of a separate embodiment may also be implemented in multiple embodiments or in any suitable sub-combination. In addition, although features may be described above as working in certain combinations and even initially claimed as such, in some cases, one or more features from the claimed combination may be removed from the combination, and the claimed combination may be directed to a sub-combination or a variation of the sub-combination.

[0360] Similarly, although operations are depicted in a particular order in the accompanying drawings, this should not be understood as requiring that such operations be performed in the particular order shown or in a sequential order, or that all of the illustrated operations be performed to achieve the desired results. In some cases, multitasking and parallel processing may be advantageous. Furthermore, the separation of various system components in the above-described embodiments should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems may generally be integrated together in a single software product or grouped into multiple software products.

[0361] Thus, certain embodiments of the present subject matter have been described. Other embodiments are within the scope of the following claims. In some cases, the actions recited in the claims can be performed in a different order and still achieve the desired results. Furthermore, the processes depicted in the accompanying drawings do not necessarily require the particular order or sequential order shown to achieve the desired results. In some implementations, multitasking and parallel processing may be advantageous.

Claims

1. A computer-implemented method for compiling instructions for at least one time slice in a one-dimensional quantum computing environment, the computer-implemented method comprising: identifying an initial set of qubit positions associated with a set of qubits associated with a set of qubit pairings for gating at a first time slice, the set of qubit pairings comprising at least one qubit pair, each qubit pair having a first qubit and a second qubit; identifying, at a first time slice, a target set of qubit positions associated with the set of qubits and the initial set of qubit positions, wherein for each qubit pair, the first qubit is associated with a first target position index in the set of target qubit positions, and the second qubit is associated with a second target position index in the set of target qubit positions, and wherein the first target position index is adjacent to the second target position index; generating an algorithmic swap command set by performing an even-odd transposition ordering based on at least the set of target qubit positions, and A qubit manipulation instruction set is generated based at least on the algorithm exchange command set, the qubit manipulation instruction set comprising a plurality of instructions configured to cause a quantum computer to perform a plurality of qubit manipulations according to the algorithm exchange command set.

2. The computer-implemented method of claim 1 , wherein generating the algorithm exchange command set comprises: determining, while performing the even-odd transposition ordering, that a second qubit pair for gating at the first time slice is associated with a first position index and a second position index, wherein the first position index and the second position index represent adjacent position indices; storing at least one command to perform a logic operation based on at least the second qubit pair; as well as A first updated target qubit position index and a second updated target qubit position index are determined for the second qubit pair, wherein the first updated target qubit position index and the second updated target qubit position index are determined based on a second time slice.

3. The computer-implemented method of claim 1 , wherein: The qubit manipulation instruction set includes any number of qubit swap instructions, any number of qubit split instructions, any number of qubit merge instructions, and any number of qubit shift instructions.

4. The computer-implemented method of claim 3 , further comprising: generating a hardware instruction set based at least on the qubit manipulation instruction set, wherein the hardware instruction set comprises at least one action to be performed by qubit manipulation hardware to position the set of qubits based on the qubit manipulation instruction set; and The hardware instruction set is executed using the qubit manipulation hardware.

5. The computer-implemented method of claim 1 , wherein identifying the set of target qubit positions comprises: identifying a starting set of position pairings corresponding to the set of qubit pairings; generating a target time slot vector based at least in part on the set of starting position pairs; Determining a target time slot midpoint vector by sorting the target time slot vectors using an even-odd transposition order; and The target set of qubit positions is generated based at least in part on the target time slot midpoint vector.

6. The computer-implemented method of claim 5 , further comprising: Determining that the starting position pairing set satisfies a first constraint, wherein the first constraint indicates that each starting position pair in the starting position pairing set includes: a first position that exists in a first subset of equal bipartitions of all positions, and a second position, said second position being present in a second subset of said equal bipartition of all positions, wherein each position in the first subset of the equal bipartition is associated with a unique position in the second subset of the bipartition.

7. The computer-implemented method of claim 6 , wherein generating the target slot vector comprises: assigning a fixed time slot from a set of available time slots to each position in the first subset of the equal dual partition; as well as generating, for each starting position pair including the first position from the first subset of the equal double partition of all positions and the second position from the second subset of the equal double partition of all positions, the target time slot vector including a second time slot representing the second position, the second time slot being generated at an index of the target time slot vector corresponding to the fixed time slot allocated to the first position in the set of available time slots, The determining of the target time slot midpoint vector by sorting the target time slot vectors using an even-odd transposition sorting method includes: For each starting position pair in the set of starting position pairs, the target time slot vector is sorted to achieve a parity check between the second time slot representing the second position and the fixed time slot allocated to the first position.

8. The computer-implemented method of claim 6, further comprising: identifying an original starting position pairing set corresponding to the set of qubit pairings; determining that the original starting position pairing set does not satisfy the first constraint; The original starting position pairing set is converted into the starting position pairing set to satisfy the first constraint by: generating a directed graph based on the original starting position pairing set; and A path selection algorithm is applied to the graph.

9. The computer-implemented method of claim 8, wherein generating the directed graph comprises: generating a first node set, the first node set representing a first subset of pairs from the original starting position pairing set, the first subset of pairs comprising a subset of even-even pairs or a subset of odd-odd pairs from the original starting position pairing set; generating a second node set representing a second subset of pairs from the original starting position pairing set, the second subset of pairs including the other of the subset of even-even pairs or odd-odd pairs from the original starting position pairing set; generating a third node set, the third node set representing a third subset of pairs from the original starting position pairing set, the third subset of pairs comprising a subset of even-odd pairs from the original starting position pairing set, the third set possibly being an empty set if no even-odd pairs exist; generating a first set of directed edges emanating from each first node associated with the first set of nodes to a second node associated with the second set of nodes, wherein the first node is associated with a starting position pair including at least one position adjacent to at least one position of a second starting position pair associated with the second node conforming to the first sorting phase; generating a single source node and a second set of directed edges, the directed edges being from the single source node to each node in the first set of nodes; as well as A single target node and a third set of directed edges are generated, the directed edges from each node in the second set of nodes to the single target node.

10. The computer-implemented method of claim 9, wherein the path selection algorithm comprises a Suurballe algorithm implementation that finds a set of node-disjoint paths from the single source node to the single destination node, the set of node-disjoint paths representing paths from the even-even pairs to the odd-odd pairs in one parallel switch command, wherein the Suurballe algorithm implementation comprises a modified Suurballe algorithm comprising: Edge weights representing a difference distance histogram are generated for one or more of the first set of directed edges, the second set of directed edges, and the third set of directed edges.

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