Superjunction transistor device and method for forming a superjunction transistor device

Abstract

A method for forming a drift region of a superjunction transistor and a superjunction transistor device is disclosed. The method includes: forming a plurality of first regions of a first doping type and a plurality of second regions of a second doping type in a semiconductor body, so that the first regions and the second regions are alternately arranged in the semiconductor body, wherein forming the first regions and the second regions includes: forming a plurality of trenches in at least one semiconductor layer; implanting first-type dopant atoms and second-type dopant atoms into each of the opposite sidewalls of the plurality of trenches; filling the plurality of trenches with semiconductor material; and diffusing the first-type dopant atoms and the second-type dopant atoms in a thermal process, so that the first-type dopant atoms form the first region, and the second-type dopant atoms form the second region. Each of the plurality of trenches has a first width, the trenches are separated by mesa regions, the mesa regions each have a second width, and the first width is greater than the second width.

Description

Technical Field

[0001] The present disclosure generally relates to superjunction transistor devices and methods for forming superjunction transistor devices, and more particularly, for forming a drift region of a superjunction transistor device. Background Art

[0002] The super junction device includes a drift region having at least one first region of a first doping type (conductivity type) and at least one second region of a second doping type (conductivity type) complementary to the first doping type. In some publications, the at least one first doping type region is referred to as a drift region, and the at least one second doping type region is referred to as a compensation region.

[0003] A drift region of a super junction device may include a plurality of first regions and second regions arranged alternately in a semiconductor body. There is a need to form such a drift region in a cost-effective manner. Summary of the invention

[0004] One example relates to a method. The method includes forming a plurality of first regions of a first doping type and a plurality of second regions of a second doping type in a semiconductor body, so that the first regions and the second regions are alternately arranged in the semiconductor body. In this method, forming the first regions and the second regions includes: forming a plurality of trenches in at least one semiconductor layer; implanting a first type of dopant atoms and a second type of dopant atoms into each of the opposite sidewalls of the plurality of trenches; filling the plurality of trenches with a semiconductor material; and diffusing the first type of dopant atoms and the second type of dopant atoms in a thermal process so that the first type of dopant atoms form the first region and the second type of dopant atoms form the second region. Each of the plurality of trenches has a first width, and the trenches are separated by mesa regions, each of the mesa regions having a second width, wherein the first width is greater than the second width.

[0005] Another example relates to a superjunction transistor device. The transistor device includes a drift region having a plurality of first regions of a first doping type and a plurality of second regions of a second doping type in a semiconductor body, wherein the first regions and the second regions are alternately arranged in the semiconductor body. The second regions include wide regions having a first width and narrow regions having a second width, wherein the wide regions and the narrow regions are alternately arranged, and wherein the first width is at least 1.05 times the second width. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The following is an explanation of the examples with reference to the accompanying drawings. The accompanying drawings are used to illustrate certain principles and therefore only illustrate aspects necessary for understanding these principles. The accompanying drawings are not drawn to scale. In the accompanying drawings, the same reference numerals represent similar features.

[0007] Figure 1shows a vertical cross-sectional view of a super junction transistor device according to an example;

[0008] Figure 2 A horizontal cross-sectional view showing an example of a drift region of a superjunction transistor device;

[0009] Figure 3 A flow chart showing one example of a method for forming a drift region;

[0010] Figure 4A and 4B shows vertical cross-sectional views of a first semiconductor layer during different process steps of a method for forming a drift region;

[0011] Figure 5A and 5B shows the top layer after another process step including forming the top layer. Figure 4A and 4B The first semiconductor layer shown in ;

[0012] Figure 6 An example of a semiconductor body including a first semiconductor layer and a top layer is shown;

[0013] Fig. 7A and 7B An example of a semiconductor body comprising several first semiconductor layers and a top layer is shown;

[0014] Figure 8 One example of a method for implanting a first type of dopant atoms and a second type of dopant atoms into a sidewall of a trench in a first semiconductor layer is shown;

[0015] Fig.9A and 9B Another example of a method for implanting a first type of dopant atoms and a second type of dopant atoms into a sidewall of a trench in a first semiconductor layer is shown;

[0016] Figures 10A-10C showing doping profiles of the first and second semiconductor regions of the drift region and the associated electric fields in a blocking state of the transistor device;

[0017] Fig.11 shows doping profiles of first and second semiconductor regions according to another example;

[0018] Fig.12 Shows Figure 1 An example of a control structure for a transistor device shown in;

[0019] Fig.13 Shows Figure 1 Another example of a control structure of a transistor device shown in ; and

[0020] Fig.14 A perspective cross-sectional view of a super junction transistor device according to another example is shown. DETAILED DESCRIPTION

[0021] In the following detailed description, reference is made to the accompanying drawings. The accompanying drawings form part of the specification and for illustrative purposes show examples of how the invention may be used and implemented. It should be understood that the features of the various embodiments described herein may be combined with each other unless explicitly stated otherwise.

[0022] Figure 1 A cross-sectional view of a section of a super junction transistor device is schematically shown. The transistor device includes a semiconductor body 100, wherein the semiconductor body 100 may include a conventional semiconductor material, such as silicon (Si) or silicon carbide (SiC). The transistor device includes a drift region 20 in the semiconductor body 100, and the drift region 20 has a plurality of first regions 21 of a first doping type (conductivity type) and a plurality of second regions 22, 23 of a second doping type (conductivity type) complementary to the first doping type. The first regions 21 and the second regions 22, 23 are alternately arranged in the semiconductor body 100, and a pn junction is formed between each first region 21 and the corresponding adjacent second region 22, 23. For illustrative purposes only, Figure 1 In the example shown in FIG. 1 , first regions 21 and second regions 22 , 23 are arranged alternately in a first lateral direction x of the semiconductor body 100 .

[0023] refer to Figure 1 , the second regions 22, 23 include two different types of second regions, namely wide regions 22 and narrow regions 23, wherein the wide regions 22 and the narrow regions 23 are arranged alternately. In each case, the wide region 22 and the adjacent narrow region 23 are separated by the corresponding first region 21. Transistor devices having wide regions 22 and narrow regions 23 of the second doping type can be produced in an efficient manner, as will be explained in further detail herein below.

[0024] The wide area 22 has a first width w22, and the narrow area 23 has a second width w23 that is smaller than the first width w22. According to one example, the first width w22 is at least 1.05 times the second width w23, w22 ≥ 1.05*w23. According to one example, the first width w22 is at least 1.1 times or at least 1.2 times the second width w23. According to one example, the first width w22 is less than 5 times, 4 times, or 2 times the second width w23.

[0025] refer to Figure 1, each of the first region 21 and the second region 22, 23 extends in a vertical direction z of the semiconductor body, wherein the vertical direction z is substantially perpendicular to the first lateral direction x. For example, the size of the first and second regions 21, 22, 23 in the vertical direction depends inter alia on the desired voltage blocking capability of the transistor device and is selected between tens of micrometers and hundreds of micrometers.

[0026] The respective widths w22, w23 of each of the second regions 22, 23 may vary along the vertical direction z, which may be due to the manufacturing process. In addition, the widths w22 of the individual wide regions 22 may deviate slightly from each other, and the widths w23 of the individual narrow regions 23 may deviate slightly from each other. Thus, according to one example, the width w22 of a single wide region 22 represents the average width of this wide region, and the widths w22 of a plurality of wide regions 22 represent the average width of the average widths of the wide regions 22. In other words, the width w23 of a single narrow region 23 represents the average width of this narrow region, and the widths w23 of a plurality of narrow regions 23 represent the average width of the average widths of the narrow regions 23. Therefore, the width w21 of a single first region 21 represents the average width of the first region, and the widths w21 of a plurality of first regions 21 represent the average width of the average widths of the first regions 21.

[0027] According to an example, the transistor device is implemented so that at each vertical position of the semiconductor body 100, the effective dopant dose of the second type of dopant atoms in the wide region 22 deviates from the effective dopant dose of the second type of dopant atoms in the narrow region 23 by less than 10%, less than 5%, or less than 1%. The “effective dopant dose” at a vertical position of the second region 22, 23 is the integral of the effective (net) doping concentration of the second region 22, 23 in a direction perpendicular to one of the pn junctions formed between the second region 22, 23 and the adjacent first region 21.

[0028] The first and second regions 21, 22, 23 may be elongated in the second lateral direction y of the semiconductor body 100. Figure 2 It is shown in Figure 2 shows a horizontal cross-sectional view of a semiconductor body in a horizontal section AA, which is perpendicular to Figure 1 According to an example, the second transverse direction y is substantially perpendicular to the first transverse direction x. By "elongated" it is meant that the lengths of the first and second regions 21, 22, 23 are significantly greater than the corresponding widths w21, w22, w23. Figure 1 and 2In the example shown in , the widths w21, w22, w23 are dimensions in a first lateral direction x, and the “length” is a dimension in a second lateral direction y of the semiconductor body 100. According to an example, “significantly greater than” means that the ratio of the length to the width is greater than 10, greater than 100 or even greater than 1000.

[0029] refer to Figure 1 , the first region 21 is connected to the drain node D of the transistor device, and the second regions 22, 23 are connected to the source node S of the transistor device. The connection between the second regions 22, 23 and the source node S is only Figure 1 . Examples of how these connections can be implemented are explained further below with reference to the examples herein. The first region 21 is connected to the drain node D via the drain region 11 of the first doping type. The drain region 11 may adjoin the first region 21. However, in Figure 1 Not shown.

[0030] Alternatively, if Figure 1 As shown in FIG. 1 , a buffer region 12 of the first doping type is arranged between the drain region 11 and the first region 21. The buffer region 12 has the first doping type, i.e., the doping type of the first region 21 and the drain region 11. According to one example, the doping concentration of the buffer region 12 is lower than the doping concentration of the drain region 11. The doping concentration of the drain region 11 is selected from, for example, 1E17 (=10 17 )cm -3 and 1E20 cm -3 The doping concentration of the buffer region 12 is selected from, for example, 1E14 cm -3 and 1E17 cm -3 According to one example, the buffer region 12 includes two or more differently doped sub-regions (not shown). One of these sub-regions may have a doping ratio of 1E14 cm -3 and 5E15 cm -3 and another of these sub-regions may have a doping concentration of 5E15cm -3 and 1E17 cm -3 between the doping concentrations.

[0031] refer to Figure 1 , the transistor device further comprises a control structure 3 connected between the source node S and the first region 21. The control structure 3 is at least partially integrated in the semiconductor body 100. Examples of how the control structure 3 can be implemented are explained below with further reference to the examples of this document. The control structure further comprises a gate node G and is configured to be dependent on a voltage V between the gate node G and the source node S. GS To control the conductive channel between the source node S and the first region 21. Figure 1In the example shown in , this function of the control structure 3 is represented by a switch connected between the source node S and the first region 21. Furthermore, the control structure 3 comprises a pn junction between the first region 21 and the source node S. Figure 1 In the example shown in , this pn junction is represented by a bipolar diode connected between the first region 21 and the source node S.

[0032] The transistor device has a current flow direction, that is, a direction in which current can flow between a source node S and a drain node D inside the semiconductor body 100. Figure 1 In the example shown in , the current flow direction corresponds to the vertical direction z of the semiconductor body 100, so that the drain region 11 is spaced apart from the control structure 3 in the vertical direction. The vertical direction z is perpendicular to the first surface ( Figure 1 ) and the direction of the second surface 102. Figure 1 The “vertical cross-sectional view” shown in FIG. 1 is a cross-sectional view in a cross section perpendicular to the first surface and the second surface 102 and parallel to the vertical direction z. Figure 1 The cross section of the vertical cross section shown in is called a horizontal cross section.

[0033] A transistor device can be operated in a forward biased state and a reverse biased state. Whether the device is in a forward biased state or a reverse biased state depends on the drain-source voltage V DS The polarity of the drain-source voltage V is the voltage between the drain node D and the source node S. In the reverse bias state, the drain-source voltage V DS The polarity of causes the diode (also referred to as the body diode) of the control structure 3 to be reverse biased, so that in this operating state, the transistor device conducts current according to the operating state of the control structure 3. In the forward bias state, the drain-source voltage V DS The polarity of is such that the diode of the control structure 3 is reverse biased. In this forward biased state, the transistor device can be operated in an on state or an off state by the control structure 3. In the on state, the control structure 3 generates a conductive channel between the source node S and the first region 21, so that current can flow between the source node S and the drain node D via the control structure 3 and the first region 21 of the first doping type. In the off state, the conductive channel is interrupted.

[0034] In the off state, the space charge region (depletion region) expands in the first region 21 and the second region 22, 23, so that the first region 21 and the second region 22, 23 can be increased with the drain-source voltage V DSIn this way, the charge carriers in the first region 21 are "compensated" by the charge carriers in the second regions 22, 23. Thus, the first region 21 can be implemented with a higher doping concentration and, therefore, a lower resistance, without reducing the voltage blocking capability of the transistor device, compared to a conventional transistor device without a second region.

[0035] With reference to the above, the drift region 20 can be produced in a highly efficient manner, and therefore, the Figure 1 An example of a method for producing the drift region 20 is explained below.

[0036] Figure 3 A flow chart of a method according to an example is shown. Figure 3 The method includes forming a plurality of trenches in at least one semiconductor layer, wherein each of the plurality of trenches has a first width, wherein the trenches are separated by mesa regions, the mesa regions each have a second width, and wherein the first width is greater than the second width (201). The method also includes: implanting a first type of dopant atoms and a second type of dopant atoms into each of opposite sidewalls of the plurality of trenches (202); filling the plurality of trenches with a semiconductor material (203); and diffusing the first type of dopant atoms and the second type of dopant atoms in a thermal process such that the first type of dopant atoms form a first region and the second type of dopant atoms form a second region (204).

[0037] Figure 4A and 4B An example of forming multiple trenches and implanting first type dopant atoms and second type dopant atoms into the sidewalls of the trenches is shown in . Each of these features shows a vertical cross-sectional view of a segment of the semiconductor layer 130 during the manufacturing process. This semiconductor layer 130 is also referred to as the first semiconductor layer hereinafter. The first semiconductor layer 130 forms a portion of the semiconductor body 100 of the completed transistor device. At the time of processing the first semiconductor layer 130, other segments of the semiconductor body 100 (such as the drain region 11 and the optional buffer region 12) may have been formed. However, these other segments are not shown in . Figure 4A and 4B Shown in.

[0038] refer to Figure 4A, the method includes forming a plurality of trenches 131 in a first surface 132 of a semiconductor layer 130, such that each of the trenches 131 extends from the first surface 132 into the semiconductor layer 130. Forming the trenches 131 may include: forming an etch mask 301 on top of the first surface 132; and etching those sections of the semiconductor layer 130 that are not covered by the etch mask 301. For example, etching the trenches includes using an anisotropic etching process. Figure 4A The first semiconductor layer 130 is shown after etching trenches 131 .

[0039] According to one example, the groove 131 is an elongated groove, that is, the length of the groove 131 (ie, the dimension of the groove 131 in the second transverse direction y) is significantly greater than the width w131 of the groove 131 (ie, its dimension in the first transverse direction x).

[0040] Each of the grooves 131 has a first side wall 133 and an opposite second side wall 134, wherein these side walls extend in the longitudinal direction (second transverse direction y) of the groove 131 and at least approximately in the vertical direction z. "At least approximately" means that the side walls 133, 134 are at least approximately perpendicular to the first surface 132. That is, the side walls 133, 134 may be perpendicular to the first surface 101 or may be tapered. Figure 4A According to an example, the angle between each of the sidewalls 133 , 134 and the first surface 132 (inside the first semiconductor layer 130 ) is between 90° and 100°, in particular between 92° and 95°.

[0041] refer to Figure 4A , the grooves 131 are spaced apart by the mesa areas 135, so that each mesa area 135 is located between two adjacent grooves 131 of the corresponding pair. Each of the mesa areas 135 has a width w135, i.e., the dimension of the corresponding mesa area 135 in the first lateral direction x. The width w131 of the groove 131 is also referred to as the first width hereinafter, and the width w135 of the mesa area 135 is also referred to as the second width hereinafter. With reference to the above, the grooves 131, and therefore also the mesa areas 135, may be tapered. According to one example, the first width w131 of one groove represents the average width of the corresponding groove 131, and the first width w131 of a plurality of grooves 131 represents the average value of the average width of the grooves 131. In other words, the width w135 of one mesa area 135 represents the average width of the corresponding mesa area 135, and the width w135 of a plurality of mesa areas 135 represents the average value of the average width of the mesa area 135.

[0042] The first width w131 is greater than the second width w135, w131>w135. According to an example, the first width w131 is at least 1.1 times, at least 1.2 times, or at least 1.5 times the second width w135, so that the trench 131 is wider than the mesa region 135 in the first lateral direction x. According to an example, the first width w131 is less than three times the second width w135, w131<3*w135. According to an example, the first width w131 is between 0.5 micrometers (μm) and 6 micrometers, in particular between 1.5 micrometers and 3.5 micrometers.

[0043] The aspect ratio a131 of the groove 131 is given by the ratio between the depth d131 (i.e. the dimension of the groove in the vertical direction z) and the first width w131.

[0044]

[0045] Although it may be desirable to form the trench 131 with a large aspect ratio, the aspect ratio is generally limited by the process of filling the trench 131 with a semiconductor material. It may be desirable to produce the semiconductor material filling the trench 131 as a single crystalline layer without any defects (e.g., voids). The larger the aspect ratio, the more difficult it is to fill the trench 131 with a defect-free semiconductor material. Thus, according to one example, the trench 131 is formed so that its aspect ratio a131 is between 2:1 and 3:1.

[0046] Figure 4A The pitch p of the trench structure shown in FIG. 1 is given by the first width w131 plus the second width w135, i.e., the pitch is defined by one of the trenches 131 and the adjacent mesa region 135,

[0047] p=w131+w135 (2)

[0048] This pitch of the trench structures is substantially equal to the center distance between two adjacent narrow regions 23 or the center distance between two adjacent wide regions 22 in the completed super junction transistor device.

[0049] At a given pitch p of the trench structure and at a given aspect ratio a131 of the trench 131, implementing the trench 131 so that the first width w131 is greater than the second width w135 has the following effect: a deeper trench can be formed compared to the case where the first width w131 is equal to the second width w135. The benefits of forming a deeper trench 131 are further explained below.

[0050] refer to Figure 4BThe method further includes implanting dopant atoms of the first type and dopant atoms of the second type into each of the opposing first and second sidewalls 133, 134 to form implant regions 24 in the mesa region 135 along the sidewalls 133, 134, so that each of these implant regions 24 includes both dopant atoms of the first doping type and dopant atoms of the second doping type. Forming the implant regions 24 may include a tilted implantation process, wherein an implantation mask 401 formed on top of the mesa region 135 may prevent dopant atoms from being implanted into the first surface 132. According to an example, the implantation mask 401 is an etching mask 301.

[0051] refer to Figure 5A and 5B Explanation of the process steps 202 and 203 (see Figure 2 ) Filling the plurality of trenches 131 with semiconductor material and diffusing the first type of dopant atoms and the second type of dopant atoms. Each of these figures shows the process steps after other process steps Figure 4B The structure shown in .

[0052] Figure 5A The semiconductor layer 130 is shown after the trench 131 is filled with a semiconductor material. Filling the trench may include epitaxially growing a second semiconductor layer 140 on top of the first semiconductor layer 130 so that the trench is completely filled. Figure 5A , the second semiconductor layer 140 may be formed such that it fills the trench and additionally covers the first surface 132 of the first semiconductor layer 130 on top of the mesa region 135. Optionally, filling the trench includes a planarization process, wherein the surface 141 of the second semiconductor layer 140 is planarized and / or wherein the thickness of the second semiconductor layer 140 above the mesa region 135 is reduced. According to one example (not shown), the second semiconductor layer 140 is planarized or etched back down to the mesa region 135, leaving only some sections of the second semiconductor layer 140 that fill the trench 131. Thus, the semiconductor layer 140 is formed such that it at least fills the trench 131 and, optionally, is also formed on top of the mesa region 135.

[0053] Epitaxially growing the second semiconductor layer 140 results in a single crystalline layer arrangement comprising the first layer 130 and the second layer 140. In this arrangement, there is no visible boundary between the first and second layers 130, 140. However, for illustration purposes only, Figure 5A The boundary between the two semiconductor layers 130 , 140 is shown by a dotted line in FIG.

[0054] Figure 5B shows the thermal process after Figure 5AIn the layer arrangement shown in , in the thermal process, the first type of dopant atoms and the second type of dopant atoms included in the implantation region 24 are diffused, so that the first type of dopant atoms form the first region 21, and the second type of dopant atoms form the second regions 22, 23. The first type of dopant atoms and the second type of dopant atoms are selected so that they have different diffusion coefficients, so that the annealing process obtains the first region 21 having an effective doping concentration of the first doping type and the second regions 22, 23 having an effective doping concentration of the second doping type. Figure 5B In the example shown in , the first type of dopant atoms has a lower diffusion coefficient than the second type of dopant atoms, so that the first region 21 is formed to be close to the position of the implantation region 24, and therefore close to the position of the first and second side walls 133, 134, while the second regions 22, 23 are spaced apart from the previous position of the side walls 133, 134.

[0055] According to one example, the first region 21 includes n-type dopant atoms, and the second regions 22, 23 include p-type dopant atoms. According to one example, the n-type dopant atoms include at least one of arsenic (As) atoms or antimony (Sb) atoms, and the p-type dopant atoms include boron (B) atoms, so that the first type of dopant atoms may include As atoms and / or Sb atoms, and the second type of dopant atoms may include B atoms. For example, in silicon, B atoms may diffuse up to four times faster than As atoms.

[0056] Due to the different diffusion coefficients, the segregation of the dopant atoms of the first type and the dopant atoms of the second type will occur, and the first region with effective doping (net doping) of the first doping type and the second region 22, 23 with effective doping of the second doping type are obtained. In addition to the doping atoms of the first doping type, the first region 21 may include doping atoms of the second doping type. However, in the first region 21, the dopant atoms of the first doping type are dominant, so that the effective doping of the first dopant type is obtained. In other words, in addition to the dopant atoms of the second doping type, the second regions 22, 23 may also include dopant atoms of the first doping type, wherein the dopant atoms of the second doping type are dominant.

[0057] refer to Figure 5B The narrow regions 23 of the second doping type are those regions formed in the previous mesa regions 135. The wide regions 22 are those regions formed in the sections of the second layer 140 of the previous trenches 131 filled.

[0058] It may be desirable to precisely adjust the amount of dopant atoms of the first type and the amount of dopant atoms of the second type included in the layer arrangement after the annealing process. According to one example, the first semiconductor layer 130 and the second semiconductor layer 140 are substantially “undoped”, so that the amount of dopant atoms of the first type and the amount of dopant atoms of the second type are substantially only defined by the implantation process. According to one example, undoped means that the basic doping concentration of each of the first and second semiconductor layers 130, 140 is less than 1E14 cm -3 or even less than 2E13 cm -3 .

[0059] After the annealing process, the first region 21 and the second regions 22, 23 form a drift region 20 of the super junction transistor device. The drift region 20 may include only one first semiconductor layer 130 and one second semiconductor layer 140, which may also be referred to as a top layer. Figure 6 A semiconductor body 100 having a drift region 20 of this type is shown in FIG.

[0060] Figure 6 A semiconductor body 100 of a superjunction transistor device is shown after an annealing process and before forming a control structure 3. In the present example, the semiconductor body 100 comprises a carrier 110 forming a drain region 11 and an optional buffer region 12, a first semiconductor layer 130 formed on top of the carrier 110, and a second semiconductor layer 140 formed on top of the first semiconductor layer 130. In the present example, a surface 141 of the second semiconductor layer forms the surface 101 of the semiconductor body 100. According to an example, the first semiconductor layer 130 is epitaxially grown on the carrier 110. The carrier may comprise a highly doped semiconductor substrate forming the drain region 11 and an epitaxial layer optionally grown on the substrate forming the buffer region 12.

[0061] Forming the drift region 20 based on only one first semiconductor layer 130 and a top layer 140, wherein the trench is formed only in the first semiconductor layer 130 and not in the top layer 140, is merely an example. Basically, any number of first semiconductor layers can be formed one above the other on a carrier, wherein a trench is formed in each of the first semiconductor layers and before forming the next or top layer of the first semiconductor layer, dopant atoms of the first and second types are implanted into opposite sidewalls of the trench. Fig. 7A The results of such a process are shown in .

[0062] Fig. 7A An example of a semiconductor body 100 is shown, which comprises a carrier 110, a plurality of first semiconductor layers 1301, 1302 formed one above the other on top of the carrier 110, and a plurality of first semiconductor layers 1303, 1304 formed one above the other on top of the carrier 110. n , and formed in the first semiconductor layer 1301, 130n The top one 130 n According to one example, the carrier 110 includes a drain region 11 and an optional buffer region 12. A plurality of first semiconductor layers 1301, 130 n Also included is a bottommost semiconductor layer 1301 formed on top of the carrier 110. This bottommost semiconductor layer 1301 has been Figure 4A and 4B The semiconductor layer 130 is processed in the same manner as explained above. That is, a plurality of trenches are formed in the bottommost semiconductor layer 1301, and implantation regions 24 have been formed in the mesa regions along opposite side walls of the trenches.

[0063] A plurality of first semiconductor layers 1301, 130 n Also includes other semiconductor layers 130 n Other semiconductor layers 130 n The other semiconductor layers 130 are formed on the bottom semiconductor layer 1301 and fill the trench in the bottom semiconductor layer 1301. n Already passed with Figure 4A and 4B The semiconductor layer 130 shown in FIG. 1 is processed in the same manner. That is, in the semiconductor layer 130 n Trenches are formed in the substrate and implanted regions 24 have been created along opposite side walls of these trenches.

[0064] exist Fig. 7A In the example shown in FIG. 1 , the semiconductor body comprises two first semiconductor layers 1301, 130 n , so that the other semiconductor body 130 n Forming the first semiconductor layers 1301 and 130 n The top one of the semiconductor layers 1301 and 1302 is formed on the top thereof. It goes without saying that before forming the topmost layer 140, two layers 1301 and 1303 may be formed one on top of the other. n Any number of first semiconductor layers 1301, 130 n , in particular, forming more than 2, more than 5 or more than 10 first semiconductor layers 1301-130 n .

[0065] Figure 7B shows the Fig. 7A As shown in Figure 7B As can be seen in FIG. 1 , the annealing process results in a plurality of first regions 21 extending continuously in the vertical direction z, and a plurality of second regions 22 , 23 extending continuously in the vertical direction z of the semiconductor body 100 .

[0066] In a superjunction transistor device, the voltage blocking capability depends largely on the length d20 of the drift region 20, where the length d20 is the dimension of the drift region 20 in the vertical direction z. In addition, a reduction in the pitch of the trench structure (which also results in a reduction in the pitch of the completed superjunction transistor device) can lead to a reduction in the on-resistance of the transistor device. On the other hand, reducing the pitch of the trench structure has the following effect: at a given aspect ratio of the trench, a trench with a smaller depth d131 is produced. For example, if the trench width w131 is equal to the terrace width w135, and the aspect ratio of the trench 131 is 2:1, the trench depth is substantially given by the pitch p of the trench structure (p=w131+w135). Thus, as the pitch p decreases, the number of first semiconductor layers to be produced in order to achieve the desired length d20 of the drift region 20 increases. However, each additional semiconductor layer increases the cost of the overall superjunction transistor device.

[0067] At a given pitch p of the trench structures and a given aspect ratio a131 of the trenches 131, producing the trenches 131 such that their width w131 is greater than the width w135 of the mesa regions 135 has the following effect: less first semiconductor layer is required in order to achieve the desired length d20 of the drift region 20 than in the case where w131=w135. Thus, the method explained hereinabove is suitable for producing the drift region 20 of a superjunction transistor device in a very cost-effective manner.

[0068] Referring to the above, forming the drift region 20 of the super junction transistor device includes: forming at least one first semiconductor layer 130; forming a plurality of trenches 131 in the at least one first semiconductor layer 130; forming an implantation region 24 in the mesa region along opposite sidewalls 133, 134 of the trenches 131; filling the trenches 131 with semiconductor material; and an annealing process. The implantation region 24 may be formed in various ways.

[0069] according to Figure 8 In an example shown in , implanting first type dopant atoms and second type dopant atoms into each of the first and second side walls 133, 134 includes: implanting molecules including both the first type dopant atoms and the second type dopant atoms into the first side wall 133 in a first implantation process; and implanting molecules including both the first type dopant atoms and the second type dopant atoms into the second side wall 134 in a second implantation process.

[0070] According to another example, the method includes implanting the first type of dopant atoms and the second type of dopant atoms into one sidewall in separate implantation processes. Fig.9A and 9B , which can include: Fig.9AAs shown in , in a first implantation process, the first type of dopant atoms are implanted into the first sidewall 133, and in a second implantation process, the first type of dopant atoms are implanted into the second sidewall 134; and Fig. 9B As shown in , the second type dopant atoms are implanted into the first sidewall 133 in the third implantation process, and the second type dopant atoms are implanted into the second sidewall 134 in the fourth implantation process.

[0071] Figures 10A-10C An example of doping concentrations of the first type of dopant atoms and the second type of dopant atoms in the horizontal layer of the drift region 20 after the annealing process is shown ( Fig. 10A ), the effective first type dopant charge in the first region 21 after the annealing process and the effective second type dopant charge in the second regions 22, 23 ( Fig. 10B ), and applying a drain-source voltage V DS The electric field strength in the first region 21 and the second region 22, 23 in the off state of the super junction transistor device is . The "effective dopant charge" is the integral of the effective doping concentration in a vertical plane parallel to the pn junction formed between the first and second regions 21, 22, 23.

[0072] exist Figures 10A-10C In the example shown in , although the transistor device includes a wide second region 22 and a narrow second region 23, the maximum field strength in the individual semiconductor regions 21, 22, 23 is substantially the same. This is highly desirable because it ensures that the voltage blocking capability is substantially the same for the pn junction formed between the first region 21 and the narrow second region 23, and for the pn junction formed between the first region 21 and the wide second region 22. This is substantially achieved by controlling the annealing process so that the total number of dopant atoms in the narrow region 23 is substantially equal to the total number of dopant atoms in the wide region 22. The total number of dopant atoms is substantially given by the integral of the dopant charge. According to one example, for example, the number of dopant atoms in the narrow region 23 and the wide region 22 can be balanced by appropriately selecting the duration and temperature of the annealing process. According to one example, the temperature is selected from between 1050°C and 1100°C, and the duration is selected from between 250 minutes and 1000 minutes. For example, the duration can be selected based on the spacing of the previous trench structure, wherein the larger the spacing, the longer the diffusion time.

[0073] Referring to the above, the carrier 110 may include a semiconductor substrate. The substrate may include oxygen and / or COP (crystal oriented particles), which may diffuse into the at least one semiconductor layer 130. The diffusion of oxygen and / or COP into the at least one semiconductor layer 130 may have an effect on the diffusion of the first type and the second type of dopant atoms. Thus, according to one example, the conditions (temperature, duration, ...) of the temperature process are selected depending on the concentration of oxygen and / or COP in the substrate.

[0074] According to one example, the process of forming the second regions 22, 23 such that each of these regions (in the same horizontal layer) has substantially the same number of dopant atoms may be supported by implanting faster diffusing second type dopant atoms deeper into the first and second sidewalls 133, 134 than slower diffusing first type dopant atoms. Fig.11 This situation is shown in Fig.11 The concentrations of the first type of dopant atoms and the second type of dopant atoms in the mesa region 135 after the implantation process and after the diffusion process are shown. The implantation depth of the first and second types of dopant atoms can be adjusted by appropriately adjusting the implantation energy.

[0075] The control structure 3 can be implemented in various ways. Figure 1 The control structure 3 is only schematically shown in the figure. Some examples are explained below. Typically, the control structure is formed in the semiconductor body 100 after forming the top layer 140 and is at least partially formed in the top layer. The control structure can be formed after the annealing process for forming the first and second regions 21, 22, 23. According to another example, the control structure 3 is at least partially formed before the annealing process, so that the same annealing process can be used to diffuse and activate the dopant atoms of the first and second regions 21, 22, 23 and the dopant atoms of the doped regions in the control structure.

[0076] Fig.12 An example of a control structure 3 is shown in more detail. In addition to the control structure 3, Fig.12 Also shown in FIG. 2 is a portion of the drift region 20 adjacent to the control structure 3. Fig.12In the example shown in , the control structure 3 includes a plurality of control units 30, which may also be referred to as transistor units. Each of these control units 30 includes a body region 31 of a second doping type, a source region 32 of a first doping type, a gate electrode 33, and a gate dielectric 34. The gate dielectric 34 dielectrically insulates the gate electrode 33 from the body region 31. The body region 31 of each control unit 30 separates the corresponding source region 32 of the control unit 30 from at least one of the plurality of first regions 21. The source region 32 and the body region 31 of each of the plurality of control units 30 are electrically connected to a source node S. In this context, "electrically connected" means an ohmic connection. That is, there is no rectifying junction between the source node S and the source region 32 and the body region 31. In Figure 2 1 and 2. The electrical connections between the source node S and the source region 32 and the body region 31 of the individual control unit 30 are only schematically shown in FIG.

[0077] Referring to the above, the body region 31 of each control unit 30 is adjacent to at least one first region 21. Since the body region 31 is of the second doping type and the first region 21 is of the first doping type, there is a pn junction between the body region 31 of each control unit 30 and the at least one first region 21. These pn junctions form Figure 1 The bipolar diode in the equivalent circuit diagram of the control structure 3 shown in represents a part of the pn junction of the control structure 3 .

[0078] exist Figure 2 In the example shown in , the gate electrode 33 of each control structure 30 is a planar electrode arranged on top of the first surface 101 of the semiconductor body 100 and is dielectrically insulated from the semiconductor body 100 by a gate dielectric 34. In the present example, the sections of the first region 21 adjacent to the individual body regions 31 extend to the first surface 101.

[0079] Fig.13 A control structure 3 according to another example is shown. Figure 3 The control structure shown in 3 is Figure 2 The control structure 3 shown in FIG. 1 is different in that the gate electrode 33 of each control unit 30 is a trench electrode. This gate electrode 33 is arranged in a trench extending from the first surface 101 into the semiconductor body 100. Figure 2 As in the example shown in , the gate dielectric 34 dielectrically insulates the gate electrode 33 from the corresponding body region 31. The body region 31 and the source region 32 of each control unit 30 are electrically connected to the source node S. In addition, the body region 31 is adjacent to at least one first region 21 and forms a pn junction with the corresponding first region 21.

[0080] exist Fig.12 and 13 In the example shown in , the control structure 3 includes a gate electrode 33, wherein the gate electrode 33 of each control unit 30 is configured to control a conductive channel between the source region 32 of the corresponding control unit 30 and one first region 21, so that each control unit 30 is associated with one first region 21. In addition, as Fig.12 and 13 As shown in FIG, the main body region 31 of each control unit 30 is adjacent to at least one second region 22, 23, so that at least one second region 22, 23 is electrically connected to the source node S via the main body region 31 of the control unit 30. For illustration purposes only, Figure 2 and 3 In the example shown in , the main body area 31 of each control unit 30 adjoins one second area 22, 23, so that each control unit 30 is associated with one second area. Figure 2 and 3 In the example shown in , the source regions 32 of two (or more) adjacent control units 30 are formed by a doping region of a first doping type, the body regions 31 of two (or more) adjacent control units 30 are formed by a doping region of a second doping type, and the gate electrodes 33 of the two (or more) control units 30 are formed by a single electrode. The gate electrode 33 may include doped polysilicon, metal, etc.

[0081] According to one example, the doping concentration of the source region 32 is selected from 1E18 cm -3 and 1E21 cm -3 and the doping concentration of the body region 31 is selected from 1E16 cm -3 and 5E18 cm -3 in the range between.

[0082] like Fig.12 and 13 As shown in the figure, associating one control unit 30 of the plurality of control units with one first area 21 and one second area 22 is merely an example. The embodiment and arrangement of the control unit 30 of the control structure 3 is largely independent of the specific embodiment and arrangement of the first area 21 and the second area 22, 23.

[0083] Fig.14, which shows that the embodiment and arrangement of the control structure 3 is largely independent of the embodiment and arrangement of the first and second regions 21, 22. In this example, the first region 21 and the second region 22 are elongated in the second lateral direction y of the semiconductor body 100, while the source region 32, the body region 31 and the gate electrode 33 of the individual control units 30 of the control structure 3 are elongated in the first lateral direction x perpendicular to the second lateral direction y. In this example, the body region 31 of one control unit 30 adjoins a plurality of first regions 21 and second regions 22.

[0084] The transistor device may be implemented as an n-type transistor device or a p-type transistor device. In an n-type transistor device, the first doping type, i.e., the doping type of the first region 21, the source region 32, the drain region 11, and the optional buffer region 12 is n-type, and the second doping type, i.e., the doping type of the second region 22, 23, and the body region 31 is p-type. In a p-type transistor device, the doping types of the aforementioned device regions are complementary to the doping types of the corresponding device regions in an n-type transistor device.

Claims

1. A method comprising: A plurality of first regions (21) of a first doping type and a plurality of second regions (22, 23) of a second doping type are formed in a semiconductor body (100), so that the first regions (21) and the second regions (22, 23) are arranged adjacently and alternately in the semiconductor body (100), Wherein, forming the first region (21) and the second region (22, 23) comprises: forming a plurality of trenches (131) in at least one semiconductor layer (130); implanting first type dopant atoms and second type dopant atoms into each of the opposing sidewalls (133, 134) of the plurality of trenches (131); filling the plurality of trenches (131) with a semiconductor material; and diffusing the first type of dopant atoms and the second type of dopant atoms in a thermal process so that the first type of dopant atoms form the first region (21) and the second type of dopant atoms form the second region (22, 23), wherein each of the plurality of grooves (131) has a first width (w131), wherein the grooves (131) are separated by mesa regions (135) each having a second width (w135), wherein the first width (w131) is greater than the second width (w135), and The second region (22, 23) includes a wide region (22) and a narrow region (23).

2. The method according to claim 1, wherein: The first width (w131) is at least 1.05 times the second width (w135).

3. The method according to claim 1, wherein: The first width (w131) is at least 1.1 times the second width (w135).

4. The method according to claim 1, wherein: The first width (w131) is at least 1.2 times the second width (w135).

5. The method according to claim 1, wherein: The first width (w131) is at least 1.5 times greater than the second width (w135).

6. The method according to any one of claims 1 to 5, wherein: The first width (w131) is less than 3 times the second width (w135).

7. The method according to any one of claims 1 to 5, wherein: The depth-to-width ratio of the groove (131) is between 2:1 and 3:

1.

8. The method according to any one of claims 1 to 5, wherein: The second type of dopant atoms are implanted deeper into the sidewalls (133, 134) than the first type of dopant atoms.

9. The method according to any one of claims 1 to 5, in, The first type of dopant atoms includes at least one of arsenic (As) and antimony (Sb) atoms, and Wherein, the second type of dopant atoms includes boron (B) atoms.

10. The method according to any one of claims 1 to 5, wherein: The total amount of dopant atoms of the first type implanted into each of the sidewalls (133, 134) deviates less than 5% from the total amount of dopant atoms of the second type implanted into the respective sidewall.

11. The method according to any one of claims 1 to 5, wherein: The total amount of dopant atoms of the first type implanted into each of the sidewalls (133, 134) deviates from the total amount of dopant atoms of the second type implanted into the corresponding sidewall by less than 2%.

12. The method according to any one of claims 1 to 5, wherein: The total amount of dopant atoms of the first type implanted into each of the sidewalls (133, 134) deviates less than 1% from the total amount of dopant atoms of the second type implanted into the respective sidewall.

13. The method according to any one of claims 1 to 5, wherein: Filling the trench (131) includes forming an epitaxial layer in the trench (131) and on top of the mesa region (135).

14. The method according to any one of claims 1 to 5, wherein: Forming a plurality of trenches (131) in at least one semiconductor layer (130) comprises: A plurality of semiconductor layers (1301-130 n ), and forming the plurality of semiconductor layers (1301-130 n ) before the next semiconductor layer in the plurality of semiconductor layers (1301-130 n ) are formed in each of the plurality of grooves (131).

15. The method according to any one of claims 1 to 5, further comprising: A control structure (3) is formed having a plurality of source regions (32) of the first doping type and a plurality of body regions (31) of the second doping type, such that: Each of the first regions (21) is adjacent to at least one of the plurality of body regions (31), and Each of the second regions (22) is adjacent to at least one of the plurality of body regions (31).

16. A super junction transistor device, comprising: A drift region having a plurality of first regions (21) of a first doping type and a plurality of second regions (22, 23) of a second doping type in a semiconductor body (100), wherein the first region (21) and the second region (22, 23) are adjacently and alternately arranged in the semiconductor body (100), wherein the second region (22, 23) comprises a wide region (22) having a first width (w22) and a narrow region (23) having a second width (w23), wherein the wide regions (22) and the narrow regions (23) are arranged alternately, and Wherein, the first width (w22) is at least 1.05 times the second width (w23).

17. The super junction transistor device according to claim 16, wherein: The first width (w22) is at least 1.1 times greater than the second width (w23).

18. The super junction transistor device according to claim 16, wherein: The first width (w22) is at least 1.2 times the second width (w23).

19. The super junction transistor device according to claim 16, wherein: The first width (w22) is at least twice the second width (w23).

20. The superjunction transistor device according to any one of claims 16 to 19, wherein: The first width (w22) is less than 5 times the second width (w23).

21. The superjunction transistor device according to any one of claims 16 to 19, wherein: The first width (w22) is less than 4 times the second width (w23).

22. The superjunction transistor device according to any one of claims 16 to 19, wherein: The first width (w22) is less than twice the second width (w23).

23. The superjunction transistor device according to any one of claims 16 to 19, wherein: The effective dopant dose of the second type of dopant atoms in the wide region (22) deviates from the effective dopant dose of the second type of dopant atoms in the narrow region (23) by less than 10%.

24. The superjunction transistor device according to any one of claims 16 to 19, wherein: The effective dopant dose of the second type of dopant atoms in the wide region (22) deviates from the effective dopant dose of the second type of dopant atoms in the narrow region (23) by less than 5%.

25. The superjunction transistor device according to any one of claims 16 to 19, wherein: The effective dopant dose of the second type of dopant atoms in the wide region (22) deviates from the effective dopant dose of the second type of dopant atoms in the narrow region (23) by less than 1%.

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