Multi-main grid back contact heterojunction solar cell and manufacturing method thereof
By using a multi-busbar back-contact heterojunction solar cell structure and low-temperature silver paste, the problems of high cost and environmental pollution have been solved, enabling large-scale production of high-efficiency, low-cost solar cells.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- GOLD STONE (FUJIAN) ENERGY CO LTD
- Filing Date
- 2021-09-13
- Publication Date
- 2026-07-10
AI Technical Summary
In existing technologies, high-efficiency back-contact batteries have high manufacturing costs, and copper electroplating technology is environmentally polluting and requires large sites, making it difficult to scale up production.
The multi-busbar back-contact heterojunction solar cell structure simplifies the production process by alternating semiconductor regions and isolation trenches, combined with staggered solder ribbon connection layers and insulating layers, and using low-temperature silver paste instead of copper electroplating.
It significantly reduces the conductivity requirements of solar cells, lowers production costs, simplifies the process, avoids environmental pollution and site requirements, and is suitable for large-scale production.
Smart Images
Figure CN113745357B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of solar cell technology, and in particular to a multi-busbar back-contact heterojunction solar cell and its fabrication method. Background Technology
[0002] In recent years, advancements in solar cell manufacturing technology have led to declining production costs and increasing conversion efficiency. Solar cell power generation is becoming increasingly widespread and is a crucial energy source for electricity supply. High-efficiency solar cells represent the future industry trend, increasing wattage per unit area while simultaneously reducing costs, thereby enhancing the added value of solar cell power generation modules.
[0003] Back-contact solar cells, one type of high-efficiency solar cell, move all the electrodes from the light-receiving surface to the back, maximizing the area of the light-receiving surface and thus improving the cell's conversion efficiency. A representative example is SUN POWER from the United States.
[0004] However, high-efficiency battery technologies currently all suffer from high manufacturing costs. For example, SunPower's back-contact batteries, which use copper plating technology, present challenges related to copper-containing wastewater treatment and environmental protection, and require large production facilities, hindering large-scale mass production. Therefore, it is necessary to develop a low-cost metal electrode structure suitable for back-contact batteries to promote the large-scale production of high-efficiency back-contact batteries. Summary of the Invention
[0005] One of the objectives of this invention is to provide a multi-busbar back-contact heterojunction solar cell that significantly reduces the conductivity requirements of fine grid lines while achieving a multi-busbar structure and reducing production costs.
[0006] One of the objectives of this invention is to provide a method for manufacturing multi-busbar back-contact heterojunction solar cells, which can greatly reduce metallization costs, avoid complex wet copper electroplating schemes, and is more conducive to the production and application of back-contact heterojunction solar cell technology.
[0007] The objective of this invention is achieved through the following technical solution:
[0008] A multi-busbar back-contact heterojunction solar cell includes a semiconductor substrate, a plurality of first semiconductor regions and second semiconductor regions disposed alternately from left to right on a first main surface of the semiconductor substrate, an isolation trench disposed between each of the first semiconductor regions and the second semiconductor regions, a row or more of first solder ribbon connection layer arrays horizontally disposed on each of the first semiconductor regions, a row or more of second solder ribbon connection layer arrays horizontally disposed on each of the second semiconductor regions, a row or more of first solder ribbon insulating layer arrays disposed on the surface of each of the first semiconductor regions and corresponding to each of the second solder ribbon connection layer arrays at the same horizontal position, and a row or more of second solder ribbon insulating layer arrays disposed on the surface of each of the second semiconductor regions and corresponding to each of the first solder ribbon connection layer arrays at the same horizontal position; the first solder ribbon connection layer arrays and the second solder ribbon connection layer arrays are staggered from top to bottom.
[0009] A method for fabricating a multi-busbar back-contact heterojunction solar cell includes the following steps:
[0010] Step A: A first semiconductor region and a second semiconductor region are alternately disposed from left to right on the first main surface of the semiconductor substrate, and an isolation trench is disposed between the first semiconductor region and the second semiconductor region.
[0011] Step B involves two or more rows of solder ribbon connection segments staggered from top to bottom on the first main surface of the semiconductor substrate where the first semiconductor region and the second semiconductor region are formed; each row of solder ribbon connection segments is only provided in the first semiconductor region or the second semiconductor region, and the first semiconductor region and the second semiconductor region are each provided with one or more rows of solder ribbon connection segments, and each first semiconductor region and each second semiconductor region are provided with solder ribbon connection segments; a row of solder ribbon connection segments provided at the same horizontal position in the first semiconductor region is a first solder ribbon connection layer array, and a row of solder ribbon connection segments provided at the same horizontal position in the second semiconductor region is a second solder ribbon connection layer array;
[0012] Step C: A first solder ribbon insulating layer array is disposed on the surface of each first semiconductor region at the same horizontal position as each second solder ribbon connecting layer array, and a second solder ribbon insulating layer array is disposed on the surface of each second semiconductor region at the same horizontal position as each first solder ribbon connecting layer array.
[0013] Compared with the prior art, the advantages of the present invention are as follows:
[0014] (1) The structure of alternating first semiconductor region and second semiconductor region is adopted. The solder ribbon connection layer array and solder ribbon insulation layer array of corresponding semiconductor regions are staggered. The solder ribbon insulation layer array separates and insulates different semiconductor regions at the same horizontal position, so that each solder ribbon is well electrically connected to the semiconductor region of the same conductivity type through the solder ribbon connection layer array, and the current of the semiconductor region of the same conductivity type is led out, realizing the multi-busbar structure of back contact heterojunction solar cell, which significantly reduces the conductivity requirements of solar cell for fine grid lines.
[0015] (2) A deposited metal conductive layer is used as the fine grid electrode. The metal conductive layer and the transparent conductive film are deposited at the same time, eliminating the need for copper electroplating. At the same time, the fine grid electrode does not require expensive low-temperature silver paste, thus greatly simplifying the cell manufacturing process and reducing production costs. Attached Figure Description
[0016] Figure 1 The following are the steps for manufacturing a solar cell according to an embodiment of the present invention;
[0017] Figure 2 A cross-sectional view of an n-type silicon wafer with a passivation layer and an anti-reflection layer formed on the front side and a first semiconductor region, an isolation region, and a second semiconductor region arranged in a cross pattern on the back side, provided for an embodiment of the present invention;
[0018] Figure 3 This is a cross-sectional view of the transparent conductive film layer and the metal conductive film layer deposited on the back of the silicon wafer according to an embodiment of the present invention;
[0019] Figure 4 This is a cross-sectional view of the etching ink printed on the surface of the isolation region on the back of a silicon wafer according to an embodiment of the present invention;
[0020] Figure 5 This is a cross-sectional view of an isolation trench formed on the back side of a silicon wafer according to an embodiment of the present invention;
[0021] Figure 6 This is a schematic diagram of the structure of the isolation trench formed on the back of the silicon wafer according to an embodiment of the present invention;
[0022] Figure 7 This is a cross-sectional view of an alternatingly spaced solder strip connection layer formed on the back side of a silicon wafer according to an embodiment of the present invention;
[0023] Figure 8 This is a schematic diagram of the structure of an alternatingly spaced solder strip connection layer formed on the back side of a silicon wafer according to an embodiment of the present invention;
[0024] Figure 9 This is a cross-sectional view of an insulating layer formed on the back side of a silicon wafer in an embodiment of the present invention, alternating with the solder ribbon connection layer;
[0025] Figure 10 This is a schematic diagram of the structure of an insulating layer with alternating solder ribbon connection layer formed on the back side of a silicon wafer according to an embodiment of the present invention. Detailed Implementation
[0026] A multi-busbar back-contact heterojunction solar cell includes a semiconductor substrate, a plurality of first semiconductor regions and second semiconductor regions disposed alternately from left to right on a first main surface of the semiconductor substrate, an isolation trench disposed between each of the first semiconductor regions and the second semiconductor regions, a row or more of first solder ribbon connection layer arrays horizontally disposed on each of the first semiconductor regions, a row or more of second solder ribbon connection layer arrays horizontally disposed on each of the second semiconductor regions, a row or more of first solder ribbon insulating layer arrays disposed on the surface of each of the first semiconductor regions and corresponding to each of the second solder ribbon connection layer arrays at the same horizontal position, and a row or more of second solder ribbon insulating layer arrays disposed on the surface of each of the second semiconductor regions and corresponding to each of the first solder ribbon connection layer arrays at the same horizontal position; the first solder ribbon connection layer arrays and the second solder ribbon connection layer arrays are staggered from top to bottom.
[0027] An isolation region is provided between the first semiconductor region and the second semiconductor region, and the isolation trench is disposed on the isolation region.
[0028] The first semiconductor region includes a first type semiconductor film layer and a first conductive film layer formed sequentially from bottom to top on the first main surface of the semiconductor substrate. The second semiconductor region includes a second type semiconductor film layer and a second conductive film layer formed sequentially from bottom to top on the first main surface of the semiconductor substrate. The isolation region includes a first type semiconductor film layer, an isolation film layer, a second type semiconductor film layer, and an isolation conductive film layer formed sequentially from bottom to top on the first main surface of the semiconductor substrate. The isolation trench divides the isolation conductive film layer into left and right parts.
[0029] The first type of semiconductor film layer includes a first passivation layer and a first semiconductor layer formed sequentially from bottom to top on a first main surface of a semiconductor substrate; the second type of semiconductor film layer includes a second passivation layer and a second semiconductor layer formed sequentially from bottom to top on a first main surface of a semiconductor substrate; the first conductive film layer, the second conductive film layer, and the isolation conductive film layer each include a transparent conductive layer and a metal conductive layer formed sequentially from bottom to top on the corresponding semiconductor layer; the isolation film layer includes an isolation insulating layer formed in the isolation region on the first semiconductor layer.
[0030] The first passivation layer and the second passivation layer respectively include an intrinsic amorphous silicon layer and / or an intrinsic microcrystalline silicon layer.
[0031] The first semiconductor layer and the second semiconductor layer include an N-type doped amorphous silicon / microcrystalline silicon layer or a P-type doped amorphous silicon / microcrystalline silicon layer. When the first semiconductor layer is an N-type doped amorphous silicon / microcrystalline silicon layer, the second semiconductor layer is a P-type doped amorphous silicon / microcrystalline silicon layer. When the first semiconductor layer is a P-type doped amorphous silicon / microcrystalline silicon layer, the second semiconductor layer is an N-type doped amorphous silicon / microcrystalline silicon layer. The isolation film layer includes at least one of a silicon nitride layer, a silicon oxide layer, and a silicon carbide layer.
[0032] The transparent conductive layer is at least one of indium tin oxide, aluminum-doped zinc oxide, gallium-doped zinc oxide, zinc-doped indium oxide, and tungsten-doped indium oxide, with a total thickness of 50-100 nm and a total sheet resistance of 20-100 Ω / □; the metallic conductive layer is at least one of copper, aluminum, nickel, nickel alloy, and indium tin oxide, with a total thickness of 200-600 nm and a total sheet resistance of 0.02-0.5 Ω / □.
[0033] The width of the isolation groove is 10-150um, and the resistance between the metal conductive layers on both sides of the isolation groove is greater than 1KΩ.
[0034] The first and second solder strip connection layer arrays are solderable low-temperature silver paste layers, solderable silver-coated copper paste layers, or solderable nickel paste layers, with a thickness of 5-30 μm and a length of 1-10 mm.
[0035] The first and second solder ribbon insulating layer arrays are insulating ink layers with a thickness of 3-25 μm, a length of 1-10 mm, and a width of 0.3-0.8 mm.
[0036] A method for fabricating a multi-busbar back-contact heterojunction solar cell includes the following steps:
[0037] Step A: A first semiconductor region and a second semiconductor region are alternately disposed from left to right on the first main surface of the semiconductor substrate, and an isolation trench is disposed between the first semiconductor region and the second semiconductor region.
[0038] Step B involves two or more rows of solder ribbon connection segments staggered from top to bottom on the first main surface of the semiconductor substrate where the first semiconductor region and the second semiconductor region are formed; each row of solder ribbon connection segments is only provided in the first semiconductor region or the second semiconductor region, and the first semiconductor region and the second semiconductor region are each provided with one or more rows of solder ribbon connection segments, and each first semiconductor region and each second semiconductor region are provided with solder ribbon connection segments; a row of solder ribbon connection segments provided at the same horizontal position in the first semiconductor region is a first solder ribbon connection layer array, and a row of solder ribbon connection segments provided at the same horizontal position in the second semiconductor region is a second solder ribbon connection layer array;
[0039] Step C: A first solder ribbon insulating layer array is disposed on the surface of each first semiconductor region at the same horizontal position as each second solder ribbon connecting layer array, and a second solder ribbon insulating layer array is disposed on the surface of each second semiconductor region at the same horizontal position as each first solder ribbon connecting layer array.
[0040] The specific method of step A is as follows: the first semiconductor region and the second semiconductor region are alternately disposed on the first main surface of the semiconductor substrate from left to right, an isolation region is disposed between the first semiconductor region and the second semiconductor region, and an isolation trench is disposed on the isolation region.
[0041] The first semiconductor region forms a first type semiconductor film layer and a first conductive film layer sequentially from bottom to top on the first main surface of the semiconductor substrate. The second semiconductor region forms a second type semiconductor film layer and a second conductive film layer sequentially from bottom to top on the first main surface of the semiconductor substrate. The isolation region forms a first type semiconductor film layer, an isolation film layer, a second type semiconductor film layer, and an isolation conductive film layer sequentially from bottom to top on the first main surface of the semiconductor substrate. An isolation groove is formed on the isolation region to divide the isolation conductive film layer into left and right parts.
[0042] The isolation groove is formed on the surface of the isolation area using laser etching or chemical etching techniques; the width of the isolation groove is 10-150 μm. The laser etching technique has a etching speed of 3-50 m / s and a pulse energy between 10 μJ and 1000 μJ. The chemical etching technique can form the isolation groove by printing protective ink followed by etching with a chemical solution, or by baking and etching with etching ink.
[0043] The first type of semiconductor film layer is mainly composed of a first passivation layer and a first semiconductor layer formed sequentially from bottom to top on the first main surface of the semiconductor substrate; the second type of semiconductor film layer is mainly composed of a second passivation layer and a second semiconductor layer formed sequentially from bottom to top on the first main surface of the semiconductor substrate; the first conductive film layer, the second conductive film layer, and the isolation conductive film layer are mainly composed of a transparent conductive layer and a metal conductive layer formed sequentially from bottom to top on the corresponding semiconductor layer; the isolation film layer is mainly composed of an isolation insulating layer formed on the first semiconductor layer in the isolation region; and an isolation groove is formed in the isolation region to separate the transparent conductive layer and the metal conductive layer into left and right parts.
[0044] The first passivation layer and the second passivation layer are at least one of intrinsic amorphous silicon and intrinsic microcrystalline silicon. The first semiconductor layer and the second semiconductor layer are either N-type doped amorphous silicon / microcrystalline silicon layers or P-type doped amorphous silicon / microcrystalline silicon layers. When the first semiconductor layer is an N-type doped amorphous silicon / microcrystalline silicon layer, the second semiconductor layer is a P-type doped amorphous silicon / microcrystalline silicon layer; when the first semiconductor layer is a P-type doped amorphous silicon / microcrystalline silicon layer, the second semiconductor layer is an N-type doped amorphous silicon / microcrystalline silicon layer. The insulating layer is at least one of silicon nitride, silicon oxide, and silicon carbide.
[0045] The transparent conductive layer and the metallic conductive layer are deposited using physical vapor deposition (PVD) or reactive plasma deposition (RPD) techniques. The transparent conductive film is at least one of indium tin oxide (ITO), aluminum-doped zinc oxide (AZO), gallium-doped zinc oxide (GZO), zinc-doped indium oxide (IZO), and tungsten-doped indium oxide (IWO), with a thickness of 50-100 nm and a sheet resistance of 20-100 Ω / □. The metallic conductive film is at least one of copper (Cu), aluminum (Al), nickel (Ni), nickel alloys, and indium tin oxide (ITO), with a thickness of 200-600 nm and a sheet resistance of 0.02-0.5 Ω / □.
[0046] The resistance between the metal conductive layers on both sides of the isolation groove is greater than 1KΩ.
[0047] The specific method of step B is to alternately set a first solder ribbon connection layer array and a second solder ribbon connection layer array from top to bottom on the first main surface of the semiconductor substrate where the first semiconductor region and the second semiconductor region are set using screen printing or printing technology; there are two or more of the first solder ribbon connection layer array and the second solder ribbon connection layer array.
[0048] The first and second solder strip connection layer arrays are formed by screen printing or printing of solderable low-temperature silver paste, solderable silver-coated copper paste or solderable nickel paste, followed by baking at 150-230℃ for 5-40 minutes to cure. The thickness is 5-30 μm and the length is 1-10 mm.
[0049] The specific method of step C is to form a second solder ribbon insulating layer array or a first solder ribbon insulating layer array at a horizontal position corresponding to the first solder ribbon connecting layer array or the second solder ribbon connecting layer array using screen printing or printing technology.
[0050] The first and second solder ribbon insulating layer arrays are formed by curing insulating ink by baking at 130-200℃ for 5-30 minutes after screen printing or printing. The thickness is 3-25um, the length is 1-10mm, and the width is 0.3-0.8mm.
[0051] On the second main surface of the semiconductor substrate, a fourth passivation layer and an antireflection layer are sequentially formed from bottom to top, with the semiconductor substrate as the base. The fourth passivation layer is at least one of intrinsic amorphous silicon, intrinsic microcrystalline silicon, N-type doped amorphous silicon, and N-type doped microcrystalline silicon; the antireflection layer is at least one of silicon nitride, silicon oxide, silicon carbide, and a transparent conductive film.
[0052] The semiconductor substrate is a cast monocrystalline silicon wafer, a monocrystalline silicon wafer, or a polycrystalline silicon wafer.
[0053] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.
[0054] The present invention will now be described in detail with reference to the accompanying drawings and embodiments:
[0055] like Figures 1 to 10 The diagram shown is an embodiment of a method for fabricating a multi-busbar back-contact heterojunction solar cell provided by the present invention.
[0056] This invention discloses a method for fabricating a multi-busbar back-contact heterojunction solar cell. Specifically, the following implementation methods can be adopted, such as... Figure 1-10 As shown:
[0057] S1. An n-type silicon wafer 10 is provided with a passivation layer 30 and an anti-reflection layer 31 formed on the front side, and a first semiconductor region 42, an isolation region 44, and a second semiconductor region 43 arranged in a cross pattern on the back side.
[0058] S2. A transparent conductive film layer 50 and a metal conductive film layer 51 are deposited on the back side of the silicon wafer 10 using physical vapor deposition (PVD) technology.
[0059] S3. An isolation groove 53 is formed on the surface of the isolation zone 44 by chemical etching technology.
[0060] S4. An alternating solder ribbon connection layer 60 is formed on the surfaces of the first semiconductor region 42 and the second semiconductor region 43 using screen printing technology.
[0061] S5. An insulating layer 61, which is alternately arranged with the solder ribbon connection layer 60, is formed on the surface of the first semiconductor region 42 and the second semiconductor region 43 by screen printing technology.
[0062] like Figure 2The diagram shows a cross-sectional view of the n-type silicon wafer 10 provided in S1. The passivation layer 30 formed on the front side of the silicon wafer 10 is intrinsically oxygen-doped microcrystalline silicon with a thickness of 5-15 nm, and the antireflection layer 31 is silicon nitride with a thickness of 80-150 nm, formed by plasma-enhanced chemical vapor deposition (PECVD). The first semiconductor region 42 has a first passivated amorphous silicon layer 20 and an N-type doped amorphous silicon and microcrystalline silicon composite layer 21 sequentially disposed on the surface of the silicon wafer 10. The second semiconductor region 43 has a second passivated amorphous layer 40 and a P-type doped amorphous silicon and microcrystalline silicon composite semiconductor layer 41 sequentially disposed on the surface of the silicon wafer 10. The isolation region 44 has, sequentially disposed on the surface of the silicon wafer 10, a first passivated amorphous silicon layer 20, an N-type doped amorphous silicon and microcrystalline silicon composite semiconductor layer 21, a silicon nitride isolation layer 22, a second passivated amorphous layer 40, and a P-type doped amorphous silicon and microcrystalline silicon composite semiconductor layer 41. The thicknesses of the first passivated amorphous silicon layer 20, the N-type doped amorphous silicon and microcrystalline silicon composite semiconductor layer 21, the second passivated amorphous layer 40, and the P-type doped amorphous silicon and microcrystalline silicon composite semiconductor layer 41 are 5-15 nm, and the thickness of the silicon nitride isolation layer 22 is 80-150 nm. All of these layers are formed by PECVD deposition. The silicon wafer 10 can be a cast monocrystalline silicon wafer or a monocrystalline silicon wafer.
[0063] like Figure 3 The figure shows a cross-sectional view of a transparent conductive film layer 50 and a metallic conductive film layer 51 deposited on the back side of silicon wafer 10 in S2. The transparent conductive film layer 50 is indium tin oxide (ITO) with a thickness of 80-100 nm and a sheet resistance of 30-40 Ω / □. The metallic conductive film layer is a copper (Cu) and nickel-copper alloy composite layer, wherein the copper layer has a thickness of 300 nm, the nickel-copper alloy layer has a thickness of 100 nm, and the sheet resistance is 0.05-0.08 Ω / □.
[0064] like Figure 4-6 The diagram shows the formation of isolation trenches 53 on the surface of isolation region 44 using chemical etching technology on the back side of S3 silicon wafer 10. Figure 4 A cross-sectional view of the surface of the isolation region 44 on the back of silicon wafer 10, where etching ink 52 is printed. Figure 5 A cross-sectional view of the isolation trench 53 formed in the isolation region 44 on the back side of silicon wafer 10. Figure 6 This is a schematic diagram of the structure of the isolation trench 53 formed on the back side of the silicon wafer 10. The isolation trench 53 is formed by baking and etching with printed etching ink 52. The width of the isolation trench 53 is 30-80um, the baking temperature is 100-180℃, the baking time is 3-30M, and the etching ink is removed with water after baking. The resistance between the metal conductive layers on both sides of the isolation trench 53 is greater than 1KΩ.
[0065] like Figure 7-8 The diagram shows an alternating layer of solder ribbons 60 formed on the back side of the S4 silicon wafer 10. Figure 7 A cross-sectional view of the alternating spacing solder strip interconnect layer 60 formed on the back side of silicon wafer 10. Figure 8 This is a schematic diagram of the alternating spacing of solder ribbon interconnect layers 60 formed on the back side of silicon wafer 10. The solder ribbon interconnect layers 60 are made of solderable low-temperature silver paste, with a thickness of 10-15 μm and a length of 5 mm. They are formed by printing and then baking at 190°C for 20 minutes to cure. The solder ribbon interconnect layers 60 are arranged alternately on the surfaces of the first semiconductor layer region 42 and the second semiconductor layer region 43. Each column of solder ribbon interconnect layers 60 perpendicular to the isolation trench 53 corresponds to a main gate, and there are 10 columns of solder ribbon interconnect layers 60.
[0066] like Figure 9-10 The diagram shows an S5 silicon wafer 10 with an insulating layer 61 alternating with the solder ribbon connection layer 60 formed on its back side. Figure 9 A cross-sectional view of the alternating insulating layers 61 formed on the back side of the silicon wafer 10. Figure 10 This is a schematic diagram of the alternating insulating layers 61 formed on the back side of the silicon wafer 10. The insulating layers 61 are formed by printing insulating ink and baking at 150°C for 20 minutes to cure. The insulating layer has a thickness of 5-10 μm, a length of 6 mm, and a width of 0.5-0.8 mm. The insulating layers 61 and the solder ribbon connection layer 60 are arranged alternately.
[0067] This invention, employing the above technical solutions, enables a multi-busbar structure for back-contact heterojunction solar cells, significantly reducing the conductivity requirements of the fine grid lines on the solar cells. Simultaneously, it utilizes a physical vapor deposition (PVD) metal conductive layer as the fine grid electrode, and only the solder ribbon connection layer uses conventionally used low-temperature silver paste. This reduces the silver paste consumption per G1 silicon wafer to 30-50 mg, far lower than the approximately 200 mg consumption of conventional heterojunction cells. Furthermore, it avoids the use of large-scale wet copper plating equipment, eliminating concerns about copper-containing wastewater treatment, environmental protection, large production sites, and high operating costs. Therefore, it greatly simplifies the cell manufacturing process, reduces production costs, and is highly beneficial for the mass production and promotion of high-efficiency back-contact heterojunction solar cells.
[0068] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.
Claims
1. A multi-busbar back-contact heterojunction solar cell, characterized in that: It includes a semiconductor substrate, a plurality of first semiconductor regions and second semiconductor regions disposed on a first main surface of the semiconductor substrate and alternately arranged from left to right, an isolation trench disposed between each of the first semiconductor regions and the second semiconductor regions, a column or more of first solder ribbon connection layer arrays horizontally disposed on each of the first semiconductor regions, a column or more of second solder ribbon connection layer arrays horizontally disposed on each of the second semiconductor regions, a column or more of first solder ribbon insulating layer arrays disposed on the surface of each of the first semiconductor regions and correspondingly disposed at the same horizontal position as each of the second solder ribbon connection layer arrays, and a column or more of second solder ribbon insulating layer arrays disposed on the surface of each of the second semiconductor regions and correspondingly disposed at the same horizontal position as each of the first solder ribbon connection layer arrays. The first and second solder ribbon connection layer arrays are staggered from top to bottom, and the corresponding solder ribbon connection layer arrays and corresponding solder ribbon insulating layer arrays are alternately arranged on the same semiconductor region. It also includes a first conductive film layer disposed on top of the first semiconductor region and a second conductive film layer disposed on top of the second semiconductor region. The first and second conductive film layers are respectively composed of a transparent conductive layer and a metal conductive layer formed sequentially from bottom to surface on the corresponding semiconductor layer as a substrate. The metal conductive layer serves as a fine gate electrode, and covers the entire outer surface of the corresponding transparent conductive layer below it, with the outer surface of the metal conductive layer being planar. The first solder ribbon connection layer array and... The first solder ribbon insulating layer array is respectively disposed at corresponding positions on the outer surface of the metal conductive layer in the first conductive film layer; the second solder ribbon connecting layer array and the second solder ribbon insulating layer array are respectively disposed at corresponding positions on the outer surface of the metal conductive layer in the second conductive film layer; the transparent conductive layer is at least one of indium tin oxide layer, aluminum-doped zinc oxide layer, gallium-doped zinc oxide layer, zinc-doped indium oxide layer, and tungsten-doped indium oxide layer, with a total thickness of 50-100 nm and a total sheet resistance of 20-100 Ω / □; the metal conductive layer is at least one of copper layer, aluminum layer, nickel layer, and nickel alloy layer, with a total thickness of 400-600 nm and a total sheet resistance of 0.02-0.5 Ω / □.
2. The multi-busbar back-contact heterojunction solar cell according to claim 1, characterized in that: An isolation region is provided between the first semiconductor region and the second semiconductor region, and the isolation trench is disposed on the isolation region.
3. The multi-busbar back-contact heterojunction solar cell according to claim 2, characterized in that: The first semiconductor region includes a first type semiconductor film layer formed sequentially from bottom to top on the first main surface of the semiconductor substrate, and a first conductive film layer disposed on the surface of the first type semiconductor film layer. The second semiconductor region includes a second type semiconductor film layer formed sequentially from bottom to top on the first main surface of the semiconductor substrate, and a second conductive film layer disposed on the surface of the second type semiconductor film layer. The isolation region includes a first type semiconductor film layer, an isolation film layer, a second type semiconductor film layer, and an isolation conductive film layer formed sequentially from bottom to top on the first main surface of the semiconductor substrate. The isolation trench divides the isolation conductive film layer into left and right parts.
4. The multi-busbar back-contact heterojunction solar cell according to claim 3, characterized in that: The first type of semiconductor film layer includes a first passivation layer and a first semiconductor layer formed sequentially from bottom to top on a first main surface of a semiconductor substrate; the second type of semiconductor film layer includes a second passivation layer and a second semiconductor layer formed sequentially from bottom to top on a first main surface of a semiconductor substrate; the isolation conductive film layer includes a transparent conductive layer and a metal conductive layer formed sequentially from bottom to top on a corresponding semiconductor layer; the isolation film layer includes an isolation insulating layer formed in the isolation region on a first semiconductor layer.
5. The method for fabricating a multi-busbar back-contact heterojunction solar cell according to any one of claims 1-4, characterized in that: It includes the following steps: Step A: A first semiconductor region and a second semiconductor region are alternately disposed from left to right on the first main surface of the semiconductor substrate, and an isolation trench is disposed between the first semiconductor region and the second semiconductor region. Step B: On the first main surface of the semiconductor substrate where the first semiconductor region and the second semiconductor region are formed, two or more columns of solder ribbon connection sections are staggered from top to bottom; each column of solder ribbon connection sections is only provided in the first semiconductor region or the second semiconductor region, and the first semiconductor region and the second semiconductor region are respectively provided with one or more columns of solder ribbon connection sections, and each first semiconductor region and each second semiconductor region are provided with solder ribbon connection sections. A column of solder ribbon connection sections located at the same horizontal position in the first semiconductor region is a first solder ribbon connection layer array, and a column of solder ribbon connection sections located at the same horizontal position in the second semiconductor region is a second solder ribbon connection layer array. Step C: First solder pad insulating layer arrays are disposed on the surface of each first semiconductor region at the same horizontal position as each second solder pad connection layer array, and second solder pad insulating layer arrays are disposed on the surface of each second semiconductor region at the same horizontal position as each first solder pad connection layer array. In step A, the process before setting the isolation trench is to sequentially form a transparent conductive layer and a metal conductive layer on the first main surface of the semiconductor substrate.
6. The method for fabricating a multi-busbar back-contact heterojunction solar cell according to claim 5, characterized in that: The specific method of step A is as follows: the first semiconductor region and the second semiconductor region are alternately disposed on the first main surface of the semiconductor substrate from left to right, an isolation region is disposed between the first semiconductor region and the second semiconductor region, and an isolation trench is disposed on the isolation region.
7. The method for fabricating a multi-busbar back-contact heterojunction solar cell according to claim 6, characterized in that: The first semiconductor region forms a first type semiconductor film layer and a first conductive film layer sequentially from bottom to top on the first main surface of the semiconductor substrate. The second semiconductor region forms a second type semiconductor film layer and a second conductive film layer sequentially from bottom to top on the first main surface of the semiconductor substrate. The isolation region forms a first type semiconductor film layer, an isolation film layer, a second type semiconductor film layer, and an isolation conductive film layer sequentially from bottom to top on the first main surface of the semiconductor substrate. An isolation groove is formed on the isolation region to divide the isolation conductive film layer into left and right parts.
8. The method for fabricating a multi-busbar back-contact heterojunction solar cell according to claim 6, characterized in that: The isolation groove is formed on the surface of the isolation area by laser etching or chemical etching technology; the width of the isolation groove is 10-150um.
9. The method for fabricating a multi-busbar back-contact heterojunction solar cell according to claim 7, characterized in that: The first type of semiconductor film layer is mainly composed of a first passivation layer and a first semiconductor layer formed sequentially from bottom to top on the first main surface of the semiconductor substrate; the second type of semiconductor film layer is mainly composed of a second passivation layer and a second semiconductor layer formed sequentially from bottom to top on the first main surface of the semiconductor substrate; the first conductive film layer, the second conductive film layer, and the isolation conductive film layer are mainly composed of a transparent conductive layer and a metal conductive layer formed sequentially from bottom to top on the corresponding semiconductor layer; the isolation film layer is mainly composed of an isolation insulating layer formed on the first semiconductor layer in the isolation region; and an isolation groove is formed in the isolation region to separate the transparent conductive layer and the metal conductive layer into left and right parts.
10. The method for fabricating a multi-busbar back-contact heterojunction solar cell according to claim 9, characterized in that: The resistance between the metal conductive layers on both sides of the isolation groove is greater than 1KΩ.
11. The method for fabricating a multi-busbar back-contact heterojunction solar cell according to claim 5, characterized in that: The specific method of step C is to form a second solder ribbon insulating layer array or a first solder ribbon insulating layer array at a horizontal position corresponding to the first solder ribbon connecting layer array or the second solder ribbon connecting layer array using screen printing or printing technology.
12. The method for fabricating a multi-busbar back-contact heterojunction solar cell according to claim 11, characterized in that: The first and second solder ribbon insulating layer arrays are formed by curing insulating ink after screen printing or printing. The thickness is 3-25um, the length is 1-10mm, and the width is 0.3-0.8mm.
13. The method for fabricating a multi-busbar back-contact heterojunction solar cell according to any one of claims 5-12, characterized in that: The specific method of step B is to alternately set a first solder ribbon connection layer array and a second solder ribbon connection layer array from top to bottom on the first main surface of the semiconductor substrate where the first semiconductor region and the second semiconductor region are set using screen printing or printing technology; there are two or more of the first solder ribbon connection layer array and the second solder ribbon connection layer array.
14. The method for fabricating a multi-busbar back-contact heterojunction solar cell according to claim 13, characterized in that: The first and second solder strip connection layer arrays are formed by screen printing or printing of solderable low-temperature silver paste, solderable silver-coated copper paste or solderable nickel paste and then curing, with a thickness of 5-30um and a length of 1-10mm.