Daisy chain clock distribution system

Abstract

This application relates to a daisy chain clock distribution system and discloses a circuit (100a) comprising a first power converter (108a) having a first voltage input (110a) and a first output (116a or 117a). The circuit (100a) further comprises a second power converter (108b) having a second voltage input (110b) coupled to the first voltage input (110a), a clock input (112b), and a second output (116b or 117b). A phase shifter (118b) is coupled between the first output (116a or 117a) and the clock input (112b) of the second power converter (108b).

Description

[0001] Citation of relevant applications

[0002] This application claims the benefit of U.S. Provisional Application No. 63 / 031,814, filed on May 29, 2020, the entire contents of which are incorporated herein by reference. Background Technology

[0003] DC-to-DC converters and AC-to-DC converters (collectively referred to as power converters) are widely used in devices that perform power conversion today. Generally, a power converter receives a nominal voltage from a power source (such as a battery) and provides a regulated output voltage at one or more voltage levels. Various power converters and topologies can be used to perform this power conversion. For example, buck converters, boost converters, and buck-boost converters are three basic types of power converter technology. Summary of the Invention

[0004] In one example, a circuit includes a first power converter having a first voltage input and a first output. The circuit also includes a second power converter having a second voltage input coupled to the first voltage input, a clock input, and a second output. A phase shifter is coupled between the first output and the clock input of the second power converter.

[0005] In another example, a circuit includes a first DC-DC power converter having a first voltage input, a first output, and a first feedback input coupled to the first output. A first inductor has a first inductor terminal and a second inductor terminal. The first inductor terminal is coupled to the first output. A second power converter has a second voltage input coupled to the first voltage input, and also has a clock input, a second output, and a second feedback input coupled to the first output. The second inductor has a third inductor terminal and a fourth inductor terminal. The third inductor terminal is coupled to the second output, and the fourth inductor terminal is coupled to the second inductor terminal. A phase shifter is coupled between the first output and the clock input of the second power converter.

[0006] In another example, a circuit includes a first power converter having a first voltage input, a first switching output, a first clock output, and a first feedback input coupled to the first switching output. A first inductor has a first inductor terminal and a second inductor terminal. The first inductor terminal is coupled to the first switching output. A second power converter has a second voltage input coupled to the first voltage input, a clock input, a second switching output, and a second feedback input coupled to the first clock output. The second inductor has a third inductor terminal and a fourth inductor terminal. The third inductor terminal is coupled to the second switching output, and the fourth inductor terminal is coupled to the second inductor terminal. A phase shifter is coupled between the first clock output and the clock input of the second power converter. Attached Figure Description

[0007] Figure 1A These are schematic diagrams illustrating some examples of circuits including multiple power converters arranged in a multiphase configuration.

[0008] Figure 1B The illustration shows the inclusion of Figure 1A The circuit of an example implementation of a phase shifter and power converter package.

[0009] Figure 2 The diagram illustrates some examples of signal curves for a multiphase regulator circuit arranged in a three-phase configuration.

[0010] Figure 3 The diagram illustrates some examples of phase shift configurations for power converters in a multiphase regulator circuit.

[0011] Figure 4 The diagram illustrates some examples of signal graphs for a multiphase regulator circuit arranged in a two-phase configuration.

[0012] Figure 5A This is a schematic diagram illustrating some examples of circuits in which each power converter has a feedback input and a compensation terminal.

[0013] Figure 5B The illustration shows the inclusion of Figure 5A The circuit of an example implementation of a phase shifter and power converter package.

[0014] Figure 6A This is a schematic diagram illustrating some examples of circuits in which each power converter has a clock output.

[0015] Figure 6B The illustration shows the inclusion of Figure 6A The circuit of an example implementation of a phase shifter and power converter package.

[0016] Figure 7 and Figure 8This is a flowchart of some examples of methods for operating a multiphase regulator that includes multiple power converters. Detailed Implementation

[0017] Many modern devices include power electronic devices. For example, a device may include a multiphase regulator circuit comprising multiple power converters arranged in parallel with each other. This circuit can be used to convert an input voltage into an output voltage and maintain the output voltage at a set level independent of the load at the output of the regulator circuit. Because the power converters are arranged in parallel, they have corresponding inputs coupled to a common voltage input and corresponding outputs coupled to a common voltage output.

[0018] In some cases, this voltage regulation is achieved by providing each power converter with a different clock signal to turn the power converter on and off at different times. In this case, the power converters operate at the same frequency as each other, but each power converter operates with a different phase than the others. More specifically, this is achieved by inputting a common clock signal to each power converter in a parallel configuration and by coupling different resistors to the phase control pins of each power converter to achieve different phases. Each power converter receiving the common clock signal may include a phase-locked loop (PLL) to adjust the phase of the common clock to the phase set by the phase control pin.

[0019] The challenge with these multiphase regulator circuits is that the need for phase control pins to set the phase of each power converter can increase the size of the power converter and / or the cost of manufacturing the power converter on an integrated circuit (IC). Furthermore, given the limited pin count of an IC, eliminating the need for these phase control pins to free them up for other purposes is beneficial. Additionally, the need for a PLL to adjust the phase of the common clock to the phase set by the phase control pins can further increase the size of the power converter and / or the cost of the power converter used in the circuit.

[0020] Various examples in this specification relate to circuits including clock distribution systems that allow for reduced circuit size and / or lower circuit cost. The circuit includes a first power converter and a second power converter. The first power converter has a first voltage input and a first output. The second power converter has a second voltage input coupled to the first voltage input, a clock input, and a second output. A phase shifter is coupled between the first output and the clock input of the second power converter. In some cases, this clock distribution system may be referred to as having a "daisy-chain" design, meaning that the power converters are coupled together in a sequence, wherein the output of one power converter in the sequence is coupled via a phase shifter to the clock input of the next power converter in the sequence.

[0021] By coupling the first output to the clock input of the second power converter using a phase shifter, a multiphase system can be created where the first and second power converters share a common clock frequency, but the second power converter has a different phase than the first power converter, without using additional pins (e.g., phase control pins) to set the clock phase at each power converter. As a result, the circuit size and / or cost of the generation circuitry can be reduced. Furthermore, since the clock signal supplied to the power converters has the desired frequency and phase for each power converter when supplied to those power converters, PLLs can be eliminated from each power converter. Therefore, the circuit size and / or cost of the generation circuitry can be further reduced.

[0022] Figure 1A This is a schematic diagram showing some examples of a circuit 100a including multiple power converters 108a-108n arranged in a multiphase configuration.

[0023] As shown in the figure, circuit 100a includes a first power converter 108a, a second power converter 108b, a third power converter 108c, and so on up to an Nth power converter 108n. Each power converter 108a-108n has a corresponding voltage input (e.g., first voltage input 110a to Nth voltage input 110n), a corresponding clock input (e.g., first clock input 112a to Nth clock input 112n), a corresponding ground terminal (e.g., first ground terminal 114a to Nth ground terminal 114n), and a corresponding switch output (e.g., first switch output 116a to Nth switch output 116n). In some examples, each power converter 108a-108n also has a corresponding clock output (e.g., first clock output 117a to Nth clock output 117n).

[0024] Generally, N can be any integer from 2 to infinity, but in one example, N ranges from 2 to 18. Furthermore, input, output, and ground terminals are examples of conductors that allow electrical and / or mechanical coupling into or out of circuits, circuit elements, devices, systems, etc. Input, output, and ground terminals can be interchangeably referred to as input terminals, output terminals, and ground terminals. Additionally, terminals can be interchangeably referred to as pins, for example, where a pin is a point connected to or from an IC chip or package.

[0025] Each voltage input 110a-110n is coupled to voltage input terminal 102. Voltage input terminal 102 can be coupled to a voltage source (not shown). Therefore, each voltage input 110a-110n can receive an input voltage from a voltage source through voltage input terminal 102. Load 126 is coupled between voltage output terminal 104 and a reference voltage power supply, in this case, the reference voltage power supply is electrical ground 124. As shown, each ground terminal 114a-114n can receive a common reference voltage, such as electrical ground 124.

[0026] As further shown, inductors 120a-120n are coupled between each switch output 116a-116n and voltage output terminal 104, respectively. More specifically, the first inductor 120a is coupled between switch output 116a and voltage output terminal 104. The second inductor 120b is coupled between switch output 116b and voltage output terminal 104. The third inductor 120c is coupled between switch output 116c and voltage output terminal 104. The Nth inductor 120n is coupled between switch output 116n and voltage output terminal 104. The illustrated circuit 100a is a buck converter, which means that the output voltage at voltage output terminal 104 is less than the input voltage at voltage input terminal 102 because each power converter has an inductor between the switch output and voltage output terminal 104.

[0027] Phase shifters 118a-118n are coupled to clock inputs 112a-112n, respectively. More specifically, the first phase shifter 118a is coupled to clock input 112a. The second phase shifter 118b is coupled to clock input 112b. The third phase shifter 118c is coupled to clock input 112c. The Nth phase shifter 118n is coupled to clock input 112n.

[0028] In some examples, power converters 108a-108n do not have clock outputs 117a-117n. Therefore, phase shifter 118a is coupled between clock source 122 and clock input 112a. Phase shifter 118b (e.g., via connection 119a) is coupled between switch output 116a and clock input 112b. Phase shifter 118c (e.g., via connection 119c) is coupled between switch output 116b and clock input 112c, and so on.

[0029] In an alternative example, power converters 108a-108n have clock outputs 117a-117n. Accordingly, phase shifter 118a is coupled between clock source 122 and clock input 112a. Phase shifter 118b (e.g., via connection 119b) is coupled between clock output 117a and clock input 112b. Phase shifter 118c (e.g., via connection 119d) is coupled between clock output 117b and clock input 112c, and so on.

[0030] In some examples, circuit 100a is configured to operate as a multiphase buck regulator, and each power converter 108a-108n is a switch-mode DC-DC converter. In such an example, circuit 100a is configured to convert the input DC voltage at voltage input terminal 102 into an output DC voltage at voltage output terminal 104 that is less than the input DC voltage. Circuit 100a is also configured to regulate the output voltage at voltage output terminal 104 independently of the load 126 applied at voltage output terminal 104. This is achieved by providing each power converter with a different clock signal to turn the power converter on and off at different times, thereby supplying current to different inductors at different times. In other examples, each power converter 108a-108n is an AC-DC converter.

[0031] Clock source 122 provides a first signal (e.g., a clock signal) having a common frequency and a first phase to phase shifter 118a. Phase shifter 118a is configured to provide a second signal having a common frequency and a second phase different from the first phase to clock input 112a. In such an example, power converter 108a performs switching based on the second signal. In some other examples, a clock signal is not received from phase shifter 118a, and power converter 108a alternatively operates based on an internal clock generated by an internal oscillator included in power converter 108a.

[0032] In some examples of power converters 108a-108n without clock outputs 117a-117n, power converter 108a is configured to provide a third signal with a common frequency and a second phase from switch output 116a to inductor 120a and phase shifter 118b. Phase shifter 118b is configured to provide a fourth signal with a common frequency and a third phase different from the first and second phases to clock input 112b. Power converter 108b is configured to provide a fifth signal with a common frequency and a third phase from switch output 116b to inductor 120b and phase shifter 118c. Phase shifter 118c is configured to provide a sixth signal with a common frequency and a fourth phase to clock input 112c, and so on, up to phase shifter 118n, power converter 108n, and inductor 120n.

[0033] In some other examples where power converters 108a-108n also include clock outputs 117a-117n, power converter 108a is configured to provide a third signal with a common frequency and a second phase to inductor 120a from switch output 116a, and a fourth signal with a common frequency and a second phase from clock output 117a to phase shifter 118b. Phase shifter 118b is configured to provide a fifth signal with a common frequency and a third phase different from the first and second phases to clock input 112b. Power converter 108b is configured to provide a sixth signal with a common frequency and a third phase to inductor 120b from switch output 116b, and a seventh signal with a common frequency and a third phase from clock output 117b to phase shifter 118c. Phase shifter 118c is configured to provide an eighth signal with a common frequency and a fourth phase to clock input 112c, and so on, up to phase shifter 118n, power converter 108n, and inductor 120n. In some examples, the fourth signal is the same as the second signal, and the seventh signal is the same as the fifth signal.

[0034] In some examples, each phase shifter 118a-118n is configured to shift the phase of the signal supplied to that phase shifter by approximately 140 degrees, for example, approximately 135 to 145 degrees, or some other suitable value. For example, when the first phase is 0 degrees, the second phase is 140 degrees, the third phase is 280 degrees, and so on, such that the Nth phase is equal to 140 degrees multiplied by N-1. As mentioned earlier, in one example, N is an integer between 2 and 18, or some other suitable integer. In some cases, when N equals 19 or more, the phases of different converters overlap. For example, the phase of the first power converter 108a overlaps with the phase of the 19th power converter because 140 multiplied by 18 equals 2520 degrees, which is a multiple of 360 degrees. However, for such multi-phase circuits, any effect of phase overlap on the circuit is negligible. Therefore, as a practical example, consider a situation where there is a second phase of 140 degrees (e.g., 140 degrees multiplied by 1) and a fourth phase of 420 degrees (e.g., 140 degrees multiplied by 3). Because the waveform repeats every 360 degrees, the fourth phase of 420 degrees will actually appear as a phase shift from zero to 60 degrees. Therefore, when comparing the second phase (e.g., a 140-degree phase shift starting from zero) and the fourth phase (e.g., equivalent to a 60-degree phase shift starting from zero), the two phases will exhibit a phase difference of only 80 degrees from each other.

[0035] In some examples, power converters 108a-108n are separate integrated circuits, and switch outputs 116a-116n correspond to corresponding switch output pins, and clock inputs 112a-112n correspond to corresponding clock input pins. By coupling each switch output pin to the subsequent clock input pin via a corresponding phase shifter, each power converter can receive a common clock frequency and corresponding phase without the need for additional pins (e.g., phase control pins) to set the phase of the clock signal at each power converter, as practiced in other methods. As a result, the circuit size and / or cost of the generation circuitry can be reduced compared to these other methods. Furthermore, while other methods have included separate PLLs for each power converter, this method eliminates these PLLs. This is because the appropriate frequency and phase are provided to the clock input pin of each power converter, thus eliminating the need for a PLL to adjust the phase of the clock signal at each power converter to the phase set by the phase control pin. Therefore, the circuit size and / or cost of the generation circuitry can be further reduced.

[0036] In some examples, Figure 1A In this circuit, the power converter can automatically adjust for any frequency change at any converter without requiring further input. For example, if the first signal experiences a frequency change, then due to... Figure 1AThe illustrated circuit 100a is designed in series, with subsequent signals reflecting this frequency change. Therefore, the circuit's performance can be improved. This can be used in many different applications, such as spread spectrum operation.

[0037] In some examples, the phase shifter and its corresponding power converter are included in a single integrated circuit and / or a single package. For example, in such an example, phase shifter 118a and power converter 108a are both included in a first package 106a. Phase shifter 118b and power converter 108b are both included in a second package 106b. Phase shifter 118c and power converter 108c are both included in a third package 106c. Phase shifter 118n and power converter 108n are both included in an Nth package 106n. In some examples, such as Figure 1A The diagram illustrates the coupling of different packages together for assembly. Figure 1A Circuit 100a. This approach using N packages allows inductors that typically consume large areas on integrated circuits to be implemented as discrete inductors, and allows for better heat dissipation due to the larger area of ​​multiple packages. Therefore, this example with N packages provides a solution that supplies good reliability at a reasonable cost.

[0038] In one example, clock source 122 is an external clock generator, such as an oscillator including a resonant circuit and an amplifier, or some other suitable clock source. For example, the resonant circuit may include a quartz and / or piezoelectric oscillator, a resistor-capacitor (RC) oscillator, a ring oscillator, or other resonant circuit.

[0039] In one example, each phase shifter is or includes a resistor-capacitor (RC) delay circuit, which includes one or more resistors coupled to one or more capacitors. The delay circuit may also include one or more comparators.

[0040] Circuit 100a includes an input capacitor 128 coupled between a voltage input terminal 102 and an electrical ground 124. Circuit 100a also includes an output capacitor 130 coupled between a voltage output terminal 104 and an electrical ground 124 and coupled in parallel with a load 126. Although only one input capacitor 128 and one output capacitor 130 are shown, circuit 100a may include additional input and / or output capacitors. The load 126 may be a low-voltage, high-current device comprising hardware or a combination of hardware and software, or it may be another type of load. For example, the load 126 may include any load that consumes current at a given voltage, such as a resistor, a sink, a microcontroller, a field-programmable gate array (FPGA), and / or a light-emitting diode (LED).

[0041] In some examples, the voltage source (not shown) includes a power source, a battery, or some other suitable voltage source. For example, the voltage source is a lithium-ion battery.

[0042] In some examples, Figure 1A This circuit is used in many different technologies, such as camera technology, sensor technology, digital cockpit technology, storage technology, optical network and communication technology, and core supply technology. Furthermore, compared to other methods, this circuit can improve performance and reduce costs. For example, in some cameras and sensors, Figure 1A The circuit offers a small package and provides a 1% gain in the accuracy of the sensor and / or camera, and can reduce costs by eliminating the need for external feedback voltage resistors as presented in some previous methods.

[0043] Figure 1B The illustration shows the inclusion of Figure 1A The circuit 100b is an example implementation of the package 106a of the phase shifter 118a and the power converter 108a. Each package 106a-106n can be implemented similarly.

[0044] As shown in the figure, phase shifter 118a includes resistor 138, comparator 142, and capacitor 140. Resistor 138 has a first resistor terminal coupled to input 132 of the phase shifter and a second resistor terminal coupled to comparator input 142. The comparator has a comparator output coupled to output 134 of phase shifter 118a. A first capacitor terminal of capacitor 140 is coupled to the second resistor terminal and input of comparator 142. A second terminal of capacitor 140 is coupled to electrical ground 124. In one example, comparator 142 is or includes a Schmitt trigger, but may alternatively be or include any suitable comparator topology.

[0045] In some examples, the power converter 108a includes a switch control circuit 144, a first transistor 146, a second transistor 148, and an inverter 150. Each transistor includes a control terminal, a first transistor terminal, and a second transistor terminal. Transistor 146 has a first transistor terminal coupled to a voltage input 110a, a second transistor terminal coupled to a switch output 116a, and a control terminal coupled to an input 145 of the inverter 150. Transistor 148 has a first transistor terminal coupled to the switch output 116a, a second transistor terminal coupled to a ground terminal 114a, and a control terminal coupled to the output of the inverter 150. The switch control circuit 144 has an input coupled to a clock input 112a and an output coupled to the control terminals of transistors 146 and 148. The inverter 150 has an input coupled to the output of the switch control circuit 144 and the control terminal of transistor 148. In some examples, the switch control circuit 144 includes one or more amplifiers, modulators, driver circuits, or other suitable circuitry. Although Figure 1B The diagram illustrates a transistor with the same circuit symbol as a metal-oxide-semiconductor field-effect transistor (MOSFET). However, other transistors can also be used, such as bipolar junction transistors (BJTs), finned FETs, and / or junction FETs.

[0046] In some examples, the power converter 108a may additionally have a clock output 117a. The clock output 117a is coupled to the clock input 112a, the switch control circuit 144, or the output of the switch control circuit 144 (e.g., any of them connected by dashed lines).

[0047] In some examples of the power converter 108a without a clock output 117a, the input 145 of the inverter 150 is coupled to the switch output 116a. In some examples of the power converter 108a that also has a clock output 117a, the input 145 of the inverter 150 is coupled to both the switch output 116a and the clock output 117a.

[0048] In some examples, Figure 1A The inductor 120a is coupled to the input 145 of the inverter 150 via the switch output 116a. In some examples, the power converter 108a does not have a clock output 117a. Figure 1A The phase shifter 118b is coupled to the input 145 of the inverter 150 via the switch output 116a. In some examples, the power converter 108a also has a clock output 117a. Figure 1A The phase shifter 118b is alternatively coupled to the input 145 of the inverter 150 via the clock output 117a.

[0049] In some examples, a phase-shifted clock signal is provided to the switching control circuitry 144 of the power converter 108a via clock input 112a. The switching control circuitry 144 can, for example, modify the phase-shifted clock signal (e.g., amplify the signal or perform some other operation) and transmit control signals based on the phase-shifted clock signal (e.g., ...). Figure 2 234) is provided to the control terminal of transistor 146 and to the control terminal of transistor 148 via inverter 150.

[0050] In some examples, when the control signal goes high, transistor 146 turns on and transistor 148 turns off, which pulls up the voltage at switch output 116a (e.g., to the input voltage at voltage input 110a) and isolates switch output 116a from ground terminal 114a. In some examples, when the control signal goes low, transistor 146 turns off and transistor 148 turns on, which pulls down the voltage at switch output 116a (e.g., to ground) and isolates switch output 116a from voltage input 110a.

[0051] Figure 2 The diagram illustrates a multiphase regulator circuit arranged in a three-phase configuration (e.g., with three power converters) (e.g., similar to...). Figure 1A Some example curve graphs of signals from a multiphase regulator circuit (200a-200c).

[0052] Graph 200a illustrates an input voltage signal 202 with a first amplitude 204 and an output voltage signal 206 with a second amplitude 208. In the illustrated example, which may be referred to in some cases as a "buck" converter, the second amplitude 208 is smaller than the first amplitude 204. In some other examples (not shown) (which may be referred to in some cases as a "boost" converter), the second amplitude 208 is larger than the first amplitude 204.

[0053] Through the voltage source at the voltage input terminal of the circuit (e.g., Figure 1A An input voltage signal 202 is provided at (102), and at the voltage output terminal (e.g., Figure 1A An output voltage signal 206 is provided at the voltage output terminal 104. An input voltage signal 202 is provided from the voltage input terminal to the first power converter (e.g., ...). Figure 1A The first voltage input of 108a) (e.g., Figure 1A 110a), and the second power converter (e.g., Figure 1A The second voltage input of (e.g., 108b) Figure 1A 110b) and third power converter (e.g., Figure 1A The third voltage input of the 108c) Figure 1A (110c).

[0054] Figure 200b illustrates the load current 214 and the inductor currents (e.g., first inductor current 220, second inductor current 222, and third inductor current 224). Therefore, these inductor currents are... Figure 1A Examples of switch output signals provided at switch outputs 116a-116n. In some examples, because... Figure 2 The example illustrated is a three-phase configuration, so the magnitude of the DC component of each inductor current (e.g., 226 and 228) is equal to one-third of the magnitude of the load current 214 (e.g., 216 and 218, respectively). As a result, the sum of the DC components of each inductor current equals the load current 214, such that the voltage output terminal of the circuit in which the load is coupled to the inductor (e.g., ...) Figure 1A Kirchhoff's current law is satisfied at the voltage output terminal 104.

[0055] In some examples, the AC component of the inductor current is compared with the load (e.g., Figure 1A 126) Parallel coupled output capacitors (e.g., Figure 1A (130) Absorption. In other words, the output capacitor coupled in parallel with the load can act as a low-pass filter.

[0056] In some examples, the load current varies over time. For instance, the load current 214 changes at a first time 210 and again at a second time 212. As a result, the output voltage 206 may briefly spike or drop after the first time 210 and the second time 212. Furthermore, the amplitude of the inductor current changes after the change in load current 214 to satisfy Kirchhoff's current law.

[0057] Graph 200c illustrates the first inductor current 220, the second inductor current 222, and the third inductor current 224 from the third time 230 to the fourth time 232. The magnitude of the DC component of each inductor current (e.g., 228) is equal to one-third of the magnitude of the load current 214 (e.g., 218). Furthermore, each inductor current has a different phase. For example, the first inductor current 220 depends on the first control signal 234 provided to the first power converter, the second inductor current 222 depends on the second control signal 236 provided to the second power converter, and the third inductor current 224 depends on the third control signal 238 provided to the third power converter.

[0058] For example, the first power converter (e.g., Figure 1A or Figure 1B The switching control circuit of 108a) (e.g., Figure 1B(144) Generates a first control signal 234 based on a clock signal received by the first power converter. For example, the switching control circuit of the first power converter generates the first control signal 234 such that the first control signal 234 has the same frequency and phase as the clock signal received by the first power converter. From the switching control circuit of the first power converter to the first transistor of the first power converter (e.g., Figure 1B 146) and the second transistor (e.g., Figure 1B 148) provides a first control signal 234 to control the first transistor and the second transistor. Similarly, the second power converter (e.g., Figure 1A The switching control circuit of 108b) is based on a second power converter, for example from a phase shifter (e.g., Figure 1A The second control signal 236 is generated from the clock signal received by the second power converter (118b). For example, the switching control circuit of the second power converter generates the second control signal 236 such that the second control signal 236 has the same frequency and phase as the clock signal received by the second power converter. The second control signal 236 is provided from the switching control circuit of the second power converter to the first transistor and the second transistor of the second power converter to control the first transistor and the second transistor. In addition, the third power converter (e.g., Figure 1A The switching control circuit of the 108c is based on a third power converter, such as from a phase shifter (e.g., Figure 1A The third control signal 238 is generated from the clock signal received by the third power converter (118c). For example, the switching control circuit of the third power converter generates the third control signal 238 such that the third control signal 238 has the same frequency and phase as the clock signal received by the third power converter. The third control signal 238 is provided from the switching control circuit of the third power converter to the first transistor and the second transistor of the third power converter to control the first transistor and the second transistor.

[0059] In some examples, each control signal has a common frequency. In some examples, the phase of the second control signal 236 differs from the phase of the first control signal 234 by approximately 140 degrees, and the phase of the third control signal 238 differs from the phase of the second control signal 236 by approximately 140 degrees (e.g., the phase of the first control signal 234 is 0 degrees, the phase of the second control signal 236 is 140 degrees, and the phase of the third control signal 238 is 280 degrees).

[0060] In some examples, the first control signal 234 is based on the first phase shifter (e.g., Figure 1A118a) provides a first clock signal (e.g., having the same frequency and phase as the first clock signal) to the first power converter. In some alternative examples, the first control signal 234 is based on a first clock signal generated from the internal clock signal of the first power converter (e.g., having the same frequency and phase as the first clock signal). In some examples, the second control signal 236 is based on a second clock signal (e.g., having the same frequency and phase as the second clock signal) provided to the second power converter from the output of the first power converter, and the third control signal 238 is based on a third clock signal (e.g., having the same frequency and phase as the third clock signal) provided to the third power converter from the output of the second power converter (e.g., as shown in the image). Figure 1A (As shown in the diagram).

[0061] Figure 2 The graphs 200a-200c illustrate a circuit with a buck configuration. However, it should be understood that this circuit can alternatively be configured to operate as a boost regulator or a buck-boost regulator.

[0062] Figure 3 Schematic diagrams 300a-300d illustrate some examples of phase shift configurations for power converters in a multiphase regulator circuit.

[0063] In some examples, when in Figure 1A When 140 degrees is used as the phase shift constant in a circuit, the maximum phase shift relative to a circuit with phases evenly spaced around a unit circle is about 40 degrees or less, regardless of the number of phases in the circuit (e.g., regardless of N).

[0064] For example, in a two-phase configuration (e.g., as illustrated by schematic diagram 300a), the first power converter operates at a reference phase (e.g., zero degrees), and the second power converter operates with a 140-degree phase shift relative to the reference phase. Therefore, the maximum phase shift of either phase relative to the phases of a two-phase configuration having phases evenly spaced around a unit circle (e.g., 0 degrees and 180 degrees) is 40 degrees.

[0065] In a three-phase configuration (e.g., as illustrated in schematic diagram 300b), the first power converter operates at a reference phase (e.g., 0 degrees). The second power converter operates with a 140-degree phase shift relative to the reference phase (e.g., the second power converter operates at approximately 140 degrees). The third power converter operates with a 140-degree phase shift relative to the phase of the second power converter (e.g., the third power converter operates at approximately 280 degrees). Therefore, the maximum phase shift of any one phase relative to the phases of a three-phase configuration having phases evenly spaced around a unit circle (e.g., 0 degrees, 120 degrees, and 240 degrees) is 40 degrees.

[0066] In a four-phase configuration (e.g., as illustrated in schematic diagram 300c), the first power converter operates at a reference phase (e.g., zero degrees). The second power converter operates with a 140-degree phase shift relative to the reference phase (e.g., the second power converter operates at approximately 140 degrees). The third power converter operates with a 140-degree phase shift relative to the second power converter (e.g., the third power converter operates at approximately 280 degrees). The fourth power converter operates with a 140-degree phase shift relative to the third power converter (e.g., the fourth power converter operates at approximately 420 degrees). Therefore, the maximum phase shift of any phase relative to the phases of a four-phase configuration having phases evenly spaced around a unit circle (e.g., 0 degrees, 90 degrees, 180 degrees, and 270 degrees) is 40 degrees.

[0067] In a five-phase configuration (e.g., as illustrated in schematic diagram 300d), the first power converter operates at a reference phase (e.g., 0 degrees). The second power converter operates with a 140-degree phase shift relative to the reference phase (e.g., the second power converter operates at approximately 140 degrees). The third power converter operates with a 140-degree phase shift relative to the second power converter (e.g., the third power converter operates at approximately 280 degrees). The fourth power converter operates with a 140-degree phase shift relative to the third power converter (e.g., the fourth power converter operates at approximately 420 degrees). The fifth power converter operates with a 140-degree phase shift relative to the fourth power converter (e.g., the fifth power converter operates at approximately 560 degrees). Therefore, the maximum phase shift of any phase relative to the phases of a five-phase configuration having phases evenly spaced around a unit circle (e.g., 0 degrees, 72 degrees, 144 degrees, 216 degrees, and 288 degrees) is 16 degrees.

[0068] By providing a 140-degree phase shift to each additional phase, the maximum phase offset of an N-phase configuration (e.g., where N is 2 to 18) is limited to 40 degrees. Therefore, the circuit's performance can be maintained independently of the number of phases in the circuit.

[0069] Figure 4 The diagram illustrates a multiphase regulator circuit arranged in a two-phase configuration (e.g., with two power converters) (e.g., similar to...). Figure 1A Some example curves of signals from a multiphase regulator circuit (400a-400d).

[0070] Specifically, graph 400a illustrates two current signals, one passing through the first inductor (e.g., ...). Figure 1A The first inductor current of the inductor 120a is 402a, and the current through the second inductor (e.g., Figure 1AThe second inductor current 402b of the inductor 120b. In the curve 400a, the phase difference between the first inductor current 402a and the second inductor current 402b is 180 degrees (e.g., the phase is uniformly distributed around a unit circle).

[0071] Graph 400b shows the voltage output terminals of the circuit that supplies current to the first and second inductors (e.g., Figure 1A The first output voltage signal 404 is located at the voltage output terminal 104. The first output voltage signal 404 has a first average value 406, a first upper peak value 408, and a first lower peak value 410. The first output voltage signal 404 has a first voltage ripple 412 (e.g., the difference between the first upper peak value 408 and the first average value 406, or the difference between the first lower peak value 410 and the first average value 406).

[0072] Curve graph 400c illustrates two alternative current signals, one passing through the first inductor (e.g., ...). Figure 1A The third inductor current 414a of the inductor 120a, and the current through the second inductor (e.g., Figure 1A The fourth inductor current 414b of inductor 120b. In curve 400c, the phase difference between the third inductor current 414a and the fourth inductor current 414b is 140 degrees.

[0073] Graph 400d illustrates a second output voltage signal 416 at the voltage output terminal of the circuit supplying current to the first and second inductors. The second output voltage signal 416 has a second average value 418, a second upper peak value 420, and a second lower peak value 422. The second output voltage signal 416 also has a second voltage ripple 424 (e.g., the difference between the second upper peak value 420 and the second average value 418, or the difference between the second lower peak value 422 and the second average value 418).

[0074] In some examples, the second voltage ripple 424 is approximately equal to the first voltage ripple 412. Therefore, the performance of a two-phase regulator circuit operating with a 140-degree phase shift can be comparable to that of a two-phase regulator circuit operating with a 180-degree phase shift.

[0075] Figure 5A This is a schematic diagram of some examples of the illustrated circuit 500a, which includes power converters 508a-508n, each power converter 508a-508n also having a corresponding feedback input (e.g., first feedback input 552a to Nth feedback input 552n) and a corresponding compensation terminal (e.g., first compensation terminal 554a to Nth compensation terminal 554n). Figure 1A The power converters 108a-108n in circuit 100a are similar. Figure 5A Each power converter 508a-508n in circuit 500a has voltage inputs 510a-510n, clock inputs 512a-512n, ground terminals 514a-514n, and switching outputs 516a-516n, respectively, coupled as shown in the figure. Furthermore, with... Figure 1A The circuit 100a is similar. Figure 5A The circuit 500a includes, as shown, a voltage input terminal 502, a voltage output terminal 504, a clock source 522, phase shifters 518a-518n, inductors 520a-520n, an input capacitor 528, an output capacitor 530, an output load 526, and an electrical ground 524. In some examples, Figure 5A The circuit 500a includes separate integrated circuit packages 506a-506n, while in other examples, Figure 5A The 500a circuit can be set in a single integrated circuit.

[0076] In some examples, each feedback input 552a-552n is coupled to voltage output terminal 504 and can receive an output voltage from voltage output terminal 504. Voltage inputs 510a-510n are coupled to voltage input terminal 502. In some examples, compensation terminals 554a-554n are coupled together. In some examples, compensation resistor 555 and compensation capacitor 557 are coupled in series between compensation terminals 554a-554n and electrical ground 524. Figure 5A The arrangement is suitable for "boost", "buck", and "boost / buck" topologies, and for example, Figure 5A The circuit can be used in power converters 508a-508n to implement a "buck" converter topology.

[0077] Figure 5B The diagram illustrates circuit 500b, which shows that includes Figure 5A An example implementation of the package 506a of the phase shifter 518a and the power converter 508a. Figure 5A Each package 506a-506n can be implemented similarly.

[0078] and Figure 1B Similar to the phase shifter 118a, Figure 5B The phase shifter 518a includes a phase shifter input 532, a resistor 538, a capacitor 540, a comparator 542, a phase shifter output 534, and an electrical ground 524, all coupled as shown in the figure. Figure 1B Similar to the 108a power converter, Figure 5BThe power converter 508a includes a first clock input 512a, a first voltage input 510a, a first switch output 516a, a first ground terminal 514a, a switch control circuit 544, a first transistor 546, and a second transistor 548, all coupled as shown. The power converter 508a also includes a feedback input 552a and a compensation terminal 554a, both coupled as shown.

[0079] Feedback input 552a and compensation terminal 554a are coupled to the switching control circuit 544 of the power converter 508a. In some examples, the switching control circuit 544 includes an error amplifier 556, a modulator 558 (e.g., a pulse width modulation comparator, etc.), and a control terminal driver 560. In some examples, an internal reference voltage source 562 and feedback input 552a are coupled to the input of the error amplifier 556. The output of the error amplifier 556 is coupled to the input of the modulator 558. The output of the error amplifier 556 is also coupled to the compensation terminal 554a. Clock input 512a is coupled to the input of the modulator 558. The output of the modulator 558 is coupled to the input of the control terminal driver 560. The output of the control terminal driver 560 is coupled to the control terminals of transistors 546 and 548.

[0080] In some examples, error amplifier 556 compares a reference voltage from internal reference voltage source 562 with the output voltage at feedback input 552a and outputs a voltage error signal. The voltage error signal is provided to compensation terminal 554a. The voltage error signal and clock signal are provided to modulator 558 from error amplifier 556 and clock input 512a, respectively. Modulator 558 compares the voltage error signal with a clock-based ramp waveform. Modulator 558 outputs a clock-based duty cycle signal to control terminal driver 560. Control terminal driver 560 outputs control signals from non-inverting output and inverting output to control terminals of transistor 546 and transistor 548, respectively.

[0081] Figure 6A This is a schematic diagram of some examples of the illustrated circuit 600a, which includes power converters 608a-608n, each power converter also having a corresponding clock output (e.g., first clock output 617a to Nth clock output 617n). Figure 5A The power converters 508a-508n in the circuit 500a are similar. Figure 6A Each power converter 608a-608n in circuit 600a has voltage inputs 610a-610n, clock inputs 612a-612n, ground terminals 614a-614n, switch outputs 616a-616n, feedback inputs 652a-652n, and compensation terminals 654a-654n, respectively, coupled as shown in the figure. Additionally, with... Figure 5AThe circuit is similar to 500a. Figure 6A The circuit 600a includes, as shown, a voltage input terminal 602, a voltage output terminal 604, a clock source 622, phase shifters 618a-618n, inductors 620a-620n, an input capacitor 628, an output capacitor 630, an output load 626, and an electrical ground 624. In some examples, Figure 6A The circuit 600a includes separate integrated circuit packages 606a-606n, while in other examples, Figure 6A The 600a circuit can be arranged in a single integrated circuit.

[0082] For example, power converter 608a includes a first clock output 617a. Power converter 608b includes a second clock output 617b. Power converter 608c includes a third clock output 617c. Power converter 608n includes an Nth clock output 617n. Clock outputs 617a-617n are separate from the switching outputs 616a-616n of the power converters. In some examples, clock outputs 617a-617n are coupled to corresponding clock inputs 612a-612n of the respective power converters 608a-608n. For example, clock input 612a is coupled to clock output 617a; clock input 612b is coupled to clock output 617b; and so on.

[0083] Clock output 617a is coupled to phase shifter 618b; clock output 617b is coupled to phase shifter 618c; and so on. Clock source 622 is configured to provide a first signal having a common frequency and a first phase to first phase shifter 618a. Phase shifter 618a is configured to provide a second signal having a common frequency and a second phase to clock input 612a. Power converter 608a is configured to provide the second signal from clock input 612a to clock output 617a. Power converter 608a is configured to provide the second signal from clock output 617a to phase shifter 618b. Phase shifter 618b is configured to provide a third signal having a common frequency and a third phase to clock input 612b. Power converter 608b is configured to provide the third signal from clock input 612b to clock output 617b. Power converter 608b is configured to provide the third signal from clock output 617b to phase shifter 618c. Phase shifter 618c is configured to provide a fourth signal with a common frequency and a fourth phase to clock input 612c, and so on.

[0084] Power converter 608a is further configured to provide a fifth signal with a common frequency and a second phase from switch output 616a to inductor 620a. Power converter 608b is further configured to provide a sixth signal with a common frequency and a third phase from switch output 616b to inductor 620b. Power converter 608c is further configured to provide a seventh signal with a common frequency and a fourth phase from switch output 616c to inductor 620c, and so on.

[0085] In some examples, the signal supplied from the switch output to the corresponding inductor has a different amplitude than the signal supplied from the clock output to the subsequent phase shifter. For example, a second signal having a common frequency and a second phase and supplied from clock output 617a to phase shifter 618b may have a different amplitude than a fifth signal having a common frequency and a second phase and supplied from switch output 616a to inductor 620a.

[0086] By having separate clock outputs for the clock signals of the respective power converters, each clock signal can have less noise (e.g., each clock signal can be free of noise present at the corresponding switch output), which improves circuit performance. Furthermore, by having separate clock outputs, the power converters can operate in discontinuous operating modes without affecting the clock signals supplied to subsequent converters. Additionally, by having separate clock outputs, any faults or failures occurring at the switch outputs can remain unaffected by the clock signals output to subsequent converters, leading to improved circuit performance and / or reliability.

[0087] In some examples, phase shifter 618a and power converter 608a are included in a first package 606a; phase shifter 618b and power converter 608b are included in a second package 606b; and so on. In some examples (not shown), Figure 5A 506a package Figure 6A 606b package and Figure 5A The 506c packages are coupled together to form a hybrid circuit (e.g., including similar...). Figure 5A Packaging and Figure 6A (A hybrid circuit in a packaged form). Other combinations are also possible.

[0088] Figure 6B The diagram illustrates circuit 600b, which shows that includes Figure 6A An example implementation of the phase shifter 618a and power converter 608a in package 606a. Each package 606a-606n can be implemented similarly.

[0089] and Figure 5B Similar to the phase shifter 518a, Figure 6BThe phase shifter 618a includes a phase shifter input 632, a resistor 638, a capacitor 640, a comparator 642, a phase shifter output 634, and an electrical ground 624, all coupled as shown in the figure. Figure 5B Similar to the 508a power converter, Figure 6B The power converter 608a includes, as shown, a first clock input 612a, a first voltage input 610a, a first switch output 616a, a first ground terminal 614a, a first transistor 646, a second transistor 648, a first feedback input 652a, a first compensation terminal 654a, a switch control circuit 644, and an internal reference voltage source 662, all coupled as shown. Figure 5B The switch control circuit is similar to that of the 544. Figure 6B The switching control circuit 644 includes an error amplifier 656, a modulator 658, and a control terminal driver 660 coupled as shown. The power converter 608a also includes a clock output 617a coupled as shown.

[0090] In some examples, clock output 617a is coupled to clock input 612a (e.g., as shown in first connection 666). In some alternative examples, clock output 617a is coupled to the output of control terminal driver 660 (e.g., as shown in second connection 668). In some other alternative examples, clock output 617a is coupled to the output of modulator 658 (e.g., as shown in third connection 670).

[0091] Figure 7 This is a flowchart of some examples of a method 700 for operating a multiphase regulator that includes multiple power converters. Figure 1A Circuit 100a or Figure 5A Circuit 500a can be configured to execute method 700.

[0092] At block 702, method 700 includes providing an input voltage from a voltage input terminal of a circuit to a first voltage input of a first power converter and a second voltage input of a second power converter. In some examples, the voltage input terminal is coupled to a voltage source. In some examples, Figure 1A and Figure 5A The circuit is configured to perform the function indicated at block 702.

[0093] In block 704, method 700 includes providing a first signal having a common frequency and a first phase to a first clock input of a first power converter. In some examples, from a first phase shifter (e.g., Figure 1A 118a) provides a first signal to the first clock input. In some other examples, the first signal is alternatively generated by the internal oscillator of the first power converter. In some examples, Figure 1A and Figure 5AThe circuit is configured to perform the function indicated at block 704.

[0094] At block 706, method 700 includes providing a second signal from a first switching output of a first power converter to an inductor coupled between the first switching output and voltage output terminals of a circuit, the second signal having a common frequency and a first phase. In some examples, the load (e.g., Figure 1A 126) is coupled to the voltage output terminal. In some examples, Figure 1A and Figure 5A The circuit is configured to perform the function indicated at block 706.

[0095] At block 708, method 700 includes providing a second signal having a common frequency and a first phase from a first switching output of a first power converter to a phase shifter. In some examples, the phase shifter is referred to as a second phase shifter (e.g., Figure 1A (118b). In some examples, Figure 1A and Figure 5A The circuit is configured to perform the function indicated at block 708.

[0096] At block 710, method 700 includes providing a third signal from the phase shifter to a second clock input of a second power converter. The third signal has a common frequency and a second phase different from the first phase. In some examples, Figure 1A and Figure 5A The circuit is configured to perform the function indicated at block 710.

[0097] In some examples, the output is then from the second switch (e.g., Figure 1A 116b) to the third phase shifter (e.g., Figure 1A 118c) provides a fourth signal having a common frequency and a second phase, and then provides a fifth signal having a common frequency and a third phase different from the first and second phases from the third phase shifter to the third clock input of the third power converter.

[0098] Figure 8 This is a flowchart of some alternative examples of a method 800 for operating a multiphase regulator that includes multiple power converters. Figure 1A Circuit 100a or Figure 6A Circuit 600a can be configured to execute method 800.

[0099] At block 802, method 800 includes providing an input voltage from a voltage input terminal of a circuit to a first voltage input of a first power converter and a second voltage input of a second power converter. In some examples, the voltage input terminal is coupled to a voltage source. In some examples, Figure 1A and Figure 6AThe circuit is configured to perform the function indicated at block 802.

[0100] At block 804, method 800 includes providing a first signal having a common frequency and a first phase to a first clock input of a first power converter. In some examples, from a first phase shifter (e.g., Figure 6A 618a) provides a first signal to the first clock input. In some other examples, the first signal is alternatively generated by the internal oscillator of the first power converter. In some examples, Figure 1A and Figure 6A The circuit is configured to perform the function indicated at block 804.

[0101] At block 806, method 800 includes providing a second signal from a first switching output of a first power converter to an inductor coupled between the first switching output and a voltage output terminal of a circuit. The second signal has a common frequency and a first phase. In some examples, the load (e.g., Figure 6A (626) is coupled to the voltage output terminal. In some examples, Figure 1A and Figure 6A The circuit is configured to perform the function indicated at block 806.

[0102] At block 808, method 800 includes providing a first signal having a common frequency and a first phase from a first clock output of a first power converter to a phase shifter. The first clock output (e.g., Figure 6A (617a) is separate from the first switch output. In some examples, the phase shifter is referred to as the second phase shifter (e.g., Figure 6A (618b). In some examples, Figure 1A and Figure 6A The circuit is configured to perform the function indicated at block 808.

[0103] At block 810, method 800 includes providing a third signal from the phase shifter to a second clock input of a second power converter. The third signal has a common frequency and a second phase different from the first phase. In some examples, Figure 1A and Figure 6A The circuit is configured to perform the function indicated at block 810.

[0104] In some examples, it is then output from a second clock (e.g., Figure 6A (617b) to the third phase shifter (e.g., Figure 6A 618c) provides a third signal having a common frequency and a second phase, and then provides a fourth signal having a common frequency and a third phase different from the first phase and the second phase from the third phase shifter to the third clock input of the third power converter.

[0105] The method has been illustrated and described above with a series of actions or functions, but the order of these actions or functions is not limited. For example, in addition to those actions or functions illustrated and / or described herein, some actions or functions may occur in a different order and / or simultaneously with other actions or functions. Furthermore, some illustrated actions or functions may be optional for implementing one or more aspects or examples of this specification. Moreover, one or more actions or functions depicted herein may be performed in one or more separate actions, functions, and / or stages. In some examples, the above-described method may be implemented in a computer-readable medium using instructions stored in memory.

[0106] In this specification, the term "coupled" may encompass a direct or indirect connection, communication, or signaling path that achieves a functional relationship consistent with this specification. Therefore, if device A generates a signal to control device B to perform a function, then: (a) in the first example, device A is directly coupled to device B; or (b) in the second example, if intermediate component C does not substantially alter the functional relationship between device A and device B, then device A is coupled to device B through intermediate component C, and therefore device B is controlled by device A via a control signal generated by device A.

[0107] Within the scope of the claims, modifications may be made to the described examples, and other embodiments are possible.

Claims

1. A circuit comprising: A first power converter having a first voltage input and a first switching output; A second power converter has a second voltage input, a clock input, and a second switch output, wherein the second voltage input is coupled to the first voltage input; A phase shifter coupled between the first switch output and the clock input of the second power converter, the phase shifter being configurable to provide a signal at the clock input in response to the state of the first switch output; A first inductor having a first inductor terminal and a second inductor terminal, wherein the first inductor terminal is coupled to the first switch output; as well as The second inductor has a third inductor terminal and a fourth inductor terminal, wherein the third inductor terminal is coupled to the second switch output and the fourth inductor terminal is coupled to the second inductor terminal.

2. The circuit of claim 1, wherein the phase shifter is configured to receive a first signal having a frequency and a first phase, and to provide at the clock input a second signal having the frequency and a second phase, the second phase being shifted 140 degrees from the first phase.

3. The circuit according to claim 1, wherein the phase shifter comprises: A resistor having a first resistor terminal and a second resistor terminal, wherein the first resistor terminal is coupled to the first switch output; A capacitor having a first capacitor terminal and a second capacitor terminal, wherein the first capacitor terminal is coupled to the second resistor terminal; as well as A comparator having a comparator input and a comparator output, wherein the comparator input is coupled to a second resistor terminal and a first capacitor terminal, and the comparator output is coupled to a clock input.

4. The circuit of claim 3, wherein the second power converter comprises: A switch control circuit having a switch control output and a switch control input, wherein the switch control input corresponds to the clock input; A first transistor has a first transistor terminal and a second transistor terminal and a first control terminal, wherein the first control terminal is coupled to the switch control output and the first transistor terminal is coupled to the second voltage input; as well as The second transistor has a third transistor terminal and a fourth transistor terminal, as well as a second control terminal, wherein the second control terminal is coupled to the switch control output, the third transistor terminal is coupled to a ground terminal, and the fourth transistor terminal is coupled to the second transistor terminal.

5. The circuit of claim 1, wherein the clock input is a second clock input, the first power converter has a first clock input, and the phase shifter is a second phase shifter, the circuit further comprising a first phase shifter coupled to the first clock input.

6. The circuit according to claim 5, wherein: The first phase shifter is configured to receive a first signal having a frequency and a first phase, and to provide a first clock signal having the frequency and a second phase at the first clock input, the second phase being shifted from the first phase by 135 degrees to 145 degrees; and The second phase shifter is configured to receive an output signal having the frequency and the second phase, and to provide a second clock signal having the frequency and a third phase at the second clock input, the third phase being shifted from the second phase by 135 degrees to 145 degrees.

7. The circuit according to claim 6, further comprising: An oscillator coupled to the first phase shifter, the oscillator being configured to provide the first signal having the first frequency and the first phase to the first phase shifter.

8. The circuit according to claim 1, wherein the phase shifter is a first phase shifter, and the circuit further comprises: A third power converter has a third voltage input, a third clock input, and a third output, wherein the third voltage input is coupled to the first voltage input; as well as A second phase shifter is coupled between the second switch output and the third clock input.

9. A circuit comprising: A first power converter has a first voltage input, a first output, and a first feedback input, wherein the first feedback input is coupled to the first output; A first inductor having a first inductor terminal and a second inductor terminal, wherein the first inductor terminal is coupled to the first output; A second power converter has a second voltage input, a clock input, a second feedback input, and a second output, wherein the second voltage input is coupled to the first voltage input, and the second feedback input is coupled to the first output; A second inductor having a third inductor terminal and a fourth inductor terminal, wherein the third inductor terminal is coupled to the second output and the fourth inductor terminal is coupled to the second inductor terminal. as well as A phase shifter coupled between the first output and the clock input of the second power converter, the phase shifter being configurable to provide a signal at the clock input in response to the state of the first output.

10. The circuit according to claim 9, further comprising: An input capacitor has a first capacitor terminal and a second capacitor terminal, wherein the first capacitor terminal is coupled to the first voltage input and the second voltage input, and the second capacitor terminal is coupled to a ground terminal; as well as An output capacitor having a third capacitor terminal and a fourth capacitor terminal, wherein the third capacitor terminal is coupled to the second inductor terminal and the fourth capacitor terminal is coupled to the ground terminal.

11. The circuit of claim 9, wherein the first power converter comprises: A switch control circuit having a first switch control input, a second switch control input, and a switch control output, wherein the first switch control input is coupled to an internal reference voltage terminal, and the second switch control input corresponds to the clock input; A first transistor has a first control terminal, a first transistor terminal, and a second transistor terminal, wherein the first control terminal is coupled to the switch control output, the first transistor terminal is coupled to the second voltage input, and the second transistor terminal is coupled to the first output; as well as The second transistor has a second control terminal, a third transistor terminal, and a fourth transistor terminal, wherein the second control terminal is coupled to the switch control output, the third transistor terminal is coupled to a ground terminal, and the fourth transistor terminal is coupled to the first output.

12. The circuit of claim 9, wherein the phase shifter is a first phase shifter, and the circuit further comprises: A third power converter has a third voltage input, a third clock input, and a third output, wherein the third voltage input is coupled to the first voltage input; as well as A second phase shifter is coupled between the second output of the second power converter and the third clock input.

13. The circuit according to claim 12, further comprising: A third inductor has a fifth inductor terminal and a sixth inductor terminal, wherein the fifth inductor terminal is coupled to the third output, and the sixth inductor terminal is coupled to the second inductor terminal and the fourth inductor terminal.

14. A circuit comprising: A first power converter has a first feedback input, a first voltage input, a first switch output, and a first clock output, wherein the first feedback input is coupled to the first switch output; A first inductor having a first inductor terminal and a second inductor terminal, wherein the first inductor terminal is coupled to the first switch output; A second power converter has a second voltage input, a clock input, a second switch output, and a second feedback input, wherein the second voltage input is coupled to the first voltage input, and the second feedback input is coupled to the first clock output; A second inductor has a third inductor terminal and a fourth inductor terminal, wherein the third inductor terminal is coupled to the second switch output and the fourth inductor terminal is coupled to the second inductor terminal. as well as A phase shifter coupled between the first clock output and the clock input of the second power converter, the phase shifter being configurable to provide a signal at the clock input in response to the state of the first switch output.

15. The circuit according to claim 14, further comprising: An input capacitor has a first capacitor terminal and a second capacitor terminal, wherein the first capacitor terminal is coupled to the first voltage input and the second voltage input, and the second capacitor terminal is coupled to a ground terminal.

16. The circuit of claim 14, further comprising: An output capacitor having a third capacitor terminal and a fourth capacitor terminal, wherein the third capacitor terminal is coupled to the second inductor terminal and the fourth capacitor terminal is coupled to a ground terminal.

17. The circuit of claim 14, wherein the first power converter comprises: A switch control circuit having a first switch control input, a second switch control input, and a switch control output, wherein the first switch control input is coupled to an internal reference voltage terminal, and the second switch control input corresponds to the clock input; A first transistor has a first control terminal, a first transistor terminal, and a second transistor terminal, wherein the first control terminal is coupled to the switch control output, the first transistor terminal is coupled to the second voltage input, and the second transistor terminal is coupled to the first switch output; as well as The second transistor has a second control terminal, a third transistor terminal, and a fourth transistor terminal, wherein the second control terminal is coupled to the switch control output, the third transistor terminal is coupled to a ground terminal, and the fourth transistor terminal is coupled to the first switch output.

18. The circuit of claim 17, wherein the switch control circuit comprises: An error amplifier having a first input, a second input, and an output, wherein the first input is coupled to the internal reference voltage terminal, and the second input is coupled to the clock input; A modulator having a modulator input and a modulator output, wherein the modulator input is coupled to the error amplifier; as well as A control terminal driver having a driver input and a driver output, wherein the driver input is coupled to the modulator output and the modulator output corresponds to the switch control output.

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