Memory system access operation status signaling

Abstract

The present application relates to access operation status signaling of a memory system. In some examples, a memory system may respond to an access command from a host system by performing an access operation such as a read or write operation. According to examples disclosed herein, a system may be configured to support access operation status signaling between a host system and a memory system, which may improve the system's ability to adapt to various access scenarios including when completion of an access operation is delayed. For example, when a memory system is performing an error recovery or media management operation, the memory system may indicate that the error recovery or media management operation is being performed or is otherwise still in progress. Such status signaling may indicate that the memory system is actively performing operations that may be used by the host system to inhibit a reset or reinitialization.

Description

[0001] Cross-references

[0002] This application claims priority to U.S. patent application No. 16 / 891,615, filed by Liang et al. on June 3, 2020, entitled “ACCESS OPERATION STATUS SIGNALING FOR MEMORY SYSTEMS,” which is assigned to the present assignee and is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The technical field relates to access operation status signaling of a memory system. Background Art

[0004] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, etc. Information is stored by programming memory cells within the memory device to various states. For example, a binary memory cell can be programmed to one of two supported states that often correspond to a logical 1 or a logical 0. In some examples, a single memory cell can support more than two possible states, and the memory cell can store any of the more than two possible states. In order to access information stored by the memory device, a component can read or sense the state of one or more memory cells within the memory device. In order to store information, a component can write or program one or more memory cells within the memory device to a corresponding state.

[0005] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), three-dimensional cross-point memory (3D XPoint), NOR and NAND memory devices, etc. Memory devices can be volatile or non-volatile. Volatile memory cells (e.g., DRAM cells) may lose their programmed state over time unless they are periodically refreshed by an external power source. Non-volatile memory cells (e.g., NAND memory cells) can maintain their programmed state for a long time even in the absence of external power. Summary of the invention

[0006] A device is described. The device may include a memory array and a control component coupled to the memory array. The control component may be configured to cause the device to: process a command received from a host system to perform an access operation on the memory array; before completing the access operation, identify that an elapsed time after receiving the command satisfies a threshold; and indicate a status of the access operation to the host system and based at least in part on identifying that the elapsed time satisfies the threshold.

[0007] A device is described. The device may include a control component configured to couple with a memory system. The control component may be configured to cause the device to: transmit to the memory system a command to perform an access operation at the memory system; process an indication of a status of the access operation received from the memory system based at least in part on an elapsed time after transmitting the command satisfying a threshold; determine a second command based at least in part on processing the indication of the status of the access operation; and transmit the second command to the memory system.

[0008] A non-transitory computer-readable medium is described. The non-transitory computer-readable medium may store code that includes instructions that, when executed by a processor of an electronic device, cause the electronic device to: process a command received from a host system to perform an access operation at a memory system; before completing the access operation, identify that an elapsed time after receiving the command satisfies a threshold; and indicate a status of the access operation to the host system and based at least in part on identifying that the elapsed time satisfies the threshold.

[0009] A non-transitory computer-readable medium is described. The non-transitory computer-readable medium may store code that includes instructions that, when executed by a processor of an electronic device, cause the electronic device to: transmit to a memory system a command to perform an access operation at the memory system; process an indication of a status of the access operation received from the memory system based at least in part on an elapsed time after transmitting the command satisfying a threshold; determine a second command based at least in part on processing the indication of the status of the access operation; and transmit the second command to the memory system. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 An example of a system supporting access operation status signaling of a memory system according to examples disclosed herein is shown.

[0011] Figure 2 An example of a system supporting access operation status signaling of a memory system according to examples disclosed herein is shown.

[0012] Figure 3 A block diagram of a memory system supporting access operation status signaling of the memory system according to examples disclosed herein is shown.

[0013] Figure 4 A block diagram of a host system supporting access operation status signaling of a memory system according to examples disclosed herein is shown.

[0014] Figure 5 and 6 The flowchart shown illustrates one or more methods of supporting access operation status signaling of a memory system according to examples disclosed herein. DETAILED DESCRIPTION

[0015] A memory system (e.g., one or more memory devices, possibly among one or more other components) may respond to access commands from a host system by performing various access operations (e.g., read operations, write operations (e.g., programming operations), erase operations, etc.) on a memory array of the memory system. In some cases, the duration for which the memory system performs such operations may be understood, defined, or otherwise predicted. When such duration is exceeded (e.g., after transmitting the access command, but before the access operation is completed), the host system may assume that the memory system has experienced a failure, and may initiate an operation to reestablish a connection with the memory system or a reset operation. However, in the event that the memory system is actively performing an operation that delays completion of the commanded access operation, such a reset operation may be unnecessary or otherwise undesirable, and may result in undue performance degradation of the system.

[0016] According to various examples disclosed herein, a system may be configured to support access operation status signaling between a host system and a memory system, which may improve the system's ability to adapt to various access scenarios. For example, when a memory system or its memory device or component is performing an error recovery operation (e.g., associated with a received access command), the memory system may indicate that the error recovery operation is being performed or is otherwise still in progress (e.g., pending). Based on such indications, the host system may determine various responsive operations, such as issuing a command or approval to continue error recovery, issuing a command or request to abort error recovery, or issuing another access command (e.g., a new read, write, or erase command that may prohibit, replace, or delay the error recovery operation), as well as other responsive commands or operations. In another example, a memory system or its memory device or component may be configured to perform various media management operations, such as wear leveling, background refresh, garbage collection, cleaning, block scanning, health monitoring, etc. In some examples, the media management operation may delay the completion of the access operation, and the memory system may be configured to indicate that such a delay (e.g., relative to the access command) may be associated with such a media management operation. By supporting access operation status signaling according to examples disclosed herein, the system may avoid unnecessary reset operations, may support improved flexibility in responding to access operation delays, or may support improved prioritization of access operations, among other benefits.

[0017] First, in reference Figure 1 Features of the present disclosure are described in the context of the systems, devices, and circuits described herein. Figure 2 The features of the present disclosure are illustrated and described in the context of the systems and related operations of the present disclosure. Figure 3-6 The described device diagrams and flow diagrams related to memory system access operation state signaling illustrate and describe these and other features of the present disclosure.

[0018] Figure 1 1 is an example of a system 100 that supports access operation status signaling of a memory system according to examples disclosed herein. The system 100 includes a host system 105 coupled to a memory system 110 .

[0019] The memory system 110 may be or include any device or set of devices, wherein the device or set of devices includes at least one memory array. For example, the memory system 110 may be or include a universal flash storage (UFS) device, an embedded multimedia controller (eMMC) device, a flash device, a universal serial bus (USB) flash device, a secure digital (SD) card, a solid-state drive (SSD), a hard disk drive (HDD), a dual in-line memory module (DIMM), a small outline DIMM (SO-DIMM), or a non-volatile DIMM (NVDIMM), among other possibilities.

[0020] System 100 may be included in a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, drone, train, car, or other transportation vehicle), a device with Internet of Things (IoT) capabilities, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or any other computing device that includes a memory and a processing device.

[0021] The system 100 may include a host system 105 that may be coupled to a memory system 110. The host system 105 may include one or more devices, and in some cases may include a processor chipset and a software stack executed by the processor chipset. For example, the host system 105 may include an application configured to communicate with the memory system 110 or a device therein. The processor chipset may include one or more cores, one or more caches (e.g., memory local to or included in the host system 105), a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 105 may use the memory system 110, for example, to write data to the memory system 110 and read data from the memory system 110. Although Figure 1 One memory system 110 is shown in FIG. 1 , but it should be understood that the host system 105 may be coupled to any number of memory systems 110 .

[0022] The host system 105 may be coupled to the memory system 110 via a physical host interface, which may provide an interface and, in at least some cases, an associated protocol for communicating control, address, data, and other signals between the memory system 110 and the host system 105. Examples of a physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a UFS interface, an eMMC interface, a Peripheral Component Interconnect Express (PCIe) interface, a USB interface, a Fibre Channel, a Small Computer System Interface (SCSI), a Serial Attached SCSI (SAS), a Double Data Rate (DDR) memory bus, a Dual In-line Memory Module (DIMM) interface (e.g., a DIMM socket interface supporting Double Data Rate (DDR)), an Open NAND Flash Interface (ONFI), Double Data Rate (DDR), Low Power Double Data Rate (LPDDR), or any other interface. In some examples, such an interface may be included in or otherwise supported between a host system controller 106 of the host system 105 and a memory system controller 115 of the memory system 110.

[0023] Memory system 110 may include memory system controller 115, memory device 130, and memory device 140. Memory device 130 may include one or more memory arrays of a first type of memory cells (e.g., a type of non-volatile memory cells), and memory device 140 may include one or more memory arrays of a second type of memory cells (e.g., a type of volatile memory cells). Figure 1 Although one memory device 130 and one memory device 140 are shown in the example of , it should be understood that the memory system 110 may include any number of memory devices 130 and memory devices 140, and in some cases, the memory system 110 may lack a memory device 130 or a memory device 140.

[0024] The memory system controller 115 may be coupled and communicate with the host system 105 (e.g., via a physical host interface). The memory system controller 115 may also be coupled and communicate with the memory device 130 or the memory device 140 to perform operations such as reading data, writing data, erasing data, or refreshing data at the memory device 130 or the memory device 140, as well as other such operations that may be generally referred to as access operations. In some cases, the memory system controller 115 may receive commands from the host system 105 and communicate with one or more memory devices 130 or the memory devices 140 to perform such commands (e.g., at a memory array within the one or more memory devices 130 or the memory devices 140). For example, the memory system controller 115 may receive commands or operations from the host system 105, and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130 or the memory device 140. Additionally, in some cases, the memory system controller 115 may exchange data with the host system 105 and one or more memory devices 130 or 140 (e.g., in response to or otherwise in conjunction with a command from the host system 105). For example, the memory system controller 115 may convert a response (e.g., a data packet or other signal) associated with the memory device 130 or 140 into a corresponding signal for the host system 105.

[0025] The memory system controller 115 may be configured for other operations associated with the memory device 130 or the memory device 140. For example, the memory system controller 115 may perform or manage operations such as wear leveling operations, garbage collection operations, error checking operations such as error detection operations or error correction operations or error correction code (ECC) operations, encryption operations, cache operations, media management operations, background refresh, health monitoring, and address translation between logical addresses (e.g., logical block addresses (LBAs)) associated with commands from the host system 105 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 130 or the memory device 140.

[0026] The memory system controller 115 may include hardware, such as one or more integrated circuits or discrete components, buffer memory, or a combination thereof. The hardware may include circuitry having dedicated (e.g., hard-coded) logic to perform the operations attributed herein to the memory system controller 115. The memory system controller 115 may be or include a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a digital signal processor (DSP)), or any other suitable processor or processing circuitry.

[0027] The memory system controller 115 may also include a local memory 120. In some cases, the local memory 120 may include a read-only memory (ROM) or other memory that may store operating codes (e.g., executable instructions) that may be executed by the memory system controller 115 to perform the functions attributed herein to the memory system controller 115. In some cases, the local memory 120 may additionally or alternatively include a static random access memory (SRAM) or other memory that may be used by the memory system controller 115, for example, for internal storage or operations related to the functions attributed herein to the memory system controller 115. Additionally or alternatively, the local memory 120 may act as a cache for the memory system controller 115. For example, when reading from or writing to the memory device 130 or the memory device 140, the data may be stored to the local memory 120 and may be available within the local memory 120 for subsequent retrieval or manipulation (update) by the host system 105 according to the cache policy (e.g., with reduced latency relative to the memory device 130 or the memory device 140).

[0028] although Figure 1The example of memory system 110 in FIG. 1 has been shown as including memory system controller 115, but in some cases memory system 110 may not include memory system controller 115. For example, memory system 110 may additionally or alternatively rely on an external controller (e.g., implemented by host system 105) or one or more local controllers 135 or 145 that may be internal to memory device 130 or memory device 140, respectively, to perform the functions attributed herein to memory system controller 115. In general, one or more functions attributed herein to memory system controller 115 may instead be performed by host system 105, local controller 135 or 145, or any combination thereof, in some cases.

[0029] Memory device 140 may include one or more arrays of volatile memory cells. For example, memory device 140 may include random access memory (RAM) memory cells, such as dynamic RAM (DRAM) memory cells and synchronous DRAM (SDRAM) memory cells. In some examples, memory device 140 may support random access operations (e.g., by host system 105) with reduced latency relative to memory device 130, or may provide one or more other performance differences relative to memory device 130.

[0030] The memory device 130 may include one or more arrays of non-volatile memory cells. For example, the memory device 130 may include NAND (e.g., NAND flash) memory, ROM, phase change memory (PCM), self-select memory, other chalcogenide-based memory, ferroelectric RAM (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash) memory, spin transfer torque (STT) MRAM, conductive bridge RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), and electrically erasable programmable ROM (EEPROM).

[0031] In some examples, memory device 130 or memory device 140 may include (e.g., on the same die or within the same package) a local controller 135 or local controller 145, respectively, which may perform operations on one or more memory cells of memory device 130 or memory device 140. Local controller 135 or local controller 145 may operate in conjunction with memory system controller 115, or may perform one or more functions attributed herein to memory system controller 115. In some cases, memory device 130 or memory device 140 including local controller 135 or local controller 145 may be referred to as a managed memory device, and may include a memory array and related circuitry (e.g., in combination with a local (e.g., on-die or within a package) controller (e.g., local controller 135 or local controller 145). An example of a managed memory device is a managed NAND (MNAND) device.

[0032] In some cases, memory device 130 may be or include a NAND device (e.g., a NAND flash device). Memory device 130 may be a package including one or more dies 160. In some examples, die 160 may be a piece of electronic grade semiconductor cut from a wafer (e.g., a silicon die cut from a silicon wafer). Each die 160 may include one or more planes 165, and each plane 165 may include a corresponding set of blocks 170, wherein each block 170 may include a corresponding set of pages 175, and each page 175 may include a set of memory cells.

[0033] In some cases, the NAND memory device 130 may include memory cells configured to store one bit of information each, which may be referred to as a single-level cell (SLC). Additionally or alternatively, the NAND memory device 130 may include memory cells configured to store multiple bits of information each, which may be referred to as a multi-level cell (MLC) if configured to store two bits of information each, a triple-level cell (TLC) if configured to store three bits of information each, a quad-level cell (QLC) if configured to store four bits of information each, or more generally, a multi-level memory cell. A multi-level memory cell may provide greater storage density relative to an SLC memory cell, but in some cases may involve narrower read or write margins or greater complexity for supporting circuitry.

[0034] In some cases, a plane 165 may refer to a group of blocks 170, and in some cases, parallel operations may occur within different planes 165. For example, parallel operations may be performed on memory cells within different blocks 170, as long as the different blocks 170 are in different planes 165. In some cases, performing parallel operations in different planes 165 may be subject to one or more restrictions, such as performing parallel operations on memory cells within different pages 175 that have the same page address within their respective planes 165 (e.g., related to command decode, page address decode circuitry, or other circuitry shared across planes 165).

[0035] In some cases, block 170 may include memory cells organized into rows (pages 175) and columns (e.g., strings, not shown). For example, memory cells in the same page 175 may share (e.g., be coupled to) a common word line, and memory cells in the same string may share (e.g., be coupled to) a common digit line (which may alternatively be referred to as a bit line).

[0036] For some NAND architectures, memory cells can be read and programmed (e.g., written) at a first level of granularity (e.g., at a page granularity level), but can be erased at a second level of granularity (e.g., at a block granularity level). That is, page 175 can be the smallest unit of memory (e.g., a collection of memory cells) that can be independently programmed or read (programmed or read simultaneously as part of a single programming or reading operation), and block 170 can be the smallest unit of memory (e.g., a collection of memory cells) that can be independently erased (e.g., erased simultaneously as part of a single erase operation). Furthermore, in some cases, a NAND memory cell can be erased before it can be rewritten with new data.

[0037] In some cases, in order to update some data within a block 170 while retaining other data within the block 170, the memory device 130 may copy the data to be retained to a new block 170 and write the updated data to one or more remaining pages of the new block 170. The memory device 130 (e.g., the local controller 135) or the memory system controller 115 may mark or otherwise indicate the data retained in the old block 170 as invalid or obsolete, and update the L2P mapping table so that the logical address (e.g., LBA) of the data is associated with the new valid block 170 instead of the old invalid block 170. In some cases, such copying and remapping may be better than erasing and rewriting the entire old block 170, for example due to latency or wear considerations. In some cases, one or more copies of the L2P mapping table may be stored within a memory unit of the memory device 130 (e.g., within one or more blocks 170 or planes 165) for use (e.g., reference and update) by the local controller 135 or the memory system controller 115.

[0038] In some cases, an L2P table may be maintained and data may be marked as valid or invalid at a page granularity level, and a page 175 may contain valid data, invalid data, or no data. Invalid data may be data that is outdated because a newer or updated version of the data is stored in a different page 175 of the memory device 130. Invalid data may have been previously programmed to an invalid page 175, but may no longer be associated with a valid logical address (e.g., a logical address referenced by the host system 105). Valid data may be the latest version of such data stored on the memory device 130. A page 175 that does not contain data may be a page 175 that has never been written to or has been erased.

[0039] In some cases, the memory system controller 115, the local controller 135, or the local controller 145 may perform operations of the memory device 130 or the memory device 140 (e.g., as part of one or more media management algorithms), such as wear leveling, background refresh, garbage collection, scrubbing, block scanning, health monitoring, or other operations, or any combination thereof. For example, within the memory device 130, a block 170 may have some pages 175 containing valid data and some pages 175 containing invalid data. To avoid waiting for some or all of the pages 175 in the block 170 to have invalid data in order to be erased and to reuse the block 170, an algorithm known as "garbage collection" may be invoked to allow the block 170 to be erased and freed as a free block for subsequent write operations. Garbage collection may refer to a set of media management operations that include, for example, selecting a block 170 containing valid and invalid data, selecting a page 175 in a block containing valid data, copying the valid data from the selected page 175 to a new location (e.g., a free page 175 in another block 170), marking the data in the previously selected page 175 as invalid, and erasing the selected block 170. Thus, the number of erased blocks 170 may be increased so that more blocks 170 may be used to store subsequent data (e.g., data subsequently received from the host system 105).

[0040] The host system 105 may issue commands to the memory system 110 to perform various access operations, and in some instances, the duration of time for the memory system 110 to perform the commanded access operation (e.g., to send data or other information associated with the completion command to the host system 105) may be understood, defined, or otherwise predictable. Such durations may be exceeded for a variety of reasons, including operational errors of the memory system 110 (e.g., unrecoverable errors, lockup or freeze conditions of the memory system 110 or its components) or other operations actively performed at the memory system 110 (e.g., error recovery operations, media management operations, other access operations). In the absence of further information (e.g., in an indeterminate state or non-deterministic state, when the operational state of the memory system 110 is unknown), the host system 105 may assume a condition of the memory system 110 to determine subsequent commands or operations when the duration of time to perform the commanded access operation is exceeded, which may result in poor performance of the system 100.

[0041] In some examples, when a threshold duration is met or exceeded after transmitting an access command, the host system 105 may assume, without further information, that an inoperable or unrecoverable failure has occurred to the memory system 110. After such a timeout detection, the host system 105 may attempt to perform a reset operation, such as a soft reset, a hard reset, a physical code reset, or a system command timeout routine, which may involve reestablishing or reconstructing a physical link with the memory system 110, or otherwise reinitializing the memory system 110 or components thereof (e.g., reinitializing the memory device 130, reinitializing the memory device 140).

[0042] However, in some cases, the delay in completing the access operation may be related to the memory system 110 actively performing operations, rather than to an inoperable or unrecoverable failure of the memory system 110. For example, completion of an access operation in response to a command may be delayed due to the memory system 110 performing an error recovery operation (which may or may not be related to the commanded access operation) or due to the memory system 110 performing a media management operation. In some cases, including those related to uncorrectable ECC (UECC) data or operations, the duration of error recovery may be relatively long (e.g., longer than a threshold duration associated with access operation completion, which may be 30 seconds or longer).

[0043] Thus, in some cases, the memory system 110 may actively perform operations according to the expected protocol despite the delayed completion of the access operation, and resetting the memory system 110 under such conditions may cause undue performance degradation or delays. In some cases, without allowing the memory system 110 to resolve the conditions or operations that delayed the completion of the access command, the memory system 110 and the host system 105 may enter a looping condition or deadlock, wherein in response to the delayed completion of the commanded access operation, the host system 105 continuously triggers a reset operation while the memory system 110 attempts to perform operations such as error recovery or media management operations.

[0044] According to various examples disclosed herein, the system 100 may be configured to support access operation status signaling between the host system 105 and the memory system 110, which may improve the ability of the system 100 to adapt to various access scenarios. For example, when the memory system 110 or a component thereof (e.g., one or both of the memory device 130 or the memory device 140) is performing an error recovery operation, the memory system 110 may indicate (e.g., via the status indication component 125) that the error recovery operation is being performed or is still in progress in other ways. In another example, the memory system 110 or a component thereof may be configured to perform various media management operations, and the memory system 110 may be configured to indicate (e.g., via the status indication component 125) that the media management operation is being performed or is still in progress in other ways. Although techniques related to access operation status signaling may be performed by the status indication component 125 of the memory system controller 115, such techniques may be performed in different manners or distributed across the status indication component of the memory system controller 115, the local controller 135 (e.g., related to operations associated with the memory device 130), the local controller 145 (e.g., related to operations associated with the memory device 140), or a combination thereof.

[0045] The host system 105 (e.g., the status indication receiver 107 of the host system controller 106) may be configured to receive such indications, which may include monitoring a signal or register state or a change or transition thereof, or polling a register of the memory system 110. Based on such indications, the host system 105 may determine various responsive actions, such as issuing a command or approval to continue error recovery or media management, issuing a command or request to abort error recovery or media management, issuing another access command (e.g., a new read, write, or erase command, which may inhibit, supersede, or delay error recovery or media management), or deferring or inhibiting other access commands, as well as other responsive commands or operations.

[0046] By supporting access operation status signaling according to the examples disclosed herein, the system 100 can distinguish between a frozen or inoperable condition of the memory system 110 and an active condition of the memory system 110, which can improve the cooperation between the host system 105 and the memory system 110. In some examples, the described techniques can enable the system 100 to avoid unnecessary reset operations or improve flexibility in responding to access operation delays. For example, the described techniques can enable the system to reduce latency under nominal conditions and make condition-specific determinations on intervening operations when access operation completion is delayed under other conditions (e.g., when the memory system 110 is performing error recovery or media management operations). In some examples, the described techniques can enable the system 100 to employ more powerful ECC techniques that may incur greater latency when executed but can improve data recovery or data integrity, which can be contextually implemented or otherwise enabled based on access operation status signaling. In some instances, the described techniques may improve the flexibility of the host system 105 in deciding how to process UECC data, which may involve a longer duration than an access operation that requires more time to recover than an access operation threshold. In some instances, the described techniques may enable the system 100 to improve prioritization of access operations, including disabling or inhibiting error recovery or media management when associated delays may adversely affect high priority access commands, which may enable the host system 105 to provide a better user experience by moving data error recovery or media management away from the gating of command queues. Thus, in connection with these and other benefits, the system 100 may advantageously employ access operation state signaling to improve performance relative to a configuration where the host system 105 assumes operating conditions of the memory system 110 in the absence of such signaling.

[0047] Figure 2 An example of a system 200 that supports access operation status signaling of a memory system according to an example disclosed herein is shown. The system 200 includes a host system 105-a and a memory system 110-a (which may be a reference Figure 1 10-a (e.g., a memory device 130 of the memory system 110-a) may include a memory array having multiple multi-level NAND memory cells. However, the techniques described herein may be applied to other memory architectures and other configurations of the host system 105 and the memory system 110.

[0048] In some examples, at 205, the host system 105-a may determine an access command (e.g., for accessing a memory of the memory system 110-a, for accessing a memory device 130 or a memory device 140 of the memory system 110-a, for accessing a memory array of the memory system 110-a). For example, the host system 105-a may determine a read command to read data from the memory system 110-a, or the host system 105-a may determine a write command to store data at the memory system 110-a.

[0049] At 210, the host system 105-a may transmit an access command (e.g., a read command, a write command, an erase command) to the memory system 110-a, which may be received by the memory system 110-a (e.g., at the memory system controller 115, at the local controller 135, or at the local controller 145). In some examples, the command of 210 may be a command to perform an access operation (e.g., a read operation, a write operation, an erase operation) on a memory array of the memory system 110-a. The memory system 110-a may initiate or perform an access operation in response to receiving the command of 210. The memory system 110-a may process the access command, which may include receiving, demodulating, decoding, or otherwise interpreting various aspects of the access command.

[0050] In some instances, at 215, the memory system 110-a (e.g., the memory system controller 115, the local controller 135, the local controller 145) may initiate or perform an error recovery operation that is initiated based at least in part on the command of 210 (e.g., based on an error, a read error, a write error when performing an access operation). In various instances, the error recovery operation may include techniques such as read retry, write retry, low-density parity check (LDPC) hard read, LDPC soft read, redundant array of independent nodes (RAIN) or redundant array of independent disks (RAID) reconstruction. In some instances, the error recovery operation of 215 may delay completion of an access operation associated with the command of 210 (e.g., transfer of read data, confirmation of data write).

[0051] In some examples, at 220, the memory system 110-a (e.g., the memory system controller 115, the local controller 135, the local controller 145) may initiate or perform a media management operation that may or may not be related to the access command of 210. For example, the memory system 110-a may perform one or more of a wear leveling operation, a background refresh operation, a garbage collection operation, a scrubbing operation, a block scan operation, a health monitoring operation, or other media management operations at 220. In some examples, the media management operation of 220 may delay completion of an access operation associated with the command of 210 (e.g., transfer of read data, confirmation of data write).

[0052] Although the operation of system 200 shows both the error recovery operation of 215 and the media management operation of 220, in various examples, system 200 may only perform one of the error recovery operation of 215 or the media management operation of 220, or system 200 may perform both the error recovery operation of 215 and the media management operation of 220, which may be performed simultaneously or during other overlapping time intervals. In addition, although the media management operation of 220 is shown as occurring after the error recovery operation of 215, in some examples, the media management operation as described with reference to the operation of 220 may occur or be initiated before the error recovery operation of 215, which may include a media management operation initiated or performed by host system 105-a before transmitting the access command at 210.

[0053] At 225, the memory system 110-a (e.g., the memory system controller 115, the local controller 135, the local controller 145, the status indication component 125) may identify that an elapsed time after the host system 105-a transmits the access command 210 or an elapsed time after the memory system 110-a receives the access command 210 satisfies (e.g., equals or exceeds) a first threshold. In some examples, the memory system 110-a may make or perform such identification before completing the access operation associated with the command 210.

[0054] In various instances, the first threshold may be configured at the memory system 110-a as part of a manufacturing or fine-tuning operation, or the first threshold may be a static, semi-static, or dynamic parameter configured by the host system 105-a. For example, to configure the first threshold, the memory system 110-a may receive an indication of a recovery time limit from the host system 105-a, which may be associated with (e.g., written to) a recovery time limit field of a mode register or other storage location at the memory system 110-a for configuration information (e.g., of a UFS read / write error recovery mode page). In some instances, such a threshold may be associated with a duration during which the memory system 110-a may freely perform various operations, but after which the memory system 110-a may be expected to transmit a response to the host system 105-a. In the absence of such a response, the host system 105-a may assume that the memory system 110-a is stuck, frozen, or otherwise inoperable, and the host system 105-a may perform a reset operation (e.g., a hard reset, reestablishing a communication link) accordingly.

[0055] At 230, the memory system 110-a (e.g., the memory system controller 115, the local controller 135, the local controller 145, the status indication component 125) may indicate a status of an access operation associated with the command of 210, which may be based on the identification of 225 that the elapsed time satisfies the first threshold. The indication of 230 may be received or processed at the host system 105-a (e.g., at the status indication receiver 107), which may include receiving, demodulating, decoding, or otherwise interpreting various aspects of the access command. In some instances, to indicate the status of the access operation, the memory system 110-a may indicate that an error recovery operation (e.g., the error recovery operation of 215, the error recovery operation associated with the access command of 210) is being performed or is still in progress. In some instances, to indicate the status of the access operation, the memory system 110-a may indicate that the access operation is delayed or the completion of the access operation is delayed due to a media management operation (e.g., of 220).

[0056] In various examples, the indication of 230 may be an active transmission by the memory system 110-a, or the indication of 230 may involve the setting of a register or other storage location (e.g., a field thereof) at the memory system 110-a that may be polled by the host system 105. For example, the indication of 230 may include setting a field defined in a UFS sense key or similar structure. For example, a new field of a register or other storage location may be defined (e.g., a resume abort field of a UFS sense key, but this is merely an example field name within an example location and is not limiting), or a new command, message, or field within a command or message may be defined.

[0057] At 235, the host system 105-a may determine (e.g., based on receiving the access operation status indicated at 230) a second access command to transmit to the memory system 110-a. The determination at 235 may take into account various access scenarios, including access operation prioritization, latency, etc. At 240 (e.g., based on the determination at 235), the host system 105-a may transmit the second access command to the memory system 110-a, which may receive the second access command (e.g., at the memory system controller 115, the local controller 135, the local controller 145) to initiate or perform one or more responsive operations. The memory system 110-a may process the access command, which may include receiving, demodulating, decoding, or otherwise interpreting various aspects of the access command.

[0058] In some examples, at 235, the host system 105-a may determine that the memory system 110-a is aborting a second command of the access operation commanded at 210. For example, the host system 105-a may determine that the data is no longer needed, or that the data may be accessed from another location (e.g., from a different memory device of the memory system 110-a, from a different LBA of the memory system 110-a). Thus, at 240, regardless of whether the memory system 110-a has been continuing to perform error recovery or suspending error recovery, the memory system 110-a may receive a command to abort the access operation, and may responsively abort the access operation, or abort an error recovery operation associated with the access operation, which may include disabling data transfer to the host system 105-a. In some examples, the host system 105-a may be configured to explicitly discard data associated with the access command of 210, and the host device may unmap, discard, or overwrite the associated LBA.

[0059] In some instances, the memory system 110-a may be configured to continue an error recovery operation or other operation beyond a threshold duration since an access command upon receiving permission or approval signaling from the host system 105-a. In other words, the memory system 110-a may request permission to continue the error recovery operation after a configured duration has elapsed after the access command of 210. In some instances, the access operation of 210 may be associated with data that is critical to the host system 105-a, and at 235, the host system 105-a may determine a second command (e.g., the command of 215) for the memory system 110-a to continue the error recovery operation. In some instances, such a command may be transmitted as a command (e.g., a second command that may be a copy of the command of 210) to continue data recovery by re-reading the same LBA again. Thus, at 240, the memory system 110-a may receive a command to continue the error recovery operation, and continue the error recovery operation based at least in part on receiving the second command. In some examples, the memory system 110 - a may continue to perform the error recovery operation of 215 after indicating the access operation status at 230 , even without permission for such indication.

[0060] In some examples, in response to the access operation status indicated at 230, the host system 105-a may determine to process another access command (e.g., an access command in the access command queue, a second access command corresponding to a different LBA), which may inhibit the access operation or related error recovery operation associated with the access command of 210. Accordingly, at 240, the memory system 110-a may receive the second access command and initiate a different access operation, which may include inhibiting the access operation associated with the command of 210 or the related error recovery operation of 215. In some examples, when the system 200 transitions to the idle state, the memory system 110-a may attempt to reread the information of the access command of 210, or retry various error recovery operations, which may provide the memory system 110-a with a longer recovery time to correct the data associated with the command of 210.

[0061] In some examples, the described techniques may be extended to multiple time limits or thresholds, or other types of thresholds (e.g., relative to the transmission of the access command at 210). For example, after indicating the access operation status at 230, the memory system 110-a may continue the commanded access operation, or error recovery or media management operations. However, upon reaching or exceeding a second threshold (e.g., relative to receiving the access command at 210, relative to indicating the access operation status at 230), the memory system 110-a may initiate or perform other operations.

[0062] In some examples, the memory system 110-a may determine to abort an error recovery operation associated with the access command of 210 after a certain time has elapsed. For example, the memory system 110-a may identify that the elapsed time after receiving the command at 210 satisfies a second threshold (e.g., meets or exceeds the second threshold) before completing the access operation, and abort the error recovery operation based at least in part on the identification. In some examples, the memory system 110-a may indicate to the host system 105-a that the error recovery operation has been aborted (e.g., as a second indication of the status of the access operation), and the host system 105-a may determine to abort the operation or another access command based on such an indication.

[0063] In some instances, the memory system 110-a can identify that a number of retries associated with an error recovery operation satisfies a threshold (e.g., meets or exceeds a threshold) before completing an access operation, and abort the error recovery operation based on such identification. In some instances, the threshold number of retries can be configured at the memory system 110-a as part of a manufacturing or fine-tuning operation, or the threshold number of retries can be a static, semi-static, or dynamic parameter configured by the host system 105-a. For example, to configure the threshold number of retries, the memory system 110-a can receive or identify an indication of a read retry count or write retry count field of a mode register (e.g., of a UFS read-write error recovery mode page) configured by the host system 105-a.

[0064] In some examples, the operations and signaling described with reference to system 200 associated with memory system 110-a may be performed by a processor such as a processor 100-100. Figure 1The described memory system controller 115 (e.g., status indication component 125) is performed or otherwise supported by the memory system controller. Although shown in the context of a host system 105-a and a memory system 110-a, in some instances, the described techniques may illustrate operations or signaling associated with a memory device 130 or a memory device 140 (e.g., a local controller 135, a local controller 145) that may or may not be supported by or transmitted via the memory system controller 115. In some instances, certain operations or signaling illustrated by the memory system 110-a may be performed at the system level (e.g., by the memory system controller 115) and certain operations or signaling may be performed at the device level (e.g., by the local controller 135, by the local controller 145). In various instances, the memory system controller 115, or the local controller 135, or the local controller 145, or a combination thereof may be referred to as a control component coupled to a memory array of the memory system 110-a and configured to cause the memory system 110-a to perform various operations described herein. Furthermore, in various examples, the host system 105 - a or components thereof may be referred to as a control component configured to be coupled with the memory system 110 - a and configured to cause the host system 105 - a to perform various operations described herein.

[0065] Figure 3 A block diagram 300 of a memory system 305 is shown that supports access operation status signaling of the memory system according to examples disclosed herein. The memory system 305 may be as described in reference Figure 1 and 2 Memory system 305 may include a command receiver component 310, a state identification component 315, a state indication component 320, an error recovery component 325, an access operation component 330, a data transfer component 335, a configuration receiver component 340, and a media management component 345. Each of these modules may communicate with each other directly or indirectly (e.g., via one or more buses).

[0066] The command receiver component 310 may receive or otherwise process commands received from a host system to perform access operations at the memory system 305 (eg, on a memory array of the memory system 305 ).

[0067] In some examples, the command receiver component 310 can receive or process a second command from the host system to abort the access operation based on an indication that the error recovery operation is still in progress.

[0068] In some examples, the command receiver component 310 can receive or process a third command from the host system to continue the error recovery operation based on indicating that the error recovery operation is still in progress.

[0069] In some examples, the command receiver component 310 can receive or process a fourth command from the host system to perform a second access operation at the memory system 305 (eg, on a memory array of the memory system 305 ).

[0070] The state recognition component 315 can recognize that an elapsed time after receiving a command satisfies a threshold before completing an access operation.

[0071] In some examples, the state identification component 315 can identify that an elapsed time after receiving the command satisfies a second threshold before completing the access operation.

[0072] In some examples, the state identification component 315 can identify that a number of retries associated with the error recovery operation satisfies a third threshold before completing the access operation.

[0073] The status indication component 320 can indicate the status of the access operation to the host system and based on identifying that the elapsed time satisfies the threshold.

[0074] In some examples, status indication component 320 can indicate to the host system that memory system 305 has aborted an error recovery operation.

[0075] The error recovery component 325 can initiate an error recovery operation based on a command (eg, received from a host system). In some examples, to indicate the status of an access operation, the status indication component 320 can indicate that the error recovery operation is still in progress.

[0076] In some examples, error recovery component 325 can continue error recovery operations based on receiving or processing the third command.

[0077] In some examples, the error recovery component 325 can, based on receiving or processing the fourth command, disable error recovery operations while performing the second access operation.

[0078] In some examples, the error recovery component 325 can suspend error recovery operations based on identifying that an elapsed time after receiving the command satisfies a second threshold.

[0079] In some examples, the error recovery component 325 can abort the error recovery operation based on identifying that a number of retries associated with the error recovery operation satisfies a third threshold.

[0080] The access operation component 330 can abort the error recovery operation or the access operation or both the error recovery operation and the access operation based on receiving or processing the second command.

[0081] The data transfer component 335 can disable data transfer to the host system based on the error recovery component 325 aborting an error recovery operation or the access operation component 330 aborting an access operation or disabling both error recovery operations and access operations.

[0082] The configuration receiver component 340 can receive or otherwise process an indication of a read retry count from the host system, and the error recovery component 325 can identify that a number of retries associated with an error recovery operation satisfies a third threshold based on the read retry count.

[0083] In some examples, configuration receiver component 340 can receive or otherwise process an indication of a restore time limit from a host system, and state identification component 315 can identify that the elapsed time satisfies a threshold based on the restore time limit.

[0084] The media management component 345 can initiate a media management operation, and to indicate the status of the access operation, the status indication component 320 can indicate that the access operation is delayed due to the media management operation.

[0085] Figure 4 A block diagram 400 is shown of a host system 405 that supports access operation status signaling of a memory system according to examples disclosed herein. The host system 405 may be as described in reference Figure 1 and 2 The host system 405 may include a command transmitter component 410, a status indication receiver component 415, a command determination component 420, and a configuration transmitter component 425. Each of these modules may communicate with each other directly or indirectly (e.g., via one or more buses).

[0086] The command transmitter component 410 may transmit commands to the memory system to perform access operations at the memory system (eg, on a memory array of the memory system).

[0087] In some examples, the command transmitter component 410 can transmit the second command to the memory system.

[0088] The status indication receiver component 415 may receive or otherwise process an indication of a status of an access operation from the memory system and based on an elapsed time after a transmit command satisfying a threshold.

[0089] In some examples, to receive or process the indication of the status of the access operation, the status indication receiver component 415 can receive or process an indication that the memory system is performing an error recovery operation associated with the command.

[0090] In some examples, status indication receiver component 415 can receive or process an indication from a memory system that the memory system has aborted an error recovery operation.

[0091] In some examples, status indication receiver component 415 can receive or process an indication from a memory system that an access operation is delayed due to a media management operation.

[0092] The command determination component 420 can determine the second command based on receiving or processing the indication of the status of the access operation.

[0093] In some examples, command determination component 420 can determine the second command based on receiving or processing an indication that the memory system is performing an error recovery operation associated with the command.

[0094] In some examples, command determination component 420 can determine the second command based on receiving an indication that the memory system has aborted an error recovery operation.

[0095] In some cases, the second command is to abort the access operation to the memory system.

[0096] In some cases, the second command is to continue error recovery operations for the memory system.

[0097] In some cases, the second command is to the memory system to perform a second access operation at the memory system.

[0098] The configuration transmitter component 425 can transmit an indication of a resume time limit from the host system to the memory system, wherein an elapsed time after a transmit command satisfies a threshold based on the resume time limit.

[0099] Figure 5 The flowchart of FIG. 5 illustrates one or more methods 500 for supporting access operation status signaling of a memory system according to aspects of the present disclosure. The operations of the method 500 may be implemented by a memory system or components thereof (e.g., a memory system controller, a memory device, a local controller) as described herein. For example, the operations of the method 500 may be implemented by a memory system or components thereof (e.g., a memory system controller, a memory device, a local controller) as described herein. Figure 3 The memory system described herein may perform, in some instances, the memory system may include a memory array having a plurality of multi-level NAND memory cells. In some instances, the memory system may execute instruction sets to control functional elements of the memory system to perform the described functions. Additionally or alternatively, the memory system may use dedicated hardware to perform aspects of the described functions.

[0100] At 505, the method may include receiving a command (e.g., an access command, a read command, a write command, an erase command) from a host system to perform an access operation at a memory system (e.g., on a memory array of the memory system). The operations of 505 may be performed according to the methods described herein. In some examples, aspects of the operations of 505 may be described in detail with reference to Figure 3 Describes the command receiver component to perform.

[0101] At 510, the method may include identifying that an elapsed time after receiving a command satisfies a threshold before completing an access operation. The operations of 510 may be performed according to the methods described herein. In some examples, aspects of the operations of 510 may be described in detail with reference to Figure 3 The described state recognition component is performed.

[0102] At 515, the method may include indicating to the host system and based on identifying that the elapsed time satisfies the threshold, the status of the access operation. The operations of 515 may be performed according to the methods described herein. In some examples, aspects of the operations of 515 may be described in detail with reference to Figure 3 The state described instructs the component to execute.

[0103] In some examples, an apparatus as described herein may perform one or more methods, such as method 500. The apparatus may include features, circuitry, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: receiving or processing, at a memory system, a command from a host system to perform an access operation at the memory system (e.g., on a memory array of the memory system); identifying, at the memory system and before completing the access operation, that an elapsed time after receiving the command satisfies a threshold; and indicating, to the host system and based on identifying that the elapsed time satisfies the threshold, a status of the access operation.

[0104] Some examples of method 500 and apparatus described herein may further include operations, features, circuitry, means, or instructions for initiating an error recovery operation based on the command, and indicating a status of the access operation may include indicating that the error recovery operation is still in progress.

[0105] Some instances of method 500 and the apparatus described herein may further include operations, features, circuit systems, means, or instructions for performing: receiving from the host system a second command to abort the access operation based on an indication that an error recovery operation may still be in progress; and aborting the error recovery operation or the access operation or both the error recovery operation and the access operation based on receiving the second command.

[0106] Some examples of method 500 and apparatus described herein may further include operations, features, circuitry, means, or instructions for inhibiting data transfer to the host system based on aborting the error recovery operation or the access operation or both the error recovery operation and the access operation.

[0107] Some instances of method 500 and the apparatus described herein may further include operations, features, circuit systems, devices, or instructions for performing: receiving a third command from the host system to continue the error recovery operation based on an indication that the error recovery operation is still in progress and continuing the error recovery operation based on receiving the third command.

[0108] Some instances of method 500 and the apparatus described herein may further include operations, features, circuit systems, devices, or instructions for performing: receiving, at the memory system, from the host system, a fourth command to perform a second access operation at the memory system; and disabling error recovery operations while performing the second access operation based on receiving the fourth command.

[0109] Some instances of method 500 and the apparatus described herein may further include operations, features, circuit systems, devices, or instructions for performing: at a memory system and before completing an access operation, identifying that an elapsed time after receiving a command satisfies a second threshold; and terminating an error recovery operation based on identifying that an elapsed time after receiving the command satisfies the second threshold.

[0110] Some examples of method 500 and apparatus described herein may further include operations, features, circuitry, means, or instructions for indicating to a host system that the memory system has aborted an error recovery operation.

[0111] Some instances of method 500 and the apparatus described herein may further include operations, features, circuit systems, devices, or instructions for performing: at a memory system and before completing an access operation, identifying that a number of retries associated with an error recovery operation satisfies a third threshold; and aborting the error recovery operation based on identifying that the number of retries associated with the error recovery operation satisfies the third threshold.

[0112] Some instances of method 500 and apparatus described herein may further include operations, features, circuit systems, means, or instructions for receiving an indication of a read retry count from a host system, and identifying that a number of retries associated with an error recovery operation satisfies a third threshold may be based on the read retry count.

[0113] Some examples of method 500 and apparatus described herein may further include operations, features, circuitry, means, or instructions for receiving an indication of a resume time limit from a host system, and identifying that the elapsed time satisfies the threshold may be based on the resume time limit.

[0114] Some examples of method 500 and apparatus described herein may further include operations, features, circuitry, means, or instructions for initiating a media management operation, and indicating a status of the access operation may include indicating that the access operation is delayed due to the media management operation.

[0115] Figure 6 600 illustrates one or more methods 600 of supporting access operation status signaling of a memory system according to aspects of the present disclosure. The operations of the method 600 may be implemented by a host system or a component thereof (eg, a host system controller) as described herein. For example, the operations of the method 600 may be implemented by a host system or a component thereof (eg, a host system controller) as described herein. Figure 4 The host system described herein performs. In some examples, the host system may execute instruction sets to control functional elements of the host system to perform the described functions. Additionally or alternatively, the host system may use dedicated hardware to perform aspects of the described functions.

[0116] At 605, the method may include transmitting to the memory system a command (e.g., an access command, a read command, a write command, an erase command) to perform an access operation at the memory system. The operations of 605 may be performed according to the methods described herein. In some examples, aspects of the operations of 605 may be described in detail with reference to Figure 4 The command transmitter component described here is used to execute.

[0117] At 610, the method may include receiving an indication of a status of an access operation from a memory system and based on an elapsed time after a transfer command satisfying a threshold. The operations of 610 may be performed according to the methods described herein. In some examples, aspects of the operations of 610 may be described in detail with reference to Figure 4 The described state instructs the receiver component to execute.

[0118] At 615, the method may include determining a second command based on receiving an indication of a status of an access operation. The operations of 615 may be performed according to the methods described herein. In some examples, aspects of the operations of 615 may be described in detail with reference to Figure 4 The command described determines the component to execute.

[0119] At 620, the host system may transmit the second command to the memory system. The operations of 620 may be performed according to the methods described herein. In some examples, aspects of the operations of 620 may be described in detail with reference to Figure 4 The command transmitter component described here is used to execute.

[0120] In some examples, an apparatus as described herein may perform one or more methods, such as method 600. The apparatus may include features, circuitry, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: transmitting from a host system to a memory system a command to perform an access operation at the memory system; receiving or processing an indication of a status of the access operation from the memory system and based on an elapsed time after transmitting the command satisfying a threshold; determining a second command based on receiving the indication of the status of the access operation; and transmitting the second command to the memory system.

[0121] In some instances of method 600 and the apparatus described herein, receiving an indication of a status of an access operation may include operations, features, circuit systems, devices, or instructions for performing the following: receiving an indication that the memory system is performing an error recovery operation associated with the command, and determining that the second command may be based on receiving an indication that the memory system is performing an error recovery operation associated with the command.

[0122] In some examples of the method 600 and apparatus described herein, the second command may be to abort the access operation to the memory system.

[0123] In some examples of the method 600 and apparatus described herein, the second command may be to continue error recovery operations for the memory system.

[0124] In some examples of the method 600 and apparatus described herein, the second command may be to perform a second access operation at the memory system for the memory system.

[0125] Some instances of method 600 and the apparatus described herein may further include operations, features, circuit systems, means, or instructions for performing the following: receiving an indication from a memory system that the memory system has aborted an error recovery operation, wherein determining the second command includes determining the second command based on receiving the indication that the memory system has aborted the error recovery operation.

[0126] Some examples of method 600 and apparatus described herein may further include operations, features, circuit systems, means, or instructions for transmitting an indication of a resume time limit from a host system to a memory system, and the elapsed time after transmitting a command satisfying a threshold may be based on the resume time limit.

[0127] In some examples of method 600 and apparatus described herein, receiving an indication of a status of an access operation may include operations, features, circuitry, means, or instructions for receiving an indication from a memory system that an access operation is delayed due to a media management operation.

[0128] It should be noted that the methods described above describe possible implementations, and that the operations and steps may be rearranged or otherwise modified, and other implementations are possible. Furthermore, parts of two or more of the methods may be combined.

[0129] A device is described. The device may include a memory array and a control component coupled to the memory array. In some examples, the memory array may include a set of multi-level NAND memory cells. The control component may be configured to cause the device to: receive or process a command from a host system to perform an access operation on the memory array; identify that an elapsed time after receiving the command satisfies a threshold before completing the access operation; and indicate a status of the access operation to the host system and based on identifying that the elapsed time satisfies the threshold.

[0130] In some examples of the device, the control component may be configured to cause the device to: initiate an error recovery operation based on the command; and indicate a status of the access operation, the control component may be configured to cause the device to indicate that the error recovery operation is still in progress.

[0131] In some instances of the device, the control component may be configured to cause the device to: receive or process a second command from the host system to abort the access operation based on an indication that the error recovery operation is still in progress; and abort the error recovery operation or the access operation or both the error recovery operation and the access operation based on receiving or processing the second command.

[0132] In some examples of the device, the control component may be configured to cause the device to: inhibit data transfer to the host system based on aborting the error recovery operation or the access operation or both the error recovery operation and the access operation.

[0133] In some instances of the device, the control component may be configured to cause the device to: receive or process a third command from the host system to continue the error recovery operation based on an indication that the error recovery operation is still in progress; and continue the error recovery operation based on receiving or processing the third command.

[0134] In some examples of the device, the control component may be configured to cause the device to: receive or process a fourth command from the host system to perform a second access operation on the memory array; and disable error recovery operations while performing the second access operation based on receiving or processing the fourth command.

[0135] In some instances of the device, the control component may be configured to cause the device to: before completing the access operation, identify that the elapsed time after receiving the command meets the second threshold; and terminate the error recovery operation based on identifying that the elapsed time after receiving the command meets the second threshold.

[0136] In some examples of the device, the control component may be configured to cause the device to: indicate to a host system that the control component has aborted the error recovery operation.

[0137] In some instances of the device, the control component may be configured to cause the device to: identify, before completing the access operation, that a number of retries associated with the error recovery operation satisfies a third threshold; and terminate the error recovery operation based on identifying that the number of retries associated with the error recovery operation satisfies the third threshold.

[0138] In some instances of the device, the control component may be configured to cause the device to receive or process an indication of a read retry count from a host system, and the control component may be configured to cause the device to identify, based on the read retry count, that a number of retries associated with an error recovery operation satisfies a third threshold.

[0139] In some instances of the device, the control component may be configured to cause the device to: receive or process an indication of a restore time limit from a host system; and indicate a status of an access operation, the control component may be configured to cause the device to identify that an elapsed time satisfies a threshold based on the restore time limit.

[0140] In some instances of the device, the control component may be configured to cause the device to: initiate a media management operation; and indicate a status of an access operation, the control component may be configured to cause the device to indicate that the access operation is delayed due to the media management operation.

[0141] A device is described. The device may include a control component configured to couple with a memory system. The control component may be configured to cause the device to: transmit a command to the memory system to perform an access operation at the memory system; receive or process an indication of a status of the access operation from the memory system and based on an elapsed time after transmitting the command satisfying a threshold; determine a second command based on receiving the indication of the status of the access operation; and transmit the second command to the memory system.

[0142] In some instances of the device, to receive an indication of a status of an access operation, the control component may be configured to receive or process an indication that the memory system is performing an error recovery operation associated with the command, and to determine the second command, the control component may be configured to cause the device to determine the second command based on receiving the indication that the memory system is performing an error recovery operation associated with the command.

[0143] In some examples, the second command may be to abort the access operation to the memory system.

[0144] In some examples, the second command may be to continue error recovery operations for the memory system.

[0145] In some examples, the second command may be to perform a second access operation at the memory system for the memory system.

[0146] In some instances of the device, the control component may be configured to cause the device to receive or process an indication from the memory system that the memory system has aborted an error recovery operation, and to determine the second command, the control component may be configured to cause the device to determine the second command based on receiving or processing the indication that the memory system has aborted the error recovery operation.

[0147] In some examples of the device, the control component may be configured to cause the device to transmit an indication of a resume time limit to the memory system, wherein the elapsed time after transmitting the command satisfying the threshold may be based on the resume time limit.

[0148] In some examples of the apparatus, the control component may be configured to cause the apparatus to receive an indication from the memory system that an access operation is delayed due to a media management operation.

[0149] A non-transitory computer-readable medium is described. The non-transitory computer-readable medium may store code including instructions that, when executed by a processor of an electronic device, cause the electronic device to: receive or process a command from a host system to perform an access operation at a memory system; before completing the access operation, identify that an elapsed time after receiving the command satisfies a threshold; and indicate a status of the access operation to the host system and based at least in part on identifying that the elapsed time satisfies the threshold.

[0150] In some instances of non-transitory computer-readable media, the instructions, when executed by a processor of an electronic device, further cause the electronic device to: initiate an error recovery operation at a memory system based at least in part on the command; and indicate a status of an access operation based at least in part on an indication that the error recovery operation is still in progress.

[0151] Another non-transitory computer-readable medium is described. The non-transitory computer-readable medium may store code that includes instructions that, when executed by a processor of an electronic device, cause the electronic device to: transmit a command to a memory system to perform an access operation at the memory system; receive or process an indication of a status of the access operation from the memory system based at least in part on an elapsed time after transmitting the command satisfying a threshold; determine a second command based at least in part on receiving or processing the indication of the status of the access operation; and transmit the second command to the memory system.

[0152] In some instances of non-transitory computer-readable media, the instructions for receiving or processing an indication of a status of an access operation, when executed by a processor of an electronic device, cause the electronic device to: receive or process an indication that a memory system is performing an error recovery operation associated with a command, and the instructions for determining a second command, when executed by the processor of the electronic device, cause the electronic device to: determine the second command based at least in part on the indication that the memory system is performing an error recovery operation associated with the command.

[0153] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some figures may illustrate signaling as a single signal; however, one of ordinary skill in the art will appreciate that a signal may represent a bus of signals, where the bus may have various bit widths.

[0154] The terms "electronic communication," "conductive contact," "connection," and "coupling" may refer to a relationship between components that supports the flow of electrons between the components. Components are considered to be in electronic communication with each other (or in conductive contact with each other, or connected to each other, or coupled to each other) if there is any conductive path between the components that can support the flow of signals between the components at any time. At any given time, based on the operation of the device containing the connected components, the conductive path between the components that are in electronic communication with each other (or in conductive contact or connected or coupled) may be an open circuit or a closed circuit. The conductive path between the connected components may be a direct conductive path between the components, or the conductive path between the connected components may be an indirect conductive path that may include an intermediate component such as a switch, transistor, or other component. In some instances, the signal flow between the connected components may be interrupted for a period of time, for example, using one or more intermediate components such as a switch or transistor.

[0155] The term "coupled" refers to the condition of moving from an open circuit relationship between components, in which signals are currently unable to communicate between components through conductive paths, to a closed circuit relationship between components, in which signals are able to communicate between components through conductive paths. When a component, such as a controller, couples other components together, the component initiates a change that allows signals to flow between other components via conductive paths that previously did not permit signal flow.

[0156] The term "isolation" refers to a relationship between components where a signal cannot currently flow between the components. Components are isolated from one another if an open circuit exists between the components. For example, components separated by a switch positioned between two components are isolated from one another when the switch is open. When a controller separates two components, the controller implements a change that prevents a signal from flowing between the components using a conductive path that previously permitted the signal to flow.

[0157] The devices discussed herein, including memory arrays, may be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some instances, the substrate is a semiconductor wafer. In other instances, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a sub-region of the substrate may be controlled by doping using various chemical species including, but not limited to, phosphorus, boron, or arsenic. Doping may be performed during the initial formation or growth of the substrate, by ion implantation, or by any other doping method.

[0158] The switch assembly or transistor discussed herein may represent a field effect transistor (FET) and include a three-terminal device including a source, a drain and a gate. The terminals may be connected to other electronic components by conductive materials (e.g., metals). The source and drain may be conductive and may include heavily doped, e.g., degenerate, semiconductor regions. The source and drain may be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., most of the carriers are electrons), then the FET may be referred to as an n-type FET. If the channel is p-type (i.e., most of the carriers are holes), then the FET may be referred to as a p-type FET. The channel may be terminated by an insulating gate oxide. Channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive voltage or a negative voltage to an n-type FET or a p-type FET, respectively, may cause the channel to become conductive. When a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned on" or "activated". When a voltage less than the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned off" or "deactivated".

[0159] The description set forth herein in conjunction with the accompanying drawings describes example configurations and does not represent all examples that may be implemented or within the scope of the claims. The term "exemplary" as used herein means "serving as an example, instance, or illustration," rather than "preferably" or "better than other examples." The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some cases, well-known structures and devices are shown in block diagram form to avoid confusing the concepts of the described examples.

[0160] In the drawings, similar components or features may have the same reference label. Additionally, various components of the same type may be distinguished by following the reference label with a dash and a second label that distinguishes among the similar components. If only the first reference label is used in the specification, the description applies to any of the similar components having the same first reference label, regardless of the second reference label.

[0161] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0162] The various schematic blocks and modules described in conjunction with the present disclosure herein may be implemented or executed using a general purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration).

[0163] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored as one or more instructions or codes on a computer-readable medium or transmitted via a computer-readable medium. Other examples and embodiments are within the scope of the present disclosure and the appended claims. For example, due to the nature of software, the functions described above may be implemented using software executed by a processor, hardware, firmware, hard wiring, or a combination of any of these. The features of the implementation functions may also be physically located at various locations, including being distributed so that parts of the functions are implemented at different physical locations. Also, as used herein, included in the claims, the "or" used in the list of items (e.g., a list of items starting with a phrase such as "at least one of" or "one or more of") indicates an inclusive list, such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). In addition, as used herein, the phrase "based on" should not be understood as referring to a closed set of conditions. For example, without departing from the scope of the present disclosure, an exemplary step described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should be equally interpreted as the phrase "based at least in part on."

[0164] Computer-readable media include both non-transitory computer storage media and communication media including any media that facilitates the transfer of computer programs from one place to another. Non-transitory storage media can be any available media that can be accessed by a general or special computer. By way of example and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disk (CD) ROM or other optical disk storage device, magnetic disk storage device or other magnetic storage device, or any other non-transitory media that can be used to carry or store the desired program code device in the form of an instruction or data structure and can be accessed by a general or special computer or a general or special processor. And, any connection is appropriately referred to as a computer-readable medium. For example, if a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technology such as infrared, radio and microwave is used to transmit software from a website, server or other remote source, then the coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technology such as infrared, radio and microwave are included in the definition of media. As used herein, disk and disc include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc, where disks usually reproduce data magnetically, while discs use lasers to reproduce data optically. Combinations of the above are also included within the scope of computer-readable media.

[0165] The description herein is provided to enable those skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein, but is given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A memory device, comprising: Memory array; as well as a control component coupled to the memory array and configured to cause the memory device to: processing commands received from a host system to perform access operations on the memory array; initiating an error recovery operation based at least in part on the command; before completing the access operation, identifying that an elapsed time after receiving the command satisfies a threshold; as well as Indicating to the host system and based at least in part on identifying that the elapsed time satisfies the threshold that the error recovery operation is still in progress.

2. The memory device of claim 1 , wherein the control component is further configured to cause the memory device to: processing a second command received from the host system to abort the access operation based at least in part on an indication that the error recovery operation is still in progress; and Based at least in part on processing the second command, the error recovery operation or the access operation or both the error recovery operation and the access operation are aborted.

3. The memory device of claim 2, wherein the control component is further configured to cause the memory device to: Data transfer to the host system is inhibited based at least in part on aborting the error recovery operation or the access operation or both the error recovery operation and the access operation.

4. The memory device of claim 1 , wherein the control component is further configured to cause the memory device to: processing a third command received from the host system to continue the error recovery operation based at least in part on indicating that the error recovery operation is still in progress; and Based at least in part on processing the third command, the error recovery operation continues.

5. The memory device of claim 1 , wherein the control component is further configured to cause the memory device to: processing a fourth command received from the host system to perform a second access operation on the memory array; and Based at least in part on processing the fourth command, the error recovery operation is disabled while performing the second access operation.

6. The memory device of claim 1, wherein the control component is further configured to cause the memory device to: before completing the access operation, identifying that the elapsed time after receiving the command satisfies a second threshold; and Based at least in part on identifying that the elapsed time after receiving the command satisfies the second threshold, the error recovery operation is aborted.

7. The memory device of claim 6, wherein the control component is further configured to cause the memory device to: An indication is given to the host system that the control component has aborted the error recovery operation.

8. The memory device of claim 1, wherein the control component is further configured to cause the memory device to: Prior to completing the access operation, identifying that a number of retries associated with the error recovery operation satisfies a third threshold; and Based at least in part on identifying that the number of retries associated with the error recovery operation satisfies the third threshold, aborting the error recovery operation.

9. The memory device of claim 8, wherein the control component is further configured to cause the memory device to: An indication of a read retry count received from the host system is processed, wherein identifying that the number of retries associated with the error recovery operation satisfies the third threshold is based at least in part on the read retry count.

10. The memory device of claim 1, wherein the control component is further configured to cause the memory device to: An indication of a resume time limit received from the host system is processed, wherein the control component is configured to cause the memory device to identify that the elapsed time satisfies the threshold based at least in part on the resume time limit.

11. The memory device of claim 1, wherein the memory array comprises a plurality of multi-level NAND memory cells.

12. A memory device comprising: Memory array; as well as a control component coupled to the memory array and configured to cause the memory device to: processing commands received from a host system to perform access operations on the memory array; initiating an error recovery operation based at least in part on the command; Initiate media management operations; before completing the access operation, identifying that an elapsed time after receiving the command satisfies a threshold; as well as Based at least in part on identifying that the elapsed time satisfies the threshold, indicating to the host system that the access operation is delayed due to the media management operation, and indicating to the host system that the error recovery operation is still in progress.

13. A memory device comprising: A control component configured to be coupled to a memory system, wherein the control component is configured to cause the memory device to: transmitting to the memory system a command to perform an access operation at the memory system; processing an indication that the memory system is performing an error recovery operation associated with the command based at least in part on an elapsed time after transmitting the command satisfying a threshold; determining a second command based at least in part on processing the indication that the memory system is performing the error recovery operation associated with the command; as well as The second command is transmitted to the memory system.

14. The memory device of claim 13, wherein the second command is to abort the access operation for the memory system.

15. The memory device of claim 13, wherein the second command is to continue the error recovery operation for the memory system.

16. The memory device of claim 13, wherein the second command is to the memory system to perform a second access operation at the memory system.

17. The memory device of claim 13, wherein the control component is further configured to cause the memory device to: processing an indication received from the memory system that the memory system has aborted the error recovery operation, wherein to determine the second command, the control component is configured to cause the memory device to determine the second command based at least in part on processing the indication that the memory system has aborted the error recovery operation.

18. A memory device comprising: A control component configured to be coupled to a memory system, wherein the control component is further configured to cause the memory device to: transmitting to the memory system a command to perform an access operation at the memory system and an indication of a recovery time limit; processing an indication that the memory system is performing an error recovery operation associated with the command based at least in part on an elapsed time after transmitting the command satisfying a threshold, wherein the elapsed time after transmitting the command satisfying the threshold is based at least in part on the recovery time limit; determining a second command based at least in part on processing the indication that the memory system is performing the error recovery operation associated with the command; as well as The second command is transmitted to the memory system.

19. A memory device comprising: A control component configured to be coupled to a memory system, wherein the control component is further configured to cause the memory device to: transmitting to the memory system a command to perform an access operation at the memory system; processing an indication from the memory system that the access operation is delayed due to a media management operation and an indication that the memory system is performing an error recovery operation associated with the command based at least in part on an elapsed time after transmitting the command satisfying a threshold; determining a second command based at least in part on processing the indication that the access operation is delayed due to the media management operation or processing the indication that the memory system is performing the error recovery operation associated with the command; as well as The second command is transmitted to the memory system.

20. A non-transitory computer-readable medium storing code, the code comprising instructions that, when executed by a processor of an electronic device, cause the electronic device to: processing commands received from a host system to perform access operations at a memory system; initiating an error recovery operation at the memory system based at least in part on the command; before completing the access operation, identifying that an elapsed time after receiving the command satisfies a threshold; Indicating to the host system and based at least in part on identifying that the elapsed time satisfies the threshold that the error recovery operation is still in progress.

21. A non-transitory computer-readable medium storing code, the code comprising instructions that, when executed by a processor of an electronic device, cause the electronic device to: transmitting to a memory system a command to perform an access operation at the memory system; processing an indication that the memory system is performing an error recovery operation associated with the command based at least in part on an elapsed time after transmitting the command satisfying a threshold; determining a second command based at least in part on processing the indication that the memory system is performing the error recovery operation associated with the command; as well as The second command is transmitted to the memory system.

Images