Memory system with selectively interfaceable memory subsystem

Abstract

The present application relates to a memory system having a selectively interfaceable memory subsystem. A memory system may include the memory subsystem that is configurable to provide volatile storage devices, non-volatile storage devices, or both to a host system. The memory subsystem may include multiple ports, each of which is capable of communicating with the host system using a different interface. The memory subsystem may be dynamically configurable to perform different functions based on the needs of the host system. In some examples, the memory system described herein may include: a first memory subsystem that provides non-volatile storage devices to the host system; a second memory subsystem that provides volatile storage devices to the host system; and a third memory subsystem that is configurable to provide volatile storage devices or non-volatile storage devices, or both, to the host system.

Description

[0001] Cross Reference

[0002] This patent application claims priority to U.S. patent application No. 16 / 893,205, filed by Liang et al. on June 4, 2020, entitled “MEMORY SYSTEM WITH SELECTIVELY INTERFACEABLE MEMORY SUBSYSTEM,” which is assigned to the present assignee and is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The technical field relates to a memory system having a selectively interfaceable memory subsystem. Background Art

[0004] The following relates generally to one or more systems for memory, and more particularly to a memory system having a selectively interfaceable memory subsystem.

[0005] Memory devices are widely used to store information in various electronic devices, such as computers, wireless communication devices, cameras, and digital displays. Information is stored by programming memory cells within the memory device to different states. For example, a binary memory cell can be programmed to one of two supported states, often corresponding to a logic 1 or a logic 0. In some instances, a single memory cell can support more than two possible states, and the memory cell can store any of these states. To access information stored by a memory device, a component can read or sense the state of one or more memory cells within the memory device. To store information, a component can write or program one or more memory cells within the memory device to a corresponding state.

[0006] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), three-dimensional cross-point memory (3D Xpoint or 3DXP), NOR and NAND memory devices, etc. Summary of the Invention

[0007] A memory system is described. The memory system may include: a first memory subsystem of a first type configured to communicate information with a host system via a first interface; a second memory subsystem of a second type configured to communicate information with the host system via a second interface; and a third memory subsystem of a third type selectively configurable to communicate information with the host system via the first interface and the second interface.

[0008] A method is described. The method may be performed by a memory system. The method may include communicating first information between a first memory subsystem of the memory system and a host system via a first interface of the memory system, the first memory subsystem being a first type of memory; communicating second information between a second memory subsystem of the memory system and the host system via a second interface of the memory system, the second memory subsystem being a second type of memory; receiving an indication via the first interface or the second interface of whether a third memory subsystem of the memory system will communicate with the host system using the first interface, the second interface, or both, the third memory subsystem being a third type of memory; and configuring the third memory subsystem to communicate with the host system via the first interface, the second interface, or both based at least in part on the indication.

[0009] A memory system is described. The memory system may include: a non-volatile memory subsystem configured to communicate information with a host system via a first interface; a volatile memory subsystem configured to communicate information with the host system via a second interface; and a third memory subsystem configured to communicate information with the host system via the first interface and the second interface, wherein when communicating information via the first interface, the third memory subsystem is configured as a second non-volatile memory subsystem, and when communicating information via the second interface, the third memory subsystem is configured as a second volatile memory subsystem. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 An example of a system supporting a memory system with a selectively interfaceable memory subsystem according to examples disclosed herein is described.

[0011] Figure 2 An example of a system supporting a memory system with a selectively interfaceable memory subsystem according to examples disclosed herein is described.

[0012] Figure 3 An example of a memory subsystem supporting a memory system having a selectively interfaceable memory subsystem according to examples disclosed herein is described.

[0013] Figure 4 A flow chart illustrating a method of supporting a memory system with a selectively interfaceable memory subsystem according to examples disclosed herein is shown.

[0014] Figure 5 A block diagram showing a memory system supporting a memory system with a selectively interfaceable memory subsystem according to examples disclosed herein.

[0015] Figure 6 A flow chart illustrating a method of supporting a memory system with a selectively interfaceable memory subsystem according to examples disclosed herein is shown. DETAILED DESCRIPTION

[0016] Memory devices can be volatile or nonvolatile. Volatile memory cells can lose their programmed state over time unless they are periodically refreshed by an external power source. For example, DRAM memory cells can be considered volatile memory cells. Nonvolatile memory cells can maintain their programmed state for extended periods of time even without an external power source. For example, NAND memory cells can be considered nonvolatile memory cells. Generally speaking, volatile memory has faster access times than nonvolatile memory. In some systems, volatile and nonvolatile memory may be referred to as "memory" and "storage device," respectively.

[0017] Computing systems typically include volatile memory that the host system can use during real-time operation and non-volatile memory for storing information. Sometimes, the system may use a storage device that is more volatile than normal storage, for example, when using artificial intelligence (AI) software or playing video games. At other times, the system may use a storage device that is more non-volatile than normal storage, for example, when using 5G data or streaming high-definition video. In order to handle those situations with less overall memory, it may be necessary to make a portion of the system's memory dynamically configurable to act as volatile memory or non-volatile memory. Such a system may be able to dynamically adjust the size of the memory and storage devices to match the needs of the system. This will be suitable for systems with physical memory limitations, such as mobile devices.

[0018] Some memory cells can function as either volatile or nonvolatile memory. For example, FeRAM memory cells can function as nonvolatile memory because they can maintain their programmed state for extended periods of time. Some FeRAM memory cells can have fast access times and function as volatile memory. In another example, some resistive RAM, such as 3DXP memory, can include FeRAM memory cells that can function as volatile memory. Other types of memory cells can also function as either volatile or nonvolatile memory.

[0019] Systems, devices, and techniques are described that include a memory subsystem having memory that can be configurable to provide volatile storage, nonvolatile storage, or both to a host system. The memory subsystem can include multiple ports, each capable of communicating with the host system using a different interface. The memory subsystem can be dynamically configurable to perform different functions based on the needs of the host system. Using this memory subsystem, the host system can dynamically adjust the size of random access memory and the size of storage to match the needs of the host system. In some examples, the memory system described herein can include: a first memory subsystem that provides nonvolatile storage to the host system; a second memory subsystem that provides volatile storage to the host system; and a third memory subsystem that is configurable to provide volatile storage or nonvolatile storage, or both, to the host system.

[0020] First, in the reference Figure 1 Features of the present disclosure are described in the context of the memory system described. Figure 2-4 Features of the present disclosure are described in the context of the described systems, subsystems, and flow charts. Figure 5-6 These and other features of the present disclosure are illustrated and described with device diagrams and flow diagrams directed to a memory system having a selectively interfaceable memory subsystem.

[0021] Figure 1 An example of a system 100 supporting a memory system with a selectively interfaceable memory subsystem according to examples disclosed herein is illustrated. The system 100 can include a host system 105 coupled to a memory system 110.

[0022] The memory system 110 may be any device or collection of devices that includes one or more memory arrays. For example, the memory system 110 may be or include a solid-state drive (SSD), a flash drive, a universal serial bus (USB) flash drive, a universal flash storage (UFS) drive, an embedded multimedia controller (eMMC) drive, a secure digital (SD) card, a hard disk drive (HDD), a dual in-line memory module (DIMM), a small outline DIMM (SO-DIMM), or a non-volatile DIMM (NVDIMM), among other possibilities.

[0023] System 100 may be included in a computing device, such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, drone, train, car, or other transportation vehicle), an Internet of Things (IoT)-enabled device, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or any other computing device that includes memory and processing devices.

[0024] The host system 105 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches (e.g., memory local to or contained within the host system 105), a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 105 may use the memory system 110, for example, to write data to and read data from the memory system 110. Although Figure 1 One memory system 110 is shown in FIG. 1 , but the host system 105 can be coupled to any number of memory systems 110 .

[0025] The host system 105 may be coupled to the memory system 110 via a physical host interface, which may provide an interface and, in at least some cases, an associated protocol for communicating control, address, data, and other signals between the memory system 110 and the host system 105. Examples of a physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a UFS interface, an eMMC interface, a Peripheral Component Interconnect Express (PCIe) interface, a USB interface, a Fibre Channel, a Small Computer System Interface (SCSI), a Serial Attached SCSI (SAS), a Double Data Rate (DDR) memory bus, a DIMM interface (e.g., a DIMM socket supporting Double Data Rate (DDR)), an Open NAND Flash Interface (ONFI), Double Data Rate (DDR), Low Power Double Data Rate (LPDDR), or any other interface.

[0026] Memory system 110 may include a memory subsystem controller 115, a memory subsystem 130, and a memory subsystem 140. Memory subsystem 130 may include one or more memory arrays of a first type of memory cells (e.g., a type of non-volatile memory cells), and memory subsystem 140 may include one or more memory arrays of a second type of memory cells (e.g., a type of volatile memory cells). Figure 11. Although one memory subsystem 130 and one memory subsystem 140 are shown in the example of , the memory system 110 may include any number of memory subsystems 130 and memory subsystems 140, and in some cases, the memory system 110 may have no memory subsystem 130 or memory subsystem 140.

[0027] The memory subsystem controller 115 may be coupled to and communicate with the host system 105 (e.g., via a physical host interface). The memory subsystem controller 115 may also be coupled to and communicate with the memory subsystem 130 or the memory subsystem 140 to perform operations such as reading data, writing data, erasing data, or refreshing data at the memory subsystem 130 or the memory subsystem 140, as well as other such operations that may generally be referred to as access operations. In some cases, the memory subsystem controller 115 may receive commands from the host system 105 and communicate with one or more memory subsystems 130 or the memory subsystems 140 to execute such commands (e.g., at a memory array within the one or more memory subsystems 130 or the memory subsystem 140). For example, the memory subsystem controller 115 may receive commands or operations from the host system 105 and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory subsystem 130 or the memory subsystem 140. And in some cases, the memory subsystem controller 115 may exchange data (e.g., in response to or otherwise associated with a command from the host system 105) with the host system 105 and one or more memory subsystems 130 or 140. For example, the memory subsystem controller 115 may convert a response (e.g., a data packet or other signal) associated with the memory subsystem 130 or 140 into a corresponding signal for the host system 105.

[0028] The memory subsystem controller 115 may be responsible for other operations associated with the memory subsystem 130 or the memory subsystem 140. For example, the memory subsystem controller 115 may perform or manage operations such as wear leveling operations, garbage collection operations, error checking operations such as error detection operations or error correction code (ECC), encryption operations, cache operations, media management operations, and address translation between logical addresses (e.g., logical block addresses (LBAs)) associated with commands from the host system 105 and physical addresses (e.g., physical block addresses) associated with memory units within the memory subsystem 130 or the memory subsystem 140.

[0029] The memory subsystem controller 115 may include hardware, such as one or more integrated circuits or discrete components, buffer memory, or a combination thereof. The hardware may include digital circuitry with dedicated (e.g., hard-coded) logic to perform the operations attributed herein to the memory subsystem controller 115. The memory subsystem controller 115 may be or include a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a digital signal processor (DSP)), or any other suitable processor or processing circuitry.

[0030] The controller may also include local memory 120. In some cases, the local memory 120 may include read-only memory (ROM) or other memory that may store operating code (e.g., executable instructions) that may be executed by the memory subsystem controller 115 to perform the functions attributed herein to the memory subsystem controller 115. In some cases, the local memory 120 may additionally or alternatively include static random access memory (SRAM) memory or other memory that may be used by the memory subsystem controller 115, for example, for internal storage or operations related to the functions attributed herein to the memory subsystem controller 115. Additionally or alternatively, the local memory 120 may act as a cache for the memory subsystem controller 115. For example, when reading from or writing to memory subsystem 130 or memory subsystem 140, the data may be stored to local memory 120 and may be available within local memory 120 for subsequent retrieval or manipulation (update) by host system 105 according to a cache policy (e.g., with reduced latency relative to memory subsystem 130 or memory subsystem 140).

[0031] Although Figure 1 The example memory system 110 in FIG. 1 has been illustrated as including a memory subsystem controller 115, but in some cases, the memory system 110 does not include a memory subsystem controller 115. For example, the memory system 110 may instead rely on an external controller (e.g., implemented by the host system 105) or one or more local controllers 135 or 145 internal to the memory subsystem 130 or the memory subsystem 140, respectively, to perform the functions attributed herein to the memory subsystem controller 115. In general, one or more functions attributed herein to the memory subsystem controller 115 may, in some cases, alternatively be performed by the host system 105, the local controller 135, or the local controller 145.

[0032] Memory subsystem 140 may include one or more arrays of volatile memory cells. For example, memory subsystem 140 may include random access memory (RAM) memory cells, such as dynamic RAM (DRAM) memory cells and synchronous DRAM (SDRAM) memory cells.

[0033] The memory subsystem 130 may include one or more arrays of non-volatile memory cells. For example, the memory subsystem 130 may include NAND (e.g., NAND flash) memory, ROM, phase change memory (PCM), select memory, other chalcogenide-based memory, ferroelectric RAM (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash) memory, spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), and electrically erasable programmable ROM (EEPROM).

[0034] In some examples, memory subsystem 130 or memory subsystem 140 may include a local controller 135 or a local controller 145, respectively, that may perform operations on one or more memory cells of memory subsystem 130 or memory subsystem 140. Local controller 135 or local controller 145 may operate in conjunction with memory subsystem controller 115, or may perform one or more functions attributed herein to memory subsystem controller 115. In some cases, memory subsystem 130 or memory subsystem 140 including local controller 135 or local controller 145 may be referred to as a managed memory device and may include a raw memory array and related circuitry, e.g., in combination with a local (e.g., on-die or in-package) controller (e.g., local controller 135 or local controller 145). An example of a managed memory device is a managed NAND (MNAND) device.

[0035] In some cases, memory subsystem 130 may be a NAND (e.g., NAND flash) device. Memory subsystem 130 may be a package that includes one or more dies 160. Die 160 may be a piece of electronic-grade semiconductor cut from a wafer (e.g., a silicon die cut from a silicon wafer). Each die 160 may include one or more planes 165, and each plane 165 may include a corresponding set of blocks 170, where each block 170 includes a corresponding set of pages 175, and each page 175 includes a set of memory cells.

[0036] In some cases, the NAND memory subsystem 130 may include memory cells configured to each store one bit of information, which may be referred to as single-level cells (SLC). Additionally or alternatively, the NAND memory subsystem 130 may include memory cells configured to each store multiple bits of information, which may be referred to as multi-level cells (MLC) if configured to each store two bits of information, triple-level cells (TLC) if configured to each store three bits of information, quad-level cells (QLC) if configured to each store four bits of information, or more generally, multi-level memory cells. Multi-level memory cells may provide greater storage density relative to SLC memory cells, but in some cases may involve narrower read or write margins or greater complexity for supporting circuitry.

[0037] In some cases, a plane 165 may refer to a group of blocks 170 for which parallel operations may be performed on different blocks 170 within different planes 165. That is, parallel operations may be performed on memory cells within different blocks 170 as long as the different blocks 170 are within different planes 165. In some cases, performing parallel operations in different planes 165 may be subject to one or more restrictions, such as performing parallel operations on memory cells within different pages 175 that have the same page address within their respective planes 165 (e.g., related to command decode, page address decode circuitry, or other circuitry shared across planes 165).

[0038] In some cases, block 170 can include memory cells organized into rows (pages 175) and columns (e.g., strings, not shown). For example, memory cells in the same page 175 can share a common word line (e.g., be coupled to a common word line), and memory cells in the same string can share a common bit line (e.g., be coupled to a common bit line).

[0039] For some NAND architectures, memory cells can be read and programmed (e.g., written) at a page 175 granularity level, but can be erased at a block 170 granularity level. That is, a page 175 can be the smallest unit of memory (e.g., a collection of memory cells) that can be independently programmed or read (programmed or read simultaneously as part of a single program or read operation), and a block 170 can be the smallest unit of memory (e.g., a collection of memory cells) that can be independently erased (e.g., erased simultaneously as part of a single erase operation). Furthermore, in some cases, a NAND memory cell can be erased before it can be rewritten with new data. Thus, for example, a used page 175 can be updated without erasing the entire block 170 containing the page 175. To update some data within a block 170 while retaining other data within the block 170, the memory subsystem 130 can copy the data to be retained to a new block 170 and write the updated data to one or more remaining pages of the new block 170. The memory subsystem 130 (e.g., the local controller 135) or the memory subsystem controller 115 may mark or otherwise indicate the data held in the old block 170 as invalid or outdated, and update a logical-to-physical (L2P) mapping table so that the logical address (e.g., LBA) of the data is associated with the new valid block 170 rather than the old invalid block 170. In some cases, such copying and remapping may be preferable to erasing and rewriting the entire old block 170, for example, due to latency or wear considerations. In some cases, one or more copies of the L2P mapping table may be stored within a memory unit of the memory subsystem 130 (e.g., within one or more blocks 170 or planes 165) for use (e.g., reference and update) by the local controller 135 or the memory subsystem controller 115.

[0040] In some cases, an L2P table may be maintained and data may be marked as valid or invalid at the page 175 granularity level, and a page 175 may contain valid data, invalid data, or no data. Invalid data may be data that is outdated because the latest or updated version of the data is stored in a different page 175 of the memory subsystem 130. Invalid data may have been previously programmed to an invalid page 175 but may no longer be associated with a valid logical address, such as a logical address referenced by the host system 105. Valid data may be the latest version of such data stored on the memory subsystem 130. A page 175 that does not contain data may be a page 175 that has never been written to or has been erased.

[0041] In some cases, the memory subsystem controller 115, the local controller 135, or the local controller 145 may perform operations for the memory subsystem 130 or the memory subsystem 140 (e.g., as part of one or more media management algorithms), such as wear leveling, flushing, garbage collection, scrubbing, etc. For example, within the memory subsystem 130, a block 170 may have some pages 175 containing valid data and some pages 175 containing invalid data. To avoid waiting for some or all of the pages 175 in the block 170 to have invalid data in order to be erased and to reuse the block 170, an algorithm known as "garbage collection" may be invoked to allow the block 170 to be erased and freed as a free block for subsequent write operations. Garbage collection may refer to a set of media management operations that include, for example, selecting a block 170 containing valid and invalid data, selecting a page 175 in the block containing valid data, copying the valid data from the selected page 175 to a new location (e.g., a free page 175 in another block 170), marking the data in the previously selected page 175 as invalid, and erasing the selected block 170. As a result, the number of erased blocks 170 may be increased, so that more blocks 170 may be used to store subsequent data (e.g., data subsequently received from the host system 105).

[0042] The system 100 may include a non-transitory computer-readable medium (e.g., local memory 120, memory subsystem 130, and / or memory subsystem 140) storing instructions (e.g., firmware) for performing the techniques for read prediction (e.g., methods 400 and 600) during the system boot procedure described herein. For example, when the instructions are executed by the controller 115 (or more specifically, a processor of the controller 115), the controller may perform the method for mapping descriptors described herein.

[0043] Memory system 100 may include: a first memory subsystem (e.g., memory subsystem 130) that provides non-volatile storage to a host system; a second memory subsystem (e.g., memory subsystem 140) that provides volatile storage to the host system; and a third memory subsystem that is configurable to provide either volatile storage, non-volatile storage, or both to the host system. The third memory subsystem may include multiple ports, each capable of communicating with the host system using a different interface. The third memory subsystem may be dynamically configurable to perform different functions based on the needs of the host system.

[0044] Figure 2 An example of a system 200 supporting a memory system having a selectively interfaceable memory subsystem according to examples disclosed herein is illustrated. The system 200 may be a reference Figure 1 An example of the system 100 is described. Figure 1 As discussed, sometimes the system may use storage devices that are more volatile than normal, such as when using artificial intelligence (AI) software or playing video games. At other times, the system may use storage devices that are more non-volatile than normal, such as when using 5G data or streaming high-definition video. System 200 can accommodate both scenarios using a memory system with dynamically reconfigurable memory.

[0045] System 200 may include a host system 205 and a memory system 210. Host system 205 may be a reference Figure 1 The host system 105 is described as an example. The memory system 210 may be referenced Figure 1 An example of the memory system 110 is depicted. The host system 205 can provide instructions to the memory system 210 to dynamically configure the memory system 210, as discussed below.

[0046] The host system 205 can be coupled to the memory system 210 via a plurality of interfaces 215. The interfaces 215 can be reference Figure 1 An example of a physical host interface described. The interface may include a pinout (a specific layout of pins and a specific assignment made to each pin) and a communication protocol for conveying information via those pins. Interface 215 may include a first interface 215-a and a second interface 215-b. In some cases, the first interface 215-a may be used to communicate with non-volatile memory, and in those cases, may be referred to as a non-volatile memory interface (e.g., a UFS interface using a UFS-related communication protocol). In some cases, the second interface 215-b may be used to communicate with volatile memory, and in those cases, may be referred to as a volatile memory interface (e.g., a DRAM interface using a DRAM-related communication protocol). Other interfaces may also couple the host system 205 with the memory system 210. The interface 215 may pass information through it and may, in at least some cases, provide an associated protocol for passing control, address, data, and other signals between the memory system 210 and the host system 205.

[0047] For example, the type of interface 215 may include, but is not limited to, a SATA interface, a UFS interface, an eMMC interface, a PCIe interface, a USB interface, a Fibre Channel, SCSI, Serial Attached SCSI, a DDR memory bus, a DIMM interface, an open NAND flash interface, an LPDDR interface, or any other interface, or any combination thereof.

[0048] The memory system 210 may include multiple memory subsystems 220 that may be coupled to the host system 205 via an interface 215. Two or more of the memory subsystems 220 may reside on a single die, such as a multi-chip package (MCP), or all of the subsystems 220 may reside on separate dies. The memory subsystems 220 may be referenced Figure 1 Memory subsystems 220 may be of the same type or of a different type. For example, the types may include, but are not limited to, magnetic hard disks, RAM, ROM, DRAM, SDRAM, FeRAM, MRAM, RRAM, flash memory, PCM, 3D Xpoint, or NOR and NAND memory devices, or others. Memory devices may be volatile or non-volatile. Volatile memory cells may lose their programmed state over time unless they are periodically refreshed by an external power source. Non-volatile memory cells can maintain their programmed state for extended periods of time even without external power.

[0049] In some examples, one of the memory subsystems 220 may be of a non-volatile type, one of the memory subsystems 220 may be of a volatile type, and one of the memory subsystems 220 may be configured as either a volatile type or a non-volatile type, or both. In some examples, the number of memory subsystems 220 is greater than the number of interfaces 215. In those cases, two or more of the memory subsystems 220 may communicate with the host system 205 using the same interface 215. In one example, one of the memory subsystems 220 may be configurable to share more than one interface 215.

[0050] In some examples, the memory system 210 may include a first memory subsystem 220-a, a second memory subsystem 220-b, and a third memory subsystem 220-c. In some examples, the first memory subsystem 220-a may be of a first type, the second memory subsystem 220-b may be of a second type, and the third memory subsystem may be of a third type.

[0051] In some examples, the first memory subsystem 220-a may be a non-volatile memory subsystem. For example, the first memory subsystem 220-a may include one or more NAND memory cells. The first memory subsystem 220-a may communicate with the host system 205 via a non-volatile memory interface 215-a. For example, the first memory subsystem 220-a may be part of a UFS device 225 that includes a central processing unit (CPU) 230 that communicates with the host system 205 via a UFS interface. That is, the first interface 215-a may be a UFS interface that the non-volatile first memory subsystem 220-a can use to communicate information with the host system 205.

[0052] In some examples, the second memory subsystem 220-b can be a volatile memory subsystem. For example, the second memory subsystem 220-b can include one or more DRAM memory units. The second memory subsystem 220-b can communicate with the host system 205 via a volatile memory interface 215-b. For example, the second memory subsystem 220-b can communicate with the host system 205 via a DRAM interface. That is, the second interface 215-b can be a volatile DRAM interface that the second memory subsystem 220-b can use to communicate information with the host system 205.

[0053] The third memory subsystem 220-c can be a memory type that is configurable to communicate with the host system 205 using two or more of the interfaces 215. In some examples, the third memory subsystem 220-c can be selectively configurable to operate as a non-volatile memory subsystem or a volatile memory subsystem. In some examples, when communicating information via the first interface 215-a, the third memory subsystem 220-c can be configured as a second non-volatile memory subsystem, and when communicating information via the second interface 215-b, the third memory subsystem can be configured as a second volatile memory subsystem. In some embodiments, the third memory subsystem 220-c can be configurable to communicate with the host system 205 using multiple interfaces simultaneously.

[0054] In some examples, the third memory subsystem 220-c may be configurable to communicate with the host system 205 via the non-volatile memory interface 215-a or the volatile memory interface 215-b, or both. For example, when configured as a non-volatile type, the third memory subsystem 220-c may communicate with the host system 205 via the first interface 215-a, and when configured as a volatile type, the third memory subsystem 220-c may communicate with the host system 205 via the second interface 215-b.

[0055] As described herein, some memory cells can function as either volatile or nonvolatile memory. For example, some resistive RAM, such as 3DXP memory, can include FeRAM memory cells that can function as volatile memory. Other types of memory cells can also function as either volatile or nonvolatile memory. For example, FeRAM memory cells can function as nonvolatile memory because they can maintain their programmed state for extended periods of time. Some FeRAM memory cells can have fast access times and can function as volatile memory.

[0056] In some examples, the third memory subsystem 220-c may include one or more resistive RAM memory cells, such as 3DXP memory cells. In some examples, the resistive RAM memory cells may be configured to function as non-volatile memory and routed through the non-volatile memory interface 215-a. In some examples, the resistive RAM memory cells may be configured to function as volatile memory and routed through the volatile memory interface 215-b. In some examples, the UFS device 225 may include NAND memory cells and resistive RAM memory cells. The NAND memory cells may be routed through the non-volatile memory interface 215-a.

[0057] The memory system 210 may include an interface bridge 235 that can couple the third memory subsystem 220-c to the correct interface 215. For example, depending on the configuration of the third memory subsystem 220-c, the interface bridge 235 can couple the memory subsystem 220-c to the first interface 215-a or the second interface 215-c. In some examples, when the third memory subsystem 220-c is configured to operate as non-volatile memory, the interface bridge 235 can route information between the third memory subsystem 220-c and the host system 205 via the CPU 230 through the non-volatile memory interface 215-a, and when the third memory subsystem 220-c is configured to operate as volatile memory, the interface bridge 235 can route information through the volatile memory interface 215-b. In some examples, the interface 215 to which the third memory subsystem 220-c is coupled can be dynamically reconfigurable.

[0058] The third memory subsystem 220-c may include a plurality of ports 240 through which the third memory subsystem 220-c may be configured to communicate information with the host system 205. Each port 240 may be coupled to the interface 215 and may be configured so that the third memory subsystem 220-c communicates information with the host system 205 via a particular interface 215. For example, a first port 240-a may be configured so that the third memory subsystem 220-c communicates information with the host system 205 via the first interface 215-a, and a second port 240-b may be configured so that the third memory subsystem 220-c communicates information with the host system 205 via the second interface 215-b. Each port 240 may be coupled to the interface bridge 235 so that information passing through each port 240 may be routed to the interface 215 through the interface bridge 235.

[0059] Figure 3 An example of a memory subsystem 300 supporting a memory system having a selectively interfaceable memory subsystem according to examples disclosed herein is illustrated. The memory subsystem 300 may be referenced Figure 2 An example of a third memory subsystem 220-c is depicted.

[0060] The memory subsystem 300 may include multiple ports 240, such as a first port 240-a and a second port 240-b. The memory subsystem 300 may also include any number of ports 240 (e.g., one, two, three, four, five, six, seven, eight, etc.). The ports 240 may be used to access the memory of the memory subsystem 300. As described herein, the ports 240 may be used to communicate with the host system 205 using different interfaces 215. The memory subsystem 300 may include an I / O interface 305 and a peripheral component 310 corresponding to each port 240. The I / O interface 305 may include drivers and receivers associated with communication between the port 240 and components external to the memory subsystem 300. The peripheral components 310 may include other components used by the ports to access the memory of the memory subsystem 300, such as drivers for word lines or digit lines, sensing components, and other components. In some examples, each peripheral component 310 may access some or all of the memory of the memory subsystem 300. In some cases, each peripheral component 310 (and therefore, each port 240) may be configurable to access any portion of the memory of the memory subsystem 300. Some of the peripheral components may be positioned below the area of the memory cells (e.g., as part of a CMOS under array (CuA) configuration).

[0061] To prevent the host system 205 from accessing the same memory unit through different interfaces 215, the memory of the memory subsystem 300 can be divided into separate portions 320. In some examples, the accessible address range corresponding to each portion 320 can be statically or dynamically defined. Each portion 320 can be configurable to communicate information with the host system 205 via one or both of the interfaces 215. For example, a first portion 320-a can be selectively configurable to communicate information with the host system 205 via the first interface 215-a and the second interface 215-b, and a second portion 320-b can be selectively configurable to communicate information with the host system 205 via the first interface 215-a and the second interface 215-b. In some examples, the second portion 320-b can be selectively configurable to communicate information with the host system 205 via the first interface 215-a and the second interface 215-b, regardless of whether the first portion 320-a uses the first interface 215-a or the second interface 215-b. In some examples, each portion 320 can be configured to communicate via a separate interface with the host system 205. In some examples, one or more registers can be used to configure the portions, port assignments, and other configurations.

[0062] In some examples, memory subsystem 300 may include multiple memory blocks 315, each allocated to portion 320. Figure 3, memory subsystem 300 may include 32 memory blocks 315, with blocks 1-18 allocated to a first portion 320-a and blocks 19-32 allocated to a second portion 320-b. In some examples, the size of each portion 320 may be dynamically or semi-statically reconfigurable. In some cases, host system 205, memory system 210, memory subsystem 220-c, or a combination thereof may be configured to adjust the size of portion 320 or the allocation of different portions or blocks to different ports.

[0063] Different portions 320 may be assigned to different ports 240. Each portion 320 may be assigned to a different port 240 such that information to and from the portion 320 may pass through the assigned ports 240. For example, a first portion 320-a may be assigned to a first port 240-a, and a second portion 320-b may be assigned to a second port 240-b, or vice versa. In some examples, the ports 240 to which the portions 320 are assigned may be dynamically reconfigurable.

[0064] Based on the configuration of the third memory subsystem 300, the interface bridge 235 can couple each port to one of the interfaces 215. Thus, information communicated between each portion 320 and the host system 205 can be routed through the interface 215 to which the corresponding port 240 is coupled. In this way, two interfaces 215 can be used simultaneously to communicate information between the host system 205 and the memory subsystem 300. In some examples, the interface 215 to which the port 240 is coupled can be dynamically reconfigurable.

[0065] The memory system 210 and its components can be dynamically configured by the host system 205. In some examples, the host system 205 can send one or more instructions to the memory system 210 via the interface 215 or any other interface. In some examples, the instructions can be received and processed by one or more of the interface bridge 235, the controller, the memory subsystem 220, or other components. If sent to the memory subsystem 220, the instructions can be processed by the memory subsystem controller 115 or the local controller 135 (see Figure 1 described) or other memory subsystem components (such as a controller, CPU or other components) receive and process.

[0066] Figure 4A flowchart illustrating a method 400 for supporting a memory system having a selectively interfaceable memory subsystem according to examples disclosed herein is shown. Method 400 can be configured to dynamically adjust the size of memory and storage devices to match the needs of the system. The operations of method 400 can be implemented by a memory system or memory subsystem as described herein, or components thereof. In some examples, the memory system or memory subsystem can execute a set of instructions to control functional elements of the memory system to perform the described functions. Additionally or alternatively, the memory system can use dedicated hardware to perform aspects of the described functions.

[0067] At 405, information can be communicated between a first memory subsystem and a host system via a first interface. In some examples, the first memory subsystem can be a first type of memory. In some examples, the first memory subsystem can be a non-volatile type. In some examples, the first interface can be a non-volatile memory interface.

[0068] At 410, information can be communicated between the second memory subsystem and the host system via a second interface. In some examples, the second memory subsystem can be a second type of memory. In some examples, the second memory subsystem can be a volatile type. In some examples, the second interface can be a volatile memory interface.

[0069] At 415, an indication of a desired configuration of the third memory subsystem may be received (e.g., by the memory system from the host system). In some examples, the third memory subsystem may be a third type of memory. In some examples, the indication may be received via the first interface, the second interface, or another interface. In some examples, the third memory subsystem may be dynamically configured based on the indication.

[0070] At 420, a determination can be made as to which interface or interfaces the third memory subsystem will use based on the indication. If the memory system determines that the third memory subsystem will use the first interface, the method can continue to 425. If the memory system determines that the third memory subsystem will use the second interface, the method can continue to 435. If the memory system determines that the third memory subsystem will use both the first interface and the second interface, the method can continue to 445.

[0071] At 425, the third memory subsystem can be configured to communicate with the host system using the first interface. In some examples, the configuration can be performed by an interface bridge, a controller, one or more of the memory subsystems, or other components.

[0072] At 430, information can be communicated between the third memory subsystem and the host system via the first interface.

[0073] At 435, the third memory subsystem can be configured to communicate with the host system using the second interface. In some examples, the configuration can be performed by one or more of the interface bridge, the controller, the memory subsystem, or other components.

[0074] At 440, information can be communicated between the third memory subsystem and the host system via the second interface.

[0075] At 445, the third memory subsystem may be configured to communicate with the host system via both the first interface and the second interface. In some examples, the configuration may be performed by an interface bridge, a controller, one or more of the memory subsystems, or other components. In some examples, the memory system may configure a first portion of the third memory subsystem to communicate with the host system via one of the interfaces, and may configure a second portion of the third memory subsystem to communicate with the host system via another interface. In some examples, the third memory subsystem may include a first port and a second port, and the memory system may determine which port to use to communicate information corresponding to each portion.

[0076] At 450, information may be communicated between the third memory subsystem and the host system via the first interface and the second interface. In some examples, information may be communicated between the third memory subsystem and the host system via both the first interface and the second interface. In some examples, the third memory subsystem may include a first port and a second port through which information is communicated. In some examples, information communicated via the first port may be routed through one of the interfaces, and information communicated via the second port may be routed through another interface. In some examples, a first portion of the third memory subsystem communicates with the host system via one of the interfaces, and a second portion of the third memory subsystem communicates with the host system via the other interface.

[0077] As indicated by the dashed lines, one or more portions of method 400 may be repeated during operation. For example, after the operations described in 430, 440, or 450, the method may return to 415 and receive another instruction. Each time the operations of 415 are repeated, the instruction received at 415 may be different from the instruction received the last time the operations were performed. The new instruction may specify changes to the interface to be used by the third memory subsystem, the configuration of any memory portions or ports, etc. Then, at 425, 435, or 445, the third memory may be reconfigured based on the new instruction. Thus, the third memory subsystem may be dynamically reconfigurable.

[0078] Figure 5 A block diagram 500 is shown of a memory system 505 supporting a memory system having a selectively interfaceable memory subsystem according to examples disclosed herein. The memory system 505 may be a memory system as described in reference to FIG. Figure 2-4An example of aspects of the described memory system. Memory system 505 can include a communication component 510, a receiving component 515, and a configuration component 520. Each of these modules can communicate with each other, directly or indirectly (eg, via one or more buses).

[0079] The communication component 510 can communicate first information between a first memory subsystem of the memory system and a host system via a first interface of the memory system, where the first memory subsystem is a first type of memory. In some examples, the communication component 510 can communicate second information between a second memory subsystem of the memory system and the host system via a second interface of the memory system, where the second memory subsystem is a second type of memory. In some examples, the communication component 510 can communicate third information between a third memory subsystem and the host system via the first interface or the second interface based on the configuration of the third memory subsystem.

[0080] In some examples, the communication component 510 can communicate third information between the third memory subsystem and the host system via the first interface. In some examples, the communication component 510 can communicate fourth information between the third memory subsystem and the host system via the second interface.

[0081] In some cases, third information can be communicated between the third memory subsystem and the host system via the first port. In some cases, fourth information can be communicated between the third memory subsystem and the host system via the second port.

[0082] In some cases, the third memory subsystem may be configured as a non-volatile memory subsystem when information is communicated via the first interface, and may be configured as a volatile memory subsystem when information is communicated via the second interface.

[0083] The receiving component 515 can receive an indication of whether a third memory subsystem of the memory system will communicate with the host system using the first interface, the second interface, or both via the first interface or the second interface. The third memory subsystem can be a third type of memory. In some cases, after configuring the first portion of the third memory subsystem, the receiving component 515 can receive a second indication from the host system.

[0084] The configuration component 520 may, based on the indication, configure the third memory subsystem to communicate with the host system via the first interface, the second interface, or both. In some examples, the configuration component 520 may, based on the indication, configure a first portion of the third memory subsystem to communicate with the host system via the first interface. In some examples, the configuration component 520 may, based on the indication, configure a second portion of the third memory subsystem to communicate with the host system via the second interface, wherein configuring the third memory subsystem is based on configuring the first portion and the second portion. In some examples, the configuration component 520 may, based on the second indication, configure the first portion of the third memory subsystem to have a different size.

[0085] Figure 6 A flowchart illustrating a method 600 for supporting a memory system having a selectively interfaceable memory subsystem according to examples disclosed herein is shown. The operations of the method 600 may be implemented by a memory system or components thereof as described herein. For example, the operations of the method 600 may be implemented by a memory system or components thereof as described herein. Figure 5 The memory system described herein performs the functions described herein. In some examples, the memory system may execute a set of instructions to control functional elements of the memory system to perform the functions described herein. Additionally or alternatively, the memory system may use dedicated hardware to perform aspects of the functions described herein.

[0086] At 605, the memory system may communicate first information between a first memory subsystem of the memory system and a host system via a first interface of the memory system, the first memory subsystem being a first type of memory. The operations of 605 may be performed according to the methods described herein. In some examples, aspects of the operations of 605 may be as described with reference to Figure 5 The described communication components are executed.

[0087] At 610, the memory system may communicate second information between a second memory subsystem of the memory system and a host system via a second interface of the memory system, the second memory subsystem being a second type of memory. The operations of 610 may be performed according to the methods described herein. In some examples, the host system may be configured as described in reference to Figure 5 The described communication components perform aspects of the operations of 610 .

[0088] At 615, the memory system may receive an indication via the first interface or the second interface of whether a third memory subsystem of the memory system will communicate with the host system using the first interface, the second interface, or both, the third memory subsystem being a third type of memory. The operation of 615 may be performed according to the methods described herein. In some examples, the operation may be performed by a processor as described in reference to Figure 5 Aspects of the operations of the receiving component performing 615 are described.

[0089] At 620, the memory system may configure the third memory subsystem to communicate with the host system via the first interface, the second interface, or both based on the indication. The operation of 620 may be performed according to the method described herein. In some examples, the method may be configured as described in reference to Figure 5 Aspects of the operations of the configuration component execution 620 are described.

[0090] In some examples, an apparatus as described herein may perform one or more methods, such as method 600. The apparatus may include features, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: communicating first information between a first memory subsystem of a memory system and a host system via a first interface of the memory system, the first memory subsystem being a first type of memory; communicating second information between a second memory subsystem of the memory system and the host system via a second interface of the memory system, the second memory subsystem being a second type of memory; receiving an indication via the first interface or the second interface of whether a third memory subsystem of the memory system is to communicate with the host system using the first interface, the second interface, or both, the third memory subsystem being a third type of memory; and configuring the third memory subsystem to communicate with the host system via the first interface, the second interface, or both based on the indication.

[0091] Some examples of the method 600 and apparatus described herein may further include operations, features, means, or instructions for communicating third information between the third memory subsystem and the host system via the first interface or the second interface based on configuring the third memory subsystem.

[0092] Some examples of method 600 and apparatus described herein may further include operations, features, means, or instructions for communicating third information between the third memory subsystem and the host system via the first interface and communicating fourth information between the third memory subsystem and the host system via the second interface.

[0093] In some examples of method 600 and the devices described herein, the third memory subsystem may include operations, features, components, or instructions for: a first port through which third information can be communicated between the third memory subsystem and the host system; and a second port through which fourth information can be communicated between the third memory subsystem and the host system.

[0094] Some instances of method 600 and the devices described herein may further include operations, features, components, or instructions for: configuring a first portion of the third memory subsystem to communicate with the host system via a first interface based on the indication; and configuring a second portion of the third memory subsystem to communicate with the host system via a second interface based on the indication, wherein configuring the third memory subsystem may be based on configuring the first portion and the second portion.

[0095] Some instances of method 600 and the apparatus described herein may further include operations, features, components, or instructions for: receiving a second indication from the host system after configuring the first portion of the third memory subsystem; and configuring the first portion of the third memory subsystem to have a different size based on the second indication.

[0096] In some examples of method 600 and devices described herein, the third memory subsystem may be configured as a non-volatile memory subsystem when information is communicated via the first interface and as a volatile memory subsystem when information is communicated via the second interface.

[0097] It should be noted that the methods described above describe possible embodiments, and that the operations and steps may be rearranged or otherwise modified, and other embodiments are possible. Furthermore, parts of two or more of the methods may be combined.

[0098] A device is described. The device may include: a first memory subsystem of a first type that is configurable to communicate information with a host system via a first interface; a second memory subsystem of a second type that is configurable to communicate information with the host system via a second interface; and a third memory subsystem of a third type that is selectively configurable to communicate information with the host system via the first interface and the second interface.

[0099] In some instances, the third memory subsystem may include operations, features, components, or instructions for: a first port configured to enable the third memory subsystem to communicate information with the host system via a first interface; and a second port configured to enable the third memory subsystem to communicate information with the host system via a second interface.

[0100] In some examples, the third memory subsystem may include a first portion of memory cells coupled to the first port and a second portion of memory cells coupled to the second port. In some examples, a first size of the first portion and a second size of the second portion may be dynamically reconfigurable.

[0101] In some examples, the third memory subsystem may include operations, features, components, or instructions for: a first portion of the memory unit that is selectively configurable to communicate information with the host system via the first interface and the second interface; and a second portion of the memory unit that is selectively configurable to communicate information with the host system via the first interface and the second interface. In some examples, the second portion of the third memory subsystem may be selectively configurable to communicate information with the host system via the first interface and the second interface, regardless of whether the first portion uses the first interface or the second interface. In some examples, the first size of the first portion and the second size of the second portion may be reconfigurable.

[0102] In some examples, the third memory subsystem may include a set of ports through which the third memory subsystem may be configured to communicate information with the host system.

[0103] In some examples, the third memory subsystem may be configured as a non-volatile memory subsystem when information is communicated via the first interface, and may be configured as a volatile memory subsystem when information is communicated via the second interface.

[0104] In some examples, the third memory subsystem of the third type may include one or more resistive RAM memory cells, such as 3DXP memory cells. In some examples, the first memory subsystem of the first type may include one or more NAND memory cells, and the second memory subsystem of the second type may include one or more DRAM memory cells. In some examples, the first interface may include a DRAM interface, and the second interface may include a UFS interface.

[0105] A device is described. The device may include: a non-volatile memory subsystem that can be configured to communicate information with a host system via a first interface; a volatile memory subsystem that can be configured to communicate information with the host system via a second interface; and a third memory subsystem that can be configured to communicate information with the host system via the first interface and the second interface, wherein when communicating information via the first interface, the third memory subsystem is configured as a second non-volatile memory subsystem, and when communicating information via the second interface, the third memory subsystem is configured as a second volatile memory subsystem.

[0106] In some examples, the third memory subsystem can be configured to communicate information via the first interface and the second interface simultaneously.In some examples, the third memory subsystem can include a first port coupled to the first interface and a second port coupled to the second interface.

[0107] In some examples, the third memory subsystem may include one or more resistive RAM memory cells, such as 3DXP memory cells. In some examples, the non-volatile memory subsystem may include one or more NAND memory cells, and the volatile memory subsystem may include one or more DRAM memory cells. In some examples, the first interface may include a DRAM interface, and the second interface may include a UFS interface.

[0108] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, one skilled in the art will understand that the signal may represent a signal bus, where the bus may have multiple bit widths.

[0109] The terms "electronic communication," "conductive contact," "connected," and "coupled" may refer to a relationship between components that supports the flow of signals between the components. Components are said to be in electronic communication with each other (or in conductive contact with each other, or connected to each other, or coupled to each other) if any conductive path exists between the components that can support the flow of signals between the components at any time. At any given time, the conductive path between components in electronic communication with each other (or in conductive contact with each other, or connected to each other, or coupled to each other) may be an open circuit or a closed circuit based on the operation of the device that includes the connected components. The conductive path between the connected components may be a direct conductive path between the components, or the conductive path between the connected components may be an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some examples, the flow of signals between the connected components may be interrupted for a period of time, for example, using one or more intermediate components such as switches or transistors.

[0110] The term "coupling" refers to the condition of moving from an open-circuit relationship between components, in which signals are currently unable to communicate between the components via a conductive path, to a closed-circuit relationship between the components in which signals can communicate between the components via the conductive path. When a component, such as a controller, couples other components together, the component initiates a change that allows signals to flow between the other components via conductive paths that previously did not permit signal flow.

[0111] The term "isolation" refers to a relationship between components where signals are currently unable to flow between them. If an open circuit exists between the components, the components are isolated from each other. For example, components separated by a switch positioned between them are isolated from each other when the switch is open. When a controller isolates two components, it implements a change that prevents signals from flowing between the components using the conductive path that previously allowed signal flow.

[0112] The devices discussed herein, including memory arrays, can be formed on a semiconductor substrate such as silicon, germanium, a silicon-germanium alloy, gallium arsenide, gallium nitride, or the like. In some examples, the substrate is a semiconductor wafer. In other examples, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a subregion of the substrate can be controlled by doping using various chemical species, including but not limited to phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate by ion implantation or by any other doping method.

[0113] The description set forth herein in conjunction with the accompanying drawings describes example configurations and does not represent all examples that may be implemented or within the scope of the claims. The term "exemplary" as used herein means "serving as an example, instance, or illustration" and is not "preferred over" or "superior to other examples." The detailed description includes specific details that provide an understanding of the described technology. However, these technologies can be practiced without these specific details. In some cases, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0114] In the accompanying drawings, similar components or features may have the same reference label. In addition, various components of the same type may be distinguished by a dash following the reference label and a second label (e.g., "215-a") to distinguish between similar components. If only the first reference label (e.g., "215") is used in the specification, the description may apply to any of the similar components having the same first reference label regardless of the second reference label.

[0115] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0116] The various illustrative blocks and modules described in connection with the present disclosure herein may be implemented or executed with a general purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0117] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored as one or more instructions or codes on a computer-readable medium or transmitted via a computer-readable medium. Other examples and embodiments are within the scope of the present disclosure and the appended claims. For example, due to the nature of software, the functions described above may be implemented using software, hardware, firmware, hard wiring, or a combination of any of these executed by a processor. The features of the implementation functions may also be physically located at various locations, including being distributed so that the various parts of the functions are implemented at different physical locations. In addition, as used herein (included in the claims), as used in a list of items (e.g., a list of items beginning with a phrase such as "at least one of" or "one or more of"), "or" indicates an inclusive list, such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). In addition, as used herein, the phrase "based on" should not be understood to refer to a set of closed conditions. For example, without departing from the scope of the present disclosure, exemplary steps described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "based at least in part on."

[0118] The description herein is provided to enable one skilled in the art to make or use the present disclosure. Various modifications of the present disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A memory system comprising: a first memory subsystem of a first type configured to communicate information with a host system via a first interface; a second memory subsystem of a second type configured to communicate information with the host system via a second interface, wherein the first type is different from the second type; as well as a third memory subsystem that is selectively configurable to communicate information with the host system via the first interface and the second interface, wherein the third memory subsystem comprises: a first port configured to enable the third memory subsystem, when configured as the first type, to communicate information with the host system via the first interface; as well as A second port is configured to enable the third memory subsystem, when configured as the second type, to communicate information with the host system via the second interface. 2 . The memory system of claim 1 , wherein the third memory subsystem comprises a first portion of memory cells coupled to the first port and a second portion of memory cells coupled to the second port. 3 . The memory system of claim 2 , wherein the first size of the first portion of the memory cells and the second size of the second portion of the memory cells are dynamically reconfigurable.

4. The memory system of claim 1 , wherein the third memory subsystem comprises: a first portion of a memory unit that is selectively configurable to communicate information with the host system via the first interface and the second interface; as well as A second portion of a memory unit is selectively configurable to communicate information with the host system via the first interface and the second interface.

5. The memory system of claim 4, wherein the second portion of the memory unit is selectively configurable to communicate information with the host system via the first interface and the second interface regardless of whether the first portion of the memory unit uses the first interface or the second interface. 6 . The memory system of claim 5 , wherein the first size of the first portion of the memory cells and the second size of the second portion of the memory cells are reconfigurable. 7 . The memory system of claim 1 , wherein the third memory subsystem comprises a plurality of ports, the third memory subsystem being configured to communicate information with the host system through the plurality of ports.

8. The memory system of claim 1, wherein the third memory subsystem is configured as a non-volatile memory subsystem when information is communicated via the first interface, and is configured as a volatile memory subsystem when information is communicated via the second interface.

9. The memory system of claim 1, wherein the third memory subsystem comprises one or more resistive RAM memory cells.

10. The memory system of claim 9, wherein: The first memory subsystem of the first type includes one or more NAND memory cells; and The second memory subsystem of the second type includes one or more dynamic random access memory (DRAM) cells.

11. The memory system of claim 1 , wherein: The first interface comprises a dynamic random access memory (DRAM) interface; and The second interface includes a universal flash storage device UFS interface.

12. A method performed by a memory system, the method comprising: communicating first information between a first memory subsystem of the memory system and a host system via a first interface of the memory system, the first memory subsystem being a first type of memory; communicating second information between a second memory subsystem of the memory system and the host system via a second interface of the memory system, the second memory subsystem being a second type of memory, wherein the first type of memory is different from the second type of memory; receiving, via the first interface or the second interface, an indication of whether a third memory subsystem of the memory system will communicate with the host system using the first interface, the second interface, or both, the third memory subsystem comprising: The first port, when the third memory subsystem is configured as the first type, information is transmitted through the A first port communicates between the third memory subsystem and the host system via the first interface; and a second port, through which the information is communicated between the third memory subsystem and the host system via the second interface when the third memory subsystem is configured as the second type; and The third memory subsystem is configured to communicate with the host system via the first interface, the second interface, or both based at least in part on the indication.

13. The method according to claim 12, further comprising: Third information is communicated between the third memory subsystem and the host system via the first interface or the second interface based at least in part on configuring the third memory subsystem.

14. The method according to claim 12, further comprising: communicating third information between the third memory subsystem and the host system via the first interface; as well as Fourth information is communicated between the third memory subsystem and the host system via the second interface.

15. The method of claim 12, further comprising: configuring a first portion of the third memory subsystem to communicate with the host system via the first interface based at least in part on the indication; as well as A second portion of the third memory subsystem is configured to communicate with the host system via the second interface based at least in part on the indication, wherein configuring the third memory subsystem is based at least in part on configuring the first portion and the second portion.

16. The method according to claim 15, further comprising: receiving a second indication from the host system after configuring the first portion of the third memory subsystem; as well as The first portion of the third memory subsystem is configured to have a different size based at least in part on the second indication.

17. The method of claim 12, wherein when information is communicated via the first interface, the third memory subsystem is configured as a non-volatile memory subsystem, and when information is communicated via the second interface, the third memory subsystem is configured as a volatile memory subsystem.

18. The method of claim 12, wherein the third memory subsystem comprises one or more resistive RAM memory cells.

19. The method of claim 12, wherein: The first memory subsystem of the first type includes one or more NAND memory cells; and The second memory subsystem of the second type includes one or more dynamic random access memory (DRAM) cells.

20. A memory system comprising: a non-volatile memory subsystem configured to communicate information with a host system via a first interface; a volatile memory subsystem configured to communicate information with the host system via a second interface; as well as a third memory subsystem configured to communicate information with the host system via the first interface and the second interface, wherein the third memory subsystem comprises: a first port configured to cause the third memory subsystem, when configured as a second non-volatile memory subsystem, to communicate information via the first interface; as well as A second port is configured to cause the third memory subsystem to communicate information via the second interface when configured as a second volatile memory subsystem.

21. The memory system of claim 20, wherein the third memory subsystem is configured to communicate information via the first interface and the second interface simultaneously.

22. The memory system of claim 20, wherein the third memory subsystem comprises one or more resistive RAM memory cells.

23. The memory system of claim 20, wherein: The non-volatile memory subsystem includes one or more NAND memory cells; and The volatile memory subsystem includes one or more dynamic random access memory (DRAM) units.

24. The memory system of claim 20, wherein: The first interface comprises a dynamic random access memory (DRAM) interface; and The second interface includes a universal flash storage device UFS interface.

Images