Semiconductor device manufacturing method and semiconductor device

Abstract

The present invention relates to a method for manufacturing a semiconductor device and a semiconductor device. The technology disclosed in this specification is a technology for ensuring the spatial distance and creepage distance between terminals and suppressing the size increase of the semiconductor device. The method for manufacturing a semiconductor device related to the technology disclosed in this specification comprises providing at least one semiconductor element, connecting a plurality of first terminals and at least one second terminal to the semiconductor element, the second terminal being a control terminal to which a lower voltage than the first terminal is applied, and forming a first bent portion on the first terminal, so that the first bent portion does not protrude on the mutually opposing surfaces of the plurality of adjacent first terminals.

Description

Technical Field

[0001] The technology disclosed in this specification relates to a method for manufacturing a semiconductor device and a semiconductor device. Background Art

[0002] For example, in the semiconductor device disclosed in Patent Document 1, a plurality of lead terminals connected to the semiconductor element are led out to the outside and are arranged separately from each other.

[0003] Patent Document 1: Japanese Patent Application Laid-Open No. 10-189859

[0004] In particular, when using semiconductor devices for high-power applications, the distance between lead terminals (terminal pitch) needs to be long to ensure adequate spacing and creepage distance. Furthermore, during lead terminal processing, the bent portion (bend) of the lead terminal may expand, shortening the distance between the lead terminals.

[0005] If the terminal pitch is increased in consideration of the above-mentioned circumstances, there is a problem that the semiconductor device becomes excessively large. Summary of the Invention

[0006] The technology disclosed in this specification has been proposed in view of the above-described problems, and is a technology for ensuring the spatial distance and creepage distance between terminals while suppressing an increase in the size of a semiconductor device.

[0007] The first method of the technology disclosed in this specification relates to a method for manufacturing a semiconductor device, wherein at least one semiconductor element is provided, a plurality of first terminals and at least one second terminal are connected to the semiconductor element, the second terminal being a control terminal to which a lower voltage is applied than the first terminal, a first bent portion is formed on the first terminal, and with respect to adjacent plurality of first terminals, the first bent portion does not protrude on surfaces facing each other.

[0008] The second embodiment of the technology disclosed in this specification relates to a semiconductor device comprising: at least one semiconductor element; and a plurality of terminals connected to the semiconductor element, wherein the plurality of terminals comprise: a plurality of first terminals having a first bent portion; and at least one second terminal being a control terminal to which a lower voltage than a voltage of the first terminal is applied, wherein, for adjacent plurality of first terminals, the first bent portion does not protrude on surfaces facing each other.

[0009] Effects of the Invention

[0010] The first embodiment of the technology disclosed in this specification relates to a method for manufacturing a semiconductor device. The method comprises providing at least one semiconductor element, connecting a plurality of first terminals and at least one second terminal to the semiconductor element. The second terminal is a control terminal to which a lower voltage is applied. The first terminal is provided with a first bent portion, and the bent portion does not protrude on opposing surfaces of adjacent first terminals. This structure prevents the bent portion from protruding on opposing surfaces between terminals to which a high voltage is applied, thereby preventing the spatial distance and creepage distance between lead terminals from being shortened. Consequently, the size of the semiconductor device can be reduced.

[0011] A second embodiment of the technology disclosed in this specification relates to a semiconductor device comprising: at least one semiconductor element; and a plurality of terminals connected to the semiconductor element, the plurality of terminals comprising: a plurality of first terminals each having a first bent portion; and at least one second terminal serving as a control terminal to which a lower voltage is applied than the first terminal, wherein the first bent portion does not protrude on opposing surfaces of adjacent first terminals. This structure prevents the bent portion from protruding on opposing surfaces between terminals to which a high voltage is applied, thereby preventing the spatial distance and creepage distance between lead terminals from being shortened. Consequently, the size of the semiconductor device can be reduced.

[0012] Furthermore, the objects, features, aspects, and advantages of the technology disclosed in this specification will become more apparent from the following detailed description and accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a plan view schematically showing an example of the structure of a semiconductor device according to an embodiment.

[0014] Figure 2 This is a cross-sectional view schematically showing an example of the structure of a semiconductor device according to an embodiment.

[0015] Figure 3 is with Figure 1 as well as Figure 2 The illustrated structure corresponds to the circuit diagram.

[0016] Figure 4 yes Figure 3 The structure shown is mainly related to the circuit diagram of the high-voltage IC and the low-voltage IC.

[0017] Figure 5 This is a flowchart showing an example of a manufacturing process of a semiconductor device according to an embodiment, particularly a manufacturing process related to lead forming.

[0018] Figure 6 It means it is completed Figure 5A top view of an example of the structure of a semiconductor device at a point in time from the power chip die bonding step to the transfer molding step.

[0019] Figure 7 It means in Figure 5 A plan view of an example of the structure of a semiconductor device at a time point after the transfer molding step, the tie bar cutting step, and the lead cutting step are completed.

[0020] Figure 8 It specifically indicates Figure 7 A diagram showing an example of the structure of a lead terminal.

[0021] Figure 9 It means in Figure 5 A plan view of an example of the structure of a semiconductor device at a time point after the lead cutting step in FIG. 1 and the lead forming step in FIG.

[0022] Figure 10 yes Figure 9 Cross-sectional view of the illustrated structure.

[0023] Figure 11 It specifically indicates Figure 9 as well as Figure 10 A diagram showing an example of the structure of a lead terminal.

[0024] Figure 12 This is a plan view showing an example of the structure of a semiconductor device at a point in time after the power chip die bonding step to the transfer molding step are completed according to the embodiment.

[0025] Figure 13 Yes Figure 12 A top view of an example of the shape of the slit is shown.

[0026] Figure 14 This is a plan view showing an example of the structure of a semiconductor device at a point in time after the power chip die bonding step to the transfer molding step are completed according to the embodiment.

[0027] Figure 15 This is a plan view showing an example of the structure of a semiconductor device at a point in time after the power chip die bonding step to the transfer molding step are completed according to the embodiment.

[0028] Figure 16 Yes Figure 15 A top view of an example of the shape of the slit is shown.

[0029] Figure 17 This is a plan view showing an example of the structure of a semiconductor device at a point in time after the power chip die bonding step to the transfer molding step are completed according to the embodiment.

[0030] Figure 18 Yes Figure 17 A top view of an example of the shape of a cutting component is shown.

[0031] Figure 19 It means in Figure 5 A plan view of an example of the structure of a semiconductor device at a time point after the transfer molding step, the tie bar cutting step, and the lead cutting step are completed. DETAILED DESCRIPTION

[0032] Below, with reference to the attached Figure 1 In the following embodiments, detailed features are shown for explaining the technology, but these features are for illustration only and are not essential features for implementing the embodiments.

[0033] The drawings are schematic and, for ease of explanation, may be simplified or simplified as appropriate. Furthermore, the sizes and positions of the structures shown in the various drawings are not necessarily accurately depicted and may be modified as appropriate. Furthermore, in drawings such as top views that are not cross-sectional views, hatching may be used to facilitate understanding of the embodiments.

[0034] In the following description, the same components are denoted by the same reference numerals and are illustrated in the figures. Their names and functions are also the same, so their detailed description may be omitted in order to avoid redundancy.

[0035] In the following description, when a certain component is described as “having,” “including,” or “having,” it is not an exclusive expression excluding the presence of other components unless otherwise specified.

[0036] In addition, in the description recorded below, even if ordinal numbers such as "1st" or "2nd" are sometimes used, these terms are used only for convenience to make the content of the implementation method easier to understand and are not limited to the order that can be generated by these ordinal numbers.

[0037] In addition, in the descriptions described below, expressions indicating an equal state, such as "same," "equal," "uniform," or "homogeneous," include, unless otherwise specified, cases where a strictly equal state is indicated, as well as cases where differences occur within the range of tolerance or obtaining the same degree of function.

[0038] In addition, in the descriptions recorded below, even though terms such as "up", "down", "left", "right", "side", "bottom", "front" or "back" are sometimes used to indicate specific positions or directions, these terms are only used for convenience to make the contents of the implementation method easier to understand and have nothing to do with the position or direction during actual implementation.

[0039] <First embodiment>

[0040] Hereinafter, a method for manufacturing a semiconductor device and a semiconductor device according to this embodiment will be described.

[0041] <About the Structure of Semiconductor Devices>

[0042] The (power) semiconductor device described as an example in the following embodiments comprises a power chip (e.g., a switching element), a diode element, and an integrated circuit (IC) on a lead frame. This is a high-power semiconductor device packaged by transfer molding. Terminals are arranged on two opposing sides of the four sides, with control-side terminals and power-side terminals separated on each side. Furthermore, the power chip may be not only a semiconductor chip using Si but also a semiconductor chip using a wide-bandgap semiconductor such as SiC.

[0043] Figure 1 1 is a plan view schematically showing an example of the structure of a semiconductor device according to this embodiment. Figure 2 This is a cross-sectional view schematically showing an example of the structure of a semiconductor device according to this embodiment.

[0044] like Figure 1 and Figure 2 As shown in the example, the semiconductor device has a bootstrap diode 12, a bootstrap diode 14, a bootstrap diode 16, a high-voltage IC 18, a low-voltage IC 20, a power chip 22, a power chip 24, a power chip 26, a power chip 28, a power chip 30, a power chip 32, a freewheeling diode 34, a freewheeling diode 36, a freewheeling diode 38, a freewheeling diode 40, a freewheeling diode 42, a freewheeling diode 44, a lead frame 112, a lead frame 114, a lead frame 116, a lead frame 118, a lead frame 120, a lead frame 122, a lead frame 124, a wire 200 connecting the components, and a molding resin 300 for encapsulating these structures.

[0045] The bootstrap diode 12 is connected to a lead frame 112 , and is further connected to a high-voltage IC 18 , which is a semiconductor element, via the lead frame 112 .

[0046] Likewise, the bootstrap diode 14 is connected to the lead frame 114 , and is connected to the high-voltage IC 18 via the lead frame 114 .

[0047] Likewise, the bootstrap diode 16 is connected to the lead frame 116 , and is connected to the high-voltage IC 18 via the lead frame 116 .

[0048] Furthermore, the power chip 22 is connected to the lead frame 118 , and is also connected to the freewheeling diode 34 and the high-voltage IC 18 via wires 200 .

[0049] Similarly, the power chip 24 is connected to the lead frame 118 , and is also connected to the freewheeling diode 36 and the high-voltage IC 18 via wires 200 .

[0050] Similarly, the power chip 26 is connected to the lead frame 118 , and is also connected to the freewheeling diode 38 and the high-voltage IC 18 via wires 200 .

[0051] Furthermore, the power chip 28 is connected to the lead frame 120 , and is also connected to the freewheeling diode 40 and the low-voltage IC 20 , which is a semiconductor element, via wires 200 .

[0052] Similarly, the power chip 30 is connected to the lead frame 122 , and is also connected to the freewheeling diode 42 and the low-voltage IC 20 via wires 200 .

[0053] Similarly, the power chip 32 is connected to the lead frame 124 , and is also connected to the freewheeling diode 44 and the low-voltage IC 20 via wires 200 .

[0054] The high-voltage IC 18 is connected to a positive power supply terminal VB (lead frame 112 , lead frame 114 , and lead frame 116 ) for three phases (U, V, W) and a floating power supply terminal VS for three phases (U, V, W) via wires.

[0055] The P-phase output terminal on the P side of lead frame 118, the U-phase output terminal on the P side of lead frame 120, the V-phase output terminal on the P side of lead frame 122, the W-phase output terminal on the P side of lead frame 124, and the floating power supply terminal VS for these three phases (U, V, and W) are terminals to which high voltages are applied. Therefore, a certain degree of spatial distance and creepage distance are required between them.

[0056] Here, wide-bandgap semiconductors may also be used for the switching elements and diode elements. Wide-bandgap semiconductors generally refer to semiconductors with a bandgap of approximately 2 eV or greater, and well-known examples include Group III nitrides such as gallium nitride (GaN), Group II oxides such as zinc oxide (ZnO), Group II sulfides such as zinc selenide (ZnSe), diamond, and silicon carbide.

[0057] Figure 1The distance A1 in represents the distance between the P-phase output terminal on the P side and the U-phase output terminal on the P side. Figure 1 The distance A2 in represents the distance between the U-phase output terminal on the P side and the V-phase output terminal on the P side. Figure 1 The distance A3 in represents the distance between the V-phase output terminal on the P side and the W-phase output terminal on the P side. Figure 1 The distance A4 in represents the distance between the W-phase output terminal on the P side and the U-phase output terminal on the N side. Figure 1 The distance A5 in represents the distance between the positive power supply terminal VB of the U phase and the floating power supply terminal VS of the V phase. Figure 1 The distance A6 in represents the distance between the positive power supply terminal VB of the V phase and the floating power supply terminal VS of the W phase. Figure 1 The distance A7 in FIG. 1 represents the distance between the positive power supply terminal VB and the UP terminal of the W phase.

[0058] On the other hand, high voltage is not applied to the control terminals arranged in the B1 area, namely the UP terminal, VP terminal, WP terminal, VCC terminal, UN terminal, VN terminal, WN terminal, and X terminal. Therefore, a certain degree of spatial distance and creepage distance are not required between these terminals. Figure 1 The X terminal in the figure is a terminal used for protection functions, etc.

[0059] Similarly, no high voltage is applied to the NV terminal and the NW terminal, which are control terminals arranged in the B2 region. Therefore, a certain spatial distance and creepage distance are not required between these terminals.

[0060] Figure 3 is with Figure 1 and Figure 2 The circuit diagram corresponding to the illustrated structure. Figure 3 As illustrated, the semiconductor device has a bootstrap diode 12, a bootstrap diode 14, a bootstrap diode 16, a high-voltage IC 18, a low-voltage IC 20, a power chip 22, a power chip 24, a power chip 26, a power chip 28, a power chip 30, a power chip 32, a freewheeling diode 34, a freewheeling diode 36, a freewheeling diode 38, a freewheeling diode 40, a freewheeling diode 42 and a freewheeling diode 44.

[0061] Figure 4 yes Figure 3 The structure shown is mainly related to the high voltage IC 18 and the low voltage IC 20. Figure 4 As illustrated, the high-voltage IC 18 and the low-voltage IC 20 are connected to a common VCC voltage, and a bootstrap diode is connected between the VCC terminal and the VB terminal of the high-voltage IC 18 .

[0062] <Regarding the method for manufacturing a semiconductor device>

[0063] Figure 5 FIG. 1 is a flowchart showing an example of a manufacturing process of a semiconductor device according to the present embodiment, particularly a manufacturing process related to lead forming. Figure 5 As illustrated, in the manufacturing process of the semiconductor device according to the present embodiment, first, in the power chip bonding process, the power chips 22, 24, 26, 28, 30, and 32 are bonded to corresponding portions of the lead frame ( Figure 5 Step ST01 in the process).

[0064] Next, in the diode chip bonding process, the bootstrap diode 12, the bootstrap diode 14, the bootstrap diode 16, the freewheeling diode 34, the freewheeling diode 36, the freewheeling diode 38, the freewheeling diode 40, the freewheeling diode 42, and the freewheeling diode 44 are bonded to corresponding portions of the lead frame ( Figure 5 Step ST02 in the process).

[0065] Next, in the IC chip bonding process, the high voltage IC 18 and the low voltage IC 20 are bonded to the corresponding parts of the lead frame ( Figure 5 Step ST03 in the process).

[0066] Next, in the wire bonding process, wires 200 are used to wire bond the power chips, diodes, and ICs bonded to corresponding locations on the lead frame. Figure 5 Step ST04 in the process).

[0067] Next, in the transfer molding process, the above structure in the wire-bonded state is partially encapsulated using a molding resin 300 ( Figure 5 Step ST05 in the process).

[0068] Next, in the connecting rod cutting step, the connecting rod portion ( Figure 5 Next, in the lead cutting process, the unnecessary portion of the lead terminal is cut off appropriately ( Figure 5 In the lead forming process, the lead terminal is bent and processed as appropriate ( Figure 5 Step ST08 in the process).

[0069] Figure 6 It means it is completed Figure 5 A top view of an example of the structure of a semiconductor device at a point in time from the power chip die bonding step to the transfer molding step.

[0070] For distances A1 to A7, which require a certain degree of spatial distance and creepage distance, slits 50, 52, 54, 56, 58, 60, and 62 are provided in the connecting rod portion, which corresponds to the region between the portions of lead 201 that become terminals when connected to the semiconductor element. Specifically, slit 56 is provided at distance A1, slit 58 is provided at distance A2, slit 60 is provided at distance A3, slit 62 is provided at distance A4, slit 50 is provided at distance A5, slit 52 is provided at distance A6, and slit 54 is provided at distance A7.

[0071] On the other hand, the slit is not provided between portions serving as terminals arranged in the B1 region and the B2 region, to which high voltage is not applied and to which a certain spatial distance and creeping distance are not required.

[0072] Figure 7 It means in Figure 5 A plan view of an example of the structure of a semiconductor device at a time point after the transfer molding step, the tie bar cutting step, and the lead cutting step are completed.

[0073] like Figure 7 As illustrated, lead terminals 202A, 202B, and 202C connected to respective lead frames extend from mold resin 300 .

[0074] Figure 7 The lead terminals extending from the molded resin 300 to the right correspond to the following from the top: Figure 1 The P-phase output terminal on the P side of lead frame 118, the U-phase output terminal on the P side of lead frame 120, the V-phase output terminal on the P side of lead frame 122, the W-phase output terminal on the P side of lead frame 124, the NU terminal, the NV terminal and the NW terminal.

[0075] in addition, Figure 7 The lead terminals extending from the molded resin 300 to the left correspond to the following from the top: Figure 1 The floating power terminal VS(U), the positive power terminal VB(U) of lead frame 112, the floating power terminal VS(V), the positive power terminal VB(V) of lead frame 114, the floating power terminal VS(W), the positive power terminal VB(W) of lead frame 116, the UP terminal, the VP terminal, the WP terminal, the VCC terminal, the UN terminal, the VN terminal, the WN terminal and three X terminals.

[0076] Here, lead terminal 202A is a lead terminal without any slits formed on the side of the portion where the terminal is formed. Furthermore, lead terminal 202B is a lead terminal with a slit formed on one side of the portion where the terminal is formed. Furthermore, lead terminal 202C is a lead terminal with slits formed on both sides of the portion where the terminal is formed.

[0077] The lead terminals 202B and 202C have their thicknesses tapered at the sides where the slits are formed. In other words, the slits at the corresponding positions are formed to narrow the regions where the lead terminals are formed.

[0078] Figure 8 It specifically indicates Figure 7 FIG. 202 is a diagram showing an example of the structure of the lead terminal 202C. Figure 8 As shown, lead terminal 202C has a processed portion 203 that undergoes bending and other processing in subsequent steps. Processed portion 203 is formed thinner than the rest of lead terminal 202C to facilitate processing. The thinner thickness of processed portion 203 stabilizes the bending position during processing of lead terminal 202C in the subsequent lead forming step. This reduces dimensional fluctuations in lead terminal 202C.

[0079] On the other hand, Figure 7 In the example of lead terminal 202A, the thickness of the portion of lead terminal 202C corresponding to processed portion 203 is the same as the thickness of the other portions of lead terminal 202A. This structure improves the electrical stability of the lead frame and also enhances processability in the steps up to the transfer molding step. Consequently, the incidence of defective products during the manufacturing process can be reduced.

[0080] Figure 9 It means in Figure 5 This is a top view of an example of the structure of a semiconductor device at a point in time after the lead cutting step in FIG. Figure 10 yes Figure 9 Cross-sectional view of the illustrated structure.

[0081] like Figure 9 and Figure 10 As shown in the example, the lead terminals 202A, 202B, and 202C connected to the respective lead frames are formed to extend toward the lead frame. Figure 9 The near side direction of the paper ( Figure 10 Bend the paper surface).

[0082] Figure 11 It specifically indicates Figure 9 and Figure 10FIG. 202 is a diagram showing an example of the structure of the lead terminal 202C. Figure 11 As shown in the example, lead terminal 202C has processed portion 203 that is formed thinner than the other portions. Therefore, even if processed portion 203 is bent toward the near end of the drawing during lead forming and expands (becomes a bent portion), this portion (the bent portion) will not be thicker than the other portions of lead terminal 202C.

[0083] On the other hand, lead terminal 202A does not have processed portion 203 like lead terminal 202C. Therefore, after being bent toward the near end of the drawing sheet by lead forming and expanding, the bent portion (bent portion) becomes thicker than the rest of lead terminal 202A.

[0084] Furthermore, the lead terminal 202B does not become thicker in the portion bent and expanded at the side where the slit is formed, but does still become thicker in the portion bent and expanded at the side where the slit is not formed.

[0085] Therefore, in the portion where no slit is formed between the lead terminals (for example, between the lead terminals 202A), the portion that expands due to the bending of the lead terminal, i.e., the bent portion, protrudes toward the direction between the lead terminals, thereby shortening the spatial distance and the creepage distance between the lead terminals. Figure 11 In the example, the distance D between the lead terminal 202A and the lead terminal 202B corresponds to the distance between the bent and expanded portions, and is shorter than the distance C when the thickness of each lead terminal does not change.

[0086] On the other hand, in the portion where the slits are formed between the lead terminals, the portion that expands due to the bending of the lead terminals, i.e., the bent portion, does not protrude in the direction between the lead terminals, and therefore the spatial distance and the creepage distance between the lead terminals do not shorten. Figure 11 In the example, the distance E between lead terminal 202B and lead terminal 202C corresponds to the distance between the end surfaces of the terminals before bending, and is the same as the distance C when the thickness of each lead terminal is unchanged. Furthermore, the bent portion of the lead terminal may be formed thinner than the other portion of the lead terminal.

[0087] As described above, by performing the tie-bar cutting and lead-cutting steps with slits formed between the lead terminals where high voltage is applied, the spatial distance and creepage distance between the lead terminals are not shortened even after the lead-forming step, even in the areas where the slits are formed. This allows for a reduction in the size of the semiconductor device. Furthermore, by performing the tie-bar cutting and lead-cutting steps with no slits formed between the lead terminals where high voltage is not applied, the lead terminal thickness is maintained, improving the electrical stability and mechanical strength of the leadframe.

[0088] <Second embodiment>

[0089] In the following description, the same components as those described in the above embodiments are denoted by the same reference numerals and their detailed descriptions are omitted as appropriate.

[0090] <Regarding the method for manufacturing a semiconductor device>

[0091] Figure 12 This is a plan view showing an example of the structure of the semiconductor device at a point in time after the power chip die bonding step to the transfer molding step according to the present embodiment are completed.

[0092] For those that require a certain degree of spatial distance and surface distance Figure 1 Slits 50A, 52A, 54A, 56A, 58A, 60A, and 62A are provided in the connecting rod portion between the portions of lead 201A that become terminals, respectively, from distance A1 to distance A7. Specifically, slit 56A is provided at a location at distance A1, slit 58A is provided at a location at distance A2, slit 60A is provided at a location at distance A3, slit 62A is provided at a location at distance A4, slit 50A is provided at a location at distance A5, slit 52A is provided at a location at distance A6, and slit 54A is provided at a location at distance A7.

[0093] On the other hand, when high voltage is not applied and a certain degree of spatial distance and creepage distance are not required, the Figure 1 The above-mentioned slit is not provided between the portions serving as terminals in the B1 region and the B2 region.

[0094] Figure 13 Yes Figure 12 FIG. 6 is a top view of an example of the shape of the slit 60A shown in FIG. Figure 13 As shown in the example, the shape of the surface of the slit 60A facing the lead terminal is a convex shape (at Figure 13In addition, the shapes of the other slits may be the same.

[0095] According to the structure of this embodiment, the slit has a convex shape on the surface facing the lead terminal, which stabilizes the bending position when the lead terminal is processed in the subsequent lead forming step, thereby suppressing dimensional fluctuations in the lead terminal.

[0096] <Third embodiment>

[0097] In the following description, the same components as those described in the above embodiments are denoted by the same reference numerals and their detailed descriptions are omitted as appropriate.

[0098] <Regarding the method for manufacturing a semiconductor device>

[0099] Figure 14 This is a plan view showing an example of the structure of the semiconductor device at a point in time after the power chip die bonding step to the transfer molding step according to the present embodiment are completed.

[0100] For those that require a certain degree of spatial distance and surface distance Figure 1 Slits 50B, 52B, 54B, 56B, 58B, 60B, and 62B are provided in the connecting rod portion between the portions of lead 201B that become terminals, respectively, from distance A1 to distance A7. Specifically, slit 56B is provided at the portion where distance A1 is set, slit 58B is provided at the portion where distance A2 is set, slit 60B is provided at the portion where distance A3 is set, slit 62B is provided at the portion where distance A4 is set, slit 50B is provided at the portion where distance A5 is set, slit 52B is provided at the portion where distance A6 is set, and slit 54B is provided at the portion where distance A7 is set.

[0101] The slits 50B, 52B, 54B, 56B, 58B, 60B, and 62B are a pair of slits formed only in the vicinity of the lead terminals.

[0102] On the other hand, when high voltage is not applied and a certain degree of spatial distance and creepage distance are not required, the Figure 1 The above-mentioned slit is not provided between the portions serving as terminals in the B1 region and the B2 region.

[0103] According to the structure of this embodiment, by forming the slits only near the lead terminals, the bending positions of the lead terminals during subsequent lead forming processes are stabilized. This reduces dimensional fluctuations in the lead terminals. Furthermore, since the area where the slits are formed is narrowed, the mechanical strength of the leadframe is enhanced.

[0104] <Fourth embodiment>

[0105] In the following description, the same components as those described in the above embodiments are denoted by the same reference numerals and their detailed descriptions are omitted as appropriate.

[0106] <Regarding the method for manufacturing a semiconductor device>

[0107] Figure 15 This is a plan view showing an example of the structure of the semiconductor device at a point in time after the power chip die bonding step to the transfer molding step according to the present embodiment are completed.

[0108] For those that require a certain degree of spatial distance and surface distance Figure 1 Slits 50C, 52C, 54C, 56C, 58C, 60C, and 62C are provided in the connecting rod portion between the portions of lead 201C that become terminals, respectively, from distance A1 to distance A7. Specifically, slit 56C is provided at the portion where distance A1 is set, slit 58C is provided at the portion where distance A2 is set, slit 60C is provided at the portion where distance A3 is set, slit 62C is provided at the portion where distance A4 is set, slit 50C is provided at the portion where distance A5 is set, slit 52C is provided at the portion where distance A6 is set, and slit 54C is provided at the portion where distance A7 is set.

[0109] The slits 50C, 52C, 54C, 56C, 58C, 60C, and 62C are a pair of slits formed only in the vicinity of the lead terminals.

[0110] On the other hand, when high voltage is not applied and a certain degree of spatial distance and creepage distance are not required, the Figure 1 The above-mentioned slit is not provided between the portions serving as terminals in the B1 region and the B2 region.

[0111] Figure 16 Yes Figure 15 FIG. 6 is a top view of an example of the shape of the slit 60C shown in FIG. Figure 16 As shown in the example, the shape of the surface of the slit 60C facing the lead terminal is a convex shape (at Figure 16In addition, the shapes of the other slits may be the same.

[0112] According to the structure of this embodiment, by forming the slits only near the lead terminals, the bending positions of the lead terminals during subsequent lead forming processes are stabilized. This reduces dimensional fluctuations in the lead terminals. Furthermore, since the area where the slits are formed is narrowed, the mechanical strength of the leadframe is enhanced.

[0113] Furthermore, the convex shape of the surface of the slit facing the lead terminal stabilizes the bending position when the lead terminal is processed in the subsequent lead forming step, thereby suppressing dimensional fluctuations in the lead terminal.

[0114] <Fifth embodiment>

[0115] In the following description, the same components as those described in the above embodiments are denoted by the same reference numerals and their detailed descriptions are omitted as appropriate.

[0116] <Regarding the method for manufacturing a semiconductor device>

[0117] Figure 17 1 is a top view showing an example of the structure of a semiconductor device at a point in time after the power chip die bonding step to the transfer molding step according to this embodiment is completed. Figure 18 Yes Figure 17 A top view of an example of the shape of the cutting member 400 is shown.

[0118] like Figure 17 and Figure 18 As shown in the example, for distances A1 to A7 requiring a certain degree of space distance and creeping distance, the end surface 401 of the cutting member 400 for cutting the tie bar of the lead 201D is convex (at Figure 18 In addition, the shapes of the end faces 401 at other parts of the cutting member 400 may also be the same.

[0119] Figure 19 It means in Figure 5 A plan view of an example of the structure of a semiconductor device at a time point after the transfer molding step, the tie bar cutting step, and the lead cutting step are completed.

[0120] like Figure 19 As illustrated, lead terminal 202D, lead terminal 202E, and lead terminal 202F connected to the respective lead frames extend from mold resin 300 .

[0121] Here, lead terminal 202D is a lead terminal in which the end surface of cut member 400, used on both sides of the portion where the terminal is formed, is not convex. Furthermore, lead terminal 202E is a lead terminal in which the end surface 401 of cut member 400, used on one side of the portion where the terminal is formed, is convex. Furthermore, lead terminal 202F is a lead terminal in which the end surface 401 of cut member 400, used on both sides of the portion where the terminal is formed, is convex.

[0122] Lead terminals 202E and 202F are tapered at the convex side portions of the cut member 400. That is, the cut member 400 at the corresponding end surface 401 is formed so that the region where the lead terminals are formed is narrowed.

[0123] According to the structure of this embodiment, the shape of the conventional lead frame is not changed. Only the shape of the cutting member 400 used in the tie bar cutting step is changed. As a result, even after the lead forming step, the spatial distance and creepage distance between the lead terminals at the portion corresponding to the end face 401 are not shortened. Furthermore, the lead terminal thickness is maintained between lead terminals not subjected to high voltage, thereby improving the electrical stability and mechanical strength of the lead frame.

[0124] <Effects of the above-described embodiment>

[0125] Next, examples of the effects produced by the above-described embodiments are shown. In addition, in the following description, the effects are described based on the specific structures illustrated in the above-described embodiments, but can also be replaced with other specific structures illustrated in this specification within the scope of producing the same effects.

[0126] Furthermore, this substitution may be performed across multiple embodiments. In other words, it is also possible to combine various structures illustrated in different embodiments to produce the same effect.

[0127] According to the embodiment described above, in the method for manufacturing a semiconductor device, at least one semiconductor element is provided. Here, the semiconductor element corresponds to, for example, an IC pair of a high-voltage IC 18 and a low-voltage IC 20. Furthermore, a plurality of first terminals and at least one second terminal are connected to the semiconductor element, and the second terminal is a control terminal to which a voltage lower than that of the first terminal is applied. Here, the first terminal corresponds to, for example, any one of the lead terminal 202B and the lead terminal 202C, etc. (hereinafter, for the sake of convenience, the first terminal is sometimes described as corresponding to any one of them). In addition, the second terminal corresponds to, for example, the lead terminal 202A, etc. Furthermore, a first bent portion is formed at the first terminal. Here, the first bent portion corresponds to, for example, the portion after the processing portion 203 is bent and expanded, etc. Furthermore, with respect to adjacent plurality of first terminals, on the surfaces facing each other (for example, on Figure 11 In the figure, the lead terminal 202B and the lead terminal 202C face each other at a distance E, and the first bent portion after the processed portion 203 is bent and expanded does not protrude.

[0128] According to such a structure, the bent portion does not protrude on the opposing surfaces between the terminals to which a high voltage is applied, so that, for example, Figure 11 As shown in FIG. 1 , the spatial and creepage distances between the lead terminals are not shortened. Consequently, the spatial and creepage distances between the terminals are maintained, while also preventing the semiconductor device from becoming larger. Furthermore, since the processed portion 203 is thinner than the rest of the lead terminal, the bent position of the lead terminal during subsequent lead forming steps is stabilized. Consequently, dimensional fluctuations in the lead terminal can be suppressed.

[0129] Furthermore, even when other configurations exemplified in this specification are appropriately added to the above configuration, that is, even when other configurations not mentioned as the above configurations in this specification are appropriately added, the same effects can be produced.

[0130] Furthermore, the order in which each process is performed can be changed unless otherwise specified.

[0131] In addition, according to the embodiment described above, a plurality of lead terminals 202A are connected to the semiconductor element. Furthermore, a second bent portion is formed in each lead terminal 202A. Furthermore, for adjacent plurality of lead terminals 202A, on the surfaces facing each other (for example, on Figure 11 The second bent portion is projected (in the surface where lead terminal 202B and lead terminal 202A face each other, defining a distance D). This structure maintains the thickness of the lead terminals (control terminals) not applied with high voltage, thereby improving the electrical stability and mechanical strength of the lead frame.

[0132] In addition, according to the embodiment described above, connecting a plurality of first terminals and lead terminals 202A to a semiconductor element means connecting leads 201 (or, leads 201A, leads 201B, leads 201C, leads 201D) to the semiconductor element, and cutting the region between the portions of the leads 201 that become the first terminals or lead terminals 202A, i.e., the connecting rod portion. Furthermore, a slit 56 or the like is formed in the connecting rod portion corresponding to the region between the plurality of adjacent first terminals. According to such a structure, by performing the connecting rod cutting process and the lead cutting process in a state where a slit is formed between the lead terminals to which a high voltage is applied, even after the lead forming process, at the portion where the slit is formed, for example, Figure 11 As shown in Figure 1, the spatial distance and creepage distance between the lead terminals do not decrease. Consequently, the size of the semiconductor device can be reduced. Furthermore, since the amount of cutting of the connecting rod is reduced in the areas where the slits are formed, the load on the cutting member (die) is reduced. Consequently, die wear can be reduced.

[0133] Furthermore, according to the embodiment described above, the surface of the slit 56A, etc., facing the adjacent plurality of first terminals is convex. This configuration stabilizes the bending position during the subsequent lead forming process, thereby suppressing dimensional fluctuations in the lead terminals.

[0134] Furthermore, according to the above-described embodiment, the slits 56B (or slits 56C) are formed only near the adjacent plurality of first terminals. With such a configuration, the region where the slits are formed is narrowed, thereby improving the mechanical strength of the lead frame.

[0135] Furthermore, according to the embodiment described above, connecting multiple first terminals and lead terminals 202A to a semiconductor element involves cutting the connecting rod portion, which is the region between the portions of lead 201D that will become the first terminals or lead terminals 202A, toward the semiconductor element. Furthermore, the cutting member 400 used to cut the connecting rod portion has a convex end surface 401 corresponding to the region between the adjacent multiple first terminals. This configuration does not modify the shape of the existing lead frame, but only the shape of the cutting member 400 used in the connecting rod cutting step. This allows the spatial distance and creepage distance between the lead terminals to remain unchanged at the portion corresponding to the end surface 401, even after the lead forming step.

[0136] According to the embodiment described above, a semiconductor device includes at least one semiconductor element and multiple terminals connected to the semiconductor element. The multiple terminals include multiple first terminals and at least one lead terminal 202A. The multiple first terminals have first bent portions, and the lead terminal 202A is a control terminal to which a lower voltage is applied than the first terminal. Furthermore, adjacent first terminals do not have protruding first bent portions on their opposing surfaces.

[0137] According to such a structure, the bent portion does not protrude on the opposing surfaces between the terminals to which a high voltage is applied, so that, for example, Figure 11 As shown in FIG. 1 , the spatial and creepage distances between the lead terminals are not shortened. Consequently, the spatial and creepage distances between the terminals are maintained, while also preventing the semiconductor device from becoming larger. Furthermore, since the processed portion 203 is thinner than the rest of the lead terminal, the bent position of the lead terminal during subsequent lead forming steps is stabilized. Consequently, dimensional fluctuations in the lead terminal can be suppressed.

[0138] Furthermore, even when other configurations exemplified in this specification are appropriately added to the above configuration, that is, even when other configurations not mentioned as the above configuration in this specification are appropriately added, the same effects can be produced.

[0139] Furthermore, according to the embodiment described above, the semiconductor device includes a plurality of lead terminals 202A. Furthermore, each lead terminal 202A has a second bent portion. Furthermore, the second bent portions protrude from the opposing surfaces of adjacent lead terminals 202A. This structure maintains the thickness of lead terminals (control terminals) not subjected to high voltage, thereby improving the electrical stability and mechanical strength of the lead frame.

[0140] In addition, according to the embodiment described above, a wide bandgap semiconductor is used as the semiconductor element. The switching element or diode element using a wide bandgap semiconductor has a high voltage resistance and a high allowable current density. Therefore, by using a wide bandgap semiconductor, the switching element or diode element can be miniaturized. In addition, by using these miniaturized switching elements or diode elements, the semiconductor device incorporating these elements can be miniaturized. In addition, since the switching element or diode element using a wide bandgap semiconductor also has high heat resistance, the cooling fins of the radiator can be miniaturized. Furthermore, since the switching element or diode element using a wide bandgap semiconductor has low power loss, the switching element or diode element can be made more efficient, and thus the semiconductor device can be made more efficient. In addition, it is preferred that both the switching element and the diode element use a wide bandgap semiconductor, but a wide bandgap semiconductor may be used for either element.

[0141] <Regarding Modifications of the Above-Described Embodiments>

[0142] In the above-described embodiments, although the materials, dimensions, shapes, relative arrangements, or implementation conditions of various components are sometimes described, these are merely illustrative in all respects and are not restrictive.

[0143] Therefore, within the technical scope disclosed in this specification, numerous modifications and equivalents not shown are conceivable, including, for example, modifications, additions, or omissions of at least one structural element, and extraction of at least one structural element from at least one embodiment and combination with structural elements from other embodiments.

[0144] In the above-described embodiments, when a material name is not particularly specified, the material includes a material containing other additives, such as an alloy, as long as no contradiction occurs.

[0145] Furthermore, in the above-described embodiments, a component described as including “one” may also include “one or more” unless there is any contradiction.

[0146] Furthermore, each structural element in the embodiments described above is a conceptual unit, and within the technical scope disclosed in this specification, it includes a case where one structural element is composed of multiple structures, a case where one structural element corresponds to a part of a certain structure, and a case where multiple structural elements are contained in one structure.

[0147] Furthermore, the respective components in the above-described embodiments include structures having other structures or shapes as long as they exhibit the same functions.

[0148] In addition, the descriptions in this specification are referenced for all purposes related to the present technology and are not admitted to be prior art.

[0149] Description of the label

[0150] 12, 14, 16 bootstrap diodes, 18 high-voltage ICs, 20 low-voltage ICs, 22, 24, 26, 28, 30, 32 power chips, 34, 36, 38, 40, 42, 44 freewheeling diodes, 50, 50A, 50B, 50C, 52, 52A, 52B, 52C, 54, 54A, 54B, 54C, 56, 56A, 56B, 56C, 58, 58A, 58B, 58C, 60, 60 A, 60B, 60C, 62, 62A, 62B, 62C slits, 112, 114, 116, 118, 120, 122, 124 lead frames, 200 wires, 201, 201A, 201B, 201C, 201D leads, 202A, 202B, 202C, 202D, 202E, 202F lead terminals, 203 processing part, 300 molding resin, 400 cutting parts, 401 end face.

Claims

1. A method for manufacturing a semiconductor device, wherein: At least one semiconductor element is provided, A plurality of first terminals and at least one second terminal are connected to the semiconductor element, the second terminal being a control terminal to which a voltage lower than that of the first terminal is applied, A first bent portion is formed on the first terminal, Regarding the adjacent plurality of first terminals, the first bent portions do not protrude on the surfaces facing each other. The plurality of second terminals are connected to the semiconductor element, A second bent portion is formed on each of the second terminals, Regarding the adjacent plurality of second terminals, the second bent portions protrude on the surfaces facing each other. At least one of the second terminals is configured such that the second bent portion does not protrude on a surface facing the first terminal, and the second bent portion protrudes on a surface facing the second terminal.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: Connecting the plurality of first terminals and the second terminals to the semiconductor element means connecting a lead to the semiconductor element and cutting a connecting rod portion, which is a region between portions of the lead that become the first terminals or the second terminals. A slit is formed in the connecting rod portion corresponding to a region between the adjacent first terminals.

3. The method for manufacturing a semiconductor device according to claim 2, wherein: A surface of the slit facing the adjacent first terminals is convex.

4. The method for manufacturing a semiconductor device according to claim 2, wherein: The slits are formed only in the vicinity of the adjacent first terminals.

5. The method for manufacturing a semiconductor device according to claim 3, wherein: The slits are formed only in the vicinity of the adjacent first terminals.

6. The method for manufacturing a semiconductor device according to any one of claims 1 to 5, wherein: Connecting the plurality of first terminals and the second terminals to the semiconductor element means connecting a lead to the semiconductor element and cutting a connecting rod portion, which is a region between portions of the lead that become the first terminals or the second terminals. The cutting member for cutting the connecting rod portion has a convex end surface corresponding to a region between the adjacent first terminals.

7. A semiconductor device comprising: At least one semiconductor device; and a plurality of terminals connected to the semiconductor element, The plurality of terminals have: a plurality of first terminals having a first bending portion; and at least one second terminal, which is a control terminal to which a lower voltage than that of the first terminal is applied, Regarding the adjacent plurality of first terminals, the first bent portions do not protrude on the surfaces facing each other. The semiconductor device has a plurality of second terminals. Each of the second terminals has a second bent portion, Regarding the adjacent plurality of second terminals, the second bent portions protrude on the surfaces facing each other. At least one of the second terminals is configured such that the second bent portion does not protrude on a surface facing the first terminal, and the second bent portion protrudes on a surface facing the second terminal.

8. The semiconductor device according to claim 7, wherein The semiconductor element uses a wide-bandgap semiconductor.

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