A laser annealing apparatus for improving a CMOS wafer shallow junction process

Abstract

The application relates to a laser annealing device for improving a CMOS wafer shallow junction process, which comprises a laser, a beam pointing adjustment system, a beam expander, a power adjustment system, a knife edge, a third beam combiner, a beam quality analyzer, an integrating mirror, a heating disc, a motion platform, a computer, a three-color temperature thermal emission detector and a laser range finder. The power adjustment system is composed of a lambda / 2 glass and a polarizer arranged on an optical path. The laser emits light with fixed power, the power adjustment system simultaneously controls the output power and the polarization, and avoids problems such as beam quality deterioration and power stability reduction caused by laser power change; the beam quality analyzer, the three-color temperature thermal emission detector and the power adjustment system jointly form an annealing power negative feedback system, and the annealing power size and stability are controlled in real time according to the annealing area temperature feedback result.

Description

Technical Field

[0001] This invention relates to a laser annealing device, specifically a laser annealing device for improving the shallow junction process of CMOS wafers, belonging to the field of laser annealing technology. Background Technology

[0002] As gate channel dimensions shrink, the short-channel effect becomes a major factor limiting the size reduction of CMOS devices. To suppress the short-channel effect, improvements are needed in device structure, hence the widespread application of shallow junction technology in advanced CMOS integrated circuit manufacturing processes. The formation of shallow junctions places higher demands on implantation and annealing processes; current integrated circuit manufacturing processes can achieve nanometer-level implantation depths. The implantation process damages the silicon wafer surface, and implantation can only emit impurity elements to specific locations on the silicon wafer. The electro-activation between impurity elements and silicon atoms, and the repair of silicon lattice damage, require subsequent annealing processes. During high-temperature annealing, polycrystalline and even amorphous silicon gain sufficient energy at high temperatures to repair lattice damage, and impurity elements form chemical bonds with surrounding silicon atoms to achieve electro-activation. Simultaneously, controlling the annealing thermal budget reduces the depth extension and lateral diffusion of implanted elements, thereby reducing the junction depth of the PN junction and avoiding the short-channel effect. Therefore, the annealing process determines the junction depth and lateral dimensions of the source-drain PN junction and the lightly doped drain PN junction.

[0003] The high annealing temperature of laser annealing for source and drain electrodes allows for the instantaneous activation of impurity elements and rapid repair of silicon crystal damage within an extremely short time. Laser annealing involves residence time in the high-temperature region on the nanosecond scale, effectively suppressing the diffusion of impurity elements. Therefore, in advanced technology nodes at 40nm and below, laser annealing technology, with its precise and controllable optical energy density, high impurity activation rate, selective melting of specific regions, and lack of thermal damage to the substrate, has become the optimal choice for source and drain electrode annealing.

[0004] The power stability of existing laser equipment is generally optimized at a fixed output power. For example, a 3KW laser can only be optimized at fixed points such as 1000W and 1500W to achieve a power stability of ±1%. However, in actual use, the annealing power needs to be adjusted in real time according to the annealing requirements, and it is impossible to maintain power stability in real time during the annealing process. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a laser annealing device for improving the shallow junction process of CMOS wafers, which can ensure that the annealing power remains stable during the annealing process.

[0006] To solve the above problems, the technical solution adopted by the present invention is as follows:

[0007] A laser annealing apparatus for improving shallow junction processes in CMOS wafers includes a laser, a beam pointing adjustment system, a beam expander, a power adjustment system, a knife edge, a third beam combiner, a beam quality analyzer, an integrating mirror, a wafer, a heating plate, a motion platform, a computer, a three-color thermal emission detector, and a laser rangefinder. The wafer is placed on the heating plate, and the heating plate is placed on the motion platform. The laser, beam pointing adjustment system, power adjustment system, beam quality analyzer, motion platform, laser rangefinder, and three-color thermal emission detector are all connected to the computer.

[0008] The laser beam emitted by the laser is incident on a beam expander after passing through a beam pointing adjustment system. Then, the output power and polarization angle of the beam are controlled by a power adjustment system. Stray light at the edge of the beam spot is removed by a knife edge. Next, a small portion of the beam is reflected and most of the beam is transmitted by a third beam combiner. The small portion of the beam is reflected into a beam quality analyzer for beam detection. Most of the transmitted beam is reflected by an integrating mirror and converted into a line spot that converges onto the wafer surface for annealing. The motion platform drives the heating plate to move to achieve the annealing trajectory.

[0009] Furthermore, the beam pointing adjustment system includes two parallel beam combiners, each equipped with a two-dimensional motorized adjustment frame, and a focusing lens and a position detector are sequentially arranged on the transmitted light path of each beam combiner.

[0010] Furthermore, the reflectivity of the beam combiner is 99%, the transmittance is 1%, the pitch and tilt adjustment angles of the two-dimensional electric adjustable frame are ≥±2°, and the response time of the position detector is <300ms and the detection accuracy is better than 0.5mard.

[0011] Furthermore, the power adjustment system consists of a λ / 2 glass plate and a polarizer positioned along the optical path. The laser outputs light at a fixed power, and the polarization angle of the beam is changed by adjusting the angle of the λ / 2 glass plate. Combined with the polarizer, both the output power and polarization are controlled simultaneously.

[0012] Furthermore, the integrating mirror is an off-axis parabolic integrating mirror with a beam adjustment angle of 0–90°, a line spot energy distribution uniformity of ≥95%, and a line spot minor axis size of ≥50μm.

[0013] Furthermore, the heating temperature range of the heating plate is 0 to 600°C, and the heating temperature uniformity is better than ±20°C.

[0014] Furthermore, the tri-color thermal emission detector monitors the temperature of the wafer annealing area in real time, and together with the power adjustment system and the beam quality analyzer, forms an annealing power negative feedback system. Based on the feedback results of the annealing area temperature, the magnitude and stability of the annealing power are controlled in real time.

[0015] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0016] 1. This invention uses a laser with a fixed output power. The addition of a λ / 2 glass plate and a polarizer not only controls the output power and polarization simultaneously, but also avoids problems such as beam quality deterioration and power stability reduction caused by changes in laser power. A beam quality analyzer is used to detect the energy distribution and power stability of the beam. A three-color thermal emission detector monitors the temperature of the wafer annealing area in real time. Together with the power adjustment system and the beam quality analyzer, they form an annealing power negative feedback system. Based on the feedback results of the annealing area temperature, the magnitude and stability of the annealing power are controlled in real time.

[0017] 2. This invention uses an integrating mirror to shape the beam, which has a simple structure and good homogenization effect. At the same time, by changing the integrating structure, the beam exit angle can be controlled, avoiding the patterning effect during annealing.

[0018] 3. This invention utilizes a heating plate to control the preheating temperature of the wafer, thereby changing the absorption coefficient of the wafer to the laser beam. By controlling the laser power and dwell time, precise control of the annealing depth can be achieved. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the laser annealing equipment used in the present invention to improve the shallow junction process of CMOS wafers.

[0020] Figure 2 This is a schematic diagram of the beam pointing adjustment system involved in the present invention.

[0021] Figure 3 This is a distribution diagram of the beam, detection, and motion platform in the wafer annealing area involved in this invention. Detailed Implementation

[0022] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The objectives, technical solutions, and advantages of the present invention will become clearer from the following description. It should be noted that the described embodiments are preferred embodiments of the present invention, but not all embodiments.

[0023] Combination Figure 1 and Figure 3 As shown, a laser annealing device for improving the shallow junction process of CMOS wafers includes: a laser 1, a beam pointing adjustment system 2, a beam expander 3, a power adjustment system 4, a knife edge 5, a third beam combiner 6, a beam quality analyzer 7, an integrating mirror 8, a wafer 9, a heating plate 10, a motion platform 11, a computer 12, a laser rangefinder 13, and a three-color thermal emission detector 14.

[0024] The tri-color thermal emission detector 14 and the laser rangefinder 13 are located above the wafer 9. The wafer 9 is placed on the heating plate 10, and the heating plate 10 is placed on the motion platform 11. The laser 1, the beam pointing adjustment system 2, the power adjustment system 4, the beam quality analyzer 7, the motion platform 11, the laser rangefinder 13, and the tri-color thermal emission detector 14 are respectively connected to the computer 12.

[0025] Preferably, the laser emits light with a wavelength of 355nm to 10640nm, a pulse frequency of 1 to 10kHz, a beam quality factor of ≤1.1, a power stability of ≤2%, and is linearly polarized.

[0026] As another preferred embodiment, the laser 1 is a Coherent Rofin DC30 carbon dioxide laser with an emission wavelength of 10.64 μm, a pulse frequency of 1–5 kHz, a beam quality factor ≤1.05, a power stability ≤1%, and a polarization type of linearly polarized light.

[0027] Combination Figure 2 As shown, the beam pointing adjustment system includes two parallel beam combiners, a first beam combiner 21 and a second beam combiner 25, each with a two-dimensional electrically adjustable frame 22 mounted on it. A first focusing lens 23 and a first position detector 24 are sequentially arranged in the transmitted light path of the first beam combiner 21, while a second focusing lens 27 and a second position detector 28 are sequentially arranged in the transmitted light path of the second beam combiner 25. Both beam combiners have a reflectivity of 99% and a transmittance of 1%. The pitch and tilt adjustment angles of the two-dimensional electrically adjustable frames are ≥±2°, and the response time of the two position detectors is 100ms with a detection accuracy better than 0.5 mad.

[0028] The power adjustment system 4 consists of a λ / 2 glass plate 41 and a polarizer 42. The laser 1 outputs light at a fixed power to maintain beam stability. The optical axis of the polarizer 42 is adjusted to the horizontal direction so that the output beam is horizontally polarized linear light. Adjusting the angle of the λ / 2 glass plate 41 changes the output power. The beam quality analyzer 7 is used to detect the energy distribution and power stability of the beam, and is combined with the power adjustment system 4 to achieve negative feedback adjustment of power stability. The integrating mirror 8 is an off-axis parabolic integrating mirror with a linear beam energy distribution uniformity of 96% and a linear beam size of 8mm*0.1mm. After passing through the integrating mirror 8, the beam is incident on the surface of the wafer 9 at a Brewster angle. The heating plate 10 has a heating temperature of 450℃ and a heating temperature uniformity of ±4℃.

[0029] The laser beam emitted by the laser 1 is incident on the beam expander 3 after passing through the beam pointing adjustment system 2. Then, the output power and polarization angle of the beam are controlled by the power adjustment system 4. After passing through the knife edge 5 to remove stray light at the edge of the spot, the beam combiner 6 is used to reflect part of the beam into the beam quality analyzer 7 for beam detection. Most of the transmitted beam is reflected by the integrating mirror 8 and converted into a line spot that converges on the surface of the wafer 9 for annealing. The wafer 9 is placed on the heating plate 10, and the motion platform 11 drives the heating plate 10 to move to realize the annealing trajectory.

[0030] Combination Figure 3 The motion platform 11 is a three-dimensional motion platform. By adjusting the motion speed and trajectory, the annealing dwell time and annealing trajectory are controlled. The three-color thermal emission detector 14 monitors the temperature of the annealing area of ​​the wafer 9 in real time. Together with the power adjustment system 4 and the beam quality analyzer 7, it forms an annealing power negative feedback system. Based on the feedback results of the annealing area temperature, the magnitude and stability of the annealing power are controlled in real time.

[0031] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Obviously, any person skilled in the art can easily conceive of substitutions or variations based on the above embodiments to obtain other embodiments, and these should all be covered within the scope of protection of the present invention.

Claims

1. A laser annealing apparatus for improving shallow junction processes in CMOS wafers, characterized in that: The system includes a laser, a beam pointing adjustment system, a beam expander, a power adjustment system, a knife edge, a third beam combiner, a beam quality analyzer, an integrating mirror, a wafer, a heating plate, a motion platform, a computer, a tri-color thermal emission detector, and a laser rangefinder. The tri-color thermal emission detector and the laser rangefinder are located above the wafer, which is placed on the heating plate. The heating plate is placed on the motion platform. The laser, beam pointing adjustment system, power adjustment system, beam quality analyzer, motion platform, laser rangefinder, and tri-color thermal emission detector are all connected to the computer. The laser beam emitted by the laser is incident on a beam expander after passing through a beam pointing adjustment system. Then, the output power and polarization angle of the beam are controlled by a power adjustment system. Stray light at the edge of the beam spot is removed by a knife edge. Next, a small portion of the beam is reflected and most of the beam is transmitted by a third beam combiner. The small portion of the beam is reflected into a beam quality analyzer for beam detection. Most of the transmitted beam is reflected by an integrating mirror and converted into a line spot that converges onto the wafer surface for annealing. The motion platform drives the heating plate to move to achieve the annealing trajectory.

2. The laser annealing equipment for improving shallow junction processes in CMOS wafers according to claim 1, characterized in that: The beam pointing adjustment system includes two parallel beam combiners, each with a two-dimensional motorized adjustment frame. A focusing lens and a position detector are sequentially arranged on the transmitted light path of each beam combiner.

3. The laser annealing equipment for improving shallow junction processes in CMOS wafers according to claim 2, characterized in that: The two beam combiners have a reflectivity of 99% and a transmittance of 1%. The pitch and tilt adjustment angles of the two-dimensional electric adjustable mirror frame are ≥±2°. The position detector has a response time of <300ms and a detection accuracy better than 0.5mard.

4. The laser annealing equipment for improving shallow junction processes in CMOS wafers according to claim 1, characterized in that: The power adjustment system consists of a λ / 2 glass plate and a polarizer placed on the optical path. The laser outputs light at a fixed power, and the polarization angle of the beam is changed by adjusting the angle of the λ / 2 glass plate. The output power and polarization are controlled simultaneously by combining the polarizer.

5. The laser annealing equipment for improving shallow junction processes in CMOS wafers according to claim 1, characterized in that: The laser emits laser light with a wavelength of 10.64 μm, a laser frequency of 1–5 kHz, a beam quality factor of ≤1.05, a power stability of ≤1%, and is horizontally polarized linearly polarized light.

6. The laser annealing equipment for improving shallow junction processes in CMOS wafers according to claim 1, characterized in that: The integrating mirror is an off-axis parabolic integrating mirror with a beam adjustment angle of 0–90°, a line spot energy distribution uniformity of ≥95%, and a line spot minor axis size of ≥50μm.

7. The laser annealing equipment for improving shallow junction processes in CMOS wafers according to claim 1, characterized in that: The heating temperature range of the heating plate is 0 to 600°C, and the heating temperature uniformity is better than ±20°C.

8. The laser annealing equipment for improving shallow junction processes in CMOS wafers according to claim 1, characterized in that: The tri-color thermal emission detector monitors the temperature of the wafer annealing area in real time. Together with the power adjustment system and the beam quality analyzer, it forms an annealing power negative feedback system. Based on the feedback results of the annealing area temperature, it controls the magnitude and stability of the annealing power in real time.

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