Semiconductor Structure and Method of Forming the Same

Abstract

The method includes: forming a first portion of a spacer layer above a first fin and forming a second portion of the spacer layer above a second fin; performing a first etching process to recess the first portion of the spacer layer relative to the second portion of the spacer layer to form a first spacer on a sidewall of the first fin; subsequently performing a second etching process to recess the second portion of the spacer layer relative to the first spacer to form a second spacer on a sidewall of the second fin, wherein the second spacer is formed to have a height greater than that of the first spacer; and forming a first epitaxial source / drain component and a second epitaxial source / drain component between the first spacer and the second spacer respectively, wherein the first epitaxial source / drain component is larger than the second epitaxial source / drain component. Embodiments of the present application also relate to a semiconductor structure and a method for forming the same.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor structures and methods of forming the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced multiple generations of ICs, each having smaller and more complex circuits than the previous generation. During the development of ICs, the functional density (i.e., the number of interconnected devices per chip area) has generally increased, while the geometric size (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. This scaling-down process generally provides benefits by increasing production efficiency and reducing related costs. This scaling also increases the complexity of processing and manufacturing ICs.

[0003] Multi-gate devices have been introduced in an effort to improve gate control by increasing gate-channel coupling, reducing off-state current, and reducing short-channel effects (SCEs). One such multi-gate device that has been introduced is the fin field-effect transistor (FinFET). The FinFET derives its name from the fin-like structure that extends from the substrate on which it is formed, and the surface of the fin-like structure serves as the channel region of the FET. FinFETs are compatible with traditional complementary metal-oxide-semiconductor (CMOS) processes, and their three-dimensional structure allows them to scale aggressively while maintaining gate control and mitigating SCEs. The performance of FinFETs can be controlled and optimized by various components including source and drain components formed in the fin-like structure (or fins hereinafter). Although current methods of forming source and drain components in FinFETs are generally adequate, they are not entirely satisfactory in all respects. Summary of the Invention

[0004] Some embodiments of the present application provide a method for forming a semiconductor structure, including: providing a substrate having a first device region and a second device region; forming a first semiconductor fin in the first device region and a second semiconductor fin in the second device region; forming a spacer layer over the substrate, wherein a first portion of the spacer layer is formed over the first semiconductor fin and a second portion of the spacer layer is formed over the second semiconductor fin; performing a first etching process to recess the first portion of the spacer layer relative to the second portion of the spacer layer, thereby forming a first fin spacer on sidewalls of the first semiconductor fin; etching the first semiconductor fin to form a first source / drain (S / D) groove between the first fin spacers; forming a first epitaxial source / drain component in the first source / drain groove; after forming the first epitaxial source / drain component, performing a second etching process to recess the second portion of the spacer layer relative to the first portion of the spacer layer, thereby forming a second fin spacer on sidewalls of the second semiconductor fin, wherein the second fin spacer is formed to have a height greater than that of the first fin spacer; etching the second semiconductor fin to form a second source / drain groove between the second fin spacers; and forming a second epitaxial source / drain component in the second source / drain groove, wherein the second epitaxial source / drain component is formed to have a size smaller than that of the first epitaxial source / drain component.

[0005] Some other embodiments of the present application provide a method for forming a semiconductor structure, including: forming a first fin and a second fin protruding from a first region of a semiconductor substrate; forming a third fin protruding from a second region of the semiconductor substrate; forming a first pseudo-gate stack above the first fin and the second fin and forming a second pseudo-gate stack above the third fin; depositing a dielectric layer above the first pseudo-gate stack and the second pseudo-gate stack; forming a first source / drain (S / D) component above the first fin and the second fin, including: performing a first etching process to remove a portion of the dielectric layer located on sidewalls of the first fin and the second fin, thereby forming a first fin sidewall (FSW) spacer having a first height, recessing the first fin and the second fin, and performing a first epitaxial process to grow the first source / drain component, thereby incorporating the recessed first fin and the second fin; forming a second source / drain component above the third fin, including: after forming the first source / drain component, performing a second etching process to remove a portion of the dielectric layer located on sidewalls of the third fin, thereby forming a second fin sidewall spacer having a second height, wherein the second height is greater than the first height, and wherein the first etching process and the second etching process use the same etchant, recessing the third fin, and performing a second epitaxial process to grow the second source / drain component between the second fin sidewall spacers; and replacing the first pseudo-gate stack and the second pseudo-gate stack with a metal gate stack.

[0006] Some further embodiments of the present application provide a semiconductor structure, comprising: a first fin and a second fin extending from a semiconductor substrate; an isolation component disposed above the semiconductor substrate to separate the first fin and the second fin, wherein the first fin and the second fin have a fin height measured from the top surface of the isolation component; a first device located above the first fin, the first device comprising: a first gate stack engaged with a first channel region of the first fin, a first epitaxial source / drain (S / D) component disposed on opposite sides of the first channel region, wherein the first epitaxial source / drain component merges the first fin together, and a first fin spacer disposed on a sidewall of the first epitaxial source / drain component, wherein the first fin spacer has a first height measured from the top surface of the isolation component; a second device located above the second fin, the second device comprising: a second gate stack engaged with a second channel region of the second fin, a second epitaxial source / drain component disposed on opposite sides of the second channel region, and a second fin spacer disposed on a sidewall of the second epitaxial source / drain component, wherein the second fin spacer has a second height greater than the first height measured from the top surface of the isolation component; and an interlayer dielectric (ILD) layer located above the first device and the second device, wherein the interlayer dielectric layer separates the second epitaxial source / drain component. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present invention may be best understood from the following detailed description when read in conjunction with the accompanying drawings. It is to be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are for illustrative purposes only. In fact, for the sake of clear discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0008] Figure 1 、 Figure 2A and Figure 2B are flowcharts illustrating methods of fabricating workpieces according to various aspects of the present invention.

[0009] Figure 3A 、 Figure 4A 、 Figure 5A 、 Figure 6A 、 Figure 7A 、 Figure 8A 、 Figure 9A 、 Figure 10A 、 Figure 11A 、 Figure 12A 、 Figure 13A 、 Figure 14A and Figure 15A are top views of exemplary workpieces at various manufacturing stages of methods according to various aspects of the present invention in Figure 1 、 Figure 2A and / or Figure 2B .

[0010] Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 11B , Figure 12B , Figure 13B and Figure 15B According to various aspects of the present invention, Figure 1 , Figure 2A and / or Figure 2B Along the various manufacturing stages of the method Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A and Figure 15A A cross-sectional view taken along dashed line AA′ of an exemplary workpiece depicted in FIG.

[0011] Figure 3C , Figure 4C , Figure 5C , Figure 6C , Figure 7C , Figure 8C , Figure 9C and Figure 15C According to various aspects of the present invention, Figure 1 , Figure 2A and / or Figure 2B Along the various manufacturing stages of the method Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A and Figure 15A A cross-sectional view of the exemplary workpiece depicted along dashed line CC'.

[0012] Figure 3D , Figure 4D , Figure 5D , Figure 6D , Figure 7D , Figure 8D and Figure 9D According to various aspects of the present invention, Figure 1 , Figure 2A and / or Figure 2B Along the various manufacturing stages of the method Figure 3A ,Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A and Figure 9A Cross-sectional views of the dashed line DD' of the exemplary workpiece depicted in

[0013] Figure 10C , Figure 11C , Figure 12C , Figure 13C and Figure 15D are respectively cross-sectional views of the dashed line EE' of the exemplary workpiece depicted in Figure 1 , Figure 2A and / or Figure 2B at each manufacturing stage of the method according to various aspects of the present invention along Figure 10A , Figure 11A , Figure 12A , Figure 13A and Figure 15A Cross-sectional views of the dashed line FF' of the exemplary workpiece depicted in

[0014] Figure 10D , Figure 11D , Figure 12D and Figure 13D are respectively cross-sectional views of the dashed line FF' of the exemplary workpiece depicted in Figure 1 , Figure 2A and / or Figure 2B at each manufacturing stage of the method according to various aspects of the present invention along Figure 10A , Figure 11A , Figure 12A and Figure 13A Cross-sectional views of the dashed line FF' of the exemplary workpiece depicted in

[0015] Figure 14B and Figure 15E are respectively cross-sectional views of the dashed line BB' of the exemplary workpiece depicted in Figure 1 , Figure 2A and / or Figure 2B at each manufacturing stage of the method according to various aspects of the present invention along Figure 14A and Figure 15A Cross-sectional views of the dashed line BB' of the exemplary workpiece depicted in

[0016] Figure 14C and Figure 15F are respectively cross-sectional views of the dashed line GG' of the exemplary workpiece depicted in Figure 1 , Figure 2A and / or Figure 2B at each manufacturing stage of the method according to various aspects of the present invention along Figure 14A and Figure 15A Cross-sectional views of the dashed line GG' of the exemplary workpiece depicted in

[0017] Figure 14D and Figure 15G are respectively at each manufacturing stage of the method according to various aspects of the present invention in Figure 1, Figure 2A and / or Figure 2B along the cross-sectional view of the dashed line HH’ of the exemplary workpiece depicted in Figure 14A and Figure 15A and DETAILED DESCRIPTION

[0018] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following present invention, the formation of a component on, connected to, and / or coupled to another component may include embodiments in which the components are formed in direct contact, and may include embodiments in which additional components may be formed between the components such that the components may not be in direct contact. In addition, spatial relative terms such as "lower", "upper", "horizontal", "vertical", "above", "over", "below", "beneath", "up", "down", "top", "bottom", etc. and their derivatives (e.g., "horizontally", "downwardly", "upwardly", etc.) are used to facilitate understanding of the relationship between one component of the present invention and another component. Spatial relative terms are intended to cover different orientations of devices including components.

[0019] Furthermore, when describing a numerical value or a numerical range using "about", "approximately", etc., the term is intended to cover numerical values within a reasonable range including the numerical value, such as within + / - 10% of the numerical value or other values understood by those skilled in the art. For example, the term "about 5 nm" covers a size range from 4.5 nm to 5.5 nm. In addition, the present invention may repeat reference numerals and / or characters in various instances. This repetition is for the purpose of simplicity and clarity and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0020] It should be noted that the present invention presents embodiments in the form of multi-gate transistors or fin multi-gate transistors, referred to herein as FinFETs. Such devices may include p-type metal-oxide-semiconductor FinFET devices or n-type metal-oxide-semiconductor FinFET devices. The FinFET devices may be dual-gate devices, triple-gate devices, bulk devices, silicon-on-insulator (SOI) devices, and / or other configurations. Although not depicted, other embodiments applicable to all-around-gate (GAA) devices, omega-gate (Ω-gate) devices, or Pi-gate (Π-gate) devices may also benefit from aspects of the present invention. Additionally, the present embodiment provides intermediate devices fabricated during the processing of an IC or portions thereof, which may include memories (such as static random-access memories or SRAMs) and / or logic circuits, passive components (such as resistors, capacitors, and inductors), and active devices, such as metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar transistors, high-voltage transistors, high-frequency transistors, other memory cells, and combinations thereof.

[0021] The present invention generally relates to semiconductor devices and their fabrication. More specifically, some embodiments relate to forming source / drain components in a device active region, such as a fin, for a FinFET configured to form logic and memory devices. FinFETs have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and reducing short-channel effects (SCEs). The FinFET fabrication process typically includes, inter alia, forming epitaxially grown source / drain components by etching and selective epitaxial growth to induce strain effects in the channel region of the FinFET. While current methods of forming FinFETs are generally adequate, they are not entirely satisfactory in all respects. For example, existing fabrication schemes may lack the ability to independently control the formation of the source / drain components to meet different design requirements applicable to different FinFETs, such as strain effects and contact resistance.

[0022] While not intended to be limiting, the present invention provides methods of forming source and drain components having increased strain effects, reduced contact resistance, and more design freedom over existing methods of forming source / drain components having different characteristics. In some embodiments, the source / drain components configured to provide different devices are separately formed to have different shapes and / or sizes. In the present embodiment, such different source / drain components are formed by controlling the height of their respective fin sidewall (FSW) spacers, which can be fabricated by implementing two patterning processes and subsequent two different etching processes.

[0023] Embodiments of the present invention provide various advantages. Although it should be understood that other embodiments may provide different advantages, not all advantages need to be discussed herein, and no particular advantage is required for all embodiments. In at least some embodiments, by forming epitaxial source / drain components, carrier mobility is increased and device performance is enhanced.

[0024] Figure 1 is a flow chart of a method 200 for manufacturing a workpiece 100 (also referred to as a semiconductor structure) configured to provide various FETs such as FinFETs. Figure 2A and Figure 2B together show a flow chart of a method 220 for manufacturing the workpiece 100, particularly its source / drain components (which are included in the block 210 as shown in Figure 1 . Additional steps may be provided before, during, and after the method 200 and / or method 220, and for other embodiments of the methods 200 and 220, some of the described steps may be replaced or eliminated. Various stages of the method 200 and / or 220 are discussed in detail with respect to Figures 3A to 15G where Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A and Figure 15A are top views of the workpiece 100; Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 11B , Figure 12B , Figure 13B and Figure 15B are cross-sectional views of the workpiece 100 along the dashed line AA' depicted in Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A and Figure 15A respectively; Figure 3C , Figure 4C , Figure 5C ,Figure 6C , Figure 7C , Figure 8C , Figure 9C and Figure 15C are respectively cross-sectional views of the workpiece 100 along the dashed line CC’ depicted in Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A and Figure 15A ; Figure 3D , Figure 4D , Figure 5D , Figure 6D , Figure 7D , Figure 8D and Figure 9D are respectively cross-sectional views of the workpiece 100 along the dashed line DD’ depicted in Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A and Figure 9A ; Figure 10C , Figure 11C , Figure 12C , Figure 13C and Figure 15D are respectively cross-sectional views of the workpiece 100 along the dashed line EE’ depicted in Figure 10A , Figure 11A , Figure 12A , Figure 13A and Figure 15A ; Figure 10D , Figure 11D , Figure 12D and Figure 13D are respectively cross-sectional views of the workpiece 100 along the dashed line FF’ depicted in Figure 10A , Figure 11A , Figure 12A and Figure 13A ; Figure 14B and Figure 15E are respectively cross-sectional views of the workpiece 100 along the dashed line BB’ depicted in Figure 14A and Figure 15A ; Figure 14C and Figure 15F are respectively cross-sectional views of the workpiece 100 along the dashed line GG’ depicted in Figure 14A and Figure 15A ; Figure 14D and Figure 15G are respectively cross-sectional views of the workpiece 100 along the dashed line HH’ depicted in Figure 14A and Figure 15A .

[0025] First, refer to Figure 1frame 202 and reference Figures 3A to 3D , method 200 receives (or is provided with) a workpiece 100 including a substrate 102. In various instances, substrate 102 may include an elemental (single element) semiconductor, such as silicon or germanium in a crystalline structure; a compound semiconductor, such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; a non-semiconductor material, such as soda-lime glass, fused silica, fused quartz, and / or calcium fluoride (CaF2), other suitable materials, or combinations thereof. In some embodiments, substrate 102 includes silicon germanium (Si 1-x Ge x ), where the component Ge(x) is from about 5% to about 50%. Additionally, the silicon germanium-containing substrate 102 may be doped with a p-type dopant, such as boron, gallium, aluminum, indium, other suitable p-type dopants, or combinations thereof.

[0026] The composition of substrate 102 may be uniform or may include various layers. The layers may have similar or different compositions, and in various embodiments, some substrate layers have non-uniform compositions to induce device strain and thereby adjust device performance. Examples of layered substrates include silicon-on-insulator (SOI) substrates 102. In some such instances, the layers of substrate 102 may include an insulator, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, other suitable insulating materials, or combinations thereof.

[0027] In some embodiments, workpiece 100 includes various doped regions (or wells) formed in or above substrate 102. Each doped region may be implanted with one or more dopants according to specific design requirements. For example, an n-type well may include an n-type dopant, such as phosphorus, arsenic, antimony, other n-type dopants, or combinations thereof, and a p-type well may include a p-type dopant, such as boron, indium, gallium, aluminum, other p-type dopants, or combinations thereof. In some embodiments, substrate 102 includes a doped region having a combination of p-type and n-type dopants. Each of the various doped regions may be formed directly on and / or in substrate 102, for example, providing a p-well structure, an n-well structure, a dual-well structure, a raised structure, or combinations thereof. Each of the various doped regions may be formed by implementing an ion implantation process, a diffusion process, other suitable doping processes, or combinations thereof.

[0028] reference Figure 1 frame 204 and reference Figures 3A to 3D, Method 200 forms fin active regions or fins 108A, 108B, 108C, and 108D (collectively fins 108) that extend or protrude from substrate 102 and are separated by isolation member 104. In this embodiment, fins 108 are longitudinally elongated in the X direction and spaced apart from each other in the Y direction. Fins 108 can include any suitable semiconductor material, including silicon, germanium, silicon germanium, and / or other semiconductor materials. In some embodiments, fins 108 include one or more epitaxially grown semiconductor materials. Fins 108 are formed by selectively etching isolation member 104 to form a groove, then epitaxially growing one or more semiconductor materials in the groove and planarizing the semiconductor materials using isolation member 104. In some embodiments, fins 108 are formed by patterning substrate 102 to form fins 108 separated by trenches, then filling the trenches with a dielectric layer, planarizing the dielectric layer, and selectively etching the dielectric layer to form isolation member 104 between fins 108. Refer to Figure 3C and Figure 3D , the separation distance between two adjacent fins 108 can be different in different regions defined in substrate 102. For example, two fins 108A can be formed with a separation distance S1 that is less than the separation distance S2 between two fins 108C.

[0029] Patterning substrate 102 can include a series of lithography and etching processes. The lithography process can include: forming a photoresist layer (resist) on substrate 102; exposing the resist to a pattern; performing a post-exposure bake process; and developing the resist to form a masking device (not shown) that includes the resist. The masking device is then used to etch trenches in substrate 102, leaving fins 108 that protrude from substrate 102. The etching process can include dry etching, wet etching, reactive ion etching (RIE), other suitable processes, or a combination thereof. After performing the etching process, the masking device is removed from substrate 102 by a suitable method, such as plasma ashing or resist stripping.

[0030] Many other embodiments of the method for forming fins 108 may be suitable. For example, fins 108 can be patterned using a double patterning or multiple patterning process. Generally, a double patterning or multiple patterning process combines lithography and self-alignment processes, thereby allowing the creation of patterns with a pitch, for example, smaller than the pitch obtainable using a single, direct lithography process. For example, in one embodiment, a sacrificial layer is formed above substrate 102 and patterned using a lithography process. A spacer is formed adjacent to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacer or mandrel can then be used to pattern fins 108.

[0031] In this embodiment, the isolation component 104 is formed to define and separate regions (or device regions) in the substrate 102. The isolation component 104 may include silicon dioxide, a low-k dielectric material (a dielectric material having a dielectric constant smaller than that of silicon dioxide, the dielectric constant of silicon dioxide being about 3.9), other suitable materials, or combinations thereof. In some embodiments, the isolation component 104 includes a shallow trench isolation component (STI), a deep trench isolation component (DTI), other types of isolation components, or combinations thereof. For example, the configuration of the isolation component 104 that separates portions of the fin 108 may include STI, while the substrate 102 may be embedded in a portion of the isolation component 104 configured as DTI, which may be formed by recessing the substrate 102 to form a through-thickness trench, subsequently filling the trench with a dielectric material, and planarizing the dielectric material with the substrate 102 to form the DTI. The isolation component 104 may be deposited by any suitable method, such as chemical vapor deposition (CVD), flowable CVD (FCVD), spin-on glass (SOG), other suitable methods, or combinations thereof.

[0032] The isolation component 104 may separate the substrate 102 into respective regions configured to provide different devices. In the depicted embodiment, for example, the substrate 102 includes four exemplary regions (or device regions) 102A, 102B, 102C, and 102D. In some embodiments, the regions 102A - 102D are designed to independently provide devices with different functions (such as logic devices or memory (such as SRAM) devices), different conduction types (such as n-type devices or p-type devices), or combinations thereof. For example, in some embodiments, regions 102A and 102B are configured to provide devices with the same function but different conduction types. Of course, this embodiment is not limited to any specific arrangement. For simplicity purposes, in the depicted embodiment, methods 200 and 220 are discussed with reference to regions 102A and 102C configured to provide a logic device and a memory device, respectively, regions 102A and 102B are configured to provide logic devices of different conduction types, and regions 102C and 102D are configured to provide memory devices of different conduction types.

[0033] Referring to Figure 1 block 206 and referring to Figures 4A to 4D, Method 200 forms dummy gate stacks (optionally referred to as placeholder gates) 112 above fins 108A and 108B, and forms dummy gate stack 114 above fins 108C and 108D. In this embodiment, dummy gate stacks 112 and 114 will be replaced by metal gate stacks at a later stage of fabrication. Each dummy gate stack passes through the channel region of fin 108 and is thus disposed between source / drain components subsequently formed in and / or above fin 108. Dummy gate stacks 112 and 114 may each at least include a gate electrode comprising, for example, polysilicon. In some embodiments, each dummy gate stack further includes an interface layer (such as silicon oxide) above fin 108, a gate dielectric layer (such as silicon oxide) above the interface layer, a gate electrode (such as polysilicon) above the gate dielectric layer, a hard mask layer, a capping layer, a barrier layer, other suitable layers, or a combination thereof. As depicted herein, a hard mask 120 is formed above the top surfaces of dummy gate stacks 112 and 114 to provide protection for subsequent etching processes. The respective layers of dummy gate stacks 112 and 114 may be formed by thermal oxidation, chemical oxidation, CVD, atomic layer deposition (ALD), physical vapor deposition (PVD), other suitable methods, or a combination thereof.

[0034] The formation of dummy gate stacks 112 and 114 may include forming the respective gate material layers and patterning the gate material layers using a lithography process and etching. The hard mask 120 can be used to pattern the gate material layers. For example, the hard mask 120 can be deposited on the gate material layers and patterned by lithography and etching processes to include respective openings. Then, the pattern defined on the hard mask 120 is transferred to the gate material layers by etching, thereby forming dummy gate stacks 112 and 114. The hard mask 120 can include silicon, nitrogen, oxygen, carbon, other suitable elements, or a combination thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide). In some instances, the hard mask 120 can include multiple films, such as a silicon nitride layer above dummy gate stacks 112 and 114 and a silicon oxide layer above the silicon nitride layer. The hard mask 120 can be patterned by any suitable method, such as the methods discussed in detail above regarding patterning fin 108.

[0035] In some embodiments, gate spacers (not depicted) having a single-layer or multi-layer structure are formed on the sidewalls of dummy gate stacks 112 and 114. The gate spacers can include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, other dielectric materials, or a combination thereof, and can be formed by depositing a dielectric material layer and performing an anisotropic etching process to remove portions of the layer, leaving the gate spacers on the sidewalls of dummy gate stacks 112 and 114.

[0036] Reference Figure 1 to block 208 and referenceFigures 5A to 5D Method 200 forms a dielectric layer 126 over substrate 102 to conformally cover fins 108 and dummy gate stacks 112 and 114. In this embodiment, dielectric layer 126 is configured to provide gate spacers 124 on the sidewalls of dummy gate stacks 112 and 114 (in addition to or optionally gate spacers formed on the sidewalls of dummy gate stacks 112 and 114 in block 206), and to provide spacers (such as FSW spacers 126A, 126B, 126C, and 126D) on the sidewalls of fins 108.

[0037] Dielectric layer 126 can include silicon, nitrogen, oxygen, carbon, other suitable elements, or combinations thereof. For example, dielectric layer 126 can include silicon nitride, silicon oxide, silicon carbide, carbon silicon nitride, silicon oxynitride, carbon silicon oxide, carbon oxynitride silicon, high-k dielectric materials (dielectric materials having a dielectric constant greater than that of silicon oxide, the dielectric constant of silicon oxide being approximately 3.9), low-k dielectric materials, other dielectric materials, or combinations thereof. In some embodiments, dielectric layer 126 has a single-layer structure. In some embodiments, dielectric layer 126 has a multi-layer structure including at least two material layers. In one such example, dielectric layer 126 includes a silicon nitride layer and a carbon oxynitride silicon layer. In another example, dielectric layer 126 includes a silicon nitride layer and a silicon oxynitride layer. In yet another example, dielectric layer 126 includes a low-k dielectric layer and a silicon nitride layer. The composition of dielectric layer 126 (and its sub-layers) can be selected based on one or more design requirements for proper device functionality. For example, dielectric materials having different dielectric constants can be selected to achieve desired levels of parasitic capacitance and etch resistance. In some cases, dielectric materials with lower dielectric constants may be suitable for reducing parasitic capacitance, while dielectric materials with higher dielectric constants may be suitable for enhancing protection against subsequent etching processes. Each sub-layer of dielectric layer 126 can be formed by suitable deposition methods, such as CVD, ALD, FCVD, PVD, other methods, or combinations thereof, to achieve a suitable thickness.

[0038] Method 200 proceeds to block 210 to form epitaxial source / drain components in fins 108, which is done by method 220 and is further discussed with reference to Figure 2A 、 Figure 2B and Figures 6A to 15D further discussed.

[0039] Refer to Figure 2A block 222 of Figures 6A to 6D, Method 220 forms a patterned photoresist layer 130 above substrate 102 to expose region 102A without exposing regions 102B - 102D. In this embodiment, the photoresist layer 130 is a three - layer photoresist, which includes a bottom layer 130A, an intermediate layer 130B above the bottom layer 130A, and a top layer 130C above the intermediate layer 130B. Together, they are configured to enhance the results of the lithography process, such as improving the resolution of the lithography process. Each layer of the photoresist layer 130 can be configured with different components to obtain enhanced etch selectivity. For example, the bottom layer 130A can be a polymer anti - reflection coating, the intermediate layer 130B can include a polymer material configured to enhance the photosensitivity of the photoresist layer 130, and the top layer 130C generally includes a photosensitive material (resist). It should be noted that although Figure 6B shows three layers of the photoresist layer 130 separately, for simplicity purposes, they will be collectively depicted as the photoresist layer 130 in the subsequent figures. The photoresist layer 130 can be patterned through a series of lithography and etching processes similar to those discussed in detail above with respect to the patterned fin 108.

[0040] Reference Figure 2A to block 224 and reference Figures 7A to 7D , Method 220 recesses the dielectric layer 126 to form a first fin sidewall (FSW) spacer 126A and a gate spacer 124. In this embodiment, reference Figure 7B and Figure 7C , Method 220 implements an etching process 302 to remove the portion of the dielectric layer 126 located in region 102A. In this embodiment, the etching process 302 includes one or more etching processes configured to recess portions of the dielectric layer 126 anisotropically, leaving portions of the dielectric layer 126 as the FSW spacer 126A on the sidewalls of the fin 108A and the gate spacer 124 on the sidewalls of the pseudo - gate stack 112. In this embodiment, the etching process 302 is adjusted such that the FSW spacer 126A is defined by a height H1, which is measured from the top surface of the isolation component 104.

[0041] In some embodiments, the etching process 302 includes one or more dry - etching processes that implement any suitable etchant selected according to the composition of the dielectric layer 126. Some exemplary dry - etching agents include CH3F, CF4, NF3, SF6, CO, CO2, SO2, CH4, Ar, HBr, O2, He, other suitable etchants, or combinations thereof. In some embodiments, the etching process 302 is implemented using a mechanism such as deep reactive ion etching (DRIE) to achieve or enhance the anisotropic etching of the dielectric layer 126.

[0042] In this embodiment, the etch process 302 includes at least a dry etch process that can be adjusted by adjusting one or more parameters, such as bias power, bias voltage, etch temperature, etch pressure, source power, etchant flow rate, other suitable parameters, or combinations thereof. In this embodiment, the bias power of the etch process 302 is adjusted to control the height H1, which subsequently controls the shape and size of the source / drain components formed above the fin 108A. In this embodiment, for a given amount of etch time, increasing the bias power results in an increased amount of bombardment by dry etchant particles, which results in a greater amount of the dielectric layer 126 being removed and thus reduces the height H1 of the FSW spacer 126A. In this embodiment, the height H1 is controlled such that the resulting source / drain components formed above two adjacent fins 108A merge together, thereby providing an enlarged source / drain component suitable for certain design requirements. In this regard, the height H1 can be adjusted to be less than about half of the fin height (FH) of the fin 108, where FH is measured from the top surface of the isolation component 104. In some embodiments, the ratio of the height H1 to the FH is from about 0.1 to about 0.3. Although this embodiment is not limited to such dimensions, it should be noted that if the ratio is less than about 0.1, the merged source / drain components may be too small to provide sufficient landing area for the subsequently formed source / drain contacts. Additionally, if the size of the resulting source / drain components is too small, the contact resistance may inadvertently be too high for the desired device performance. On the other hand, a ratio greater than about 0.3 may cause the source / drain components to favor vertical growth rather than lateral merging, resulting in separated, unmerged source / drain components formed above adjacent fins 108A. In some instances, the height H1 can be from about 6 nm to about 14 nm. In some embodiments, the etch process 302 is implemented to remove a small amount of the gate spacer 124, thereby slightly reducing the height and / or thickness of the gate spacer 124. It should be noted that this reduction generally does not affect the overall performance of the gate spacer 124.

[0043] Reference Figure 2A to block 226 and reference Figures 8A to 8D , method 220 forms source / drain recesses 131 between each exposed fin 108A and the FSW spacer 126A. In this embodiment, forming the source / drain recesses 131 includes applying an etch process 304 that selectively removes portions of the fin 108A without removing or substantially removing portions of the dummy gate stack 112, the isolation component 104, or the dielectric layer 126. In this embodiment, the source / drain recesses 131 are formed to a depth D1. In some instances, the depth D1 can be from about 47 nm to about 57 nm; of course, this embodiment is not limited to such dimensions. In some instances, the ratio of the height H1 to the depth D1 can be from about 1:10 to about 1:3.

[0044] The etching process 304 can be a dry etching process, a wet etching process, other suitable etching processes, or a combination thereof. In some embodiments, the wet etching process implements a wet etchant including hydroxides such as potassium hydroxide (KOH) and / or ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2), sulfuric acid (H2SO4), TMAH, other suitable wet etching solutions, or a combination thereof. For example, the wet etchant can implement an NH4OH-H2O2-H2O mixture (referred to as an ammonia-peroxide mixture or APM) or an H2SO4-H2O2 mixture (referred to as a sulfuric acid-peroxide mixture or SPM). In some embodiments, the dry etching process uses a dry etchant that includes fluorine-containing etching gases such as CF4, SF6, CH2F2, CHF3, and / or C2F6, oxygen-containing gases, chlorine-containing gases such as Cl2, CHCl3, CCl4, and / or BCl3, bromine-containing gases such as HBr and / or CHBr3, iodine-containing gases, He, Ar, O2, other suitable gases, and / or plasmas, or a combination thereof. In some embodiments, the etching process 304 additionally implements an oxidation process. For example, the etching process 304 can expose the fin 108A to an ozone environment to oxidize the portion of the fin 108A exposed by the patterned photoresist layer 130, and the oxidized portion is subsequently removed by a cleaning process and / or an etching process such as those described herein. After implementing the etching process 304, the method 220 can implement a wet cleaning process using SPM, a diluted HF solution, other suitable solutions, or a combination thereof to remove any etching by-products.

[0045] Reference Figure 2A to the block 228 and reference Figures 9A to 9D , the method 220 forms a first source / drain component 132 in the source / drain recess 131. In the present embodiment, the method 220 implements an epitaxial process 306 to grow the source / drain component 132. The epitaxial process 306 can be a selective epitaxial growth (SEG) process implemented using any deposition technique such as a CVD deposition technique (e.g., vapor phase epitaxy (VPE) and / or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy, other suitable processes, or a combination thereof. The epitaxial process 306 can use gaseous precursors such as silicon-containing gases including SiH4 and / or germanium-containing gases including GeH4 and / or liquid precursors that interact with the components of the fin 108A to form an epitaxial Si layer or an epitaxial SiGe layer in the source / drain component 132.

[0046] The source / drain component 132 can be doped in-situ by introducing one or more dopants during the epitaxial process 306. Optionally, the source / drain component 132 (or their layers) can be epitaxially grown using a suitable SEG process and then an implantation process (such as a junction implantation process) is applied to introduce dopants into the source / drain component 132. The dopants can include p-type dopants (such as boron, BF2, aluminum, gallium, and / or indium), n-type dopants (such as phosphorus, arsenic, and / or antimony), other suitable dopants, or combinations thereof. The source / drain component 132 can include one or more epitaxial layers having different concentrations of the same dopant. In some instances, the different epitaxial layers can include different types of dopants. The composition of the source / drain component 132 can be selected based on the type of device it is configured to provide. For embodiments where the source / drain component 132 is configured to provide an n-type device (such as an n-type logic device), the source / drain component 132 includes one or more epitaxial Si layers doped with an n-type dopant such as phosphorus (Si:P). For embodiments where the source / drain component 132 is configured to provide a p-type device (such as a p-type logic device), the source / drain component 132 includes one or more epitaxial SiGe layers doped with a p-type dopant such as boron (SiGe:B). In some embodiments, the epitaxial SiGe layer configured for a p-type device further includes antimony (SiGe:Sn:B) configured to adjust the lattice constant of the epitaxial layer. The epitaxial process 306 can also include performing one or more annealing processes to activate the dopants in the source / drain component 132. Suitable annealing processes include rapid thermal annealing (RTA), laser annealing, other suitable processes, or combinations thereof. After forming the source / drain component 132, the patterned photoresist layer 130 is removed by a suitable process, such as plasma ashing and / or resist stripping.

[0047] In this embodiment, referring to Figure 9C , the epitaxial process 306 forms the source / drain component 132 from two adjacent source / drain grooves 131 that merge the adjacent fins 108A together. In this embodiment, referring to Figure 9B, The merging enhances the strain effect on the channel region 140 below the pseudo-gate stack 112, which can improve the carrier mobility of the resulting device. Additionally, the enlarged volume of the source / drain component 132 can lead to a reduction in contact resistance and thus enhance device performance. In some embodiments, the merging creates an air gap (or void) 138 formed between the FSW spacers 126A and below the bottom of the merged source / drain component 132, thereby providing an additional isolation function for the source / drain component 132. Moreover, the merging allows the top surface (ET) of the source / drain component 132 to be substantially elongated to a width W1' along the direction (direction Y) of the pseudo-gate stack 112, which is used to expand the landing area of the source / drain contact that can be subsequently formed above it. In addition to the height of the FSW spacers 126A (such as height H1), the size and shape of the source / drain component 132 can depend on factors such as the composition of the epitaxial layer, the separation distance S1 between the fins 108A, and / or the deposition conditions of the epitaxial process 306.

[0048] In some embodiments, the maximum width W1 of the source / drain component 132 exceeds FH. In some instances, the width W1 can be from about 65 nm to about 75 nm, and the ratio of the width W1 to FH can be from about 1.2 to about 1.4; of course, this embodiment is not limited to such dimensions. Additionally, in this embodiment, referring Figure 9B and Figure 9C , the distance H2 between the top surface of the fin 108A (FT) and ET is greater than zero. In some instances, the distance H2 can be from about 3 nm to about 10 nm; of course, this embodiment is not limited to such dimensions.

[0049] Referring Figure 2A to block 230 of Figures 10A to 10D and referring

[0050] to Figure 2A , method 220 forms a patterned photoresist layer 134 above the workpiece 100 to expose the region 102C without exposing the regions 102A, 102B, and 102D. The photoresist layer 134 can be a three-layer photoresist similar to the photoresist layer 130, which has been discussed in detail above with respect to block 222. The photoresist layer 134 can be patterned through a series of photolithography processes similar to those discussed in detail above with respect to patterning the fins 108. Figures 11A to 11D Referring Figure 11B, Method 220 implements an etching process 308 to remove a portion of the dielectric layer 126 located in region 102C. In this embodiment, the etching process 308 includes one or more etching processes configured to anisotropically recess portions of the dielectric layer 126, leaving portions of the dielectric layer 126 as the FSW spacers 126B on the sidewalls of the fins 108C and as the gate spacers 124 on the sidewalls of the pseudo-gate stack 114. In this embodiment, the FSW spacer 126B is defined by a height H3 that is measured from the top surface of the isolation component 104. The etching process 308 may implement one or more dry etching processes similar or identical to those discussed above with respect to the etching process 302 and may utilize the same dry etchant as the etching process 302; however, the parameters of the etching process 308 are adjusted in a manner different from the parameters of the etching process 302 such that the source / drain components subsequently formed in region 102C are different in configuration from those in region 102A.

[0051] Specifically, in this embodiment, still referring to Figure 11B, instead of adjusting the bias power, the etch process 308 is adjusted by adjusting the frequency of the power output (a process referred to as “synchronous pulsing”) such that the dry etchant (discussed above with respect to etch process 302) is applied intermittently. In other words, the etch process 308 repeats “on” (i.e., when the dry etchant (or pulse) is applied) and “off” (i.e., when the dry etchant is not applied) at a specified frequency to allow for an alternation between material removal and redeposition. When the etch process 308 is “on”, portions of the dielectric layer 126 are removed by chemical reaction with the dry etchant and / or particle bombardment, thereby reducing the height H3. Conversely, when the etch process 308 is “off”, etch by-products (such as carbonaceous polymer materials) are redeposited on the surface of the workpiece 100 including, for example, the FSW spacer 126B and the gate spacer 124, thereby increasing the height H3 of the FSW spacer 126B and / or smoothing the surface profile. Thus, the height H3 can be finely tuned by adjusting the duration and / or frequency of the on / off pulses implemented during the etch process 308. For example, if the duration of the “on” state is longer than the duration of the “off” state, for a given amount of etch time, the height H3 may be lower compared to when the duration of the “off” state is longer than the duration of the “on” state. Additionally, the height H3 can be adjusted by adjusting the number of on / off cycles. For example, increasing the number of cycles reduces the height H3. Additionally, other factors such as the type of dry etchant and the concentration of the dry etchant can also be independently controlled during the synchronous pulsing process to achieve the desired FSW spacer height and morphology. For example, by adjusting the duration and / or frequency of the synchronous pulse, the top surface of the resulting FSW spacer 126B can be adjusted to have a relatively flat rather than rounded profile. Additionally, any unintentional thinning or shortening of the gate spacer 124 exposed in the third region 108C can be remedied by the redeposition of etch by-products during the “off” state of the etch process 308. In other words, due to the lack of etch / redeposition cycles during the etch process 302, the height of the gate spacer 124 formed in the region 102C may be greater than the height of the gate spacer 124 formed in the region 102A.

[0052] In the present embodiment, the height H3 is formed to be greater than the height H1, such that the resulting source / drain components formed between the FSW spacers 126B are different in shape and size from those formed between the FSW spacers 126A. In some embodiments, the height H3 is controlled such that the resulting source / drain components are formed over different fins 108C and each is smaller in size than the combined source / drain components 132 formed between the FSW spacers 126A, as discussed above. In this regard, the height H3 can be at least about half of the previously defined fin height FH. In some embodiments, the ratio of the height H3 to the FH is from about 0.5 to about 0.7. In some instances, the height H3 can be from about 29 nm to about 37 nm. Although the present embodiment is not limited by such dimensions, it should be noted that if the ratio of the height H3 to the FH is less than about 0.5, the subsequently formed source / drain components over two adjacent fins 108C can merge to form a single source / drain component. On the other hand, if the ratio of the height H3 to the FH is greater than about 0.7, the resulting source / drain components (although not merged) can introduce a higher contact resistance due to their smaller size.

[0053] Reference Figure 2A to block 234 and reference Figures 12A to 12D , method 220 forms source / drain trenches 135 in each exposed fin 108C and between the FSW spacers 126B. In the present embodiment, forming the source / drain trenches 135 includes applying an etching process 310 that selectively removes portions of the fin 108C without removing or substantially removing portions of the dummy gate stack 114, the isolation component 104, or the dielectric layer 126. The details of the etching process 310 can be similar to those of the etching process 304 discussed above. In some embodiments, the etching process 310 is subsequently followed by a wet cleaning process, also similar to that discussed above with respect to the etching process 304. The source / drain trenches 135 can be formed to a depth D2. In some embodiments, the depth D2 is less than the depth D1, such that the bottom surface of the source / drain trench 135 is above the bottom surface of the source / drain trench 131, as Figure 12B depicted. In some instances, the ratio of the height H3 to the depth D2 can be from about 0.6 to about 1.0, and the depth D2 can be from about 35 nm to about 45 nm; of course, the present embodiment is not limited to such dimensions.

[0054] Reference Figure 2A to block 236 and reference Figures 13A to 13D, Method 220 forms source / drain component 136 in source / drain recess 135. In this embodiment, method 220 implements epitaxial process 312 to grow source / drain component 136. Epitaxial process 312 can be similar to epitaxial process 306 discussed in detail above. For example, epitaxial process 312 can implement a suitable SEG process to form one or more epitaxial layers in source / drain recess 135, where the epitaxial layers are doped with a suitable dopant in-situ or subsequently during an implantation process. As discussed above regarding source / drain component 132, the dopant for source / drain component 136 is selected based on the device type that source / drain component 136 is configured to provide. For embodiments where source / drain component 136 is configured to provide an n-type device, source / drain component 136 includes one or more epitaxial Si layers doped with an n-type dopant, and for embodiments where source / drain component 136 is configured to provide a p-type device, source / drain component 136 includes one or more epitaxial SiGe layers doped with a p-type dopant. In some embodiments, source / drain component 132 and source / drain component 136 are configured to provide devices of the same conductivity type (e.g., both n-type or both p-type); alternatively, source / drain component 132 and source / drain component 136 are configured to provide devices of different conductivity types (e.g., n-type and p-type, respectively). Epitaxial process 312 can also include implementing a suitable annealing process similar to that discussed above to activate the dopant in source / drain component 136. In this embodiment, since depth D2 is less than depth D1, as discussed above, the bottom surface of source / drain component 136 is located above the bottom surface of source / drain component 132. After forming source / drain component 136, the patterned photoresist layer 134 is removed by a suitable process, such as plasma ashing and / or resist stripping.

[0055] In this embodiment, referring to Figure 13C, the epitaxial process 312 forms source / drain components 136 from each of the source / drain trenches 135 such that the resulting source / drain components 136 are separated from each other rather than merged together. In the present embodiment, adjusting the height H3 of the FSW spacer 126B to be greater than the height H1 of the FSW spacer 126A allows the epitaxial layer of the source / drain components 136 to grow in a substantially vertical direction between the FSW spacers 126B. In some embodiments, the height H3 is adjusted to at least half of FH. Accordingly, the size of the source / drain components 136 is smaller than the size of the source / drain components 132. For example, in some embodiments, the maximum width W2 of the source / drain components 136 is much less than FH, and the distance H4 between the top surface FT of the fin 108C and the top surface ET of the source / drain components 136 is less than the distance H2 of the source / drain components 132. In some cases, the ratio of the width W2 to FH can be from about 0.3 to about 0.5, where the width W2 can be from about 18 nm to about 28 nm. In some embodiments, the distance H4 is less than zero, such as from about -2 nm to about 0 nm, indicating that ET is disposed below FT or at the same level as FT. In some embodiments, as depicted herein, the distance H4 is greater than zero, such as from about 0 nm to about 3 nm, indicating that ET is disposed above FT. Of course, the present embodiment is not limited to these dimensions. The reduced volume of the source / drain components 136 also results in the ET of the source / drain components 136 being much less elongated than the ET of the source / drain components 132, as discussed above, i.e., the distance W2' is less than the distance W1'.

[0056] In addition to the height of the FSW spacer (such as the height H3), the size and shape of the source / drain components 136 can depend on factors such as the composition of the epitaxial layer, the separation distance S2 between the fins 108C, and / or the deposition conditions of the epitaxial process 312.

[0057] Now referring jointly to Figure 2B boxes 238 to 250 of [[ID=2 , method 220 forms source / drain components 142 in region 102B and source / drain components 146 in region 102D. In the depicted embodiment, region 102B is configured to provide a device with the same function as region 102A but a different conductivity type, and region 102D is configured to provide a device with the same function as region 102C but a different conductivity type. For example, in the depicted embodiment, regions 102A and 102B are configured to provide a p-type logic device and an n-type logic device, respectively, while regions 102C and 102D are configured to provide a p-type SRAM device and an n-type SRAM device, respectively.

[0058] In this embodiment, blocks 238 through 250 depict a series of lithography, etching, and epitaxial processes that are substantially similar to those discussed in blocks 222 through 236. For example, referring to block 238, method 220 forms a third patterned photoresist layer (not depicted) over workpiece 100 to expose region 102B covered by dielectric layer 126, without exposing regions 102A, 102C, or 102D. The third patterned photoresist layer can be substantially similar to the patterned photoresist layer 130 as discussed above. Referring to block 240, and method 220 implements an etching process that is substantially similar or identical to etching process 302, thereby forming gate spacers 124 on the sidewalls of the pseudo-gate stack 112 and forming FSW spacers 126C on the sidewalls of fin 108B, as ​ and ​ depicted. In this embodiment, by adjusting the bias power during etching of dielectric layer 126, FSW spacer 126C is formed to have a height H5 that is less than FH. In some exemplary embodiments, height H5 is less than half of FH, where the ratio of height H3 to FH is from about 0.1 to about 0.3. Although this embodiment does not limit height H5 to a specific dimension, the etching process applied in block 240 is adjusted such that the resulting source / drain components formed between FSW spacers 126C merge two adjacent fins 108B together. In some embodiments, height H5 is substantially similar to height H1 of FSW spacer 126A, and thus less than height H3 of FSW spacer 126B. In some instances, height H5 can be less than height H1, such that the merged source / drain component formed therebetween is larger than merged source / drain component 132. If height H5 is less than height H1, then a greater etch bias power (higher voltage) can be applied in the etching process when compared to etching process 302 to form FSW spacer 126C.

[0059] Referring to block 242, method 220 forms source / drain recesses (not depicted) in portions of the second fin 108B that are between FSW spacers 126C in an etching process similar to etching process 304. Subsequently, referring to block 244 and referring to ​ and ​, Method 220 forms source / drain component 142 in the source / drain recess in an epitaxial growth process similar to epitaxial process 306, during which source / drain component 142 merges two recessed fins 108B together, thereby forming air gap 144 with FSW spacer 126C. Source / drain component 142 can be configured to have a conductivity type different from that of source / drain component 132. For embodiments where source / drain component 132 is configured to provide a p-type device (such as a p-type logic device), source / drain component 142 is configured to provide an n-type device (such as an n-type logic device). In this regard, source / drain component 142 can include one or more epitaxial Si layers doped with an n-type dopant (such as an Si:P layer), as discussed above with respect to source / drain component 132. An annealing process can be implemented after forming source / drain component 142 to activate the dopants in source / drain component 142. After forming source / drain component 142, method 220 removes the third patterned photoresist layer configured to expose region 102B by any of the above suitable methods.

[0060] Source / drain component 142 can be configured to have a geometry substantially similar to that of source / drain component 132, but the specific dimensions of source / drain component 142 can be different from those of source / drain component 132. For example, the merged source / drain component 142 can be formed to have a maximum width W4 of about 65 nm to about 75 nm, and the ratio of width W4 to FH can be about 1.2 to about 1.4. In a further example, the top surface ET can be substantially elongated to a width W4' similar to width W1', and the distance H6 between the top surface FT and ET of fin 108B is greater than zero and can be, for example, about 3 nm to about 10 nm. Of course, this embodiment is not limited to such dimensions. In some embodiments, FSW spacer 126C is adjusted to be smaller than FSW spacer 126A, such that the merged source / drain component 142 is larger than the merged source / drain component 132.

[0061] Referring to block 246, method 220 forms a fourth patterned photoresist layer (not depicted) over workpiece 100 to expose region 102D covered by dielectric layer 126 without exposing regions 102A - 102C. The fourth patterned photoresist layer can be substantially similar to the patterned photoresist layer 130 discussed above. Referring to block 248, method 220 implements an etching process substantially similar to etching process 308, thereby forming gate spacer 124 on the sidewalls of pseudo-gate stack 114 and forming FSW spacer 126D on the sidewalls of fin 108D, as ​ and ​Depicted in. In this embodiment, the etchant (such as the dry etchant discussed above with respect to etch process 308) is intermittently applied by adjusting the synchronization pulse of the etch process applied in block 248, i.e., alternating between an "on" state and an "off" state. As discussed in detail above, the "on" state of the synchronization pulse actively recesses the dielectric layer 126 to form the FSW spacer 126D and the gate spacer 124, while the "off" state allows any etch by-products to redeposit above the workpiece 100, thus providing control to finely adjust the height H7 and smooth the recessed profile of the FSW spacer 126D. In this regard, the removal rate of the dielectric layer 126 can be adjusted by adjusting the frequency of the "on" and "off" state cycles and / or the duration of each state applied. In some cases, the unintentional recess of the gate spacer 124 can be mitigated by such an adjustment process.

[0062] In this embodiment, the height H7 is adjusted in block 248 such that the resulting source / drain components formed between the FSW spacers 126D are separated from each other rather than merging with each other as in the case of the source / drain components 142. In this regard, the height H7 is greater than the height H5 of the FSW spacer 126C and the height H1 of the FSW spacer 126A. In some embodiments, the height H7 is at least about half of FH, and in some cases, the ratio of the height H7 to FH can be from about 0.5 to about 0.7, similar to the height H3 discussed above. In some instances, the height H7 can be similar to the height H3 of the FSW spacer 126B.

[0063] Referring to block 250, method 220 forms source / drain grooves (not depicted) in the portion of the fin 108B that is between the FSW spacers 126D in an etch process similar to etch process 310 discussed above. Subsequently, referring to block 252 and referring ​ and Figure 14D, Method 220 implements an epitaxial growth process similar to the epitaxial growth process 312 discussed above, such that the resulting source / drain components 146 grow respectively from each of the source / drain grooves formed in the block 250. The source / drain components 146 can be configured to have a conductivity type different from that of the source / drain components 136. For embodiments where the source / drain components 136 are configured to provide p-type devices (such as p-type memory devices), the source / drain components 146 are configured to provide n-type devices (such as n-type memory devices). In this regard, the source / drain components 146 can include one or more epitaxial Si layers doped with an n-type dopant (such as a Si:P layer), as discussed above with respect to the source / drain components 132. An annealing process can be implemented after the formation of the source / drain components 142 to activate the dopants in the source / drain components 142. After the formation of the source / drain components 142, Method 220 removes the third patterned photoresist layer configured to expose the region 102B by any of the above suitable methods.

[0064] In this embodiment, adjusting the height H7 of the FSW spacer 126D to be greater than the height H5 of the FSW spacer 126C allows the epitaxial layer of the source / drain component 146 to grow substantially in the vertical direction between the FSW spacers 126D. In other words, when compared with the source / drain component 142, increasing the height H7 relative to the height H5 reduces the overall size of the source / drain component 146. For example, in some embodiments, the maximum width W5 of the source / drain component 146 is much smaller than FH, and the distance H8 between the fin top surface FT and the top surface ET of the source / drain component 146 is less than the distance H6 of the source / drain component 142. In some instances, the ratio of the width W5 to FH can be from about 0.3 to about 0.5. In some embodiments, similar to the description of the distance H4 above, the distance H8 is less than zero, such as from about -2 nm to about 0 nm, indicating that ET is disposed below FT. In some embodiments, the distance H8 is greater than zero, such as from about 0 nm to about 3 nm, indicating that ET is disposed above FT. Additionally, due to the height H7, the reduced size of the source / drain component 146 results in an elongation of ET defined by the width W5' that is less than the width W4' of the source / drain component 142. Furthermore, the differences in size and shape between the source / drain component 142 and the source / drain component 146 can depend on factors such as the composition of the epitaxial layer, the separation distance between the fins (such as the distances S3 and S4), and / or the deposition conditions of the epitaxial process.

[0065] In the depicted embodiment, although source / drain component 132 and source / drain component 142 are formed to have similar dimensions and geometries, and source / drain component 136 and source / drain component 146 are formed to have similar dimensions and geometries, the present embodiment is not limited to these configurations. For example, the present invention is also applicable to an etching process similar to etching process 308 rather than etching process 302, in which source / drain component 142 is formed as a separated rather than a merged component. Similarly, by implementing an etching process similar to etching process 302 rather than etching process 308, source / drain component 146 can be formed as a merged rather than a separated component. In other words, since the four regions 102A - 102D are independently and separately processed, the method provided herein allows source / drain components of various shapes and sizes to be formed in different device regions, thereby meeting various design requirements. This advantage can be realized when existing methods for forming source / drain components in different device regions can no longer support at a reduced length scale.

[0066] Now returning to reference Figure 1 to block 212 and reference Figures 15A through 15G , method 200 continues by respectively replacing dummy gate stacks 112 and 114 with metal gate stacks 152 and 154. In the present embodiment, metal gate stack 152 is joined to a portion of fin 108A to form a first FET, such as a first p-type FET, and is joined to a portion of fin 108B to form a second FET of a different conductivity type from the first FET, such as a first n-type FET. Similarly, metal gate stack 154 is joined to a portion of fin 108C to form a third FET, such as a second p-type FET, and is joined to a portion of fin 108D to form a fourth FET of a different conductivity type from the third FET, such as a second n-type FET. Additionally, in the present embodiment, the first FET (or the second FET) and the third FET (or the fourth FET) are configured to perform different functions. For example, the first FET (or the second FET) can be configured as a logic device and the third FET (or the fourth FET) can be configured as a memory device. The formation of metal gate stacks 152 and 154 is described in detail below.

[0067] Method 220 may first deposit an interlayer dielectric (ILD) layer 150 over a workpiece 100 that includes source / drain components 132, 136, 142, and 146. The ILD layer 150 serves as an insulator that supports and isolates conductive traces formed over the workpiece 100. The ILD layer 150 may include any suitable dielectric material, such as silicon oxide, doped silicon oxide, such as borophosphosilicate glass (BPSG), tetraethyl orthosilicate (TEOS), undoped silicate glass, fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), low-k dielectric materials, other suitable dielectric materials, or combinations thereof. The ILD layer 150 may be deposited by any suitable method, such as plasma-enhanced CVD (PECVD), FCVD, SOG, other suitable deposition processes, or combinations thereof. Subsequently, a CMP process may be implemented to remove any excess dielectric material and planarize the top surface of the workpiece 100. Optionally, the hard mask 120 may be used as a polish stop layer during the CMP process and removed by an additional etching process after the CMP is implemented.

[0068] Subsequently, method 220 removes the dummy gate stacks 112 and 114 or portions thereof, separately or together, by a suitable selective etching process. The selective etching process is configured to remove dummy gate material, such as polysilicon, relative to the ILD layer 150, creating gate trenches (not depicted). The selective etching process may include any suitable etching technique, such as wet etching, dry etching, RIE, ashing, other etching methods, or combinations thereof. In one example, the selective etching process is a dry etching process that utilizes a fluorine-based etchant. In some embodiments, the selective etching process includes multiple etching steps that utilize different etching chemistries, each targeted at a specific material of the dummy gate layer.

[0069] Thereafter, method 220 fills the gate trenches with various gate materials, such as a gate dielectric layer (not shown separately) and a gate electrode (not shown separately), each including one or more material layers. The gate dielectric layer may include a high-k dielectric material, such as a metal oxide (e.g., LaO, AlO, ZrO, TiO, Ta2O5, Y2O3, SrTiO3 (STO), BaTiO3 (BTO), BaZrO, HfZrO, HfLaO, HfTaO, HfTiO, (Ba,Sr)TiO3 (BST), Al2O3, etc.), a metal silicate (e.g., HfSiO, LaSiO, AlSiO, etc.), other suitable materials, or combinations thereof. In some embodiments, the gate dielectric layer is deposited in the gate trenches by any suitable method, such as ALD, CVD, metal-organic CVD (MOCVD), PVD, other suitable methods, or combinations thereof. Subsequently, method 220 forms a gate electrode over the gate dielectric layer, where the gate electrode may include one or more work function metal layers and a metal fill layer over the work function metal layer. The work function metal layer may include a p-type work function metal layer or an n-type work function metal layer. Exemplary work function metal layers include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable work function materials, or combinations thereof. The work function metal layer may be deposited by CVD, PVD, other suitable processes, or combinations thereof. The metal fill layer may include aluminum (Al), tungsten (W), copper (Cu), cobalt (Co), ruthenium (Ru), other suitable materials, or combinations thereof. The metal fill layer may be formed by CVD, PVD, plating, other suitable processes, or combinations thereof. In some embodiments, method 220 forms other material layers, such as an interface layer, a barrier layer, a capping layer, and / or other suitable layers, as part of the metal gate stacks 152 and / or 154. After depositing the metal gate materials, one or more CMP processes are implemented to produce a substantially flat top surface of the metal gate stacks 152 and 154.

[0070] Reference Figure 1For the frame 214, the method 200 implements additional processing steps. For example, the method 200 may form source / drain contacts in the ILD layer disposed above the workpiece 100, where the source / drain contacts are configured to be electrically coupled to the source / drain components 132, 136, 142, and 146. Thereafter, the method 200 may continue to form an interconnect structure to couple the various devices of the workpiece 100 to the IC. The interconnect structure includes metal lines in a plurality of metal layers for horizontal coupling and vias / contacts for vertical coupling between adjacent metal layers or between the bottom metal layer and device components (such as source / drain components and metal gate stacks) on the substrate 102. The source / drain contacts and the interconnect structure may include one or more suitable conductive materials, such as Cu, Al, W, Co, Ru, metal silicides, metal nitrides, or other suitable conductive materials. The source / drain contacts and the interconnect structure may be formed by a damascene process, such as a single damascene process or a dual damascene process, which includes photolithographic patterning, etching, deposition, and CMP. The illustrated workpiece 100 is merely an example of some embodiments of the methods 200 and 220. Without departing from the scope of the present invention, the methods 200 and 220 may have various other embodiments.

[0071] The present invention provides a semiconductor structure and a method of manufacturing the same. The method includes different procedures for forming epitaxially grown source / drain components for respective devices. Although not intended to be limiting, one or more embodiments of the present invention provide many benefits for semiconductor devices including FinFETs and their formation. For example, in the present embodiment, at least two types of FinFETs are formed by different procedures. The first type may be a logic device, and the second type may be a memory (such as SRAM) device. Specifically, in the present embodiment, the source / drain components of the first type and the second type are formed by adjusting the height of their respective FSW spacers in different lithographic and etching processes, and then implementing their epitaxial growth processes between the respective FSW spacers at different heights to form source / drain components with different configurations. Thus, by separately adjusting the height of the FSW spacers for different FinFETs, source / drain components of different sizes and geometries can be achieved to realize various advantages, such as reduced contact resistance, increased contact area with the source / drain contacts, enhanced charge mobility due to strain effects on the channel region, and / or other advantages. In addition, the present invention provides design freedom to differently and independently process different FinFETs to meet their respective design specifications. However, it should be noted that the first type of FinFET and the second type of FinFET are not limited to logic devices and memory devices respectively, and may be other types of devices with different specifications. For example, according to various design considerations, the first type of FinFET may be a p-type device, and the second type of device may be an n-type FinFET, and vice versa.

[0072] In one aspect, the present invention provides a method, which includes: forming a first semiconductor fin in a first device region and a second semiconductor fin in a second device region above a substrate; forming a spacer layer above the substrate, wherein a first portion of the spacer layer is formed above the first semiconductor fin and a second portion of the spacer layer is formed above the second semiconductor fin; performing a first etching process to recess the first portion of the spacer layer relative to the second portion of the spacer layer, thereby forming a first fin spacer on sidewalls of the first semiconductor fin; forming a first epitaxial S / D component between the first fin spacers; subsequently performing a second etching process to recess the second portion of the spacer layer relative to the first portion of the spacer layer, thereby forming a second fin spacer on sidewalls of the second semiconductor fin, wherein the second fin spacer is formed to have a height greater than that of the first fin spacer; and forming a second epitaxial S / D component between the second fin spacers, wherein the second epitaxial S / D component is formed to have a size smaller than that of the first epitaxial S / D component.

[0073] In another aspect, the present invention provides a method, which includes: forming a first fin and a second fin protruding from a first region of a semiconductor substrate; forming a third fin protruding from a second region of the semiconductor substrate; forming a first pseudo-gate stack above the first fin and the second fin and a second pseudo-gate stack above the third fin; depositing a dielectric layer above the first pseudo-gate stack and the second pseudo-gate stack; forming a first source / drain (S / D) component above the first fin and the second fin, wherein the first S / D component incorporates the first fin and the second fin; forming a second S / D component above the third fin; and replacing the first pseudo-gate stack and the second pseudo-gate stack with a metal gate stack. In this embodiment, forming the first S / D component includes: performing a first etching process to remove portions of the dielectric layer located on sidewalls of the first fin and the second fin, thereby forming a first fin sidewall (FSW) spacer having a first height; recessing the first fin and the second fin; and performing a first epitaxial process to grow the first S / D component, thereby incorporating the recessed first fin and the second fin. In this embodiment, forming the second S / D component includes: performing a second etching process to remove portions of the dielectric layer located on sidewalls of the third fin, thereby forming a second FSW spacer having a second height, wherein the second height is greater than the first height, and wherein the first etching process and the second etching process use the same etchant; recessing the third fin; and performing a second epitaxial process to grow the second S / D component between the second FSW spacers.

[0074] In yet another aspect, the present invention provides a semiconductor structure, the semiconductor structure comprising: a first fin and a second fin extending from a semiconductor substrate; an isolation member disposed above the semiconductor substrate to separate the first fin and the second fin, wherein the first fin and the second fin have a fin height measured from the top surface of the isolation member; a first device located above the first fin; a second device located above the second fin; and an interlayer dielectric (ILD) layer located above the first device and the second device. In this embodiment, the first device comprises: a first gate stack engaged with a first channel region of the first fin; a first epitaxial source / drain (S / D) member disposed on opposite sides of the first channel region, wherein the first epitaxial S / D member merges the first fin together; and a first fin spacer disposed on sidewalls of the first epitaxial S / D member, wherein the first fin spacer has a first height measured from the top surface of the isolation member. In this embodiment, the second device comprises: a second gate stack engaged with a second channel region of the second fin; a second epitaxial S / D member disposed on opposite sides of the second channel region, and a second fin spacer disposed on sidewalls of the second epitaxial S / D member, wherein the second fin spacer has a second height greater than the first height measured from the top surface of the isolation member.

[0075] Some embodiments of the present application provide a method of forming a semiconductor structure, comprising: providing a substrate having a first device region and a second device region; forming a first semiconductor fin in the first device region and a second semiconductor fin in the second device region; forming a spacer layer above the substrate, wherein a first portion of the spacer layer is formed above the first semiconductor fin and a second portion of the spacer layer is formed above the second semiconductor fin; performing a first etching process to recess the first portion of the spacer layer relative to the second portion of the spacer layer, thereby forming a first fin spacer on sidewalls of the first semiconductor fin; etching the first semiconductor fin to form a first source / drain (S / D) groove between the first fin spacers; forming a first epitaxial source / drain member in the first source / drain groove; after forming the first epitaxial source / drain member, performing a second etching process to recess the second portion of the spacer layer relative to the first portion of the spacer layer, thereby forming a second fin spacer on sidewalls of the second semiconductor fin, wherein the second fin spacer is formed to have a height greater than a height of the first fin spacer; etching the second semiconductor fin to form a second source / drain groove between the second fin spacers; and forming a second epitaxial source / drain member in the second source / drain groove, wherein the second epitaxial source / drain member is formed to have a size smaller than a size of the first epitaxial source / drain member.

[0076] In some embodiments, the first semiconductor fin is configured to provide a logic device, and wherein the second semiconductor fin is configured to provide a memory device. In some embodiments, etching the first portion of the spacer layer includes: forming a patterned photoresist layer to expose the first portion of the spacer layer but not the second portion of the spacer layer; performing the first etching process; and removing the patterned photoresist layer from the substrate after forming the first epitaxial source / drain component and before performing the second etching process. In some embodiments, the patterned photoresist layer is a first patterned photoresist layer, and wherein etching the second portion of the spacer layer includes: forming a second patterned photoresist layer to expose the second portion of the spacer layer but not the first portion of the spacer layer; performing the second etching process; and removing the second patterned photoresist layer after forming the second epitaxial source / drain component. In some embodiments, performing the first etching process includes adjusting the bias power of the first etching process. In some embodiments, performing the second etching process includes intermittently applying an etchant. In some embodiments, intermittently applying the etchant includes cyclically recessing the second portion of the spacer layer and redepositing etch by-products over the second semiconductor fin. In some embodiments, the first semiconductor fin and the second semiconductor fin are configured to form devices of the same conduction type. In some embodiments, the first semiconductor fin and the second semiconductor fin are configured to form devices of different conduction types.

[0077] Some other embodiments of the present application provide a method for forming a semiconductor structure, including: forming a first fin and a second fin protruding from a first region of a semiconductor substrate; forming a third fin protruding from a second region of the semiconductor substrate; forming a first pseudo-gate stack above the first fin and the second fin and forming a second pseudo-gate stack above the third fin; depositing a dielectric layer above the first pseudo-gate stack and the second pseudo-gate stack; forming a first source / drain (S / D) component above the first fin and the second fin, including: performing a first etching process to remove a portion of the dielectric layer located on sidewalls of the first fin and the second fin, thereby forming a first fin sidewall (FSW) spacer having a first height, recessing the first fin and the second fin, and performing a first epitaxial process to grow the first source / drain component, thereby incorporating the recessed first fin and the second fin; forming a second source / drain component above the third fin, including: after forming the first source / drain component, performing a second etching process to remove a portion of the dielectric layer located on the sidewall of the third fin, thereby forming a second fin sidewall spacer having a second height, wherein the second height is greater than the first height, and wherein the first etching process and the second etching process use the same etchant, recessing the third fin, and performing a second epitaxial process to grow the second source / drain component between the second fin sidewall spacers; and replacing the first pseudo-gate stack and the second pseudo-gate stack with a metal gate stack.

[0078] In some embodiments, the first region and the second region provide devices with different functions, different conductivity types, or a combination thereof. In some embodiments, the first region and the second region provide devices with different functions but the same conductivity type. In some embodiments, the first fin, the second fin, and the third fin are formed to a fin height, and wherein the first height is formed to be less than half of the fin height, and the second height is formed to be at least half of the fin height. In some embodiments, the first etching process and the second etching process are respectively performed to form a first gate spacer on the sidewall of the first pseudo-gate stack and a second gate spacer on the sidewall of the second pseudo-gate stack. In some embodiments, the second gate spacer has a height greater than that of the first gate spacer.

[0079] Some further embodiments of the present application provide a semiconductor structure, comprising: a first fin and a second fin extending from a semiconductor substrate; an isolation member disposed above the semiconductor substrate to separate the first fin and the second fin, wherein the first fin and the second fin have a fin height measured from the top surface of the isolation member; a first device located above the first fin, the first device comprising: a first gate stack engaged with a first channel region of the first fin, a first epitaxial source / drain (S / D) member disposed on opposite sides of the first channel region, wherein the first epitaxial source / drain member merges the first fin together, and a first fin spacer disposed on the sidewalls of the first epitaxial source / drain member, wherein the first fin spacer has a first height measured from the top surface of the isolation member; a second device located above the second fin, the second device comprising: a second gate stack engaged with a second channel region of the second fin, a second epitaxial source / drain member disposed on opposite sides of the second channel region, and a second fin spacer disposed on the sidewalls of the second epitaxial source / drain member, wherein the second fin spacer has a second height greater than the first height measured from the top surface of the isolation member; and an interlayer dielectric (ILD) layer located above the first device and the second device, wherein the interlayer dielectric layer separates the second epitaxial source / drain member.

[0080] In some embodiments, the first device is a logic device and the second device is a memory device. In some embodiments, the top surface of the first epitaxial source / drain member is located above the top surface of the first fin. In some embodiments, the bottom surface of the first epitaxial source / drain member is located below the bottom surface of the second epitaxial source / drain member. In some embodiments, the width of the first epitaxial source / drain member is greater than the fin height.

[0081] The features of several embodiments are outlined above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that they can readily use the present invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructs do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the present invention.

Claims

1. A method of forming a semiconductor structure, comprising: Provide a substrate having a first device region and a second device region; Form a first semiconductor fin in the first device region and a second semiconductor fin in the second device region; Form a spacer layer over the substrate, wherein a first portion of the spacer layer is formed over the first semiconductor fin and a second portion of the spacer layer is formed over the second semiconductor fin; Perform a first etching process to recess the first portion of the spacer layer relative to the second portion of the spacer layer, thereby forming a first fin spacer on sidewalls of the first semiconductor fin; Etch the first semiconductor fin to form a first source / drain trench between the first fin spacers; Form a first epitaxial source / drain component in the first source / drain trench; After forming the first epitaxial source / drain component, perform a second etching process to recess the second portion of the spacer layer relative to the first portion of the spacer layer, including cyclically recessing the second portion of the spacer layer and redepositing etch by-products over the second semiconductor fin, thereby forming a second fin spacer on sidewalls of the second semiconductor fin, wherein the second fin spacer is formed to have a height greater than a height of the first fin spacer; Etch the second semiconductor fin to form a second source / drain trench between the second fin spacers; and Form a second epitaxial source / drain component in the second source / drain trench, wherein the second epitaxial source / drain component is formed to have a size smaller than a size of the first epitaxial source / drain component.

2. The method according to claim 1, wherein, The first semiconductor fin is configured to provide a logic device, and wherein the second semiconductor fin is configured to provide a memory device.

3. The method according to claim 1, wherein, Etching the first portion of the spacer layer includes: Forming a patterned photoresist layer to expose the first portion of the spacer layer but not expose the second portion of the spacer layer; Performing the first etching process; and After forming the first epitaxial source / drain component and before performing the second etching process, removing the patterned photoresist layer from the substrate.

4. The method according to claim 3, wherein, The patterned photoresist layer is a first patterned photoresist layer, and wherein etching the second portion of the spacer layer includes: Forming a second patterned photoresist layer to expose the second portion of the spacer layer but not expose the first portion of the spacer layer; Performing the second etching process; and After forming the second epitaxial source / drain component, removing the second patterned photoresist layer.

5. The method according to claim 1, wherein, Performing the first etching process includes adjusting a bias power of the first etching process.

6. The method according to claim 5, wherein, Performing the second etching process includes intermittently applying an etchant.

7. The method according to claim 6, wherein, Intermittently applying the etchant includes cyclically recessing the second portion of the spacer layer and redepositing etch by-products over the second semiconductor fin.

8. The method according to claim 1, wherein, The first semiconductor fin and the second semiconductor fin are configured to form devices of the same conductivity type.

9. The method according to claim 1, wherein, The first semiconductor fin and the second semiconductor fin are configured to form devices of different conductivity types.

10. A method of forming a semiconductor structure, comprising: Form a first fin and a second fin protruding from a first region of a semiconductor substrate; Form a third fin protruding from a second region of the semiconductor substrate; Form a first pseudo-gate stack above the first fin and the second fin and a second pseudo-gate stack above the third fin; Deposit a dielectric layer above the first pseudo-gate stack and the second pseudo-gate stack; Form a first source / drain component above the first fin and the second fin, including: Perform a first etching process to remove portions of the dielectric layer on sidewalls of the first fin and the second fin, thereby forming first fin sidewall spacers having a first height, Recess the first fin and the second fin, and Perform a first epitaxial process to grow the first source / drain component, thereby incorporating the recessed first fin and the second fin; Form a second source / drain component above the third fin, including: After forming the first source / drain component, perform a second etching process to remove portions of the dielectric layer on sidewalls of the third fin, including cyclically recessing the portions of the dielectric layer on sidewalls of the third fin and redepositing etch by-products above the third fin, thereby forming second fin sidewall spacers having a second height, wherein the second height is greater than the first height, and wherein the first etching process and the second etching process use the same etchant, Recess the third fin, and Perform a second epitaxial process to grow the second source / drain component between the second fin sidewall spacers; and Replace the first pseudo-gate stack and the second pseudo-gate stack with metal gate stacks.

11. The method according to claim 10, wherein, The first region and the second region provide devices with different functions, different conduction types, or a combination thereof.

12. The method according to claim 10, wherein, The first region and the second region provide devices with different functions but the same conduction type.

13. The method according to claim 10, wherein, The first fin, the second fin, and the third fin are formed to a fin height, and wherein the first height is formed to be less than half of the fin height, and the second height is formed to be at least half of the fin height.

14. The method according to claim 10, wherein, Perform the first etching process and the second etching process to form first gate spacers on sidewalls of the first pseudo-gate stack and second gate spacers on sidewalls of the second pseudo-gate stack, respectively.

15. The method according to claim 14, wherein, The second gate spacer has a height greater than that of the first gate spacer.

16. A semiconductor structure, comprising: A first fin and a second fin extend from a semiconductor substrate; An isolation component is disposed above the semiconductor substrate to separate the first fin and the second fin, wherein the first fin and the second fin have a fin height measured from a top surface of the isolation component; A first device is located above the first fin, and the first device includes: A first gate stack is joined to a first channel region of the first fin, A first epitaxial source / drain component is disposed on opposite sides of the first channel region, wherein the first epitaxial source / drain component incorporates the first fin together, and A first fin spacer is disposed on a sidewall of the first epitaxial source / drain component, wherein the first fin spacer has a first height measured from the top surface of the isolation component; A second device is located above the second fin, and the second device includes: A second gate stack is joined to a second channel region of the second fin, A second epitaxial source / drain component is disposed on opposite sides of the second channel region, and A second fin spacer is disposed on a sidewall of the second epitaxial source / drain component, wherein the second fin spacer is formed by repeating a cycle of recess and re-deposition and has a second height greater than the first height measured from the top surface of the isolation component, and a top surface of the second fin spacer is adjusted to have a relatively flat rather than a circular profile; and An interlayer dielectric layer is located above the first device and the second device, wherein the interlayer dielectric layer separates the second epitaxial source / drain components.

17. The semiconductor structure according to claim 16, wherein, The first device is a logic device and the second device is a memory device.

18. The semiconductor structure according to claim 16, wherein, A top surface of the first epitaxial source / drain component is located above a top surface of the first fin.

19. The semiconductor structure according to claim 16, wherein, A bottom surface of the first epitaxial source / drain component is located below a bottom surface of the second epitaxial source / drain component.

20. The semiconductor structure according to claim 16, wherein, A width of the first epitaxial source / drain component is greater than the fin height.

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