A unidirectional thyristor electrostatic protection device with an embedded N+ injection region in an isolation layer

Abstract

The present invention discloses a unidirectional thyristor electrostatic protection device with an embedded N+ injection region in an isolation layer. The present invention adds an N+ injection region connected to an anode in a shallow N well. When the device is reversely conducted, a parasitic diode is formed with the cathode, so that the reverse path does not need to pass through an isolation ring, and static electricity tends to be discharged from the parasitic diode, thereby reducing the on-resistance of the reverse conduction path, and can effectively improve the reverse failure current and reverse current discharge capacity of the device; the unidirectional thyristor electrostatic release device of the present invention has the characteristics of low on-resistance, and can achieve a high protection level while effectively improving the reverse failure current and reverse current discharge capacity of the device.

Description

Technical Field

[0001] The invention relates to the field of electrostatic protection, and in particular to a unidirectional silicon controlled electrostatic protection device with an isolation layer and an embedded N+ injection region. Background Art

[0002] Electrostatic Discharge ( Electro Static Discharge, ESD ) The phenomenon refers to the accumulation of a certain value of charge in the external environment or internal structure of an integrated circuit chip during its manufacture, transportation, and use. All processes may occur on the integrated circuit pins. As the integration of integrated circuit manufacturing processes becomes higher and higher, the harm caused by ESD to chips and electronic products is also increasing, and the economic losses caused by this are as high as tens of billions of dollars. Therefore, solving the harm caused by ESD to chips has become one of the important problems faced by chip engineers in various countries.

[0003] ESD electrostatic protection devices are currently one of the effective means to solve the damage caused by ESD to chips. They protect circuits by being connected in parallel with the protected circuits. When the protected circuits are working normally, the ESD electrostatic protection devices are in a closed state and do not affect the normal operation of the circuits. When ESD occurs, the ESD electrostatic protection devices are turned on before the circuits, providing a discharge path for the ESD circuits and protecting the circuits from damage by ESD.

[0004] Silicon Controlled Rectifier (SCR) is one of the commonly used device structures for ESD protection. Figure 1 is a cross-sectional view of an existing unidirectional SCR device. Figure 2 This is the forward and reverse equivalent circuit diagram of the existing unidirectional SCR device. Due to its own positive feedback structure, it has the advantages of strong current discharge capability, strong robustness, high protection level, etc., and is widely used in high-performance, high-protection level circuits; however, the problem of its high reverse conduction resistance is also the reason that restricts the application of SCR devices in circuits. Summary of the invention

[0005] The invention provides a unidirectional thyristor electrostatic protection device with an embedded N+ injection region in an isolation layer, which improves the reverse failure current and reverse current discharge capacity of the device.

[0006] To achieve the above object, the technical solution of the embodiment of the present invention is implemented as follows:

[0007] An embodiment of the present invention provides a unidirectional thyristor electrostatic protection device with an isolation layer and an embedded N+ injection region, comprising a P-type substrate;

[0008] A P-type epitaxial layer is provided above the P-type substrate, and an N-type buried layer is provided between the P-type substrate and the P-type epitaxial layer;

[0009] A first high-voltage N-well and a second high-voltage N-well are arranged above the N-type buried layer from left to right;

[0010] A first deep N-well is provided above the first high-voltage N-well, and a second deep N-well is provided above the second high-voltage N-well;

[0011] A first shallow P well is provided on the left side of the first deep N well, a first shallow N well is provided in the upper right part of the first deep N well, a second shallow P well is provided between the first deep N well and the second deep N well, a second shallow N well is provided above the second deep N well, and a third shallow P well is provided on the right side of the second deep N well;

[0012] The first shallow P well is provided with a first P+ injection region; the first shallow N well is provided with a first N+ injection region; the second shallow P well is provided with a second P+ injection region and a second N+ injection region from left to right, the second shallow N well is provided with a third N+ injection region and a third N+ injection region from left to right; the third shallow P well is provided with a fourth P+ injection region;

[0013] The first P+ injection region, the second P+ injection region, the second N+ injection region and the fourth P+ injection region are connected together and serve as the cathode of the device; the first N+ injection region, the third P+ injection region and the third N+ injection region are connected together and serve as the anode of the device.

[0014] Among them, a first field oxygen isolation region is provided between the left side of the first P+ injection region and the left edge of the P-type epitaxial layer, a second field oxygen isolation region is provided between the right side of the first P+ injection region and the left side of the first N+ injection region, a third field oxygen isolation region is provided between the right side of the first N+ injection region and the left side of the second P+ injection region, a fourth field oxygen isolation region is provided between the right side of the second P+ injection region and the left side of the second N+ injection region, a fifth field oxygen isolation region is provided between the right side of the second N+ injection region and the left side of the third P+ injection region, a sixth field oxygen isolation region is provided between the right side of the third P+ injection region and the left side of the third N+ injection region, a seventh field oxygen isolation region is provided between the right side of the third N+ injection region and the left side of the fourth P+ injection region, and an eighth field oxygen isolation region is provided between the right side of the fourth P+ injection region and the right edge of the P-type epitaxial layer.

[0015] Among them, the left part of the first field oxygen isolation region is located on the surface of the left edge of the P-type epitaxial layer, and the right part of the first field oxygen isolation region is located on the surface of the first P+ injection region; the left part of the eighth field oxygen isolation region is located on the surface of the fourth P+ injection region, and the right part of the eighth field oxygen isolation region is located on the surface of the right edge of the P-type epitaxial layer.

[0016] Wherein, the equivalent circuit of the electrostatic protection device includes:

[0017] a first NPN transistor, wherein the second N+ implantation region serves as an emitter of the first NPN transistor, the second shallow P-well serves as a base of the first NPN transistor, and the second shallow N-well, the second deep N-well and the second high-voltage N-well serve as a collector of the first NPN transistor;

[0018] a first PNP transistor, wherein the third P+ implant serves as an emitter of the first PNP transistor, the second shallow N-well, the second deep N-well and the second high-voltage N-well serve as a base of the first PNP transistor, and the second shallow P-well serves as a collector of the first PNP transistor;

[0019] a first diode, wherein the second shallow P-well serves as a P-terminal of the first diode, and the first shallow N-well serves as an N-terminal of the first diode;

[0020] a second diode, wherein the second shallow P-well serves as a P-terminal of the second diode, and the second shallow N-well serves as an N-terminal of the second diode;

[0021] a first shallow P-well parasitic resistor formed in a second shallow P-well;

[0022] A first shallow N-well parasitic resistor is formed in the second shallow N-well.

[0023] Among them, the equivalent circuit of the electrostatic protection device includes: one end of the first shallow P-well parasitic resistor is connected to the second P+ injection area, the other end of the first shallow P-well parasitic resistor, the base of the first NPN transistor, the collector of the first PNP transistor and one end of the second shallow N-well parasitic resistor are connected together, the emitter of the first NPN transistor is connected to the second N+ injection area, the collector of the first NPN transistor and the base of the first PNP transistor are connected together, the emitter of the first PNP transistor is connected to the third P+ injection area, and the other end of the second shallow N-well parasitic resistor is connected to the third N+ injection area; the first shallow P-well parasitic resistor, the first NPN transistor, the second shallow N-well parasitic resistor and the first PNP transistor together constitute a forward SCR current discharge path.

[0024] Among them, it includes: the N end of the first diode is connected to one end of the first shallow N-well parasitic resistor, the other end of the first shallow N-well parasitic resistor is connected to the first N+ injection region, the P end of the first diode, one end of the first shallow P-well parasitic resistor and the P end of the second diode are connected together, the other end of the first shallow P-well parasitic resistor is connected to the second P+ injection region, the N end of the second diode is connected to one end of the second shallow N-well parasitic resistor, and the other end of the second shallow N-well parasitic resistor is connected to the third N+ injection region; the first diode, the first shallow N-well parasitic resistor, the first shallow P-well parasitic resistor, the second shallow N-well parasitic resistor and the second diode together constitute a reverse SCR current discharge path.

[0025] Among them, when the ESD high-voltage pulse reaches the anode of the device and the cathode of the device is grounded, the second shallow N-well and the P-type epitaxial layer and the second shallow P-well undergo avalanche breakdown, and the avalanche carriers flow through the first shallow P-well parasitic resistance. When the voltage drop across the first shallow P-well parasitic resistance is greater than 0.7V, the first NPN transistor is turned on, so the base potential of the first PNP transistor drops and turns on. Finally, the first PNP transistor and the first NPN transistor form positive feedback, and the forward SCR path opens the discharge current.

[0026] When the ESD high voltage pulse reaches the cathode of the device and the anode of the device is grounded, the first diode and the second diode are connected in parallel and start to discharge current, which can reduce the on-resistance in the original path and improve the reverse failure current and reverse current discharge capability of the device.

[0027] An embodiment of the present invention provides a unidirectional thyristor electrostatic protection device with an embedded N+ injection region in an isolation layer. The N+ injection region is embedded in the isolation layer, so that the reverse path becomes two diodes in parallel. In this way, compared with the traditional unidirectional SCR device, the present invention increases the number of diodes in the reverse path while reducing the on-resistance of the reverse path, thereby improving the reverse failure current and reverse current discharge capacity of the unidirectional SCR device. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is a cross-sectional view of a currently known unidirectional SCR electrostatic protection device;

[0029] Figure 2 This is the forward and reverse equivalent circuit diagram of the currently known unidirectional SCR electrostatic protection device;

[0030] Figure 3a A cross-sectional view of the forward current path of a unidirectional thyristor electrostatic protection device with an isolation layer and an embedded N+ injection region provided in an embodiment of the present invention;

[0031] Figure 3bA cross-sectional view of the reverse current path of a unidirectional thyristor electrostatic protection device with an isolation layer and an embedded N+ injection region provided in an embodiment of the present invention;

[0032] Figure 4 The forward and reverse equivalent circuit diagram of a unidirectional thyristor electrostatic protection device with an isolation layer and an embedded N+ injection region provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0033] The present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used in the specification of the present invention herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0035] like Figure 3a and Figure 3b As shown, the present invention provides a unidirectional thyristor electrostatic protection device with an embedded N+ injection region in an isolation layer, comprising a P-type substrate 100; a P-type epitaxial layer 300 is provided above the P-type substrate, and an N-type buried layer 200 is provided between the P-type substrate 100 and the P-type epitaxial layer 300; a first high-voltage N-well 401 and a second high-voltage N-well 401 are provided above the N-type buried layer 200 from left to right; a first deep N-well 501 is provided above the first high-voltage N-well 401, and a second deep N-well 502 is provided above the second high-voltage N-well 402; a first shallow P-well 601 is provided on the left side of the first deep N-well 501, a first shallow N-well 602 is provided in the upper right of the first deep N-well 501, a second shallow P-well 603 is provided between the first deep N-well 501 and the second deep N-well 502, and a second shallow N-well 604 is provided above the second deep N-well 502. , a third shallow P well 605 is provided on the right side of the second deep N well 502; a first P+ injection region 701 is provided in the first shallow P well 601; a first N+ injection region 702 is provided in the first shallow N well 602; a second P+ injection region 703 and a second N+ injection region 704 are provided in the second shallow P well 603 from left to right, and a third P+ injection region 705 and a third N+ injection region 706 are provided in the second shallow N well 604 from left to right; a fourth P+ injection region 707 is provided in the third shallow P well 605; the first P+ injection region 701, the second P+ injection region 703, the second N+ injection region 704 and the fourth P+ injection region 707 are connected together and serve as the cathode of the device; the first N+ injection region 702, the third P+ injection region 705 and the third N+ injection region 706 are connected together and serve as the anode of the device.

[0036] A first field oxygen isolation region 801 is provided between the left side of the first P+ implantation region 701 and the left edge of the P-type epitaxial layer 300, a second field oxygen isolation region 802 is provided between the right side of the first P+ implantation region 701 and the left side of the first N+ implantation region 702, a third field oxygen isolation region 803 is provided between the right side of the first N+ implantation region 702 and the left side of the second P+ implantation region 703, a fourth field oxygen isolation region 804 is provided between the right side of the second P+ implantation region 703 and the left side of the second N+ implantation region 704, A fifth field oxygen isolation region 805 is provided between the right side of the second N+ injection region 704 and the left side of the third P+ injection region 705, a sixth field oxygen isolation region 806 is provided between the right side of the third P+ injection region 705 and the left side of the third N+ injection region 706, a seventh field oxygen isolation region 807 is provided between the right side of the third N+ injection region 706 and the left side of the fourth P+ injection region 707, and an eighth field oxygen isolation region 808 is provided between the right side of the fourth P+ injection region 707 and the right edge of the P-type epitaxial layer 300.

[0037] The left portion of the first field oxygen isolation region 801 is located at the surface of the left edge of the P-type epitaxial layer 300, and the right portion of the first field oxygen isolation region 801 is located at the surface of the first P+ injection region 701; the left portion of the eighth field oxygen isolation region 808 is located at the surface of the fourth P+ injection region 707, and the right portion of the eighth field oxygen isolation region 808 is located at the surface of the right edge of the P-type epitaxial layer 300.

[0038] like Figure 4 As shown, the equivalent circuit of the electrostatic protection device includes: a first NPN transistor T1, wherein the second N+ injection region 704 serves as the emitter of the first NPN transistor T1, the second shallow P well 603 serves as the base of the first NPN transistor T1, the second shallow N well 604, the second deep N well 502 and the second high-voltage N well 402 serve as the collector of the first NPN transistor T1; a first PNP transistor T2, wherein the third P+ injection region 705 serves as the emitter of the first PNP transistor T2, the second shallow N well 604, the second deep N well 502 and the second high-voltage N well 402 serve as the base of the first PNP transistor T2, and the third P+ injection region 706 serves as the emitter of the first PNP transistor T2. The second shallow P-well 603 is used as the collector of the first PNP transistor T2; the first diode BJT1, wherein the second shallow P-well 603 is used as the P-end of the first diode BJT1, and the first shallow N-well 602 is used as the N-end of the first diode BJT1; the second diode BJT2, wherein the second shallow P-well 603 is used as the P-end of the second diode BJT2, and the second shallow N-well 604 is used as the N-end of the second diode BJT2; the first shallow N-well parasitic resistor Rn1 formed in the first shallow N-well 602; the first shallow P-well parasitic resistor Rp formed in the second shallow P-well 603; the second shallow N-well parasitic resistor Rn2 formed in the second shallow N-well 604;

[0039] One end of the first shallow P-well parasitic resistor Rp is connected to the second P+ injection region 603, the other end of the first shallow P-well parasitic resistor Rp, the base of the first NPN transistor T1, the collector of the first PNP transistor T2 and one end of the second shallow N-well parasitic resistor Rn2 are connected together, the emitter of the first NPN transistor T1 is connected to the second N+ injection region 704, the collector of the first NPN transistor T1 and the base of the first PNP transistor T2 are connected together, the emitter of the first PNP transistor T2 is connected to the third P+ injection region 705, and the other end of the second shallow N-well parasitic resistor Rn2 is connected to the third N+ injection region 706; the first shallow P-well parasitic resistor Rp, the first NPN transistor T1, the second shallow N-well parasitic resistor Rn2 and the first PNP transistor T2 together constitute a forward SCR current discharge path;

[0040] The N-terminal of the first diode BJT1 is connected to one end of the first shallow N-well parasitic resistor Rn1, and the other end of the first shallow N-well parasitic resistor Rn1 is connected to the first N+ injection region 702. The P-terminal of the first diode BJT1, one end of the first shallow P-well parasitic resistor Rp and the P-terminal of the second diode BJT2 are connected together, and the other end of the first shallow P-well parasitic resistor Rp is connected to the second P+ injection region 703. The N-terminal of the second diode BJT2 is connected to one end of the second shallow N-well parasitic resistor Rn2, and the other end of the second shallow N-well parasitic resistor Rn2 is connected to the third N+ injection region 706. The first diode BJT1, the first shallow N-well parasitic resistor Rn1, the first shallow P-well parasitic resistor Rp, the second shallow N-well parasitic resistor Rn2 and the second diode BJT2 together constitute a reverse SCR current discharge path.

[0041] When the ESD high-voltage pulse reaches the anode of the device and the cathode of the device is grounded, the second shallow N-well 604 and the P-type epitaxial layer 300 and the second shallow P-well 603 undergo avalanche breakdown, and the avalanche carriers flow through the first shallow P-well parasitic resistor Rp. When the voltage drop across the first shallow P-well parasitic resistor Rp is greater than 0.7V, the first NPN-type transistor T1 is turned on, so the base potential of the first PNP-type transistor T2 drops and turns on. Finally, the first PNP-type transistor T2 and the first NPN-type transistor T1 form positive feedback, and the positive SCR path opens to discharge current.

[0042] When the ESD high voltage pulse reaches the cathode of the device and the anode of the device is grounded, the first diode BJT1 and the second diode BJT2 are connected in parallel and start to discharge current, which can reduce the on-resistance in the original path and improve the reverse failure current and reverse current discharge capability of the device.

[0043] Compared with the existing unidirectional SCR device, the unidirectional thyristor electrostatic protection device with an embedded N+ injection region in the isolation layer manufactured by the present invention has an embedded N+ injection region in the isolation layer without increasing the device area, so that the reverse failure current and reverse current discharge capacity of the device are improved. The application of this new SCR device in ESD protection design can effectively protect the internal circuit of the chip and ensure a high protection level.

Claims

1. A unidirectional thyristor electrostatic protection device with an embedded N+ injection region in an isolation layer, characterized in that: including a P-type substrate; A P-type epitaxial layer is provided above the P-type substrate, and an N-type buried layer is provided between the P-type substrate and the P-type epitaxial layer; A first high-voltage N-well and a second high-voltage N-well are sequentially arranged above the N-type buried layer from left to right; A first deep N-well is provided above the first high-voltage N-well, and a second deep N-well is provided above the second high-voltage N-well; A first shallow P well is provided on the left side of the first deep N well, a first shallow N well is provided in the upper right part of the first deep N well, a second shallow P well is provided between the first deep N well and the second deep N well, a second shallow N well is provided above the second deep N well, and a third shallow P well is provided on the right side of the second deep N well; A first P+ injection region is provided in the first shallow P well; a first N+ injection region is provided in the first shallow N well; A second P+ injection region and a second N+ injection region are sequentially provided in the second shallow P well from left to right, and a third P+ injection region and a third N+ injection region are sequentially provided in the second shallow N well from left to right; A fourth P+ injection region is provided in the third shallow P well; The first P+ injection region, the second P+ injection region, the second N+ injection region and the fourth P+ injection region are connected together and serve as the cathode of the device; the first N+ injection region, the third P+ injection region and the third N+ injection region are connected together and serve as the anode of the device.

2. The one-way thyristor electrostatic protection device with an embedded N+ injection region in an isolation layer according to claim 1, characterized in that: A first field oxygen isolation region is provided between the left side of the first P+ injection region and the left edge of the P-type epitaxial layer, a second field oxygen isolation region is provided between the right side of the first P+ injection region and the left side of the first N+ injection region, a third field oxygen isolation region is provided between the right side of the first N+ injection region and the left side of the second P+ injection region, a fourth field oxygen isolation region is provided between the right side of the second P+ injection region and the left side of the second N+ injection region, a fifth field oxygen isolation region is provided between the right side of the second N+ injection region and the left side of the third P+ injection region, a sixth field oxygen isolation region is provided between the right side of the third P+ injection region and the left side of the third N+ injection region, a seventh field oxygen isolation region is provided between the right side of the third N+ injection region and the left side of the fourth P+ injection region, and an eighth field oxygen isolation region is provided between the right side of the fourth P+ injection region and the right edge of the P-type epitaxial layer.

3. The one-way thyristor electrostatic protection device with an embedded N+ injection region in an isolation layer according to claim 2, characterized in that: The left portion of the first field oxygen isolation region is located on the surface of the left edge of the P-type epitaxial layer, and the right portion of the first field oxygen isolation region is located on the surface of the first P+ injection region; the left portion of the eighth field oxygen isolation region is located on the surface of the fourth P+ injection region, and the right portion of the eighth field oxygen isolation region is located on the surface of the right edge of the P-type epitaxial layer.

4. The one-way thyristor electrostatic protection device with an embedded N+ injection region in an isolation layer according to claim 3, characterized in that: The equivalent circuit of the electrostatic protection device includes: a first NPN transistor, wherein the second N+ implantation region serves as an emitter of the first NPN transistor, the second shallow P-well serves as a base of the first NPN transistor, and the second shallow N-well, the second deep N-well and the second high-voltage N-well serve as a collector of the first NPN transistor; a first PNP transistor, wherein the third P+ implant serves as an emitter of the first PNP transistor, the second shallow N-well, the second deep N-well and the second high-voltage N-well serve as a base of the first PNP transistor, and the second shallow P-well serves as a collector of the first PNP transistor; a first diode, wherein the second shallow P-well serves as a P-terminal of the first diode, and the first shallow N-well serves as an N-terminal of the first diode; a second diode, wherein the second shallow P-well serves as a P-terminal of the second diode, and the second shallow N-well serves as an N-terminal of the second diode; a first shallow N-well parasitic resistor formed in the first shallow N-well; a first shallow P-well parasitic resistor formed in a second shallow P-well; A second shallow N-well parasitic resistor is formed in the second shallow N-well.

5. The one-way thyristor electrostatic protection device with an embedded N+ injection region in an isolation layer according to claim 4, characterized in that: The equivalent circuit of the electrostatic protection device includes: one end of the first shallow P-well parasitic resistor is connected to the second P+ injection region, the other end of the first shallow P-well parasitic resistor, the base of the first NPN transistor, the collector of the first PNP transistor and one end of the second shallow N-well parasitic resistor are connected together, the emitter of the first NPN transistor is connected to the second N+ injection region, the collector of the first NPN transistor and the base of the first PNP transistor are connected together, the emitter of the first PNP transistor is connected to the third P+ injection region, and the other end of the second shallow N-well parasitic resistor is connected to the third N+ injection region; the first shallow P-well parasitic resistor, the first NPN transistor, the second shallow N-well parasitic resistor and the first PNP transistor together constitute a forward SCR current discharge path.

6. The one-way thyristor electrostatic protection device with an embedded N+ injection region in an isolation layer according to claim 5, characterized in that: The equivalent circuit of the electrostatic protection device includes: the N terminal of the first diode is connected to one end of the first shallow N-well parasitic resistor, the other end of the first shallow N-well parasitic resistor is connected to the first N+ injection region, the P terminal of the first diode, one end of the first shallow P-well parasitic resistor and the P terminal of the second diode are connected together, the other end of the first shallow P-well parasitic resistor is connected to the second P+ injection region, the N terminal of the second diode is connected to one end of the second shallow N-well parasitic resistor, and the other end of the second shallow N-well parasitic resistor is connected to the third N+ injection region; the first diode, the first shallow N-well parasitic resistor, the first shallow P-well parasitic resistor, the second shallow N-well parasitic resistor and the second diode together constitute a reverse SCR current discharge path.

7. The one-way thyristor electrostatic protection device with an embedded N+ injection region in an isolation layer according to claim 5, characterized in that: When the ESD high-voltage pulse reaches the anode of the device and the cathode of the device is grounded, avalanche breakdown occurs between the second shallow N-well and the P-type epitaxial layer and the second shallow P-well, and avalanche carriers flow through the first shallow P-well parasitic resistance. When the voltage drop across the first shallow P-well parasitic resistance is greater than 0.7V, the first NPN-type transistor is turned on, so the base potential of the first PNP-type transistor drops and turns on. Finally, the first PNP-type transistor and the first NPN-type transistor form positive feedback, and the forward SCR path opens to discharge current.

8. The one-way thyristor electrostatic protection device with an embedded N+ injection region in an isolation layer according to claim 7, characterized in that: When an ESD high voltage pulse reaches the cathode of the device and the anode of the device is grounded, the first diode and the second diode are connected in parallel and start to discharge current.

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