Display substrate and manufacturing method thereof, and display device

Abstract

A display substrate is provided, comprising a display area, the hole edge area, at least one wiring area, at least one through hole area and at least one blind hole area, wherein at least one wiring area surrounds a through hole area or a blind hole area, the hole edge area surrounds the wiring area, and the display area surrounds the hole edge area, wherein the display substrate comprises: a base substrate and a driving circuit layer arranged on the base substrate. The base substrate has an opening in the through hole area. The driving circuit layer comprises: at least one metal layer and at least one insulating layer, wherein at least one metal layer is located in the display area and the wiring area; the at least one metal layer comprises a plurality of signal lines, and the plurality of signal lines are arranged to avoid the through hole area and the blind hole area. At least one insulating layer is located in the display area, the hole edge area, the wiring area and the blind hole area. The blind hole area is light-transmissive.

Description

Technical Field

[0001] The present disclosure belongs to the field of display technology, and in particular relates to a display substrate and a preparation method thereof, and a display device. Background Art

[0002] In display devices, grooves and holes are usually dug in flexible panels to meet users' increasing requirements for screen-to-body ratio of electronic devices. Currently, a relatively mature technology that can increase the screen-to-body ratio of display panels is the in-screen hole technology.

[0003] The in-screen hole technology requires sacrificing part of the display area (Active Area) of the display panel. The sacrificed display area is used to arrange optical sensors such as cameras and sensors. Summary of the invention

[0004] On the one hand, a display substrate is provided, comprising a display area, a hole edge area, at least one wiring area, at least one through hole area and at least one blind hole area, wherein the at least one wiring area surrounds a through hole area or a blind hole area, the hole edge area surrounds the wiring area, and the display area surrounds the hole edge area, wherein the display substrate comprises: a base substrate and a driving circuit layer disposed on the base substrate. The base substrate has an opening in the through hole area.

[0005] The driving circuit layer includes: at least one metal layer and at least one insulating layer, at least one metal layer is located in the display area, the hole edge area and the wiring area; the at least one metal layer includes a plurality of signal lines, and the plurality of signal lines are arranged to avoid the through hole area and the blind hole area. At least one insulating layer is located in the display area, the hole edge area, the wiring area and the blind hole area. The blind hole area is light-transmissive.

[0006] In some embodiments, the at least one through-hole region includes two through-hole regions, the at least one blind-hole region includes one blind-hole region, and the blind-hole region is disposed between the two through-hole regions.

[0007] In some embodiments, the shape of the through hole area is circular or elliptical; the shape of the blind hole area is rectangular, rounded rectangle, a shape of rectangles of different widths spliced ​​along their length, or a shape of rounded rectangles of different widths spliced ​​along their length.

[0008] In some embodiments, the plurality of signal lines include a plurality of data lines and a plurality of gate drive signal lines. The plurality of gate drive signal lines extend in a first direction as a whole; the plurality of data lines extend in a second direction as a whole. The first direction intersects the second direction.

[0009] At least one data line includes a portion located in the wiring area and arranged around the through-hole area and / or a portion arranged around the blind hole area; at least one gate drive signal line includes a portion located in the wiring area and arranged around the through-hole area and / or a portion arranged around the blind hole area.

[0010] In some embodiments, the multiple signal lines also include multiple initialization signal lines; the multiple initialization signal lines extend as a whole along the first direction; at least one initialization signal line includes a portion located in the wiring area and arranged around the through hole area and / or a portion arranged around the blind hole area.

[0011] In some embodiments, the plurality of signal lines further include a plurality of light-emitting control signal lines; the plurality of light-emitting control signal lines extend in a first direction as a whole. At least one light-emitting control signal line includes a portion located in the wiring area and arranged around the through-hole area and / or a portion arranged around the blind-hole area; or, at least one light-emitting control signal line is located in the display area and the hole edge area, and is cut off at a position extending along the first direction to the through-hole area and / or the blind-hole area.

[0012] In some embodiments, the at least one metal layer includes a first gate layer, a second gate layer and a source-drain metal layer; the at least one insulating layer includes a first insulating layer, a second insulating layer and an interlayer insulating layer. The driving circuit layer also includes a semiconductor layer; the semiconductor layer is located in the display area and the hole edge area.

[0013] The semiconductor layer is arranged on one side of the substrate; the first insulating layer is arranged on the side of the semiconductor layer away from the substrate; the first gate layer is arranged on the side of the first insulating layer away from the substrate; the second insulating layer is arranged on the side of the first gate layer away from the substrate; the second gate layer is arranged on the side of the second insulating layer away from the substrate; the interlayer insulating layer is arranged on the side of the second gate layer away from the substrate; the source-drain metal layer is arranged on the side of the second gate layer away from the substrate.

[0014] In some embodiments, when the multiple signal lines include multiple data lines, multiple light-emitting control signal lines, multiple gate drive signal lines and multiple initialization signal lines, the multiple data lines are located in the source-drain metal layer; the multiple light-emitting control signal lines and the multiple gate drive signal lines are located in the first gate layer; and the multiple initialization signal lines are located in the second gate layer.

[0015] In some embodiments, the display substrate further comprises: a light emitting device layer disposed on a side of the driving circuit layer away from the base substrate; the light emitting device layer is located in the display area and the hole edge area.

[0016] The light-emitting device layer includes: a first electrode layer, a pixel defining layer, a functional layer and a second electrode layer. The first electrode layer is arranged on the side of the driving circuit layer away from the base substrate, and the first electrode layer includes a plurality of first electrodes. The pixel defining layer is arranged on the side of the first electrode layer away from the base substrate, and a plurality of openings are arranged in the pixel defining layer, and each opening exposes at least a portion of a first electrode. The functional layer is arranged on the side of the first electrode layer away from the base substrate, and the functional layer includes a plurality of light-emitting portions, and each light-emitting portion is located in an opening. The second electrode layer is arranged on the side of the functional layer and the pixel defining layer away from the base substrate.

[0017] The display area is provided with a plurality of pixel structures, each pixel structure includes a pixel circuit and a light-emitting device; the light-emitting device includes a first electrode electrically connected to the pixel circuit, a light-emitting portion and a portion of the second electrode layer corresponding to the light-emitting portion.

[0018] The hole edge area is provided with a plurality of redundant pixel structures; each redundant pixel structure includes a redundant pixel circuit and / or a redundant light-emitting device; the redundant light-emitting device includes a light-emitting portion and a portion of the second electrode layer corresponding to the light-emitting portion; or, the redundant light-emitting device includes a first electrode, a light-emitting portion and a portion of the second electrode layer corresponding to the light-emitting portion, and the first electrode is not electrically connected to the redundant pixel circuit.

[0019] In some embodiments, the pixel circuit and the redundant pixel circuit each include at least one thin film transistor, and the thin film transistor includes an active layer, a gate, a source, and a drain.

[0020] The active layer is located in the semiconductor layer, the gate is located in the first gate layer, the source and the drain are located in the source-drain metal layer; the hole edge area includes a first sub-area close to the wiring area, and a second sub-area other than the first sub-area.

[0021] The display substrate further includes: a plurality of via holes arranged in the second sub-region of the hole edge region and a plurality of redundant via holes arranged in the first sub-region of the hole edge region. Each via hole penetrates the first insulating layer, the second insulating layer and the interlayer insulating layer; the plurality of redundant pixel circuits are arranged in the second sub-region of the hole edge region, and the source and drain of each thin film transistor in the plurality of redundant pixel circuits are electrically connected to the active layer through two of the via holes. Each redundant via hole penetrates the first insulating layer, the second insulating layer and the interlayer insulating layer.

[0022] The display substrate further includes: a planarization layer disposed between the driving circuit layer and the light-emitting device layer, the planarization layer being located in the display area, the hole edge area, the wiring area and the blind hole area; a portion of the planarization layer fills the plurality of redundant vias.

[0023] In some embodiments, the display substrate further comprises at least one encapsulation dam area; each encapsulation dam area is located between a through hole area and a wiring area surrounding the through hole area, and surrounds the through hole area. The first insulating layer, the second insulating layer and the interlayer insulating layer are also located in the at least one encapsulation dam area.

[0024] The display substrate further comprises: a plurality of packaging dams; each packaging dam area is provided with at least one packaging dam, the packaging dam surrounds the through hole area, and the packaging dam is provided on a side of the driving circuit layer away from the base substrate. In the case where each packaging dam area is provided with at least two packaging dams, the at least two packaging dams are sequentially spaced apart along the radial direction of the through hole area.

[0025] The display substrate further comprises: at least one encapsulation dam disposed in each encapsulation dam region comprises a first encapsulation dam and a second encapsulation dam, wherein the first encapsulation dam is located on a side of the second encapsulation dam away from the through hole region, and the thickness of the second encapsulation dam along a third direction is greater than the thickness of the first encapsulation dam along the third direction; wherein the third direction is perpendicular to the base substrate.

[0026] The second encapsulation dam includes: a first portion, a second portion and a first spacer portion; the first portion is disposed on the same layer as the planarization layer; the second portion is disposed on a side of the first portion away from the base substrate; the second portion is disposed on the same layer as the pixel definition layer. The first spacer portion is disposed on a side of the second portion away from the base substrate.

[0027] The first encapsulation dam includes: a third portion and a second spacer portion; the third portion is arranged in the same layer as the pixel defining layer; the second spacer portion is arranged on a side of the third portion away from the base substrate, and the second spacer portion is made of the same material as the first spacer portion and is arranged in the same layer.

[0028] In some embodiments, the display substrate further includes at least one first isolation region and at least one second isolation region; the first insulating layer, the second insulating layer and the interlayer insulating layer are also located in the at least one first isolation region and the at least one second isolation region.

[0029] Each first isolation region is located between the wiring region and the packaging dam region and surrounds the packaging dam region; each second isolation region is located between the through hole region and the packaging dam region and surrounds the through hole region.

[0030] The display substrate further includes: a plurality of first isolation columns and a plurality of second isolation columns, each first isolation region is provided with at least one first isolation column, each first isolation column is arranged around the first encapsulation dam, and the first isolation column is arranged on a side of the interlayer insulating layer away from the base substrate; a groove is arranged on the sidewall of the first isolation column. Each second isolation region is provided with at least one second isolation column, each second isolation column is arranged around the through hole region, and the second isolation column is arranged on a side of the interlayer insulating layer away from the base substrate; a groove is arranged on the sidewall of the second isolation column.

[0031] In some embodiments, the first isolation column and the second isolation column are located in the source-drain metal layer.

[0032] In some embodiments, the first isolation column and the second isolation column both include a first metal pattern, a second metal pattern, and a third metal pattern stacked in sequence, and an outer boundary of an orthographic projection of the second metal pattern on the base substrate is located inside an outer boundary of an orthographic projection of the first metal pattern and the third metal pattern on the base substrate, so as to form the groove on the sidewalls of the first isolation column and the sidewalls of the second isolation column.

[0033] In some embodiments, the second isolation region is further provided with at least one fourth metal pattern and at least one fifth metal pattern, the fourth metal pattern is located in the first gate layer, and the fifth metal pattern is located in the second gate layer. Each fourth metal pattern and each fifth metal pattern surround the through-hole region. The orthographic projections of the second isolation column, the fourth metal pattern and the fifth metal pattern on the substrate have a common overlapping area.

[0034] In some embodiments, when at least two first isolation columns are provided in each first isolation region, the at least two first isolation columns are sequentially spaced apart along a radial direction of the through hole region.

[0035] The portion of the driving circuit layer located between two connected first isolation columns has a first groove, and the first groove exposes the base substrate; when at least two second isolation columns are provided in each second isolation area, the at least two second isolation columns are arranged in sequence and spaced apart along the radial direction of the through-hole area; the portion of the driving circuit layer located between two adjacent second isolation columns has a recess.

[0036] In some embodiments, the display substrate further includes an encapsulation layer disposed on a side of the light-emitting device layer away from the base substrate.

[0037] The encapsulation layer includes: a first inorganic encapsulation film layer, an organic encapsulation film layer, and a second inorganic encapsulation film layer. The first inorganic encapsulation film layer is arranged on the side of the light-emitting device layer away from the substrate substrate; the first inorganic encapsulation film layer is located in the second isolation area, the encapsulation dam area, the first isolation area, the wiring area, the hole edge area, the display area, and the blind hole area. The organic encapsulation film layer is arranged on the side of the first inorganic encapsulation film layer away from the substrate substrate; the organic encapsulation film layer is located in the encapsulation dam area, the first isolation area, the wiring area, the hole edge area, the display area, and the blind hole area. The second inorganic encapsulation film layer is arranged on the side of the organic encapsulation film layer away from the substrate substrate; the second inorganic encapsulation film layer encapsulates the second isolation area, the encapsulation dam area, the first isolation area, the wiring area, the hole edge area, the display area, and the blind hole area.

[0038] On the other hand, a display device is provided, comprising the display substrate as described in any one of the above aspects, at least one first sensor and at least one second sensor, each first sensor is arranged in a through hole area; each second sensor is arranged in a blind hole area.

[0039] In some embodiments, the at least one first sensor comprises a camera, and the at least one second sensor comprises at least one of an infrared sensor, a proximity light sensor, a flood illuminator, and an ambient light sensor.

[0040] On the other hand, a method for preparing a display substrate is provided, comprising: providing a base substrate; the base substrate comprises a display area, a hole edge area, at least one wiring area, at least one through hole area and at least one blind hole area, the at least one wiring area surrounds a through hole area or a blind hole area, the hole edge area surrounds the wiring area, and the display area surrounds the hole edge area.

[0041] A driving circuit layer is formed on the base substrate; the driving circuit layer includes: at least one metal layer and at least one insulating layer, at least one metal layer is located in the display area, the hole edge area, the wiring area and the hole edge area; the at least one metal layer includes a plurality of signal lines, and the plurality of signal lines are arranged to avoid the through hole area and the blind hole area. At least one insulating layer is located in the display area, the hole edge area, the wiring area, the through hole area and the blind hole area;

[0042] A planarization layer is formed on a side of the driving circuit layer away from the base substrate, and the planarization layer is located in the display area, the hole edge area, the wiring area, the through hole area, and the blind hole area. A light-emitting device layer is formed on a side of the planarization layer away from the base substrate; the light-emitting device layer is located in the display area and the hole edge area.

[0043] An encapsulation layer is formed on a side of the light emitting device layer away from the base substrate; the encapsulation layer is located in the display area, the hole edge area, the wiring area, the through hole area and the blind hole area. The base substrate, the driving circuit layer, the planarization layer and the encapsulation layer are removed from the through hole area. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required to be used in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the product involved in the embodiments of the present disclosure, the actual process of the method, the actual timing of the signal, etc.

[0045] Figure 1 is a top view of a display substrate according to some embodiments of the present disclosure;

[0046] Figure 2 is a schematic diagram of an overall circuit architecture of a display substrate according to some embodiments of the present disclosure;

[0047] Figure 3 for Figure 1 An enlarged view of the middle region G1;

[0048] Figure 4 for Figure 1 Another magnified view of the middle region G1;

[0049] Figure 5 for Figure 1 Another enlarged view of the middle region G1;

[0050] Figure 6 for Figure 3 A cross-sectional view along the section line A-A';

[0051] Figure 7 A cross-sectional view of a display substrate before cutting through hole areas and blind hole areas according to some embodiments of the present disclosure;

[0052] Fig. 8A is a wiring diagram of a region G1 of a display substrate according to an embodiment of the present disclosure;

[0053] Figure 8B is another wiring diagram of the region G1 of the display substrate according to an embodiment of the present disclosure;

[0054] Figure 8C is another wiring diagram of the region G1 of the display substrate according to an embodiment of the present disclosure;

[0055] Fig. 9 for Figure 4 Enlarged view of middle region G2;

[0056] Fig.10 for Fig. 9 Enlarged view of middle region G7;

[0057] Fig.11 for Figure 4 Enlarged view of middle region G3;

[0058] Fig.12 for Fig.10 Enlarged view of middle region G8;

[0059] Fig.13 is an equivalent circuit diagram of a pixel circuit in a display substrate according to an embodiment of the present disclosure;

[0060] Fig.14A for Figure 7 Enlarged view of middle region G6;

[0061] Fig. 14B for Figure 7 Enlarged view of middle region G4';

[0062] Fig.15 is a cross-sectional view of a display area of ​​a display substrate according to some embodiments of the present disclosure;

[0063] Fig.16 is a cross-sectional view of a display area of ​​another display substrate according to some embodiments of the present disclosure;

[0064] Fig.17 is a cross-sectional view of a hole edge region of a display substrate according to some embodiments of the present disclosure;

[0065] Fig.18 is a cross-sectional view of a hole edge region of another display substrate according to some embodiments of the present disclosure;

[0066] Fig.19 for Figure 7 Enlarged view of middle region G4;

[0067] Fig. 20 for Figure 7 Enlarged view of middle area G5;

[0068] Fig.21 The present invention is a flow chart of a method for preparing a display substrate according to an embodiment of the present invention. DETAILED DESCRIPTION

[0069] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0070] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and other forms thereof, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open, inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0071] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0072] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0073] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0074] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0075] The use of "adapted to" or "configured to" herein is meant to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0076] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0077] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0078] The display device includes a display substrate and an optical sensor. Taking a mobile phone as an example, the display device includes optical sensors such as a camera, a proximity light sensor, and a 3D sensing module. These optical components need to receive light from the display surface side of the display device to achieve corresponding functions. In the display device, it is usually necessary to open a hole in the display substrate to embed the optical sensor in the display substrate.

[0079] The display substrate includes a display area and a frame area located on at least one side of the display area. In some embodiments, the holes opened in the display substrate by the opening technology include two types: punch holes and blind holes. Both the punch holes and the blind holes are opened in the display area. The advantage of the through-hole design is that there is no film layer at the opening to block the optical sensor, so the light transmittance is high, which is suitable for placing devices with high transmittance requirements such as cameras. At the blind hole, a transparent film layer is still retained at the actual opening. The transmittance of the blind hole is lower than the transmittance of the through hole without a film layer, but higher than the transmittance of the display area of ​​the display substrate. It is usually used to place components with slightly lower transmittance requirements, such as light sensors.

[0080] In the preparation process of the display substrate, it is necessary to cut the stacked multiple film layers to form through holes. Therefore, the through hole design needs to add a packaging structure around the through hole to ensure the reliability of the product. The packaging structure has a large size and occupies a part of the space, thereby reducing the area of ​​the display area, which is not conducive to improving the screen-to-body ratio. Therefore, the number of through holes opened in the display area is limited; while the blind hole design does not require a packaging structure to be set around the blind hole, and will not occupy too much area of ​​the display area. At present, the inventor has found that the relevant products are only provided with through holes or only with blind holes. For display products that are only provided with through holes, the through hole position is only used to place optical sensors with higher transmittance requirements such as cameras, and the remaining optical sensors need to be placed in the frame area of ​​the display substrate, occupying the frame size, which is not conducive to the narrowing of the frame of the display substrate. For display products that are only provided with blind holes, if an optical sensor with higher transmittance requirements is set in the blind hole, the working effect of the optical sensor will be affected due to the loss of transmittance, for example, causing the camera imaging quality to be slightly poor.

[0081] Based on this, some embodiments of the present disclosure provide a display substrate and a display device, in which through holes and blind holes are simultaneously arranged in the display substrate. By combining the design of through holes and blind holes, the advantages of the transmittance of through holes and the advantages of blind holes that do not require a packaging structure, the screen-to-body ratio of the display substrate is increased and the border is reduced without losing the working effect of the optical sensor.

[0082] like Figure 1 As shown, some embodiments of the present disclosure provide a display substrate 100, which can be, for example, an OLED (Organic Light-Emitting Diode) display substrate, a micro organic light-emitting diode (MicroOrganic Light-Emitting Diode, Micro OLED) display substrate, a quantum dot organic light-emitting diode (QuantumDot Light Emitting Diodes, QLED) display substrate, a mini light-emitting diode (Mini Light-Emitting Diode, Mini LED) display substrate or a micro light-emitting diode (Micro Light-Emitting Diode, Micro LED) display substrate, etc.

[0083] The display substrate 100 includes a display area 10a, a frame area 10b, at least one wiring area 10c, at least one through-hole area 10d, and at least one blind hole area 10e, wherein the at least one wiring area 10c surrounds one through-hole area 10d or one blind hole area 10e, each wiring area 10c surrounds one through-hole area 10d or one blind hole area 10e, and the display area 10a surrounds the wiring area 10c. That is, the number of the wiring areas 10c is equal to the sum of the number of the at least one through-hole area 10d and the at least one blind hole area 10e.

[0084] Among them, each wiring area 10c surrounds a through hole area 10d or a blind hole area 10e, which means that each wiring area 10c is arranged around a through hole area 10d, or each wiring area 10c is arranged around a blind hole area 10e, and the display area 10a surrounds the wiring area 10c, which means that the display area 10a is located outside the wiring area 10c.

[0085] In some embodiments, Figure 1 , Figure 3 to Figure 5 As shown, the display substrate 100 also includes a hole edge area 10f located between the display area 10a and the at least one wiring area 10c. It can be understood that there is a closed area G1 in the display area 10a. For example, the closed area G1 is in a capsule shape. The closed area G1 includes at least one wiring area 10c, at least one through hole area 10d and at least one blind hole area 10e and a hole edge area 10f, wherein the display area 10a surrounds the hole edge area 10f, the hole edge area 10f surrounds the at least one wiring area 10c, the hole edge area 10f is in contact with the display area 10a and the at least one wiring area 10c, each wiring area 10c surrounds a through hole area 10d or a blind hole area 10e, and the frame area 10b surrounds the display area 10a.

[0086] The display substrate 100 includes a plurality of sub-pixels and a plurality of signal lines, wherein each through-hole area 10b is provided with a through-hole, each blind-hole area 10c is provided with a blind-hole, at least one wiring area 10c is used to set a signal line, and only a signal line is set without setting a sub-pixel and any structure in the sub-pixel, and a plurality of signal lines are densely arranged in at least one wiring area 10c. The display area 10a is used to set a plurality of sub-pixels, each of which includes a pixel structure, so that the display area 10a can display, and the hole edge area 10f is used to set a plurality of redundant pixel structures, and the hole edge area 10f cannot display. Of course, the plurality of signal lines included in the display substrate 100 are also set in the display area 10a and the hole edge area 10f.

[0087] The number, position, size and shape of at least one through hole area 10d and at least one blind hole area 10e can be set according to actual needs, for example, according to the number of optical sensors with higher transmittance requirements and the number of optical sensors with lower transmittance requirements among the optical sensors included in the display device.

[0088] For example, Figure 1 , Figure 3 and Figure 4 As shown, the display substrate 100 includes two through-hole areas 10d and one blind hole area 10e, and the blind hole area 10e is arranged between the two through-hole areas 10d, so that the display substrate 100 includes three wiring areas 10c, wherein two wiring areas 10c surround the two through-hole areas 10d respectively, and another wiring area 10c surrounds the blind hole area 10e. In other examples, the blind hole area is not arranged between the through-hole areas, but is arranged on one side of two adjacent through-hole areas.

[0089] against Figure 3 and Figure 4 According to the design, the two cameras can be placed in the two through holes of the two through hole areas 10d respectively, and other optical sensors can be placed in the blind holes of the blind hole area 10e.

[0090] In some embodiments, the shape of the blind hole and the through hole can be circular, rectangular, or other regular or irregular shapes. For example, the shape of the through hole area 10d is circular, elliptical, or a combination of a rectangle and a double semicircle; the shape of the blind hole area 10e is rectangular, rounded rectangle, a combination of rectangles of different widths along the length direction, or a combination of rounded rectangles of different widths along the length direction. Figure 3 As shown, the through hole area 10d is circular in shape, the through holes in the through hole area 10d are circular in shape, the blind hole area 10e is a rounded rectangle in shape, and the blind holes in the blind hole area 10c are also rounded rectangles in shape. Figure 4 As shown, the through hole area 10d is circular in shape, the through holes in the through hole area 10d are circular in shape, and the blind hole area 10e is a shape formed by splicing two rounded rectangles of different widths along their length direction, and the two rounded rectangles of different sizes are spliced ​​to form a shape similar to a milk bottle. Figure 5 As shown, the two through-hole regions 10d are respectively a large through-hole region 10d1 and a small through-hole region 10d2 adjacent to each other. The large through-hole region 10d1 is in the shape of a rounded rectangle, and the small through-hole region 10d2 is in the shape of a circle.

[0091] The dimensions of the through holes and blind holes can be set as required, e.g. Figure 3 and Figure 4 As shown, when the through hole or blind hole is circular, its diameter can be in the range of 2mm to 4mm. Figure 3As shown, the diameter of the circular through hole can be in the range of 2 mm to 4 mm, and the length and width dimensions of the irregular-shaped blind hole need to be matched with the dimensions of the circular through hole as required. Figure 5 As shown, the length of the large through hole area 10d1 can be in the range of 9mm to 10mm, and the width can be 4mm; the diameter of the small through hole area 10d2 can be 4mm. The left part of the large through hole area 10d1 can be used to place a camera, and the right part can be used to place an optical sensor.

[0092] In some embodiments, Figure 3 and Figure 4 As shown, the display substrate 100 further includes at least one encapsulation area 10g, each encapsulation area 10g is located between a through-hole area 10d and a wiring area 10c surrounding the through-hole area 10d, and surrounds the through-hole area 10d, that is, the number of encapsulation areas 10g is equal to the number of through-hole areas 10d. When the through-hole area 10d is circular in shape, the corresponding encapsulation area 10g is annular in shape. A packaging structure is arranged in each encapsulation area 10g, and the packaging structure is arranged around the through-hole area 10d.

[0093] In some examples, each packaging area 10g includes a packaging dam area 10g3, that is, the display substrate 100 includes at least one packaging dam area 10g3, each packaging dam area 10g3 is located between a through hole area 10d and a wiring area 10c surrounding the through hole area 10d, and surrounds the through hole area 10d. Each packaging dam area 10g3 is provided with at least one packaging dam, and each packaging dam is provided around the through hole area 10d.

[0094] In some examples, each encapsulation region 10g further includes a first isolation region 10g1 and a second isolation region 10g2, that is, the display substrate 100 further includes at least one first isolation region 10g1 and at least one second isolation region 10g2; each first isolation region 10g1 is located between a wiring region 10c and a encapsulation dam region 10g3, and surrounds the encapsulation dam region 10g3; each second isolation region 10g2 is located between a through hole region 10d and a encapsulation dam region 10g3, and surrounds the through hole region 10d. Each first isolation region 10g1 is provided with at least one first isolation column, and each second isolation region 10g2 is provided with at least one second isolation column.

[0095] The at least one packaging dam, the at least one first isolation column and the at least one second isolation column constitute a packaging structure.

[0096] like Figure 3 and Figure 4 As shown, along the center of a through hole area 10d toward the outside, a second isolation area 10g2, a packaging dam area 10g3, a first isolation area 10g1 and a wiring area 10c are sequentially arranged around it.

[0097] like Figure 3 and Figure 4 As shown, for the spacing between the through hole area 10d and the blind hole area 10e, and as Figure 5 As shown, when setting the spacing between two adjacent through-hole areas 10d, it is necessary to ensure that space in the packaging area 10g is reserved to set up the packaging structure.

[0098] In summary, if Figure 6 As shown, in the display substrate 100 provided by some embodiments of the present disclosure, by setting at least one through hole area 10d and at least one blind hole area 10e, a through hole is set in the through hole area 10d, and a blind hole is set in the blind hole area 10e, so that the through hole and the blind hole are set in the display substrate 100 at the same time. In this way, through the design of the combination of the through hole and the blind hole, the optical sensor 200 with a higher transmittance requirement such as a camera can be placed in the through hole, and the optical sensor 300 with a lower transmittance requirement such as an infrared sensor, a proximity light sensor, a floodlight illuminator, and an ambient light sensor can be placed in the blind hole, so that the optical requirements of different optical sensors can be met, for example, the imaging quality of the camera can be improved. Since the blind hole does not need to be provided with a packaging structure, and does not need to be provided with a packaging area corresponding to the blind hole area, compared with the through hole design, the area of ​​the closed area does not need to be too large, so that the area of ​​the display area 10a can be guaranteed, and the integrity of the display screen is guaranteed, and the optical sensor does not need to be set in the frame area, and the size of the frame area can be reduced, which is conducive to narrowing the frame of the display substrate and improving the screen ratio of the display substrate.

[0099] like Figure 6 As shown, an optical sensor 200 requiring high light transmittance, such as a camera, can be arranged on a side of the display substrate away from the driving circuit layer, facing the through hole, and can extend into the through hole; an optical sensor 300 with lower light transmittance, such as an infrared sensor, a proximity light sensor, a flood illuminator, and an ambient light sensor, can be arranged on a side of the display substrate, facing the blind hole, and the optical sensor 300 with high light transmittance and the optical sensor 300 with lower light transmittance are arranged on the same side of the display substrate 100.

[0100] In the following embodiments of the present disclosure, Figure 3 and Figure 4 The arrangement of the through hole area 10d and the blind hole area 10e is taken as an example to introduce the specific structure of the display substrate 100.

[0101] Among them, Figure 1As shown, the display substrate 100 includes a display area 10a, and the display area 10a has a closed area G1. The display substrate 100 includes two through-hole areas 10d, a blind hole area 10e, two second isolation areas 10g2, two packaging dam areas 10g3, two first isolation areas 10g1, three wiring areas 10c and a hole edge area 10f located in the closed area G1. The blind hole area 10e is located between the two through-hole areas 10d. Each through-hole area 10d is circular in shape. Around a through-hole area 10d, a wiring area 10c, a second isolation area 10g2, a packaging dam area 10g3 and a first isolation area 10g1 are sequentially arranged. The wiring area 10c, the second isolation area 10g2, the packaging dam area 10g3 and the first isolation area 10g1 are all in the shape of a ring, and a wiring area 10c in the middle surrounds the blind hole area 10e. The areas within the closed area G1 except for two through-hole areas 10d, one blind hole area 10e, two second isolation areas 10g2, two package dam areas 10g3, two first isolation areas 10g1 and two wiring areas 10c are all hole edge areas 10f.

[0102] The overall circuit structure of the display substrate is first introduced below.

[0103] like Figure 2 As shown, 1001 represents the overall outer contour of the display substrate 100; the display substrate includes a display area (i.e., a pixel array area) 10a and a peripheral area 10b located around the display area 10a. The display substrate 100 includes a plurality of sub-pixels P located in the display area 10a, a plurality of data lines DL, a plurality of light emitting control signal lines EL, and a plurality of gate driving signal lines GL. Exemplarily, a plurality of sub-pixels P are arranged in an array, for example, a plurality of sub-pixels P are arranged in M ​​rows and N columns, a plurality of light-emitting control signal lines EL and a plurality of gate drive signal lines GL are extended along a first direction X, for example, a plurality of light-emitting control signal lines EL are E1-EM (M is an integer greater than 1), a plurality of gate drive signal lines GL are G1-GM (M is an integer greater than 1), a plurality of data lines DL are extended along a second direction Y, for example, a plurality of data lines DL are D1-DN (N is an integer greater than 1), each control signal line EL is electrically connected to a row of sub-pixels P, a gate drive signal line GL is electrically connected to a row of sub-pixels P, and each data line DL is electrically connected to a column of sub-pixels P. The first direction X and the second direction Y intersect, and the angle between the first direction X and the second direction Y is, for example, 90°.

[0104] The display substrate 100 further includes a gate driving circuit 101 and a light emitting control circuit 102 located in the peripheral area 10b. The gate driving circuit 101 includes a plurality of cascaded shift registers 1011, for example, the plurality of shift registers 1011 are respectively arranged on both sides of the display area 10a, and the shift registers 1011 of the same level are electrically connected to a gate driving signal line GL. The gate driving circuit 101 is configured to provide, for example, a gate scanning signal shifted row by row to the plurality of sub-pixels P. The light emitting control circuit 102 includes a plurality of cascaded light emitting control units 1021, for example, the plurality of light emitting control units 1021 are respectively arranged on both sides of the display area 10a, and the light emitting control units 1021 of the same level are electrically connected to a plurality of light emitting control signal lines EL, and the light emitting control circuit 102 is configured to provide, for example, a light emitting control signal shifted row by row to the plurality of sub-pixels P.

[0105] The plurality of data lines DL are electrically connected to the source driver 103 , and the source driver 103 is configured to provide data signals to the plurality of sub-pixels P through the plurality of data lines DL.

[0106] Each sub-pixel P includes a pixel structure 1, and each pixel structure 1 includes a pixel circuit 11 and a light-emitting device 12; illustratively, the pixel circuit 11 may be a circuit structure having 7T1C, 8T2C or 4T1C in the art, and the light-emitting device 12 may be, for example, an organic light-emitting diode (OLED) or a quantum dot light-emitting diode (QLED). The pixel circuit 11 operates under the control of a data signal transmitted through a data line DL, a gate scanning signal transmitted through a gate drive signal line GL, and a light-emitting control signal transmitted through a light-emitting control signal line EL, so as to drive the light-emitting element to emit light, thereby realizing operations such as display.

[0107] It should be noted that, for the convenience of description, Figure 2 The overall circuit structure of the display substrate shown and the above description are explained by taking the case where the closed area G1 is not provided in the display area 10a as an example. In the case where the closed area G1 is not provided in the display area 10a, the plurality of data lines DL, the plurality of light-emitting control signal lines EL and the plurality of gate drive signal lines GL need to avoid the through hole area 10d and the blind hole area 10e. No sub-pixel P capable of emitting light is provided in the closed area G1.

[0108] The film structure of the display panel 100 is described below.

[0109] like Figure 7 As shown, the display substrate 100 includes: a base substrate 2 and a driving circuit layer 3 arranged on the base substrate 2 .

[0110] It should be noted that the preparation of the through holes and openings in the display substrate 100 is usually to complete the preparation of all the film layer structures included in the display substrate 100, and then remove the film layers in the corresponding areas. For example, all the stacked layers in the through hole area 10d are cut and all the film layers in the through hole area 10d are removed, or part of the stacked layers in the blind hole area 10e are cut and part of the film layers in the blind hole area 10e are removed. Figure 7 The cross-sectional view of the display substrate 100 shown is a structural view of the display substrate 100 before the cutting step, and the portion to be cut and removed is marked in the figure.

[0111] The base substrate 2 has an opening in the through hole area 10d. For example, when the display substrate 100 includes two through hole areas 10d, the base substrate 2 has two openings. Exemplarily, the base substrate 2 includes a stacked substrate 21 and a buffer layer 22. And the base substrate 2 can be other composite base substrates. For example, the base substrate 2 is a flexible substrate.

[0112] The driving circuit layer 3 includes at least one metal layer 31 and at least one insulating layer 32 .

[0113] Among them, at least one insulating layer 32 is located in the display area 10a, the wiring area 10c and the blind hole area 10e; the material of at least one insulating layer 32 is a light-transmitting material to ensure the light transmittance of the blind hole area 10e.

[0114] In some embodiments, at least one insulating layer 32 is also located in the hole edge region 10 f and the packaging region 10 .

[0115] At least one metal layer 31 is located in the display area 10a and the wiring area 10c. In some examples, at least one metal layer 31 is also located in the hole edge area 10f. Figure 8A to Figure 8C As shown, the at least one metal layer 21 includes a plurality of signal lines, for example, the plurality of signal lines are a plurality of data lines DL, a plurality of light emitting control signal lines EL, a plurality of gate driving signal lines GL and a plurality of initialization signal lines VINT.

[0116] The at least one metal layer 31 is not disposed in the blind hole area 10e to avoid blocking light and affecting the light transmittance of the blind hole area 10e. The plurality of signal lines are disposed away from the through hole area 10d and the blind hole area 10e.

[0117] Exemplarily, the arrangement of the plurality of signal lines avoiding the through-hole area 10d and the blind-hole area 10e includes: at least a portion of at least one of the plurality of signal lines is routed around the through-hole area 10d and / or the blind-hole area 10e to avoid the through-hole area 10d and the blind-hole area 10e. Alternatively, at least one of the plurality of signal lines is cut off at a position passing through the through-hole area 10d and / or the blind-hole area 10e to avoid the through-hole area 10d and the blind-hole area 10e.

[0118] In some examples, such as Figure 8A to Figure 8C As shown, the plurality of data lines DL extend as a whole along the second direction Y, and the plurality of light emitting control signal lines EL, the plurality of gate driving signal lines GL and the plurality of initialization signal lines VINT extend as a whole along the first direction X. The extension direction of the plurality of signal lines in the present disclosure refers to the overall extension trend of the plurality of signal lines, that is, the overall direction of the plurality of signal lines is along a certain direction, and is not affected by the fact that a portion of the signal lines located in the closed area G1 is arranged around the through hole area 10d and / or the blind hole area 10e.

[0119] The following description is based on the assumption that two through hole regions 10d and one blind hole region 10e are arranged along the first direction X.

[0120] like Fig. 8A , Figures 9 to 11 As shown, at least one data line DL includes a portion located in the wiring area 10c and arranged around the through-hole area 10d and / or arranged around the blind hole area 10e, and the other portions of this data line DL are located in the display area 10a and the wiring area 10f. For example, in the case of no hole digging, a plurality of data lines DL that should have passed through the closed area G1 in a straight line along the second direction Y need to be arranged around the through-hole area 10d or around the blind hole area 10e to avoid the through-hole area 10d and the blind hole area 10e. At least one data line DL includes a portion arranged around the through-hole area 10d, and the portion is an arc. Since the encapsulation area 10g is arranged around the through-hole area 10d, the portion of the data line DL arranged around the through-hole area 10d is actually arranged around the encapsulation area 10g. At least one data line DL includes a portion arranged around the blind hole area 10e, and the portion is a combination of an arc and a straight line.

[0121] Except for at least one data line DL passing through the closed area G1 , other data lines DL are disposed in the display area 10 a , and each data line DL extends along the second direction Y and straightly passes through the display area 10 a .

[0122] like Fig. 8A , Figures 9 to 11As shown, at least one initialization signal line VINT includes a portion located in the wiring area 10c and arranged around the through-hole area 10d and / or arranged around the blind-hole area 10e, and the other portion of this initialization signal line VINT is located in the display area 10a and the wiring area 10f. For example, the initialization signal line VINT that should have passed through the closed area G1 in a straight line along the first direction X without digging a hole needs to be arranged around the through-hole area 10d and around the blind-hole area 10e to avoid the through-hole area 10d and the blind-hole area 10e, and at least one light-emitting control signal line EL includes a portion arranged around the through-hole area 10d and a portion arranged around the blind-hole area 10e. Since a packaging area 10g is arranged around the through-hole area 10d, the portion of the initialization signal line VINT that runs around the through-hole area 10d actually runs around the packaging area 10g. This portion successively runs around the packaging area 10g around the first through-hole area 10d, around the blind hole area 10e, and then around the packaging area 10g around the second through-hole area 10d.

[0123] Except for at least one initialization signal line VINT passing through the closed area G1 , other initialization signal lines VINT are disposed in the display area 10 a , and each initialization signal line VINT extends along the first direction X and passes straight through the display area 10 a .

[0124] like Fig. 8A , Figures 9 to 11 As shown, at least one gate drive signal line GL includes a portion located in the wiring area 10c and arranged around the through hole area 10d and / or a portion arranged around the blind hole area 10e, and the other portion of this gate drive signal line GL is located in the display area 10a and the wiring area 10f. For example, the gate drive signal line GL that should originally go straight through the closed area G1 along the first direction X without digging a hole needs to go around the through-hole area 10d and the blind-hole area 10e to avoid the through-hole area 10d and the blind-hole area 10e. At least one gate drive signal line GL includes a portion that goes around the through-hole area 10d and a portion that goes around the blind-hole area 10e. Since a packaging area 10g is provided around the through-hole area 10d, the portion of the gate drive signal line GL that goes around the through-hole area 10d actually goes around the packaging area 10g. This portion successively goes around the packaging area 10g around the first through-hole area 10d, goes around the blind-hole area 10e, and then goes around the packaging area 10g around the second through-hole area 10d.

[0125] Except for at least one gate driving signal line GL passing through the closed area G1 , other gate driving signal lines GL are disposed in the display area 10 a , and each gate driving signal line GL extends along the first direction X and passes straight through the display area 10 a .

[0126] For the light emission control signal line EL, in some embodiments, as Figure 8B As shown, at least one light-emitting control signal line EL includes a portion located in the wiring area 10c and arranged around the through-hole area 10d and / or a portion arranged around the blind-hole area 10e, and the other portion of the light-emitting control signal line EL is located in the display area 10a and the wiring area 10f. For example, the light-emitting control signal line EL that should originally pass through the closed area G1 in a straight line along the first direction X without digging a hole needs to be arranged around the through-hole area 10d and around the blind-hole area 10e, and at least one light-emitting control signal line EL includes a portion arranged around the through-hole area 10d and a portion arranged around the blind-hole area 10e. Since the through-hole area 10d is surrounded by a packaging area 10g, the portion of the light-emitting control signal line EL arranged around the through-hole area 10d is actually arranged around the packaging area 10g, and the portion is arranged around the packaging area 10g around the first through-hole area 10d, around the blind-hole area 10e, and then around the packaging area 10g around the second through-hole area 10d.

[0127] In other embodiments, Figure 4 , Figure 8C , Figures 9 to 11 As shown, at least one light emitting control signal line EL includes portions located in the display area 10a and the hole edge area 10c, and is cut off at a position extending to the through hole area 10d and the blind hole area 10e along the first direction X. The light emitting control signal line EL does not include a portion located in the wiring area 10c.

[0128] like Figure 4 and Figure 8C As shown in FIG. 1 , the light-emitting control signal line EL, which should have passed through the closed area G1 in the first direction X without drilling holes, is cut off at the position where it extends to the through hole area 10d and the blind hole area 10e. Figure 4 and Figure 8C In FIG. 1 , the thin dotted line indicates the light control signal line EL that should originally pass through the closed area G1 along the first direction X, and the thick solid line indicates the truncated light control signal line EL. It can be seen that the light control signal line EL is truncated into multiple parts.

[0129] For example, Figure 4 and Figure 8C As shown, among the at least one light emitting control signal line EL passing through the closed area G1, each light emitting control signal line EL includes a first light emitting control signal line EL1 and a second light emitting control signal line EL2. Fig.11As shown, the first light-emitting control signal line EL1 of each light-emitting control signal line EL is located in the display area 10a and the hole edge area 10f. The first light-emitting control signal line EL1 extends from both sides of the display area 10a to the middle along the first direction X, and is terminated at a position close to the wiring area 10c around the through hole area 10d. Fig.10 As shown, the second light-emitting control signal line EL2 of each light-emitting control signal line EL is located in the wiring area 10f between the adjacent through-hole area 10d and the blind hole area 10e, and the length of the second light-emitting control signal line EL2 is relatively short. The second light-emitting control signal line EL2 extends along the first direction X and both ends thereof are terminated at a position close to the wiring area 10c.

[0130] Each light-emitting control signal line EL is electrically connected to the light-emitting control circuit 102 located in the border area 10b through the first light-emitting control signal line EL1, and transmits the light-emitting control signal to control the sub-pixels of the display area 10a for display. The second light-emitting control signal line EL2 is not electrically connected to the light-emitting control circuit 102, so the light-emitting control signal line EL has no electrical signal transmission. Since the hole edge area 10f itself does not have a display function, this design will not affect the overall display effect of the display substrate 100.

[0131] Except for at least one light emitting control signal line EL passing through the closed area G1 , other light emitting control signal lines EL are disposed in the display area 10 a , and each light emitting control signal line EL extends along the first direction X and straightly passes through the display area 10 a .

[0132] It should be noted that in order to ensure that the plurality of signal lines passing through the closed area G1 can be arranged at the original intervals in the display area 10 a , the plurality of signal lines are arranged more densely in the wiring area 10 c .

[0133] In some embodiments, Figure 7 , Figure 14B to Figure 18 As shown, the at least one metal layer 31 includes a first gate layer 311 , a second gate layer 312 and a source-drain metal layer 313 ; the at least one insulating layer 32 includes a first insulating layer 321 , a second insulating layer 322 and an interlayer insulating layer 323 .

[0134] The driving circuit layer 3 further includes a semiconductor layer 33 , and the semiconductor layer 33 is located in the hole edge area 10 f and the display area 10 a .

[0135] like Figure 7 , Fig. 14B and Fig.15As shown, the semiconductor layer 33 is arranged on one side of the substrate 2, the first insulating layer 321 is arranged on the side of the semiconductor layer 33 away from the substrate 2, the first gate layer 311 is arranged on the side of the first insulating layer 321 away from the substrate 2; the second insulating layer 322 is arranged on the side of the first gate layer 311 away from the substrate 2; the second gate layer 312 is arranged on the side of the second insulating layer 322 away from the substrate 2; the interlayer insulating layer 323 is arranged on the side of the second gate layer 312 away from the substrate 2; the source-drain metal layer 313 is arranged on the side of the second gate layer 312 away from the substrate 2.

[0136] In some embodiments, the plurality of data lines DL are located in the source-drain metal layer 313. The plurality of light emitting control signal lines EL are located in the first gate layer 311 or the second gate layer 312; the plurality of gate driving signal lines GL are located in the second gate layer 312 or the first gate layer 311. For example, Figure 7 As shown, the plurality of light emitting control signal lines EL and the plurality of gate driving signal lines GL are all located in the first gate layer 311, and the plurality of initialization signal lines VINT are located in the second gate layer 312.

[0137] In some examples, such as Fig. 14B As shown, each data line DL includes a first data line pattern DL1, a second data line pattern DL2 and a third data line pattern DL3 which are stacked in sequence, and materials of the first data line pattern DL1, the second data line pattern DL2 and the third data line pattern DL3 are all metals. For example, the material of the first data line pattern DL1 and the third data line pattern DL3 is titanium, and the material of the second data line pattern DL2 is aluminum. Each data line DL is a titanium-aluminum-titanium structure, thereby improving the anti-oxidation performance of the data line DL while ensuring the conductivity of the data line DL.

[0138] In some embodiments, Fig.11 , Fig.15 and Fig.16 As shown, the display area 10a is provided with a plurality of pixel structures 1, each pixel structure 1 includes a pixel circuit 11 and a light emitting device 12, and the pixel circuit 11 and the light emitting device 12 are electrically connected. Fig.11 , Fig.17 and Fig.18 As shown, the hole edge area 10f is provided with a plurality of redundant pixel structures 1', the hole edge area 10f cannot display, and the redundant pixel structure 1' cannot work normally. Each redundant pixel structure 1' includes a redundant pixel circuit 11' and a redundant light-emitting device 12'. The redundant pixel circuit 11' has the same structure as the pixel circuit 11. The pixel circuit 11 and the light-emitting device 12 in the pixel structure 1, and the redundant pixel circuit 11' and the redundant light-emitting device 12' in the redundant pixel structure 1' are respectively introduced below.

[0139] In some embodiments, Figure 7 , Figure 15 to Figure 18 As shown, the display substrate 100 further includes a light emitting device layer 4 disposed on a side of the driving circuit layer 3 away from the base substrate 2. The light emitting device layer 4 is located in the display area 10a and the hole edge area 10f.

[0140] The light emitting device layer 4 includes a first electrode layer 41 , a functional layer 42 , a second electrode layer 43 and a pixel defining layer 44 .

[0141] The first electrode layer 41 is disposed on a side of the driving circuit layer 3 away from the base substrate 2. The first electrode layer 41 includes a plurality of first electrodes 411. Exemplarily, the first electrode layer 41 is an anode layer, and the first electrode 411 is an anode. The material of the first electrode layer 41 is, for example, at least one of ITO, IZO, Au, Pt, and Si.

[0142] The pixel defining layer 44 is disposed on a side of the first electrode layer 41 away from the base substrate 2. A plurality of openings K1 are disposed in the pixel defining layer 44. Each opening K1 exposes at least a portion of a first electrode 411, and each opening K1 is located in a sub-pixel P. Fig.11 As shown, in the display area 10 a , the pixel defining layer 44 is opened, and the outline of each opening K1 is within a first electrode 411 .

[0143] The functional layer 42 is disposed on a side of the first electrode layer 41 away from the base substrate 2 . The functional layer 42 includes a plurality of light emitting portions 421 . Each light emitting portion 421 is located in an opening K1 .

[0144] In some embodiments, the functional layer 42 further includes a hole transport layer (HTL) and an electron transport layer (ETL).

[0145] Exemplarily, the hole transport layer is disposed on the side of the first electrode layer 41 away from the base substrate 2, the plurality of light-emitting portions 421 are disposed on the side of the hole transport layer away from the base substrate 2, and the electron transport layer is disposed on the side of the plurality of light-emitting portions 421 away from the base substrate 2. The hole transport layer and the electron transport layer include portions located within the plurality of openings K1 and portions located outside the plurality of openings K1, for example Figure 7 The functional layer 42 in the cross-sectional view shown refers to a hole transport layer and an electron transport layer, and does not include the plurality of light-emitting portions 421 .

[0146] The second electrode layer 43 is disposed on a side of the functional layer 42 and the pixel defining layer 44 away from the base substrate 2 . Exemplarily, the second electrode layer 43 is a cathode layer.

[0147] In some embodiments, the light emitting device layer 4 further includes: a capping layer (CPL) disposed on a side of the second electrode layer 43 away from the base substrate 2. The capping layer is configured to enhance the light emitting efficiency of the light emitting device.

[0148] In some embodiments, the light emitting device layer 4 further includes a support layer 45 . The support layer 45 is disposed between the pixel defining layer 44 and the second electrode layer 43 . The support layer 45 and the pixel defining layer 44 may be made of the same material.

[0149] like Figure 7 As shown, the display substrate 100 further includes a planarization layer 5 disposed between the driving circuit layer 3 and the light emitting device layer 4 , and the planarization layer 5 is located in the display area 10a , the wiring area 10c , the hole edge area 10f and the blind hole area 10e . The planarization layer 5 covers the source and drain metal layer 313 .

[0150] In some embodiments, the material of the planarization layer 5 is a light-transmissive insulating material, for example, the material of the planarization layer 5 is silicon oxide, silicon nitride, or silicon oxynitride.

[0151] In some embodiments, Fig.16 As shown, the planarization layer 5 is a double-layer structure, and the planarization layer 5 includes a first planarization layer 51 and a second planarization layer 52 which are stacked. The first planarization layer 51 is closer to the base substrate 2 than the second planarization layer 52 .

[0152] In this case, if Fig.16 As shown, the display substrate 100 further includes a plurality of switching electrodes 411 ′, each of which is electrically connected to one of the first electrodes 411 , and the switching electrode 411 ′ is electrically connected to the pixel circuit 11 through a via hole.

[0153] In addition, the display substrate 100 further includes a passivation layer 5' disposed between the first planarization layer 51 and the source-drain metal layer 313, and the passivation layer 5' may be formed of materials such as silicon oxide, silicon nitride or silicon oxynitride; the passivation layer 5' covers the source-drain metal layer 313. The via hole penetrates the first planarization layer 51 and the passivation layer 5', so that the transfer electrode 411' is electrically connected to the thin film transistor in the pixel circuit 11 through the via hole.

[0154] In some embodiments, Fig.15 and 16 As shown, in the multiple pixel structures 1 arranged in the display area 10a, each pixel structure 1 includes a pixel circuit 11 and a light emitting device 12. The light emitting device 12 includes a first electrode 411 electrically connected to the pixel circuit 11, a light emitting portion 421 and a portion of the second electrode layer 43 corresponding to the light emitting portion 421.

[0155] In other embodiments, Fig.17and Fig.18 As shown, in the multiple redundant pixel structures 1' arranged in the hole edge area 10f, each redundant pixel structure 1' includes a redundant pixel circuit 11' and / or a redundant light-emitting device 12'. The hole edge area 10f cannot display, and the redundant pixel structure 1' cannot work normally. Each redundant pixel structure 1' includes a redundant pixel circuit 11' and a redundant light-emitting device 12'. The redundant pixel circuit 11' has the same structure as the pixel circuit 11. Fig.17 As shown, the redundant light emitting device 12' includes a light emitting portion 421 and a portion of the second electrode layer 43 corresponding to the light emitting portion 421; or Fig.18 As shown, the redundant light emitting device 12 ′ includes a first electrode 411 , a light emitting portion 421 and a portion of the second electrode layer 43 corresponding to the light emitting portion 421 , and the first electrode 411 is not electrically connected to the redundant pixel circuit 11 ′.

[0156] In some embodiments, the pixel circuit 11 and the redundant pixel circuit 11' both include at least one thin film transistor T and a storage capacitor. The pixel circuit 11 and the redundant pixel circuit 11' have the same circuit structure, for example, both have a 7T1C, 8T2C or 4T1C circuit structure. Fig.12 for Fig.10 and Fig.11 Region G8 and Fig.11 The enlarged view of the middle area G8' is shown in Figure 2. Fig.12 As shown, as an example, the pixel circuit 11 and the redundant pixel circuit 11' are both 7T1C circuit structures. Taking the redundant pixel circuit 11' located in the hole edge area 10f as an example, the structure of the redundant pixel circuit 11' is introduced below.

[0157] like Fig.12 and Fig.13 As shown, the redundant pixel circuit 11' includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a driving transistor Td and a storage capacitor Cst. For one redundant pixel circuit 11', the redundant pixel circuit 11' is electrically connected to three gate drive signal lines GL and one light emitting control signal line EL, and the three gate drive signal lines GL are respectively a gate scanning line Gate, a first reset signal line Reset1 and a second reset signal line Reset2.

[0158] It should be noted that the display substrate 100 further includes a plurality of first voltage signal lines VDD disposed in the display area 10 a and the hole edge area 10 f . Exemplarily, the plurality of first voltage signal lines VDD are located in the source-drain metal layer 313 .

[0159] A first end of the storage capacitor Cst is electrically connected to the first voltage signal line VDD, and a second end of the storage capacitor Cst is electrically connected to the first node N1.

[0160] The control electrode of the driving transistor Td is electrically connected to the first node N1. The control electrode of the first transistor T1 is electrically connected to the first reset signal line Reset1, the first electrode of the first transistor T1 is electrically connected to the initialization signal line VINT, and the second electrode of the first transistor T1 is electrically connected to the first node N1.

[0161] The control electrode of the second transistor T2 is electrically connected to the gate scanning line Gate, the first electrode of the second transistor T2 is electrically connected to the second electrode of the driving transistor Td, and the second electrode of the second transistor T2 is electrically connected to the first node N1.

[0162] A control electrode of the third transistor T3 is electrically connected to the gate scanning line Gate, a first electrode of the third transistor T3 is electrically connected to the data line DL, and a second electrode of the third transistor T3 is electrically connected to the third node N3.

[0163] A control electrode of the fourth transistor T4 is electrically connected to the light emission control line EL, a first electrode of the fourth transistor T4 is electrically connected to the first voltage signal line VDD, and a second electrode of the fourth transistor T4 is electrically connected to the third node N3.

[0164] A control electrode of the fifth transistor T5 is electrically connected to the second reset signal line Reset2 , a first electrode of the fifth transistor T5 is electrically connected to the initialization signal line VINT, and a second electrode of the fifth transistor T5 is electrically connected to the fourth node N4 .

[0165] A control electrode of the sixth transistor T6 is electrically connected to the light emitting control line EL, a first electrode of the sixth transistor T6 is electrically connected to the third node N3, and a second electrode of the sixth transistor T6 is electrically connected to the fourth node N4.

[0166] like Fig.11 As shown, in the display area 10a, the pixel structure 1 includes a pixel circuit 11 and a light emitting device 12, and the second electrode of the sixth transistor T6 in the pixel circuit 11 is electrically connected to the first electrode 411 of the light emitting device 12, so that the sixth transistor T6 transmits the driving signal to the first electrode 411 to control the light emitting device 12 to emit light. In some embodiments, Fig.10 and Fig.11 As shown, in the hole edge area 10f, the redundant pixel structure 1' includes a pixel circuit 11' and a light-emitting device 12'. The light-emitting device 12' does not include a first electrode. Therefore, the second electrode of the sixth transistor T6 in the pixel circuit 11' is not electrically connected to other devices, and the light-emitting device 12' does not emit light, so that the hole edge area 10f does not display.

[0167] In some embodiments, each thin film transistor T includes an active layer t1, a gate t2, a source t3, and a drain t4. The active layer t1 is located in the semiconductor layer 33, the gate t2 is located in the first gate layer 311, and the source t3 and the drain t4 are located in the source-drain metal layer 313. The gate t2 of the thin film transistor T is arranged in the same layer with a plurality of light emitting control signal lines EL and a plurality of gate driving signal lines GL, and the source t3 and the drain t4 of the thin film transistor T are arranged in the same layer with a plurality of data lines DL. Figure 15 to Figure 18 The thin film transistor in the cross-sectional view shown in FIG. 1 may be considered as the sixth transistor T6 in the pixel circuit 11 or the redundant pixel circuit 11 ′.

[0168] like Fig.15 As shown, the storage capacitor Cst may include a first electrode plate c1 and a second electrode plate c2. The first electrode plate c1 is located in the first gate layer 311 and is arranged on the same layer as the gate t2 of the thin film transistor T, and multiple light-emitting control signal lines EL and multiple gate driving signal lines GL. The second electrode plate c2 is located in the second gate layer 312 and is arranged on the same layer as the multiple initialization signal lines VINT, and the first electrode plate c1 and the second electrode plate c2 are arranged opposite to each other.

[0169] The materials of the gate electrode t2, the first electrode plate c1 and the second electrode plate c2 of the thin film transistor T may include metal materials or alloy materials, such as molybdenum, aluminum and titanium. The source electrode 210 and the drain electrode 211 of the thin film transistor T may include metal materials or alloy materials, such as a metal single layer or multilayer structure formed by molybdenum, aluminum and titanium, for example, the multilayer structure is a multi-metal layer stack, such as titanium, aluminum, titanium (Al / Ti / Al) three-layer metal stack, etc.

[0170] like Fig.10 and Fig.11 As shown, the hole edge area 10f includes a first sub-area 10f1 close to the wiring area 10c, and a second sub-area 10f2 other than the first sub-area 10f1. The first sub-area 10f1 is located outside the second sub-area 10f2. Each thin film transistor T in the pixel circuit 11' of the multiple redundant pixel structures 1' is arranged in 10f2, and the space of the first sub-area 10f1 is narrow, and the thin film transistor T cannot be arranged.

[0171] The display substrate 100 further includes: a plurality of via holes K2 disposed in the second sub-region 10f2 of the hole side region 10f, and a plurality of redundant via holes K3 disposed in the first sub-region 10f1 of the hole side region 10f.

[0172] Each via K2 penetrates the first insulating layer 321, the second insulating layer 322 and the interlayer insulating layer 323. A plurality of redundant pixel structures 1' are arranged in the second sub-region 10f2 of the hole edge region 10f, and the source t3 and the drain t4 of each thin film transistor T of the plurality of redundant pixel structures 1' are electrically connected to its active layer t1 through the via K2. Exemplarily, the source t3 and the drain t4 of each thin film transistor T are electrically connected to its active layer t1 through two vias K2, respectively.

[0173] Of course, the display substrate 100 further includes a plurality of via holes K2 disposed in the display area 10a, and the source t3 and the drain t4 of each thin film transistor T in the pixel structure 1 in the display area 10a are electrically connected to its active layer t1 through the via holes K2. Exemplarily, the source t3 and the drain t4 of each thin film transistor T are electrically connected to its active layer t1 through two via holes K2, respectively.

[0174] Each redundant via hole K3 penetrates the first insulating layer 321, the second insulating layer 322, and the interlayer insulating layer 323. A portion of the planarization layer 5 fills the plurality of redundant via holes K3.

[0175] In some examples, the size of multiple redundant vias K3 can be set according to the spatial size of the first sub-area 10f1, and the number may not be limited. The purpose of setting multiple redundant vias K3 is to balance the difference in density of vias K in the hole edge area 10f and the display area 10a, and to ensure uniform characteristics of the thin film transistors.

[0176] The structure provided in the packaging area 10g of the display substrate 100 is described below.

[0177] In some embodiments, Figure 7 As shown, the display substrate 100 further includes at least one encapsulation dam area 10g3, each encapsulation dam area 10g3 is located between a through hole area 10d and a wiring area 10c surrounding the through hole area 10d, and surrounds the through hole area 10d. Exemplarily, the display substrate 100 includes two encapsulation dam areas 10g3, each encapsulation dam area 10g3 surrounding a through hole area 10d.

[0178] The first insulating layer 321 , the second insulating layer 322 and the interlayer insulating layer 323 are also located in the at least one encapsulation dam region 10g3 .

[0179] The display substrate 100 further includes a plurality of packaging dams 6 ; each packaging dam area 10g3 is provided with at least one packaging dam 6 , each packaging dam 6 surrounds the through hole area 10d , and the packaging dam 6 is provided on a side of the driving circuit layer 3 away from the base substrate 2 .

[0180] In the case where at least two encapsulation dams 6 are provided in each encapsulation dam area 10g3, the at least two encapsulation dams 6 are sequentially spaced apart along the radial direction of the through hole area 10d.

[0181] In some examples, such as Figure 7 As shown, at least one encapsulation dam 6 disposed in each encapsulation dam area 10g3 includes a first encapsulation dam 61 and a second encapsulation dam 62, and the first encapsulation dam 61 is located on a side 10d of the second encapsulation dam 62 away from the through hole area.

[0182] The thickness of the second encapsulation dam 62 along the third direction Z is greater than the thickness of the first encapsulation dam 61 along the third direction Z; wherein the third direction Z is perpendicular to the base substrate 2 .

[0183] For example, Figure 7 As shown, the second encapsulation dam 62 includes a first portion 62a, a second portion 62b and a first spacer portion 62c, wherein the first portion 62a is disposed on the same layer as the planarization layer 5. The second portion 62b is disposed on a side of the first portion 62a away from the base substrate 2, and the second portion 62b is disposed on the same layer as the pixel defining layer 44. The first spacer portion 62c is disposed on a side of the second portion 62b away from the base substrate 2.

[0184] The first encapsulation dam 61 includes a third portion 61a and a second spacer portion 61b. The third portion 61a is disposed on the same layer as the pixel defining layer 44; the second spacer portion 61b is disposed on a side of the third portion 61a away from the base substrate 2, and the second spacer portion 61b is made of the same material as the first spacer portion 62c and disposed on the same layer.

[0185] In some examples, such as Figure 7 As shown, the hole transport layer and the electron transport layer in the functional layer 42 and the second electrode layer 43 are also located in the packaging dam area 10g3, and the functional layer 42 and the second electrode layer 43 are sequentially stacked on the side of the multiple packaging dams 6 away from the base substrate 2.

[0186] In some embodiments, Figure 7 As shown, the display substrate 100 further includes at least one first isolation region 10g1 and at least one second isolation region 10g2. Each first isolation region 10g1 is located between the wiring region and the packaging dam region 10g3, and surrounds the packaging dam region 10g3; each second isolation region 10g2 is located between the through hole region 10d and the packaging dam region 10g3, and surrounds the through hole region 10d. Exemplarily, the display substrate 100 includes two first isolation regions 10g1 and two second isolation regions 10g2.

[0187] The first insulating layer 321 , the second insulating layer 322 , and the interlayer insulating layer 323 are also located in the at least one first isolation region 10g1 and the at least one second isolation region 10g2 .

[0188] like Figure 7 , Fig.19 and Fig. 20As shown, the display substrate 100 further includes: a plurality of first isolation columns 7 and a plurality of second isolation columns 8 .

[0189] Each first isolation region 10g1 is provided with at least one first isolation column 7, and each first isolation column 7 is arranged around the first packaging dam 61. When at least two first isolation columns 7 are provided in each first isolation region 10g1, the at least two first isolation columns 7 are arranged in sequence and spaced apart along the radial direction of the through-hole region 10d.

[0190] Each second isolation region 10g2 is provided with at least one second isolation column 8, and each second isolation column 8 is arranged around the through-hole region 10d. When at least two second isolation columns 8 are provided in each second isolation region 10g2, the at least two second isolation columns 8 are arranged in sequence and spaced apart along the radial direction of the through-hole region 10d.

[0191] In some embodiments, Figure 7 As shown, the first isolation column 7 and the second isolation column 8 are arranged on the side of the interlayer insulating layer 323 away from the substrate 2; for example, the first isolation column 7 and the second isolation column 8 are located in the source-drain metal layer 313. The first isolation column 7 and the second isolation column 8 are arranged in the same layer as the plurality of data lines DL.

[0192] In some examples, such as Figure 7 As shown, the hole transport layer and the electron transport layer in the functional layer 42, and the second electrode layer 43 are also located in at least one first isolation region 10g1 and at least one second isolation region 10g2, and the functional layer 42 and the second electrode layer 43 are stacked in sequence on the side of multiple first isolation columns 7 and multiple second isolation columns 8 away from the base substrate 2.

[0193] At least one first spacer column 1c and at least one second spacer column 8 can isolate the organic light-emitting material (materials of the hole transport layer and the electron transport layer) to prevent water and oxygen from invading the light-emitting device. Figure 7 As shown, since at least one first isolation column 7 has a certain thickness and is raised in the display substrate, when the functional layer 42 is formed, the hole transport layer and the electron transport layer of the functional layer 42 will be separated at the first isolation column 7 to make the functional layer 42 discontinuous, thereby preventing water and oxygen entering the functional layer 42 from the through-hole area from invading the light-emitting device in the display area 10a (for example, the light-emitting portion 421 in the light-emitting device) and affecting the display effect.

[0194] As a possible design, Fig.19 and Fig. 20As shown, a groove is provided on the side wall of the first isolation column 7; and a groove is provided on the side wall of the second isolation column 8. Exemplarily, the first isolation column 7 and the second isolation column 8 both include a first metal pattern 8a, a second metal pattern 8b, and a third metal pattern 8c which are sequentially stacked, and the outer boundary of the orthographic projection of the second metal pattern 8b on the substrate 2 is located inside the outer boundary of the orthographic projection of the first metal pattern 8a and the third metal pattern 8c on the substrate 2, so as to form a groove on the side wall of the first isolation column 7 and the side wall of the second isolation column 8.

[0195] In some embodiments, when each data line DL includes a first data line pattern DL1, a second data line pattern DL2, and a third data line pattern DL3 which are sequentially stacked, the first metal pattern 8a is disposed in the same layer as the first data line pattern DL, the second metal pattern 8b is disposed in the same layer as the second data line pattern DL2, and the third metal pattern 8c is disposed in the same layer as the third data line pattern DL3. The materials of the first metal pattern 8a and the third metal pattern 8c are titanium, and the material of the second metal pattern 8b is aluminum, so that each of the first isolation column 7 and the second isolation column 8 is a titanium-aluminum-titanium structure. In this way, the plurality of data lines DL and the first isolation column 7 and the second isolation column 8 can be prepared by the same drawing process, which is conducive to simplifying the process.

[0196] In some embodiments, Fig. 20 As shown, each second isolation region 10g2 is further provided with at least one fourth metal pattern 8d and at least one fifth metal pattern 8e, the fourth metal pattern 8d is located in the first gate layer 311, and the fifth metal pattern 8e is located in the second gate layer 312. Each fourth metal pattern 8d and each fifth metal pattern 8e surrounds the through hole region 10d.

[0197] The orthographic projections of the second isolation column 8, the fourth metal pattern 8d and the fifth metal pattern 8e on the base substrate 2 have a common overlapping area. Exemplarily, the number of at least one fourth metal pattern 8d and the number of at least one fifth metal pattern 8e are equal to the number of at least one second isolation column 8. A fifth metal pattern 8e is disposed directly below each second isolation column 8, and a fourth metal pattern 8d is disposed directly below each fifth metal pattern 8e.

[0198] At least one fourth metal pattern 8d and at least one fifth metal pattern 8e are used to elevate the second isolation column 8 and can also alleviate cracks in the base substrate 2 .

[0199] In some embodiments, Fig.19 As shown, when each first isolation region 10g1 is provided with at least two first isolation pillars 7 , a portion of the driving circuit layer 3 located between two adjacent first isolation pillars 7 has a first groove 1d . Exemplarily, the first groove 1d exposes the base substrate 2 .

[0200] In some examples, after the first insulating layer 321, the second insulating layer 322, and the interlayer insulating layer 323 in the driving circuit layer 3 are prepared, the first insulating layer 321, the second insulating layer 322, and the interlayer insulating layer 323 are removed by an etching process between two adjacent first isolation pillars 7 to form a first trench 1d, so that the base substrate 2 is exposed to form the first trench 1d. In other examples, only the portion of the interlayer insulating layer 323 between two adjacent first isolation pillars 7 may be removed to expose the second insulating layer 322, or only the portion of the interlayer insulating layer 323 and the second insulating layer 322 between two adjacent first isolation pillars 7 may be removed to expose the first insulating layer 321 to form a shallower first trench 1d.

[0201] like Fig. 20 As shown, in the case where each second isolation region 10g2 is provided with at least two second isolation pillars 8, a portion of the driving circuit layer 3 located between two connected second isolation pillars 8 has a recess 1f.

[0202] Since each second isolation region 10g2 is also provided with at least one fourth metal pattern 8d and at least one fifth metal pattern 8e, and the fourth metal pattern 8d and the fifth metal pattern 8e are arranged directly below the second isolation column 8, after the fourth metal pattern 8d is formed, a natural recess is formed between two adjacent fourth metal patterns 8d during the deposition of the second insulating layer 322, and then the fifth metal pattern 8e is formed. In the process of depositing the interlayer insulating layer 323, a natural recess is formed between two adjacent fifth metal patterns 8e, and there is no need to etch the insulating layer.

[0203] In some embodiments, Figure 7 , Figure 15 to Figure 18 As shown, the display substrate 100 further includes an encapsulation layer 9 disposed on a side of the light emitting device layer 4 away from the base substrate 2 .

[0204] The encapsulation layer 9 includes a first inorganic encapsulation thin film layer 91 , an organic encapsulation thin film layer 92 and a second inorganic encapsulation thin film layer 93 .

[0205] The first inorganic encapsulation film layer 91 is arranged on the side of the light emitting device layer 4 away from the base substrate 2; the first inorganic encapsulation film layer 91 is located in the second isolation area 10g2, the encapsulation dam area 10g3, the first isolation area 10g1, the wiring area 10c, the hole edge area 10f, the display area 10a and the blind hole area 10e. The organic encapsulation film layer 92 is arranged on the side of the first inorganic encapsulation film layer 91 away from the base substrate 2; the organic encapsulation film layer 92 is located in the encapsulation dam area 10g3, the first isolation area 10g1, the wiring area 10c, the hole edge area 10f, the display area 10a and the blind hole area 10e. The second inorganic encapsulation film layer 93 is arranged on the side of the organic encapsulation film layer 92 away from the base substrate 2; the second inorganic encapsulation film layer 93 encapsulates the second isolation area 10g2, the encapsulation dam area 10g3, the first isolation area 10g1, the wiring area 10c, the hole edge area 10f, the display area 10a and the blind hole area 10e.

[0206] like Figure 7 and Fig.14A As shown, the film layer structure in the blind hole area 10e includes the first insulating layer 321 of the substrate substrate 2, the second insulating layer 322, the interlayer insulating layer 323, the flat layer 5 and the encapsulation layer 9. In some embodiments, the multiple film layers in the blind hole area 10e can also be etched to retain part of the above film layer structure. For example, the film layer in the blind hole area 10e can include one or more layers of the substrate substrate 2, the first insulating layer 321, the second insulating layer 322, the interlayer insulating layer 323, the flat layer 5 and the encapsulation layer 9, such as only including the substrate substrate 2, the first insulating layer 321, the second insulating layer 322, the interlayer insulating layer 323, or only including the substrate substrate 2, the first insulating layer 321, the second insulating layer 322, the interlayer insulating layer 323 and the flat layer 5. Generally, the blind hole area 10e retains Figure 4 The layers shown in the figure are arranged to keep the thickness of the display substrate from changing greatly and avoid the formation of lamination bubbles between the layers when laminating the layers using the lamination process. The light passes through the film layers along the incident direction of the light and reaches the sensor 105 corresponding to the blind hole.

[0207] In order to ensure that the blind hole area 10e can have a certain light transmittance, it is required that the substrate 2, the first insulating layer 321, the second insulating layer 322, the interlayer insulating layer 323, the flat layer 5 and the encapsulation layer 9 are all made of transparent materials. For example, the substrate 2 can be made of organic materials such as polyimide, and the first insulating layer 321, the second insulating layer 322, and the interlayer insulating layer 323 can be made of materials such as silicon oxide and silicon oxynitride. The flat layer 206 can be made of organic materials, such as photoresist, acrylic polymers, silicon-based polymers and other materials. The first inorganic encapsulation film layer 91 and the second inorganic encapsulation film layer 93 of the encapsulation layer 9 are used to prevent water and oxygen from entering the light-emitting device of the display area 10a from the display side of the display substrate 100 and the through-hole area 10d; the first inorganic encapsulation film layer 91 and the second inorganic encapsulation film layer 93 can be made of inorganic materials such as silicon nitride and silicon oxide. The organic encapsulation film layer 92 is used to achieve a planarization effect to facilitate the production of the second inorganic encapsulation film layer 93. The organic encapsulation film layer 92 can be made of materials such as acrylic-based polymers and silicon-based polymers.

[0208] Some embodiments of the present disclosure further provide a display device 1000 , which includes the display substrate 100 of the above embodiment and a driving circuit for driving the display substrate.

[0209] In some embodiments, Figure 6 As shown, the display device 1000 further includes at least one first sensor 200 and at least one second sensor 300 .

[0210] Each first sensor 100 is disposed in a through hole area 10d, and the first sensor 200 is located in the through hole. The first sensor 200 is disposed opposite to the through hole in the through hole area 10b. Exemplarily, the display substrate 200 has a display surface side B and a non-display surface side B' opposite to each other. The first sensor 200 is located on the non-display surface side B' of the display substrate 100 and can extend into the through hole. At least one first sensor 200 is a device with high light transmittance requirements, for example, the first sensor 200 includes a camera.

[0211] Each second sensor 300 is disposed in a blind hole area 10e, and each second sensor 300 is disposed opposite to a blind hole in at least one blind hole area 10c, and the first sensor 200 is located on the non-display surface side B' of the display substrate 100. At least one second sensor 300 is a device with low light transmittance requirements, for example, the second sensor 300 includes at least one of an infrared sensor, a proximity light sensor, a flood illuminator, and an ambient light sensor.

[0212] Exemplarily, the sensing surfaces of the at least one first sensor 200 and the at least one second sensor 300 are both oriented toward the display surface side B of the display substrate 100 to receive light from the display surface side B of the display substrate 100 .

[0213] In the above-mentioned display device 1000, compared with the related art of only performing through holes (for placing cameras) or through hole design combined with frame sensor arrangement, it not only ensures the quality of the display device in realizing the sensor function, but also is conducive to realizing a narrow frame; compared with the traditional arrangement of only blind holes or blind holes combined with frame sensors, it is more conducive to the imaging quality of the camera and is conducive to realizing a narrow frame.

[0214] Some other embodiments of the present disclosure also provide a method for preparing a display substrate, such as Fig.21 As shown, the preparation method comprises:

[0215] S1. Provide a substrate 2. The substrate 2 includes a display area 10a, at least one wiring area 10c, at least one through-hole area 10d and at least one blind-hole area 10e, each wiring area 10c surrounds a through-hole area 10d or a blind-hole area 10e, and the display area 10a surrounds the wiring area 10c.

[0216] In some embodiments, the base substrate 2 further includes a hole edge region 10f, and the hole edge region 10f is located between the wiring region 10c and the display region 10a, that is, the hole edge region 10f surrounds the wiring region 10c, and the display region 10a surrounds the hole edge region 10f.

[0217] It should be noted that the display area 10a, wiring area 10c, through hole area 10d and blind hole area 10e in the base substrate 2 are consistent with the display area 10a, wiring area 10c, hole edge area 10f, through hole area 10d and blind hole area 10e in the display substrate 100 to be formed.

[0218] S2 , forming a driving circuit layer 3 on the base substrate 2 . The driving circuit layer 3 includes: at least one metal layer 31 and at least one insulating layer 32 .

[0219] At least one metal layer 31 is located in the display area 10a, the wiring area 10c, and the hole edge area 10f. At least one metal layer includes a plurality of signal lines, at least a portion of at least one of the plurality of signal lines surrounds the through hole area 10d and / or the blind hole area 10e.

[0220] Exemplarily, the plurality of signal lines include a plurality of data lines DL, a plurality of light emitting control signal lines EL, a plurality of gate driving signal lines GL and a plurality of initialization signal lines VINT. For the specific arrangement of the plurality of signal lines, see Figure 8A to Figure 8C The above description will not be repeated here.

[0221] At least one insulating layer 32 is located in the display area 10a, the wiring area 10c, the through hole area 10d and the blind hole area 10e, and the hole edge area 10f.

[0222] In some examples, such as Figure 7 As shown, the at least one metal layer 31 includes a first gate layer 311, a second gate layer 312 and a source-drain metal layer 313; the at least one insulating layer 32 includes a first insulating layer 321, a second insulating layer 322 and an interlayer insulating layer 323. The driving circuit layer 3 also includes a semiconductor layer 33, which is located in the display area 10a and the hole edge area 10f.

[0223] In S2, forming a driving circuit layer 3 on the base substrate 2 includes:

[0224] S21 , forming a semiconductor layer 33 on one side of the base substrate 2 .

[0225] S22 , forming a first insulating layer 321 on a side of the semiconductor layer 33 away from the base substrate 2 .

[0226] S23 , forming a first gate layer 311 on a side of the first insulating layer 321 away from the base substrate 2 .

[0227] S24 , forming a second insulating layer 322 on a side of the first gate layer 311 away from the base substrate 2 .

[0228] S25 , forming a second gate layer 312 on a side of the second insulating layer 322 away from the base substrate 2 .

[0229] S26 , forming an interlayer insulating layer 323 on a side of the second gate layer 312 away from the base substrate 2 .

[0230] S27 , forming a source-drain metal layer 313 on a side of the interlayer insulating layer 323 away from the base substrate 2 .

[0231] Among them, the preparation method of the semiconductor layer 33, the first insulating layer 321, the second insulating layer 322 and the interlayer insulating layer 323 can be a deposition process, and the preparation method of the first gate layer 311, the second gate layer 312 and the source and drain metal layer 313 can be a sputtering process to form a metal film layer, and then an etching process to form multiple patterns.

[0232] In the display area 10a, the driving circuit layer 3 includes a plurality of pixel circuits 11, each of which includes at least one thin film transistor. In the aperture edge area 10f, the driving circuit layer 3 includes a plurality of redundant pixel circuits 11', each of which includes at least one thin film transistor.

[0233] In some embodiments, Figure 4As shown, at least one metal layer 31 is also located in the through hole area 10d to form a redundant pixel circuit 11' in the through hole area 10d. Providing the redundant pixel circuit 11' in the through hole area 10d can make the thickness of the display substrate 100 more uniform, and in the subsequent process of cutting the display substrate in the through hole area 10d, the cutting is uniform.

[0234] Among them, the first gate layer 311 formed in S23 includes multiple gate scanning signal lines GL, multiple light-emitting control signal lines EL and gates of multiple thin film transistors, and the multiple gate scanning signal lines GL, multiple light-emitting control signal lines EL and the gates of multiple thin film transistors are formed by the same patterning process. The second gate layer 312 formed in S25 includes multiple initialization signal lines VINT, and the multiple initialization signal lines VINT are formed by the same patterning process. The source-drain metal layer 313 formed in S27 includes multiple data lines DL and the source and drain of multiple thin film transistors, and the multiple data lines DL and the source and drain of multiple thin film transistors are formed by the same patterning process.

[0235] S3. Form a planarization layer 5 on the side of the driving circuit layer 3 away from the base substrate 2. The planarization layer 5 is located in the display area 10a, the wiring area 10c, the through hole area 10d, the blind hole area 10e, and the hole edge area 10f.

[0236] Exemplarily, a coating process is used to coat the material of the planarization layer on the side of the source / drain metal layer 313 away from the substrate. For example, the material of the planarization layer 5 includes photoresist, acrylic-based polymer, silicon-based polymer, and the like.

[0237] S4. Form a light-emitting device layer 4 on a side of the planarization layer 5 away from the base substrate 2; the light-emitting device layer is located in the display area 10a.

[0238] In some examples, the light emitting device layer 4 includes a first electrode layer 41 , a functional layer 42 , a second electrode layer 43 , and a pixel defining layer 44 .

[0239] S41, forming a light emitting device layer 4 on a side of the planarization layer 5 away from the base substrate 2 includes:

[0240] A first electrode layer 41 is formed on a side of the planarization layer 5 away from the base substrate 2 . The first electrode layer 41 includes a plurality of first electrodes 411 . Each first electrode 411 is electrically connected to a thin film transistor in the driving bottom single-channel layer 3 through a via hole penetrating the planarization layer 5 .

[0241] S42 , forming a pixel defining layer 44 on a side of the first electrode layer 41 away from the base substrate 2 , and forming a plurality of openings K1 in the pixel defining layer 44 , each opening K1 exposing at least a portion of a first electrode 411 .

[0242] In some examples, the pixel defining layer 44 may also be formed in the hole edge region 10 f , and the pixel defining layer located in the hole edge region 10 f may not be provided for multiple openings.

[0243] S43 , forming a functional layer 42 on a side of the first electrode layer 41 away from the base substrate 2 , wherein the functional layer 42 includes a plurality of light-emitting portions 421 , and each light-emitting portion 421 is located in an opening K1 .

[0244] S44 , forming a second electrode layer 43 on a side of the functional layer 42 and the pixel defining layer 44 away from the base substrate 2 .

[0245] In the display area 10a, the light emitting device layer 4 includes a plurality of light emitting devices 12, each of which includes a first electrode 411 electrically connected to the pixel circuit 11, a light emitting portion 421, and a portion of the second electrode layer 43 corresponding to the light emitting portion 421. In the hole edge area 10f, the light emitting device layer 4 includes a plurality of redundant light emitting devices 12', each of which includes a light emitting portion 421 and a portion of the second electrode layer 43 corresponding to the light emitting portion 421; or Fig.18 As shown, the redundant light emitting device 12 ′ includes a first electrode 411 , a light emitting portion 421 and a portion of the second electrode layer 43 corresponding to the light emitting portion 421 , and the first electrode 411 is not electrically connected to the redundant pixel circuit 11 ′.

[0246] S5. Form a packaging layer 9 on the side of the light emitting device layer 4 away from the base substrate 2; the packaging layer 9 is located in the display area 10a, the wiring area 10c, the through hole area 10d and the blind hole area 10e, and the hole edge area 10f.

[0247] The encapsulation layer 9 includes a first inorganic encapsulation thin film layer 91 , an organic encapsulation thin film layer 92 and a second inorganic encapsulation thin film layer 93 .

[0248] Forming the encapsulation layer 9 on the side of the light emitting device layer 4 away from the base substrate 2 includes:

[0249] S51 , forming a first inorganic encapsulation thin film layer 91 on a side of the light emitting device layer 4 away from the base substrate 2 .

[0250] S52 , forming an organic encapsulation thin film layer 92 on a side of the first inorganic encapsulation thin film layer 91 away from the base substrate 2 .

[0251] S51 , forming a second inorganic encapsulation thin film layer 93 on a side of the organic encapsulation thin film layer 92 away from the base substrate 2 .

[0252] S6, removing the portions of the base substrate 2, the driving circuit layer 3, the planarization layer 5 and the packaging layer 9 located in the through-hole area.

[0253] Exemplarily, laser cutting or mechanical punching may be used to cut away the film layers at the through hole area 10 d to obtain the display substrate 100 having the through hole.

[0254] like Figure 4 and Figure 5 As shown, before the display substrate 100 is cut, a positioning mark structure M is also provided on the display substrate in the through hole area 10d for cutting positioning. The positioning mark structure is located in the circuit metal layer 313 and can be formed by the same patterning process as the multiple data lines DL and the source and drain of the thin film transistor. There is no redundant pixel circuit 11' at the location of the positioning mark structure M.

[0255] In some embodiments, S6 further includes removing a portion of the encapsulation layer 9 located in the blind hole area 10e. Alternatively, S6 further includes removing a portion of one insulating layer of at least one insulating layer of the driving circuit layer 3 located in the blind hole area 10e. For example, the portion of the interlayer insulating layer 323 located in the blind hole area 10e is removed to make the film layer thickness in the blind hole area 10e thinner and the light transmittance better.

[0256] In some embodiments, Figure 3 to Figure 5 , Figure 7 As shown, the substrate 2 also includes at least one packaging dam area 10g3, at least one first isolation area 10g1 and at least one second isolation area 10g2; each packaging dam area is located between a through-hole area and a wiring area surrounding the through-hole area, and surrounds the through-hole area, each first isolation area is located between the wiring area and the packaging dam area, and surrounds the packaging dam area; each second isolation area is located between the through-hole area and the packaging dam area, and surrounds the through-hole area.

[0257] In step S2 of forming the driving circuit layer 3 on the base substrate 2, the at least one insulating layer 32 formed is also located in at least one packaging dam area 10g3, at least one first isolation area 10g1, and at least one second isolation area 10g2. In step S3 of forming the planarization layer 5, the planarization layer 5 formed is also located in at least one packaging dam area 10g3, at least one first isolation area 10g1, and at least one second isolation area 10g2.

[0258] In some embodiments, the source-drain metal layer 313 formed in S27 further includes a plurality of first isolation pillars 7 and a plurality of second isolation pillars 8. That is, the plurality of first isolation pillars 7 and the plurality of second isolation pillars 8 and the plurality of data lines DL are formed by a unified patterning process. Each first isolation region 10g1 is provided with at least one first isolation pillar 7, each first isolation pillar 7 is provided around the first encapsulation dam 61, and each second isolation region 10g2 is provided with at least one second isolation pillar 8, each second isolation pillar 8 is provided around the through-hole region 10d.

[0259] The first isolation column 7 and the second isolation column 8 each include a first metal pattern 8a, a second metal pattern 8b and a third metal pattern 8c which are stacked in sequence, and the outer boundary of the orthographic projection of the second metal pattern 8b on the substrate 2 is located inside the outer boundary of the orthographic projection of the first metal pattern 8a and the third metal pattern 8c on the substrate 2, so as to form a groove on the side wall of the first isolation column 7 and the side wall of the second isolation column 8. In the process of forming a plurality of first isolation columns 7 and a plurality of second isolation columns 8 in S27, the film layers where the first metal pattern 8a, the second metal pattern 8b and the third metal pattern 8c are located are formed in sequence, and each film layer is etched in sequence, so that the area of ​​each second metal pattern 8b is smaller than the area of ​​the first metal pattern 8a and the area of ​​the third metal pattern 8c.

[0260] In some examples, an etching process is used to remove portions of the first insulating layer 321 , the second insulating layer 322 and the interlayer insulating layer 323 located between two adjacent first isolation pillars 7 , so that the base substrate 2 is exposed to form a first trench 1 d between two adjacent first isolation pillars 7 .

[0261] In some embodiments, the method for preparing the display substrate 100 further includes the step of forming a plurality of encapsulation dams 6. Each encapsulation dam area 10g3 is provided with at least one encapsulation dam 6, each encapsulation dam 6 surrounds the through hole area 10d, and the encapsulation dam 6 is provided on the side of the driving circuit layer 3 away from the base substrate 2.

[0262] In S3 , while forming the planarization layer 5 on the side of the driving circuit layer 3 away from the base substrate 2 , at least one first portion 62 a of a second encapsulation dam 62 is formed on the encapsulation dam 6 , and the first portion 62 a is disposed on the same layer as the planarization layer 5 .

[0263] For example, Figure 7 As shown, the formed second encapsulation dam 62 includes a first portion 62a, a second portion 62b and a first spacer portion 62c, wherein the first portion 62a is disposed on the same layer as the planarization layer 5. The second portion 62b is disposed on a side of the first portion 62a away from the base substrate 2, and the second portion 62b is disposed on the same layer as the pixel defining layer 44. The first spacer portion 62c is disposed on a side of the second portion 62b away from the base substrate 2.

[0264] The first encapsulation dam 61 formed includes: a third portion 61a and a second spacer portion 61b. The third portion 61a is disposed on the same layer as the pixel defining layer 44; the second spacer portion 61b is disposed on a side of the third portion 61a away from the base substrate 2, and the second spacer portion 61b is made of the same material as the first spacer portion 62c and disposed on the same layer.

[0265] S5. Forming an encapsulation layer 9 on the side of the light-emitting device layer 4 away from the base substrate 2 includes: a first inorganic encapsulation thin film layer 91 is also located in the second isolation area 10g2, the encapsulation dam area 10g3 and the first isolation area 10g1, an organic encapsulation thin film layer 92 is also located in the encapsulation dam area 10g3 and the first isolation area 10g1, and a second inorganic encapsulation thin film layer 92 is located in the second isolation area 10g2, the encapsulation dam area 10g3 and the first isolation area 10g1.

[0266] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be thought of by any person skilled in the art within the technical scope disclosed in the present disclosure should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A display substrate, characterized in that: The device comprises a display area, a hole edge area, a plurality of wiring areas, at least one packaging area, at least one through hole area and at least one blind hole area, wherein the wiring area surrounds a through hole area or a blind hole area, the hole edge area surrounds the wiring area, and the display area surrounds the hole edge area, wherein the blind hole area is adjacent to the wiring area surrounding the blind hole area, the packaging area is arranged between the through hole area and the wiring area surrounding the through hole area; and a packaging structure is arranged in the packaging area; The display substrate comprises: A substrate substrate; the substrate substrate has an opening in the through hole area; A driving circuit layer is provided on the substrate; the driving circuit layer comprises: At least one metal layer is located in the display area, the hole edge area and the wiring area; the at least one metal layer includes a plurality of signal lines, and the plurality of signal lines are arranged to avoid the through hole area and the blind hole area; At least one insulating layer is located in the display area, the hole edge area, the wiring area and the blind hole area; The blind hole area is light-transmissive; the through hole area and the blind hole area are used to set an optical sensor.

2. The display substrate according to claim 1, characterized in that: The at least one through hole region includes two through hole regions, the at least one blind hole region includes one blind hole region, and the blind hole region is arranged between the two through hole regions.

3. The display substrate according to claim 1, characterized in that: The shape of the through hole area is circular or elliptical; The shape of the blind hole area is a rectangle, a rounded rectangle, a shape formed by joining rectangles of different widths along their length, or a shape formed by joining rectangles of different widths along their length.

4. The display substrate according to claim 1, characterized in that: The plurality of signal lines include a plurality of data lines and a plurality of gate drive signal lines; The plurality of gate drive signal lines extend in a first direction as a whole; the plurality of data lines extend in a second direction as a whole; wherein the first direction intersects with the second direction; At least one data line includes a portion located in the wiring area and arranged around the through hole area and / or a portion arranged around the blind hole area; At least one gate driving signal line includes a portion located in the wiring area and arranged around the through hole area and / or a portion arranged around the blind hole area.

5. The display substrate according to claim 4, characterized in that: The plurality of signal lines further include a plurality of initialization signal lines; The plurality of initialization signal lines extend overall along the first direction; At least one initialization signal line includes a portion located in the wiring area and arranged around the through hole area and / or a portion arranged around the blind hole area.

6. The display substrate according to claim 5, characterized in that: The plurality of signal lines further include a plurality of light emission control signal lines; The plurality of light-emitting control signal lines extend along the first direction as a whole; At least one light-emitting control signal line includes a portion located in the wiring area and arranged around the through-hole area and / or a portion arranged around the blind-hole area; or, At least one light-emitting control signal line includes parts located in the display area and the hole edge area, and is cut off at a position extending to the through hole area and / or the blind hole area along the first direction.

7. The display substrate according to any one of claims 1 to 6, characterized in that: The at least one metal layer includes a first gate layer, a second gate layer and a source-drain metal layer; the at least one insulating layer includes a first insulating layer, a second insulating layer and an interlayer insulating layer; The driving circuit layer further comprises a semiconductor layer; the semiconductor layer is located in the display area and the hole edge area; The semiconductor layer is arranged on one side of the substrate; The first insulating layer is disposed on a side of the semiconductor layer away from the substrate; The first gate layer is disposed on a side of the first insulating layer away from the base substrate; The second insulating layer is disposed on a side of the first gate layer away from the base substrate; The second gate layer is arranged on a side of the second insulating layer away from the base substrate; The interlayer insulating layer is arranged on a side of the second gate layer away from the base substrate; The source-drain metal layer is arranged on a side of the second gate layer away from the base substrate.

8. The display substrate according to claim 7, characterized in that: In the case where the plurality of signal lines include a plurality of data lines, a plurality of light emission control signal lines, a plurality of gate drive signal lines and a plurality of initialization signal lines, The plurality of data lines are located in the source-drain metal layer; The plurality of light emitting control signal lines and the plurality of gate driving signal lines are located in the first gate layer; The plurality of initialization signal lines are located in the second gate layer.

9. The display substrate according to claim 7, characterized in that: Also includes: A light emitting device layer disposed on a side of the driving circuit layer away from the base substrate; The light emitting device layer is located in the display area and the hole edge area; The light emitting device layer comprises: A first electrode layer is disposed on a side of the driving circuit layer away from the base substrate, wherein the first electrode layer includes a plurality of first electrodes; A pixel defining layer disposed on a side of the first electrode layer away from the base substrate, wherein a plurality of openings are disposed in the pixel defining layer, and each opening exposes at least a portion of a first electrode; A functional layer disposed on a side of the first electrode layer away from the base substrate, the functional layer comprising a plurality of light-emitting portions, each of which is located in an opening; A second electrode layer is disposed on a side of the functional layer and the pixel defining layer away from the base substrate; The display area is provided with a plurality of pixel structures, each pixel structure includes a pixel circuit and a light-emitting device; the light-emitting device includes a first electrode electrically connected to the pixel circuit, a light-emitting portion, and a portion of the second electrode layer corresponding to the light-emitting portion; The hole edge area is provided with a plurality of redundant pixel structures; each redundant pixel structure includes a redundant pixel circuit and / or a redundant light-emitting device; the redundant light-emitting device includes a light-emitting portion and a portion of the second electrode layer corresponding to the light-emitting portion; or, the redundant light-emitting device includes a first electrode, a light-emitting portion and a portion of the second electrode layer corresponding to the light-emitting portion, and the first electrode is not electrically connected to the redundant pixel circuit.

10. The display substrate according to claim 9, characterized in that: The pixel circuit and the redundant pixel circuit each include at least one thin film transistor, and the thin film transistor includes an active layer, a gate, a source electrode, and a drain electrode; The active layer is located in the semiconductor layer, the gate is located in the first gate layer, and the source and the drain are located in the source-drain metal layer; The hole edge area includes a first sub-area close to the wiring area, and a second sub-area except the first sub-area; The display substrate further comprises: A plurality of via holes are arranged in the second sub-region of the hole edge region, each via hole penetrates the first insulating layer, the second insulating layer and the interlayer insulating layer; the plurality of redundant pixel circuits are arranged in the second sub-region of the hole edge region, and the source and drain of each thin film transistor in the plurality of redundant pixel circuits are electrically connected to the active layer through the via holes; A plurality of redundant via holes are arranged in a first sub-region of the hole edge region, each redundant via hole passing through the first insulating layer, the second insulating layer and the interlayer insulating layer; A planarization layer is arranged between the driving circuit layer and the light-emitting device layer, and the planarization layer is located in the display area, the hole edge area, the wiring area and the blind hole area; a portion of the planarization layer fills the multiple redundant vias.

11. The display substrate according to claim 10, characterized in that: The at least one packaging area includes at least one packaging dam area; each packaging dam area is located between a through-hole area and a wiring area surrounding the through-hole area, and surrounds the through-hole area; The first insulating layer, the second insulating layer and the interlayer insulating layer are also located in the at least one encapsulation dam area; The display substrate further comprises: Multiple encapsulation dams; Each packaging dam area is provided with at least one packaging dam, the packaging dam surrounds the through hole area, and the packaging dam is provided on a side of the driving circuit layer away from the substrate; In the case where at least two packaging dams are provided in each packaging dam area, the at least two packaging dams are sequentially spaced apart along the radial direction of the through hole area.

12. The display substrate according to claim 11, characterized in that: At least one packaging dam disposed in each packaging dam area includes a first packaging dam and a second packaging dam, wherein the first packaging dam is located on a side of the second packaging dam away from the through hole area; The thickness of the second encapsulation dam along the third direction is greater than the thickness of the first encapsulation dam along the third direction; wherein the third direction is perpendicular to the substrate; The second encapsulation dam comprises: The first part is arranged on the same layer as the planarization layer; A second portion disposed on a side of the first portion away from the base substrate; the second portion is disposed on the same layer as the pixel defining layer; A first spacer portion disposed on a side of the second portion away from the base substrate; The first encapsulation dam comprises: The third part is arranged on the same layer as the pixel defining layer; A second spacer portion is disposed on a side of the third portion away from the base substrate, and the second spacer portion is made of the same material and is disposed in the same layer as the first spacer portion.

13. The display substrate according to claim 12, characterized in that: The at least one encapsulation region further comprises at least one first isolation region and at least one second isolation region; The first insulating layer, the second insulating layer and the interlayer insulating layer are also located in the at least one first isolation region and the at least one second isolation region; Each first isolation region is located between the wiring region and the packaging dam region, and surrounds the packaging dam region; each second isolation region is located between the through-hole region and the packaging dam region, and surrounds the through-hole region; The display substrate further comprises: A plurality of first isolation columns, each first isolation region is provided with at least one first isolation column, each first isolation column is arranged around the first encapsulation dam, and the first isolation column is arranged on a side of the interlayer insulating layer away from the substrate; a groove is arranged on a sidewall of the first isolation column; A plurality of second isolation columns, each second isolation region is provided with at least one second isolation column, each second isolation column is arranged around the through hole region, and the second isolation column is arranged on a side of the interlayer insulating layer away from the base substrate; a groove is arranged on a sidewall of the second isolation column; The at least one packaging dam, the at least one first isolation column, and the at least one second isolation column constitute the packaging structure.

14. The display substrate according to claim 13, characterized in that: The first isolation column and the second isolation column are located in the source-drain metal layer.

15. The display substrate according to claim 13, characterized in that: The first isolation column and the second isolation column both include a first metal pattern, a second metal pattern and a third metal pattern stacked in sequence, and the outer boundary of the orthographic projection of the second metal pattern on the base substrate is located inside the outer boundary of the orthographic projection of the first metal pattern and the third metal pattern on the base substrate, so as to form the groove on the side wall of the first isolation column and the side wall of the second isolation column.

16. The display substrate according to any one of claims 13 to 15, characterized in that: The second isolation region is further provided with at least one fourth metal pattern and at least one fifth metal pattern, the fourth metal pattern is located in the first gate layer, and the fifth metal pattern is located in the second gate layer; Each fourth metal pattern and each fifth metal pattern surround the through-hole region; The orthographic projections of the second isolation column, the fourth metal pattern and the fifth metal pattern on the base substrate have a common overlapping area.

17. The display substrate according to any one of claims 13 to 15, characterized in that: In the case where at least two first isolation columns are provided in each first isolation region, the at least two first isolation columns are sequentially spaced apart along the radial direction of the through hole region; A portion of the driving circuit layer located between two connected first isolation columns has a first groove, and the first groove exposes the base substrate; In the case where at least two second isolation columns are provided in each second isolation region, the at least two second isolation columns are sequentially spaced apart along the radial direction of the through hole region; A portion of the driving circuit layer located between two adjacent second isolation columns has a recess.

18. The display substrate according to any one of claims 13 to 15, characterized in that: Also includes: An encapsulation layer disposed on a side of the light emitting device layer away from the base substrate; The encapsulation layer comprises: A first inorganic encapsulation thin film layer is disposed on a side of the light-emitting device layer away from the base substrate; the first inorganic encapsulation thin film layer is located in the second isolation area, the encapsulation dam area, the first isolation area, the wiring area, the hole edge area, the display area and the blind hole area; An organic encapsulation thin film layer is disposed on a side of the first inorganic encapsulation thin film layer away from the base substrate; the organic encapsulation thin film layer is located in the encapsulation dam area, the first isolation area, the wiring area, the hole edge area, the display area and the blind hole area; A second inorganic encapsulation film layer is arranged on the side of the organic encapsulation film layer away from the base substrate; the second inorganic encapsulation film layer encapsulates the second isolation area, the encapsulation dam area, the first isolation area, the wiring area, the hole edge area, the display area and the blind hole area.

19. A display device, characterized in that: include: The display substrate according to any one of claims 1 to 18; at least one first sensor, each first sensor being disposed in a through hole area; At least one second sensor, each second sensor is arranged in a blind hole area.

20. The display device according to claim 19, characterized in that The at least one first sensor includes a camera, and the at least one second sensor includes at least one of an infrared sensor, a proximity light sensor, a flood illuminator, and an ambient light sensor.

21. A method for preparing a display substrate, characterized in that: include: providing a substrate base plate; The substrate comprises a display area, a hole edge area, a plurality of wiring areas, at least one packaging area, at least one through hole area and at least one blind hole area, the wiring area surrounds a through hole area or a blind hole area, the hole edge area surrounds the wiring area, the display area surrounds the hole edge area, the blind hole area is adjacent to the wiring area surrounding the blind hole area, and the packaging area is arranged between the through hole area and the wiring area surrounding the through hole area; A packaging structure is arranged in the packaging area; forming a driving circuit layer on the base substrate; The driving circuit layer comprises: At least one metal layer is located in the display area, the hole edge area and the wiring area; the at least one metal layer includes a plurality of signal lines, and the plurality of signal lines are arranged to avoid the through hole area and the blind hole area; At least one insulating layer is located in the display area, the hole edge area, the wiring area, the through hole area and the blind hole area; Forming a planarization layer on a side of the driving circuit layer away from the base substrate, wherein the planarization layer is located in the display area, the hole edge area, the wiring area, the through hole area and the blind hole area; A light-emitting device layer is formed on a side of the planarization layer away from the base substrate; the light-emitting device layer is located in the display area and the hole edge area; An encapsulation layer is formed on a side of the light-emitting device layer away from the base substrate; the encapsulation layer is located in the display area, the hole edge area, the wiring area, the through hole area and the blind hole area, and the through hole area and the blind hole area are used to set an optical sensor; Portions of the base substrate, the driving circuit layer, the planarization layer and the encapsulation layer located in the through-hole area are removed.

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