Method for manufacturing semiconductor device and semiconductor device

Abstract

The semiconductor device includes: a semiconductor nanostructure, arranged above a substrate; a source / drain epitaxial layer, contacting the semiconductor nanostructure; a gate dielectric layer, arranged on each channel region of the semiconductor nanostructure and wrapping each channel region of the semiconductor nanostructure; a gate electrode layer, arranged on the gate dielectric layer and wrapping each channel region; and insulating spacers, respectively arranged in the intervals. The intervals are defined by adjacent semiconductor nanostructures, gate electrode layers, and source / drain regions. The source / drain epitaxial layer includes a plurality of doped SiGe layers with different Ge contents, and at least one of the source / drain epitaxial layers is undoped SiGe or Si. Embodiments of the present application also relate to methods for manufacturing semiconductor devices.

Description

Technical Field

[0001] Embodiments of the present application relate to a method of manufacturing a semiconductor device and a semiconductor device. Background Art

[0002] As the semiconductor industry has developed to nanotechnology process nodes that pursue higher device density, higher performance and lower cost, the dual challenges from manufacturing and design issues have produced the development of three-dimensional designs, such as multi-gate field effect transistors (FETs), including fin FETs (Fin FETs) and all-around gate (GAA) FETs. In Fin FETs, the gate electrode is adjacent to three sides of the channel region, wherein the gate dielectric layer is between the gate electrode and the channel region. Because the gate structure surrounds (wraps) the fin on three surfaces, the transistor basically has three gates that control the current through the fin or channel region. Unfortunately, the fourth side (the bottom of the channel) is far away from the gate electrode and is therefore not subject to strict gate control. In contrast, in GAA FETs, all sides of the channel region are surrounded by gate electrodes, which allows for more complete depletion in the channel region and produces a smaller short channel effect due to a steeper subthreshold current swing (SS) and a smaller drain-induced barrier reduction (DIBL). As transistor size continues to shrink, there is a need to further improve GAA FETs. Summary of the invention

[0003] Some embodiments of the present application provide a method for manufacturing a semiconductor device, comprising: forming a fin structure in which a first semiconductor layer and a second semiconductor layer are alternately stacked; forming a sacrificial gate structure above the fin structure; etching a source / drain region of the fin structure not covered by the sacrificial gate structure to form a source / drain gap; forming a base epitaxial layer at the bottom of the source / drain gap; and forming a source / drain epitaxial layer on the base epitaxial layer, wherein the base epitaxial layer comprises an undoped semiconductor material.

[0004] Other embodiments of the present application provide a method for manufacturing a semiconductor device, comprising: forming a fin structure in which a first semiconductor layer and a second semiconductor layer are alternately stacked; forming a sacrificial gate structure above the fin structure; etching the source / drain region of the fin structure not covered by the sacrificial gate structure to form a source / drain spacer; laterally etching the first semiconductor layer through the source / drain spacer; and forming an internal spacer made of a dielectric material on each end of the etched first semiconductor layer; forming a base epitaxial layer at the bottom of the source / drain spacer; and forming a source / drain epitaxial layer on the base epitaxial layer, wherein, after forming the base epitaxial layer and before forming the source / drain epitaxial layer, at least one process selected from the group consisting of a photolithography process and an etching process is performed.

[0005] Some other embodiments of the present application provide a semiconductor device, comprising: a semiconductor nanostructure, arranged above a substrate; a source / drain epitaxial layer, in contact with the semiconductor nanostructure; a gate dielectric layer, arranged on each channel region of the semiconductor nanostructure and wrapping each channel region of the semiconductor nanostructure; a gate electrode layer, arranged on the gate dielectric layer and wrapping each channel region; and insulating spacers, respectively arranged in intervals, wherein the intervals are defined by adjacent semiconductor nanostructures, the gate electrode layer and the source / drain regions, wherein the source / drain epitaxial layer comprises an undoped base epitaxial layer and a plurality of epitaxial semiconductor layers having different compositions from each other formed on the base epitaxial layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustrative purposes. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figures 1A to 1D Various views of a semiconductor FET device according to an embodiment of the present invention are shown. Figure 1A is a cross-sectional view along the X direction (source-drain direction), Figure 1B is corresponding to Figure 1A The Y1-Y1 cross-sectional view, Figure 1C is corresponding to Figure 1A The Y2-Y2 cross-sectional view, and Figure 1D Shows the corresponding Figure 1A Cross-sectional view of Y3-Y3.

[0008] Figure 2 One of the various stages in fabricating a semiconductor GAA FET device according to an embodiment of the present invention is shown.

[0009] Figure 3 One of the various stages in fabricating a semiconductor GAA FET device according to an embodiment of the present invention is shown.

[0010] Figure 4A and Figure 4B One of the various stages in fabricating a semiconductor GAA FET device according to an embodiment of the present invention is shown.

[0011] Figure 5 One of the various stages in fabricating a semiconductor GAA FET device according to an embodiment of the present invention is shown.

[0012] Figure 6One of the various stages in fabricating a semiconductor GAA FET device according to an embodiment of the present invention is shown.

[0013] Figure 7 One of the various stages in fabricating a semiconductor GAA FET device according to an embodiment of the present invention is shown.

[0014] Figure 8 One of the various stages in fabricating a semiconductor GAA FET device according to an embodiment of the present invention is shown.

[0015] Fig. 9A and Fig. 9B One of the various stages in fabricating a semiconductor GAA FET device according to an embodiment of the present invention is shown.

[0016] Fig. 10A and Fig. 10B One of the various stages in fabricating a semiconductor GAA FET device according to an embodiment of the present invention is shown.

[0017] Fig.11A and Fig. 11B One of the various stages in fabricating a semiconductor GAA FET device according to an embodiment of the present invention is shown.

[0018] Fig. 12A and Fig. 12B One of the various stages in fabricating a semiconductor GAA FET device according to an embodiment of the present invention is shown.

[0019] Fig.13A and Fig. 13B One of the various stages in fabricating a semiconductor GAA FET device according to an embodiment of the present invention is shown.

[0020] Fig.14A and Fig. 14B One of the various stages in fabricating a semiconductor GAA FET device according to an embodiment of the present invention is shown.

[0021] Fig.15A and Fig. 15B One of the various stages in fabricating a semiconductor GAA FET device according to an embodiment of the present invention is shown.

[0022] Fig.16A and Fig. 16B One of the various stages in fabricating a semiconductor GAA FET device according to an embodiment of the present invention is shown.

[0023] Fig.17A and Fig. 17B One of the various stages in fabricating a semiconductor GAA FET device according to an embodiment of the present invention is shown.

[0024] Fig.18A and Fig.18B One of the various stages in fabricating a semiconductor GAA FET device according to an embodiment of the present invention is shown.

[0025] Fig.19A , Fig.19B , Fig.19C and Fig.19D Various stages in manufacturing a semiconductor GAA FET device according to an embodiment of the present invention are shown.

[0026] Fig. 20 The composition variation of the source / drain epitaxial layer according to an embodiment of the present invention is shown (graph).

[0027] Fig.21A and Fig. 21B A cross-sectional view is shown at one of the various stages in the fabrication of a semiconductor GAA FET device in accordance with an embodiment of the present invention.

[0028] Fig.22A and Fig. 22B A cross-sectional view of a semiconductor GAA FET device according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0029] It should be understood that the following disclosure provides many different embodiments or examples for realizing different features of the present invention. Specific embodiments or examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, the size of the element is not limited to the disclosed range or value, but may depend on the process conditions and / or the desired characteristics of the device. In addition, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. For simplicity and clarity, the various components may be drawn arbitrarily in different proportions.

[0030] Moreover, for ease of description, spatially relative terms such as "under," "below," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or other) elements or components as shown in the figures. In addition to the orientation shown in the figures, spatially relative terms are intended to include different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly. In addition, the term "made of" may mean "including" or "consisting of." In the present invention, unless otherwise described, the phrase "one of A, B and C" means "A, B and / or C" (A, B, C, A and B, A and C, B and C, or A, B and C), and does not mean one element from A, one element from B, and one element from C.

[0031] Generally, when releasing nanostructures such as nanowires (NWs) and nanosheets by selectively etching a sacrificial semiconductor layer, it is difficult to control the amount of lateral etching. When the NW release etching process is implemented after removing the pseudo polysilicon gate, the lateral end of the NW may be etched because the lateral etching control or etching budget for the NW release etching is insufficient. If there is no etching stop layer, the gate electrode may contact the source / drain (source / drain) epitaxial layer. In addition, the impact on the gate-to-drain capacitance (Cgd) is greater. If there is no dielectric film between the gate and the source / drain region, Cgd becomes larger, which will reduce the circuit speed. In addition, in FinFET or GAA FET, the source / drain (source / drain) epitaxial layer is required to be defect-free. In the present invention, a novel method for manufacturing a source / drain (source and / or drain) epitaxial layer for GAA FET and stacked channel FET is provided. In the present invention, source / drain refers to source and / or drain. It should be noted that in the present invention, source and drain are used interchangeably and their structures are basically the same.

[0032] Figures 1A to 1D Various views of a semiconductor GAA FET device according to an embodiment of the present invention are shown. Figure 1A is a cross-sectional view along the X direction (source-drain direction), Figure 1B is corresponding to Figure 1A The Y1-Y1 cross-sectional view, Figure 1C is corresponding to Figure 1A The Y2-Y2 cross-sectional view, and Figure 1D Shows the corresponding Figure 1A In some embodiments, Figures 1A to 1D The semiconductor GAA FET device is a p-type FET.

[0033] like Figures 1A to 1CAs shown, a semiconductor nanostructure 25 vertically arranged along the Z direction (the normal direction of the main surface of the substrate 10) is provided above the semiconductor substrate 10. In some embodiments, the substrate 10 includes a single crystal semiconductor layer at least on its surface portion. The substrate 10 may include a single crystal semiconductor material such as, but not limited to, Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP. In some embodiments, the substrate 10 is made of crystalline Si.

[0034] The substrate 10 may include one or more buffer layers (not shown) in its surface region. The buffer layer may be used to gradually change the lattice constant from that of the substrate to that of the source / drain region. The buffer layer may be formed of an epitaxially grown single crystalline semiconductor material such as, but not limited to, Si, Ge, GeSn, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, GaN, GaP, and InP. In a particular embodiment, the substrate 10 includes a silicon germanium (SiGe) buffer layer epitaxially grown on the silicon substrate 10. The germanium concentration of the SiGe buffer layer may increase from 30% atomic germanium in the bottommost buffer layer to 70% atomic germanium in the topmost buffer layer.

[0035] like Figures 1A to 1C As shown, a semiconductor line or sheet (collectively referred to as a nanostructure) 25 as a channel layer is disposed above the substrate 10. In some embodiments, the semiconductor nanostructure 25 is disposed on the fin structure 11 (see FIG. 1 ) protruding from the substrate 10 (bottom fin structure 11). Figure 3 ) above. Each of the channel layers 25 is wrapped by a gate dielectric layer 82 and a gate electrode layer 84. In some embodiments, the thickness T1 of the semiconductor nanostructure 25 is in the range of about 5 nm to about 60 nm, and the width W1 of the semiconductor nanostructure 25 is in the range of about 5 nm to about 120 nm. In some embodiments, the width of the semiconductor wire or sheet is greater than the thickness. In some embodiments, the width is up to two or five times the thickness of the semiconductor nanostructure 25. In some embodiments, the semiconductor nanostructure 25 is made of Si, SiGe or Ge.

[0036] In some embodiments, an interfacial dielectric layer is formed between the channel of the semiconductor nanostructure 25 and the gate dielectric layer 82. In some embodiments, the gate dielectric layer 82 comprises a high-k dielectric layer. The gate structure comprises the gate dielectric layer 82, the gate electrode layer 84, and the sidewall spacer 45. Figures 1A to 1C Four semiconductor nanostructures 25 are shown, but the number of semiconductor nanostructures 25 is not limited to four, and may be as small as one or more than four, and may be as many as 10. By adjusting the number of semiconductor wires, the drive current of the GAA FET device may be adjusted.

[0037] In addition, the source / drain epitaxial layer 50 is disposed above the substrate 10. The source / drain epitaxial layer 50 is in direct contact with the end surface of the channel layer 25, and is separated from the gate electrode layer 84 by the insulating internal spacer 35 and the gate dielectric layer 82. In some embodiments, a base epitaxial layer 49 is formed below the source / drain epitaxial layer 50. In some embodiments, the semiconductor nanostructure 25 and the base epitaxial layer 49 are made of the same material (e.g., Si, SiGe or Ge), except for the doping conditions (doping elements and / or doping concentrations). In some embodiments, the base epitaxial layer 49 is made of an undoped semiconductor material, and the semiconductor nanostructure 25 is made of the same undoped or doped semiconductor material as the base epitaxial layer. In some embodiments, when the base epitaxial layer 49 and the semiconductor nanostructure (wire or sheet) 25 are made of SiGe, the Ge amount is the same or different from each other. In other embodiments, the semiconductor nanostructure 25 and the base epitaxial layer 49 are made of different semiconductor materials.

[0038] In some embodiments, an additional insulating layer (not shown) is conformally formed on the inner surface of the spacer region. Figure 1A As shown, the cross section along the X direction of the inner spacer 35 has a circular shape (eg, a semicircular shape or a U shape) protruding toward the gate electrode.

[0039] An interlayer dielectric (ILD) layer 70 is disposed over the source / drain epitaxial layer 50, and a conductive contact layer 72 is disposed on the source / drain epitaxial layer 50, and a conductive plug 75 passing through the ILD layer 70 is disposed over the conductive contact layer 72. The conductive contact layer 72 includes one or more layers of conductive material. In some embodiments, the conductive contact layer 72 includes a silicide layer, such as WSi, NiSi, TiSi, or CoSi or other suitable silicide materials or alloys of metal elements and silicon and / or germanium. In some embodiments, an etch stop layer 68 is disposed between the sidewall spacer 45 and the ILD layer 70 and on a portion of the upper surface of the epitaxial layer 50.

[0040] In some embodiments, Figures 1A to 1D The FET shown is a p-type FET. The source / drain epitaxial layer includes one or more layers of Si, SiGe, Ge, SiGeSn, SiSn, and GeSnP. In some embodiments, the source / drain epitaxial layer also includes boron (B).

[0041] Figures 2 to 18B 1 shows various stages of manufacturing a semiconductor FET device according to an embodiment of the present invention. It should be understood that additional embodiments of the method may be Figures 2 to 18BAdditional operations are provided before, during, and after the processes shown, and some of the operations described below may be replaced or eliminated. The order of operations / processes may be interchanged. Figures 2 to 18B In the embodiments, the Figures 1A to 1D The above embodiments are described with the same or similar materials, configurations, sizes, and / or processes, and their detailed descriptions may be omitted.

[0042] like Figure 2 As shown, first semiconductor layers 20 and second semiconductor layers 25 are alternately formed over a substrate 10. The first semiconductor layer 20 and the second semiconductor layer 25 are made of materials having different lattice constants, and may include one or more layers of Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, or InP.

[0043] In some embodiments, the first semiconductor layer 20 and the second semiconductor layer 25 are made of Si, Si compounds, SiGe, Ge or Ge compounds. In some embodiments, the first semiconductor layer 20 is Si 1-x Ge x , wherein x is equal to or greater than about 0.1 and equal to or less than about 0.6, and the second semiconductor layer 25 is Si or Si 1-y Ge y , wherein y is less than x and is equal to or less than about 0.2. In the present invention, "M compound" or "M-based compound" means that the majority of the compound is M.

[0044] In other embodiments, the second semiconductor layer 25 is Si 1-x Ge x , wherein x is equal to or greater than about 0.1 and equal to or less than about 0.6, and the first semiconductor layer 20 is Si or Si 1-y Ge y , where y is less than x and is equal to or less than approximately 0.2.

[0045] A first semiconductor layer 20 and a second semiconductor layer 25 are epitaxially formed over the substrate 10. The thickness of the first semiconductor layer 20 may be equal to or greater than the thickness of the second semiconductor layer 25, and in some embodiments, is in the range of about 5 nm to about 60 nm, and in other embodiments, is in the range of about 10 nm to about 30 nm. In some embodiments, the thickness of the second semiconductor layer 25 is in the range of about 5 nm to about 60 nm, and in other embodiments, is in the range of about 10 nm to about 30 nm. The thickness of the first semiconductor layer 20 may be the same as or different from the thickness of the second semiconductor layer 25. Although in Figure 2Four first semiconductor layers 20 and four second semiconductor layers 25 are shown in the figure, but the number is not limited to four, and may be 1, 2, 3, or greater than 4, and less than 20. In some embodiments, the number of first semiconductor layers 20 is one greater than the number of second semiconductor layers 25 (i.e., the top layer is the first semiconductor layer).

[0046] After forming the stacked semiconductor layers, the fin structure is formed by using one or more photolithography and etching operations, such as Figure 3 As shown. The fin structure can be patterned by any suitable method. For example, the fin structure can be patterned using one or more photolithography processes including a double patterning process or a multiple patterning process. Typically, the double patterning or multiple patterning process combines photolithography and self-alignment processes, thereby allowing the creation of patterns with, for example, a pitch smaller than that obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fin structure.

[0047] like Figure 3 As shown, the fin structures 29 extend in the X direction and are arranged in the Y direction. The number of fin structures is not limited to Figure 3 In some embodiments, one or more dummy fin structures are formed on both sides of the fin structure 29 to improve pattern fidelity in the patterning operation. Figure 3 As shown, the fin structure 29 has an upper portion constituted by the stacked semiconductor layers 20 , 25 and the well portion 11 .

[0048] In some embodiments, the width of the upper portion of the fin structure 29 along the Y direction is in a range from about 10 nm to about 40 nm, and in other embodiments, in a range from about 20 nm to about 30 nm.

[0049] After forming the fin structure 29, an insulating material layer including one or more insulating materials is formed over the substrate so that the fin structure is completely embedded in the insulating layer. The insulating material for the insulating layer may include silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN, fluorine-doped silicate glass (FSG), or low-k dielectric material formed by LPCVD (low pressure chemical vapor deposition), plasma enhanced CVD (PECVD), or flowable CVD. An annealing operation may be performed after forming the insulating layer. Then, a planarization operation such as a chemical mechanical polishing (CMP) method and / or an etch-back method is performed so that the upper surface of the uppermost second semiconductor layer 25 is exposed from the insulating material layer. In some embodiments, before forming the insulating material layer, one or more fin liner layers are formed over the fin structure. In some embodiments, the fin liner layer includes a first fin liner layer formed over the substrate 10 and over the sidewalls of the bottom portion of the fin structure 11 and a second fin liner layer formed on the first fin liner layer. The fin liner layer is made of silicon nitride or a silicon nitride-based material (e.g., SiON, SiCN, or SiOCN). The fin liner layer may be deposited by one or more processes such as physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD), but any acceptable process may be utilized.

[0050] Then, if Figure 3 As shown, the insulating material layer is recessed to form an isolation insulating layer 15 so that the upper portion of the fin structure 29 is exposed. Through this operation, the fin structures 29 are separated from each other by the isolation insulating layer 15, which is also called shallow trench isolation (STI). The isolation insulating layer 15 can be made of a suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectrics (such as carbon-doped oxides), very low-k dielectrics (such as porous carbon-doped silicon dioxide), polymers (such as polyimide), combinations of these, etc. In some embodiments, the isolation insulating layer 15 is formed by a process such as CVD, flowable CVD (FCVD), or a spin-on glass process, but any acceptable process can be used.

[0051] In some embodiments, the insulating material layer 15 is recessed until the upper portion of the fin structure (well layer) 11 is exposed. In other embodiments, the upper portion of the fin structure 11 is not exposed. The first semiconductor layer 20 is a sacrificial layer that is subsequently partially removed, and the second semiconductor layer 25 is subsequently formed into a semiconductor line as a channel layer of a p-type GAA FET. In other embodiments, the second semiconductor layer 25 is a sacrificial layer that is subsequently partially removed, and the first semiconductor layer 20 is subsequently formed into a semiconductor line as a channel layer.

[0052] After forming the isolation insulating layer 15, a sacrificial (dummy) gate structure 40 is formed. Figure 4A and Figure 4B shown. Figure 4A and Figure 4B The structure after forming a sacrificial gate structure 40 over the exposed fin structure 29 is shown. The sacrificial gate structure 40 is formed over the portion of the fin structure that will become the channel region. The sacrificial gate structure 40 defines the channel region of the GAA FET. The sacrificial gate structure 40 includes a sacrificial gate dielectric layer 41 and a sacrificial gate electrode layer 42. The sacrificial gate dielectric layer 41 includes one or more layers of insulating material, such as a silicon oxide-based material. In one embodiment, silicon oxide formed by CVD is used. In some embodiments, the thickness of the sacrificial gate dielectric layer 41 is in the range of about 1 nm to about 5 nm.

[0053] The sacrificial gate structure 40 is formed by first blanket depositing a sacrificial gate dielectric layer 41 over the fin structure. Then a sacrificial gate electrode layer is blanket deposited over the sacrificial gate dielectric layer and over the fin structure so that the fin structure is completely embedded in the sacrificial gate electrode layer. The sacrificial gate electrode layer includes silicon such as polysilicon or amorphous silicon. In some embodiments, the thickness of the sacrificial gate electrode layer is in the range of about 100nm to about 200nm. In some embodiments, the sacrificial gate electrode layer undergoes a planarization operation. The sacrificial gate dielectric layer and the sacrificial gate electrode layer are deposited using CVD including LPCVD and PECVD, PVD, ALD or other suitable processes. Subsequently, a mask layer is formed over the sacrificial gate electrode layer. The mask layer includes a pad silicon nitride layer 43 and a silicon oxide mask layer 44.

[0054] Next, if Figure 4A and Figure 4B As shown, a patterning operation is performed on the mask layer, and the sacrificial gate electrode layer is patterned into a sacrificial gate structure 40. The sacrificial gate structure includes a sacrificial gate dielectric layer 41, a sacrificial gate electrode layer 42 (e.g., polysilicon), a pad silicon nitride layer 43, and a silicon oxide mask layer 44. By patterning the sacrificial gate structure, the stacked layers of the first semiconductor layer and the second semiconductor layer are partially exposed on opposite sides of the sacrificial gate structure, thereby defining source / drain regions, such as Figure 4A and Figure 4B As shown. In the present invention, the source and drain can be used interchangeably, and their structures are basically the same. Figure 4A and Figure 4B In the embodiment, a sacrificial gate structure is formed on two fin structures, but the number of sacrificial gate structures is not limited to one. In some embodiments, two or more sacrificial gate structures are arranged in the X direction. In some embodiments, one or more dummy sacrificial gate structures are formed on both sides of the sacrificial gate structure to improve pattern fidelity.

[0055] In addition, a first capping layer 45 for sidewall spacers is formed over the sacrificial gate structure 40, such as Figure 4A and Figure 4B As shown. The first capping layer 45 is deposited in a conformal manner so that it is formed to have substantially equal thicknesses on vertical surfaces (such as the sidewalls, horizontal surfaces, and top of the sacrificial gate structure). In some embodiments, the first capping layer 45 has a thickness in the range of about 5 nm to about 20 nm. The first capping layer 45 includes one or more of silicon nitride, SiON, SiCN, SiCO, SiOCN, or any other suitable dielectric material. The capping layer 45 can be formed by ALD or CVD or any other suitable method.

[0056] Figure 5 A cross-sectional view along the X direction is shown. Next, as Figure 5 As shown, the first capping layer 45 is anisotropically etched to remove the first capping layer 45 disposed on the source / drain region while leaving the first capping layer 45 on the side of the sacrificial gate structure 40 as a sidewall spacer. Then, by using one or more photolithography and etching operations, the stacked structure of the first semiconductor layer 20 and the second semiconductor layer 25 is etched down at the source / drain region to form a source / drain spacer 21. In some embodiments, the substrate 10 (or the bottom portion of the fin structure 11) is also partially etched. In some embodiments, n-type FETs and p-type FETs are manufactured separately, and in this case, a region for one type of FET is processed and a region for the other type of FET is covered by a protective layer such as silicon nitride. In some embodiments, as Figure 5 As shown, the recessed fin structure has a U-shape. In other embodiments, the recessed fin structure has a V-shape showing the (111) facets of the silicon crystal. In other embodiments, the groove has an inverted trapezoidal shape or a rectangular shape.

[0057] In some embodiments, the groove is formed by a dry etching process that may be anisotropic. An anisotropic etching process may be implemented using a process gas mixture including BF2, Cl2, CH3F, CH4, HBr, O2, Ar, other etchant gases. The plasma is a remote plasma generated in a different plasma generation chamber connected to the processing chamber. The process gas may be activated into a plasma by any suitable method for generating plasma (such as a transformer coupled plasma (TCP) system, an inductively coupled plasma (ICP) system, a magnetic enhanced reactive ion technology). The process gas used in the plasma etching process includes an etching gas such as H2, Ar, other gases or a combination of gases. In some embodiments, a carrier gas such as N2, Ar, He and Xe is used in a plasma etching process using hydrogen (H) radicals. The H radicals may be formed by flowing H2 gas into the plasma generation chamber and igniting the plasma in the plasma generation chamber. In some embodiments, an additional gas such as Ar may be ignited into a plasma in the plasma generation chamber. The H radicals may selectively etch the (111) plane or the (100) plane above the (110) plane. In some cases, the etching rate of the (100) plane can be about three times higher than the etching rate of the (111) plane. Due to this selectivity, during the second patterning process, etching by H radicals along the (111) plane or the (110) plane of silicon may tend to slow down or stop.

[0058] In addition, if Figure 6 As shown, the first semiconductor layer 20 is laterally etched in the X direction at the source / drain spacer 21 to form a cavity 22. When the first semiconductor layer 20 is SiGe and the second semiconductor layer 25 is Si, the first semiconductor layer 20 can be selectively etched by using a wet etchant such as, but not limited to, a mixed solution of H2O2, CH3COOH, and HF, followed by H2O cleaning. In some embodiments, etching by the mixed solution and cleaning by water are repeated 10 to 20 times. In some embodiments, the etching time by the mixed solution is in the range of about 1 minute to about 2 minutes. In some embodiments, the mixed solution is used at a temperature in the range of about 60°C to about 90°C. In some embodiments, other etchants are used.

[0059] Next, if Figure 7As shown, a first insulating layer 30 is conformally formed on the etched lateral ends of the first semiconductor layer 20 in the source / drain spacer 21 and above the sacrificial gate structure 40 and on the end surface of the second semiconductor layer 25. The first insulating layer 30 includes one of silicon nitride and silicon oxide, SiON, SiOC, SiCN and SiOCN or any other suitable dielectric material. The first insulating layer 30 is made of a material different from the sidewall spacer (first capping layer) 45. In some embodiments, the first insulating layer 30 has a thickness in the range of about 1.0nm to about 10.0nm. In other embodiments, the first insulating layer 30 has a thickness in the range of about 2.0nm to about 5.0nm. The first insulating layer 30 can be formed by ALD or any other suitable method. By conformally forming the first insulating layer 30, the cavity 22 is completely filled with the first insulating layer 30.

[0060] After forming the first insulating layer 30, an etching operation is performed to partially remove the first insulating layer 30, thereby forming an inner spacer 35, such as Figure 8 As shown. In some embodiments, the end surface of the inner spacer 35 is more recessed than the end surface of the second semiconductor layer 25. The recess amount is in the range of about 0.2nm to about 3nm, and in other embodiments, in the range of about 0.5nm to about 2nm. In other embodiments, the recess amount is less than 0.5nm and can be equal to zero (i.e., the end surface of the inner spacer 35 and the end surface of the second semiconductor layer 25 are flush with each other).

[0061] In some embodiments, before forming the first insulating layer 30, an additional insulating layer having a thickness smaller than the first insulating layer 30 is formed, and thus the inner spacer 35 has a two-layer structure. In some embodiments, the width (lateral length) of the inner spacer 35 is not constant.

[0062] exist Fig. 9A and FIG. 9B to FIG. 18A and Fig.18B , “A” diagram shows an n-type FET, and “B” diagram shows a p-type FET.

[0063] Then, if Fig. 9A and Fig. 9BAs shown, a base epitaxial layer 49 is formed on the recessed fin structure 11 at the bottom of the source / drain spacer 21. In some embodiments, the base epitaxial layer 49 is undoped Si or undoped SiGe. In some embodiments, the semiconductor material of the base epitaxial layer 49 is the same as the semiconductor material (e.g., Si, SiGe or Ge) of the second semiconductor layer 25, except for doping (such as doping elements and / or doping concentrations). In some embodiments, the base epitaxial layer 49 is made of undoped semiconductor material, and the second semiconductor layer 25 is made of the same undoped or doped semiconductor material as the base epitaxial layer. In some embodiments, when the base epitaxial layer 49 and the second semiconductor layer 25 are made of SiGe, the amount of Ge is the same or different from each other. In other embodiments, the second semiconductor layer 25 and the base epitaxial layer 49 are made of different semiconductor materials.

[0064] In some embodiments, the thickness of the base epitaxial layer 49 is in the range of about 5 nm to about 50 nm, depending on the design and process requirements. In some embodiments, the top of the base epitaxial layer is equal to or lower than the bottom of the bottommost inner spacer 35 or the bottom of the bottommost first semiconductor layer 20. In some embodiments, the base epitaxial layer does not contact the bottommost inner spacer 35. In other embodiments, the base epitaxial layer contacts the bottommost inner spacer 35.

[0065] In some embodiments, no gap or seam is formed in the base epitaxial layer 49. In other embodiments, the top of the base epitaxial layer 49 is equal to ± about 5nm of the upper surface of the isolation insulating layer 15. The base epitaxial layer 49 is formed by using an epitaxial growth method of CVD, ALD or molecular beam epitaxy (MBE), using HCl, SiH2Cl2 and SiH4 for Si epitaxial layer or HCl, SiH2Cl2 and GeH4 for SiGe epitaxial layer. In some embodiments, epitaxial growth is a selective growth including etching operations and deposition operations implemented alternately. In some embodiments, the base epitaxial layer is substantially not formed on the end face of the second semiconductor layer 25. In some embodiments, a thin semiconductor layer (e.g., about 0.5-1.0nm) is formed on the end face of the second semiconductor layer 25. The thin semiconductor layer can be removed before forming the source / drain epitaxial layer.

[0066] In some embodiments, a cleaning operation and / or an annealing operation is performed before forming the base epitaxial layer 49. In some embodiments, the cleaning operation includes remote plasma cleaning using a mixed gas of NH3 and NF3 to remove the silicon oxide layer. In some embodiments, the annealing is performed at a temperature in the range of about 650° C. to about 700° C. for about 720 seconds to about 1000 seconds.

[0067] Next, if Fig. 10A and Fig. 10BAs shown, the region for the n-type FET is covered by a capping layer 51. The capping layer 51 is formed by using one or more deposition (e.g., dielectric layer deposition), photolithography and / or etching operations (e.g., patterning operations). In some embodiments, the capping layer 51 is a photoresist layer or a dielectric layer, such as silicon nitride, silicon oxide, aluminum oxide, or any other suitable material.

[0068] Then, a source / drain epitaxial layer 55 is formed in the source / drain spacer 21 for the p-type FET, as shown in FIG. Fig.11A and Fig. 11B As shown below. 19A to 19D The operation of forming the source / drain epitaxial layer 55 is explained. In some embodiments, the source / drain epitaxial layer 55 includes one or more layers of SiGe doped with B. Fig. 11B As shown, a source / drain epitaxial layer 55 is selectively formed on the semiconductor region. The source / drain epitaxial layer 55 is formed to contact the end surface of the second semiconductor layer 25 and to contact the inner spacer 35.

[0069] Next, if Fig. 12A and Fig. 12B As shown, the capping layer 51 is removed from the n-type FET region, and the region for the p-type FET is covered by a capping layer 53. The capping layer 53 is formed by using one or more deposition, photolithography and / or etching operations. In some embodiments, the capping layer 53 is a photoresist layer or a dielectric layer, such as silicon nitride, silicon oxide, aluminum oxide, or any other suitable material.

[0070] Then, a source / drain epitaxial layer 50 is formed in the source / drain spacer 21 for the n-type FET, as shown in FIG. Fig.13A and Fig. 13B As shown below. 19A to 19D The operation of forming the source / drain epitaxial layer 50 is explained. In some embodiments, the source / drain epitaxial layer 50 includes one or more layers of SiP, SiAs and / or SiCP. Fig.13A As shown, a source / drain epitaxial layer 50 is selectively formed on the semiconductor region. The source / drain epitaxial layer 50 is formed to contact the end surface of the second semiconductor layer 25 and to contact the inner spacer 35.

[0071] Then, if Fig.14A and Fig. 14B As shown, the capping layer 53 is removed. In other embodiments, the epitaxial layer 50 for the n-type FET is formed first, and then the epitaxial layer 55 for the p-type FET is formed.

[0072] Then, if Fig.15A and Fig. 15BAs shown, an etch stop layer 68 is formed. The etch stop layer 68 includes one of silicon nitride and silicon oxide, SiON, SiOC, SiCN and SiOCN or any other suitable dielectric material. The etch stop layer 68 is made of a material different from the sidewall spacer (first capping layer) 45. The etch stop layer 68 can be formed by ALD or any other suitable method. Next, a first interlayer dielectric (ILD) layer 70 is formed above the etch stop layer 68. The material used for the ILD layer 70 includes a compound containing Si, O, C and / or H, such as silicon oxide, SiCOH and SiOC. Organic materials such as polymers can be used for the ILD layer 70.

[0073] After forming the ILD layer 70, a planarization operation such as CMP is performed to expose the top of the sacrificial gate electrode layer 42. Fig.16A and Fig. 16B shown.

[0074] Then, if Fig.17A and Fig. 17B As shown, the sacrificial gate electrode layer 42 and the sacrificial gate dielectric layer 41 are removed. During the removal of the sacrificial gate structure, the ILD layer 70 protects the source / drain epitaxial layers 50 and 55. The sacrificial gate structure can be removed using plasma dry etching and / or wet etching. When the sacrificial gate electrode layer 42 is polysilicon and the ILD layer 70 is silicon oxide, a wet etchant such as a TMAH solution can be used to selectively remove the sacrificial gate electrode layer 42. Thereafter, the sacrificial gate dielectric layer 41 is removed using plasma dry etching and / or wet etching.

[0075] After removing the sacrificial gate structure, the first semiconductor layer 20 is removed, thereby forming a line or piece (channel region) of the second semiconductor layer 25. Fig.17A and Fig. 17B The first semiconductor layer 20 may be removed or etched using an etchant that can selectively etch the first semiconductor layer 20 relative to the second semiconductor layer 25, as described above. Fig.13A and Fig. 13B As shown, since the first insulating layer (internal spacer) 35 is formed, etching of the first semiconductor layer 20 stops at the first insulating layer 35. In other words, the first insulating layer 35 serves as an etching stopper for etching the first semiconductor layer 20.

[0076] After forming the semiconductor lines or sheets (channel regions) of the second semiconductor layer 25, a gate dielectric layer 82 is formed around each of the channel regions. In addition, gate electrode layers 84N and 84P are formed on the gate dielectric layer 82, such as Fig.18A and Fig.18BIn some embodiments, the structure and / or material of the gate electrode for the n-type GAA FET is different from the structure and / or material of the gate electrode for the p-type GAA FET.

[0077] In some embodiments, the gate dielectric layer 82 includes one or more layers of dielectric materials, such as silicon oxide, silicon nitride or high-k dielectric materials, other suitable dielectric materials and / or combinations thereof. Examples of high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-aluminum oxide (HfO2-Al2O3) alloys, other suitable high-k dielectric materials and / or combinations thereof. In some embodiments, the gate dielectric layer 82 includes an interface layer (not shown) formed between the channel layer and the dielectric material.

[0078] The gate dielectric layer 82 may be formed by CVD, ALD, or any suitable method. In one embodiment, the gate dielectric layer 82 is formed using a highly conformal deposition process such as ALD to ensure that a gate dielectric layer having a uniform thickness is formed around each channel layer. In one embodiment, the thickness of the gate dielectric layer 82 is in a range of about 1 nm to about 6 nm.

[0079] A gate electrode layer is formed on the gate dielectric layer 82 to surround each channel layer. The gate electrode includes one or more layers of conductive materials, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials and / or combinations thereof.

[0080] The gate electrode layer can be formed by CVD, ALD, electroplating or other suitable methods. The gate electrode layer is also deposited above the upper surface of the ILD layer 70. Then, the gate dielectric layer and the gate electrode layer formed above the ILD layer 70 are planarized by using, for example, CMP until the top surface of the ILD layer 70 is exposed. In some embodiments, after the planarization operation, the gate electrode layer 84 is recessed and a capping insulating layer (not shown) is formed above the recessed gate electrode 84. The capping insulating layer includes one or more layers of silicon nitride-based materials, such as silicon nitride. The capping insulating layer is formed by depositing an insulating material and a subsequent planarization operation.

[0081] In some embodiments of the present invention, the gate electrode layer includes one or more work function adjustment layers (not shown) disposed above the gate dielectric layer 82. The work function adjustment layer is made of a conductive material, such as a single layer of TiN, TaN, TaAlC, TiC, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi or TiAlC, or a multilayer of two or more of these materials. In some embodiments, for p-channel FETs, one or more of TiAlC, Al, TiAl, TaN, TaAlC, TiN, TiC and Co are used as work function adjustment layers. For n-channel FETs, one or more of TaN, TaAlC, TiN, TiC, Co, TiAl, HfTi, TiSi and TaSi are used as work function adjustment layers. The work function adjustment layer can be formed by ALD, PVD, CVD, electron beam evaporation or other suitable processes. In addition, for n-channel FETs and p-channel FETs that can use different metal layers, work function adjustment layers can be formed separately.

[0082] Subsequently, a contact hole is formed in the ILD layer 70 and the etch stop layer 68 by using dry etching to expose the upper portion of the source / drain epitaxial layer 50. In some embodiments, a silicide layer is formed over the source / drain epitaxial layer 50. The silicide layer includes one or more of WSi, CoSi, NiSi, TiSi, MoSi, and TaSi. Then, a conductive contact layer 72 is formed in the contact hole, such as Figures 1A to 1D As shown. The conductive contact layer 72 includes one or more of Co, Ni, W, Ti, Ta, Cu, Al, TiN and TaN. In addition, a conductive contact plug 75 is formed on the conductive contact layer 72. The conductive contact plug 75 includes one or more of Co, Ni, W, Ti, Ta, Cu, Al, TiN and TaN.

[0083] It should be understood that the GAA FET undergoes further CMOS processing to form various components, such as contacts / vias, interconnect metal layers, dielectric layers, passivation layers, etc.

[0084] 19A to 19D The process steps for fabricating the source / drain epitaxial layers 50 , 55 according to an embodiment of the present invention are shown. Fig. 20 The composition variation of the source / drain epitaxial layer according to an embodiment of the present invention is shown (graph). Fig. 20 An image of the source / drain epitaxial layer is also shown. It should be understood that additional embodiments of the method may be 19A to 19D Additional operations are provided before, during, and after the processes shown, and some of the operations described below may be replaced or eliminated. The order of operations / processes may be interchanged. 19A to 19D In the embodiments, the Figures 1A to 1DThe above embodiments are described with the same or similar materials, configurations, sizes, and / or processes, and their detailed descriptions may be omitted.

[0085] Fig.19A A cross-sectional view is shown after forming the base epitaxial layer 49. Before forming the source / drain epitaxial layers 50 and 55, a pre-cleaning operation is respectively performed to remove an oxide layer formed on the surface of the recessed fin structure.

[0086] In some embodiments, the pre-cleaning operation includes a plasma treatment using Ar and / or NH3 plasma. In some embodiments, the process temperature is in the range of about room temperature to about 300°C. Then, a chemical cleaning operation is performed using HCl gas to remove residual gas from the vacuum chamber, which would otherwise cause defects and nodular defects at the N / P boundary. In some embodiments, the process temperature of the chemical cleaning is higher than the pre-cleaning temperature and is in the range of about 400°C to about 700°C, and in other embodiments, in the range of about 500°C to about 600°C.

[0087] After chemical cleaning, a first epitaxial layer 50 - 1 is formed, such as Fig.19B As shown. In some embodiments, for n-type FET, the first epitaxial layer 50-1 is made of SiP or SiAs for the source / drain epitaxial layer 50, and for p-type FET, the first epitaxial layer 50-1 is made of SiGe doped with B for the source / drain epitaxial layer 55. In some embodiments, dopants (e.g., P, As, or B) are diffused into the base epitaxial layer 49, thereby forming a lightly doped region (having a lower dopant concentration than the first epitaxial layer and a higher dopant concentration than the base epitaxial layer 49) between the first epitaxial layer 50-1 and the base epitaxial layer 49.

[0088] In some embodiments, for a p-type FET, the second semiconductor layer 25 is made of Si 1-x Ge x For a p-type FET, the Ge content in the first epitaxial layer 50-1 is the same as the Ge content in the second semiconductor layer 25, or in some embodiments, the difference in Ge content is about 0.01 to 0.03.

[0089] In some embodiments, Fig. 20 As shown, the Ge content increases as the first epitaxial layer 50-1 grows. In some embodiments, the Ge content increases from about 0% atom (Si) to about 15-25% atom, for example, 20% atom (Si). 0.8 Ge 0.2 In some embodiments, the average B concentration of the first epitaxial layer 50 - 1 is about 5×10 19 Atom / cm3 About 1×10 21 Atom / cm 3 In other embodiments, the range is about 1×10 20 Atom / cm 3 About 5×10 20 Atom / cm 3 In some embodiments, the B concentration increases as the first epitaxial layer 50-1 is grown. In some embodiments, the first epitaxial layer 50-1 for p-type FET is formed by an epitaxial growth method using CVD, ALD, or molecular beam epitaxy (MBE) using HCl, SiH2Cl2, and GeH4. In some embodiments, the epitaxial growth is a selective growth including an etching operation and a deposition operation performed alternately.

[0090] In some embodiments, for n-type FETs, the second semiconductor layer 25 is made of Si. In some embodiments, the first epitaxial layer 50-1 does not include Ge and is made of SiP, SiPA, or SiAs. In some embodiments, P or As can be considered as a dopant or impurity in the Si layer. When the first epitaxial layer 50-1 includes P, the P content increases as the first epitaxial layer 50-1 is grown. In some embodiments, the average P concentration of the first epitaxial layer 50-1 is about 5×10 19 Atom / cm 3 About 1×10 21 Atom / cm 3 In other embodiments, the range is about 1×10 20 Atom / cm 3 About 5×10 20 Atom / cm 3 In some embodiments, the first epitaxial layer 50-1 for n-type FET is formed by an epitaxial growth method using CVD, ALD or molecular beam epitaxy (MBE) using HCl, SiH2Cl2 and SiH4. In some embodiments, the epitaxial growth is a selective growth including an etching operation and a deposition operation performed alternately.

[0091] In some embodiments, the thickness of the first epitaxial layer 50-1 measured in the horizontal direction over the second semiconductor layer 25 is in a range of about 2 nm to about 10 nm. The thickness of the first epitaxial layer 50-1 measured in the vertical direction over the base epitaxial layer 49 is less than the thickness of the base epitaxial layer and greater than the horizontal thickness, and in some embodiments, is in a range of about 10 nm to about 20 nm.

[0092] The process temperature for forming the first epitaxial layer 50-1 is lower than the temperature of the baking / annealing operation and higher than the temperature for forming the first epitaxial layer 50-1. In some embodiments, the process temperature for forming the first epitaxial layer 50-1 is in the range of about 550°C to about 750°C, and in other embodiments, in the range of about 600°C to about 700°C.

[0093] After forming the first epitaxial layer 50 - 1 , the second epitaxial layer 50 - 2 is formed. Fig.19C shown.

[0094] In some embodiments, for a p-type FET, the second epitaxial layer 50-2 is made of SiGe doped with B. Fig. 20 As shown, the Ge content increases with the growth of the second epitaxial layer 50-2. In some embodiments, the Ge content increases from about 20% atom to as high as about 30-60% atom. In some embodiments, the average B concentration of the second epitaxial layer 50-2 is equal to or higher than the maximum B concentration of the first epitaxial layer 50-1, and is about 1×10 19 Atom / cm 3 About 5×10 21 Atom / cm 3 In other embodiments, the range is about 5×10 19 Atom / cm 3 About 2×10 21 Atom / cm 3In some embodiments, the thickness of the second epitaxial layer 50-2 measured in the horizontal direction at the end of the second semiconductor layer 25 is in the range of about 20nm to about 60nm, depending on the design and / or process requirements. The thickness of the second epitaxial layer 50-1 measured in the vertical direction is greater than the horizontal thickness, and in some embodiments, is in the range of about 40nm to about 100nm. In some embodiments, the second epitaxial layer 50-2 for p-type FET is formed by using HCl, SiH2Cl2 and GeH4 using an epitaxial growth method using CVD, ALD or molecular beam epitaxy (MBE). In some embodiments, the epitaxial growth is a selective growth including alternating etching operations and deposition operations. In some embodiments, the last step is an etching operation to remove the top of the second epitaxial layer 50-2 so that the second epitaxial layer does not contact the gate sidewall spacer 45. In some embodiments, the second epitaxial layer 50-2 contacts the uppermost one of the second semiconductor layer 25. In some embodiments, the top of the second epitaxial layer 50-2 is about 1-10nm higher than the top of the uppermost second semiconductor layer 25. The process temperature for forming the second epitaxial layer 50-2 is lower than the temperature of the baking / annealing operation and higher than the temperature for forming the first epitaxial layer 50-1. In some embodiments, the process temperature for forming the second epitaxial layer 50-2 is in the range of about 550°C to about 750°C, and in other embodiments, in the range of about 600°C to about 700°C.

[0095] In some embodiments, for n-type FETs, the second epitaxial layer 50-2 is made of SiP. In some embodiments, the P content increases as the second epitaxial layer 50-2 grows. In some embodiments, the average P concentration of the second epitaxial layer 50-2 is equal to or higher than the maximum P concentration of the first epitaxial layer 50-1, and is approximately 1×10 19 Atom / cm 3 About 5×10 21 Atom / cm 3 In other embodiments, the range is about 5×10 19 Atom / cm 3 About 2×10 21 Atom / cm 3 In some embodiments, the second epitaxial layer 50-2 for n-type FET is formed by an epitaxial growth method using CVD, ALD or molecular beam epitaxy (MBE) using PH3, SiH2Cl2 and SiH4. In some embodiments, the process temperature for forming the second epitaxial layer 50-2 is in the range of about 550°C to about 750°C, and in other embodiments, in the range of about 600°C to about 700°C.

[0096] In some embodiments, Fig.19DAs shown, a third epitaxial layer 50-3 is formed over the second epitaxial layer 50-2 to facilitate subsequent alloy formation operations, such as forming a silicide layer. In some embodiments, for p-type FETs, the third epitaxial layer 50-3 is made of SiGe doped with B, and for n-type FETs, the third epitaxial layer 50-3 is made of SiP.

[0097] In some embodiments, the Ge content decreases as the epitaxial layer 50-4 is grown. Fig. 20 As shown, the Ge content decreases from about 30-60% atom to about 20-30% atom. In some embodiments, the Ge content is substantially constant and is in the range of about 40% atom to about 60% atom. In some embodiments, the average Ge content of the third epitaxial layer 50-3 is less than the Ge content of the second epitaxial layer and higher than the Ge content of the first epitaxial layer. In some embodiments, the average B or P concentration of the third epitaxial layer 50-3 is about 5×10 20 Atom / cm 3 About 5×10 21 Atom / cm 3 In other embodiments, the range is about 1×10 21 Atom / cm 3 About 3×10 21 Atom / cm 3In some embodiments, the B or P concentration decreases as the third epitaxial layer 50-3 grows. In other embodiments, the B or P concentration is substantially constant in the third epitaxial layer 50-3. In some embodiments, the thickness of the third epitaxial layer 50-3 measured in the horizontal direction at the end of the second semiconductor layer 25 is in the range of about 10nm to about 30nm, depending on the design and / or process requirements. The thickness of the third epitaxial layer 50-3 measured in the vertical direction is greater than the horizontal thickness, and in some embodiments, in the range of about 20nm to about 60nm. In some embodiments, the third epitaxial layer 50-3 for p-type FETs is formed using HCl, SiH2Cl2 and GeH4 by using an epitaxial growth method using CVD, ALD or molecular beam epitaxy (MBE). In some embodiments, the third epitaxial layer 50-3 for n-type FETs is formed using PH3, SiH2Cl2 and SiH4 by using an epitaxial growth method using CVD, ALD or molecular beam epitaxy (MBE). In some embodiments, the process temperature for forming the third epitaxial layer 50-3 is in the range of about 600° C. to about 700° C. In some embodiments, an ion implantation operation for introducing B or P into the second epitaxial layer or the third epitaxial layer is performed in addition to or instead of the third epitaxial layer. In some embodiments, the third epitaxial layer 50-3 is in direct contact with the first epitaxial layer 50-1, and in other embodiments, the third epitaxial layer 50-3 is separated from the first epitaxial layer 50-1 by the second epitaxial layer 50-2.

[0098] In some embodiments, the first to third epitaxial layers are formed continuously in the same chamber by changing deposition conditions (e.g., gas, pressure, and / or temperature) as in-situ deposition, while the base epitaxial layer is formed ex-situ in a different chamber from the one in which the source / drain epitaxial layer (discontinuous) is formed. In some embodiments, the base epitaxial layer 49 is lightly doped, with a doping amount less than that of the first epitaxial layer (e.g., about 1 / 100 to about 1 / 10 less than that of the first epitaxial layer). In some embodiments, the epitaxial layer 49 may be doped because impurities or Ge diffuse from the source / drain epitaxial layer 50 or 55. In some embodiments, the doping amount (if any) is about 1×10 17 Atom / cm 3 About 0.5×10 19 Atom / cm 3 .

[0099] Fig.21A and Fig. 21B The structure is shown after forming source / drain spacers 21. Fig.21AIn some embodiments, when the gate length Lg is small, for example, in the range of about 5 nm to about 9 nm, the depth of the source / drain spacer 21 from the top of the fin structure 11 is in the range of about 5 nm to about 30 nm, and the bottom shape of the spacer 21 has a V shape, such as Fig.21A In some embodiments, when the gate length Lg is large, for example, in the range of about 20 nm to about 50 nm, the depth of the source / drain spacer 21 from the top of the fin structure 11 is in the range of about 15 nm to about 50 nm, and the bottom shape of the spacer 21 has a U-shape, as shown in FIG. Fig. 21B shown.

[0100] Fig.22A and Fig. 22B FIG. 4 shows a cross-sectional view of a semiconductor GAA FET device according to an embodiment of the present invention. Fig.22A and Fig. 22B In the embodiments, the Figures 1A to 1D The above embodiments are described with the same or similar materials, configurations, sizes, and / or processes, and their detailed descriptions may be omitted.

[0101] In some embodiments, Fig.22AAs shown, the bottom of the base epitaxial layer 49 (the bottom of the source / drain interval 21) has a V shape. In some embodiments, the V-shaped groove of the source / drain interval 21 is formed by a dry etching process that can be anisotropic. Anisotropic etching processes can be implemented using a process gas mixture including BF2, Cl2, CH3F, CH4, HBr, O2, Ar, and other etchant gases. Plasma is a remote plasma generated in different plasma generation chambers connected to the processing chamber. The process gas can be activated into plasma by any suitable method for generating plasma (such as transformer coupled plasma (TCP) system, inductively coupled plasma (ICP) system, magnetic enhanced reactive ion technology). The process gas used in the plasma etching process includes etching gases such as H2, Ar, other gases or combinations of gases. In some embodiments, carrier gases such as N2, Ar, He, and Xe are used in a plasma etching process using hydrogen (H) radicals. H radicals can be formed by flowing H2 gas into the plasma generation chamber and igniting the plasma in the plasma generation chamber. In some embodiments, additional gases such as Ar can be ignited into plasma in the plasma generation chamber. H radicals can selectively etch the (100) plane above the (111) plane or the (110) plane. In some cases, the etching rate of the (100) plane can be about three times that of the (111) plane. Due to this selectivity, during the second patterning process, etching by H radicals along the (111) plane or the (110) plane of silicon may tend to slow down or stop. The V-groove can be applied to both n-type and p-type FETs.

[0102] In some embodiments, the channel region is formed by the first semiconductor nanostructure 20, such as Fig. 22B In some embodiments, the first semiconductor layer 20 is made of SiGe, and the second semiconductor layer 25 is made of Si. Figure 6 In the lateral etching shown, the second semiconductor layer 25 is etched laterally instead of the first semiconductor layer 20, and an internal spacer 35 is formed on the etched end surface of the second semiconductor layer. The base epitaxial layer 49 is made of the same material (SiGe) as the first semiconductor layer 20. Fig.17A and Fig. 17B In the nanostructure release process shown, the second semiconductor layer 25 is removed instead of the first semiconductor layer 20, and a gate structure is formed around the first semiconductor layer 20. In some embodiments, Fig. 22B The FET shown is a p-type FET. In some embodiments, a Fig.18A The n-type FET is formed on the same substrate as shown Fig. 22B A p-type FET is shown.

[0103] In an embodiment of the present invention, a substrate epitaxial layer 49 as an undoped semiconductor layer is first formed in the source / drain interval. Because the growth rate of the undoped Si or SiGe layer is relatively lower than the growth rate of the doped Si or SiGe layer, the formation of gaps or seams in the source / drain epitaxial layer can be suppressed or avoided. In addition, the undoped substrate epitaxial layer can improve the short channel effect. In some embodiments, the epitaxial growth of the substrate epitaxial layer 49 and the epitaxial growth of the source / drain epitaxial layer 50 or 55 are continuously implemented in the same chamber by changing one or more deposition (in-situ deposition) conditions.

[0104] It should be understood that not all advantages are necessarily discussed herein, that no particular advantage is required for all embodiments or examples, and that other embodiments may provide different advantages.

[0105] According to one aspect of the present invention, a fin structure is formed in which a first semiconductor layer and a second semiconductor layer are alternately stacked, a sacrificial gate structure is formed above the fin structure, a source / drain region of the fin structure not covered by the sacrificial gate structure is recessed, thereby forming a source / drain interval, a substrate epitaxial layer is formed at the bottom of the source / drain interval, and a source / drain epitaxial layer is formed on the substrate epitaxial layer. The substrate epitaxial layer includes an undoped semiconductor material. In one or more embodiments above and below, the second semiconductor layer and the substrate epitaxial layer are made of the same semiconductor material. In one or more embodiments above and below, the semiconductor device is an n-type field effect transistor (FET), and the undoped semiconductor material is undoped Si. In one or more embodiments above and below, the semiconductor device is a p-type field effect transistor (FET), and the undoped semiconductor material is undoped SiGe. In one or more embodiments above and below, the first semiconductor layer is laterally etched through the source / drain interval, and an internal spacer made of a dielectric material is formed on each end of the etched first semiconductor layer. The substrate epitaxial layer is formed after the internal spacer is formed. In one or more embodiments above and below, the substrate epitaxial layer is not in contact with the internal spacer. In one or more embodiments above and below, the semiconductor device is an n-type field effect transistor (FET). In forming the source / drain epitaxial layer, a first epitaxial layer made of SiP is formed on the substrate epitaxial layer, a second epitaxial layer having a higher P content than the first epitaxial layer is formed on the first epitaxial layer, and a third epitaxial layer having a lower P content than the second epitaxial layer is formed on the second epitaxial layer. In one or more embodiments above and below, the semiconductor device is a p-type field effect transistor (FET). In forming the source / drain epitaxial layer, a first epitaxial layer made of SiGe is formed on the substrate epitaxial layer, a second epitaxial layer having a higher Ge content than the first epitaxial layer is formed on the first epitaxial layer, and a third epitaxial layer having a lower Ge content than the second epitaxial layer is formed on the second epitaxial layer. In one or more embodiments above and below, the first epitaxial layer includes B, and the B concentration of the first epitaxial layer increases as the first epitaxial layer is grown.

[0106] According to another aspect of the present invention, in a method for manufacturing a semiconductor device, a fin structure is formed in which a first semiconductor layer and a second semiconductor layer are alternately stacked, a sacrificial gate structure is formed above the fin structure, and the source / drain region of the fin structure not covered by the sacrificial gate structure is etched to form a source / drain gap; the first semiconductor layer is laterally etched through the source / drain gap, and an internal spacer made of a dielectric material is formed on each end of the etched first semiconductor layer, a base epitaxial layer is formed at the bottom of the source / drain gap, and a source / drain epitaxial layer is formed on the base epitaxial layer. After forming the base epitaxial layer and before forming the source / drain epitaxial layer, at least one process selected from the group consisting of a photolithography process and an etching process is implemented. In one or more embodiments above and below, the base epitaxial layer includes an undoped semiconductor material. In one or more embodiments above and below, the second semiconductor layer and the base epitaxial layer are made of the same semiconductor material. In one or more embodiments above and below, in forming the source / drain epitaxial layer, a first epitaxial layer is formed on the base epitaxial layer, a second epitaxial layer is formed on the first epitaxial layer, and a third epitaxial layer is formed on the second epitaxial layer, and the first epitaxial layer to the third epitaxial layer are continuously formed in the same chamber by changing one or more deposition conditions. In one or more embodiments above and below, the base epitaxial layer is formed of HCl and at least one selected from the group consisting of SiH4, SiH2Cl2 and GeH4. In one or more embodiments above and below, in forming the base epitaxial layer, deposition phases and etching phases are alternately implemented.

[0107] According to another aspect of the present invention, in a method for manufacturing a semiconductor device, a first fin structure and a second fin structure are formed, and a first semiconductor layer and a second semiconductor layer are alternately stacked in each of the first fin structure and the second fin structure. A first sacrificial gate structure is formed above the first fin structure, and a second sacrificial gate structure is formed above the second fin structure. A first source / drain spacing is formed by etching a first source / drain region of the first fin structure that is not covered by the first sacrificial gate structure, and a second source / drain spacing is formed by etching a second source / drain region of the second fin structure that is not covered by the second sacrificial gate structure. A first base epitaxial layer is formed at the bottom of the first source / drain spacing, and a second base epitaxial layer is formed at the bottom of the second source / drain spacing. The second base epitaxial layer is covered by a first covering layer. A first source / drain epitaxial layer is formed on the first base epitaxial layer while covering the second base epitaxial layer. The first covering layer is removed. The first source / drain epitaxial layer is covered by a second covering layer. A second source / drain epitaxial layer is formed on the second base epitaxial layer while covering the first source / drain epitaxial layer. In one or more embodiments above and below, the first substrate epitaxial layer and the second substrate epitaxial layer include undoped semiconductor materials. In one or more embodiments above and below, the second semiconductor layer and the first substrate epitaxial layer and the second substrate epitaxial layer are made of the same semiconductor material. In one or more embodiments above and below, in forming the first source / drain epitaxial layer, a first epitaxial layer is formed on the first substrate epitaxial layer, a second epitaxial layer is formed on the first epitaxial layer, and a third epitaxial layer is formed on the second epitaxial layer, and the first epitaxial layer to the third epitaxial layer are continuously formed in the same chamber by changing one or more deposition conditions. In one or more embodiments above and below, the substrate epitaxial layer and the first epitaxial layer are doped with P or B, and the doping amount of the substrate epitaxial layer is 1 / 100 to 1 / 10 of the doping amount of the first epitaxial layer.

[0108] According to another aspect of the present invention, a semiconductor device includes: a semiconductor nanostructure, arranged above a substrate; a source / drain epitaxial layer, contacting the semiconductor nanostructure; a gate dielectric layer, arranged on each channel region of the semiconductor nanostructure and wrapping each channel region of the semiconductor nanostructure; a gate electrode layer, arranged on the gate dielectric layer and wrapping each channel region; and an insulating spacer, respectively arranged in the interval, and the interval is defined by adjacent semiconductor nanostructures, gate electrode layers and source / drain regions. The source / drain epitaxial layer includes an undoped base epitaxial layer and a plurality of epitaxial semiconductor layers having different compositions from each other formed on the base epitaxial layer. In one or more embodiments above and below, the plurality of epitaxial semiconductor layers are SiGe layers having different Ge contents from each other. In one or more embodiments above and below, the Ge content of at least one of the SiGe layers increases along the growth direction of the SiGe layer. In one or more embodiments above and below, at least one of the SiGe layers includes B, and the B content of at least one of the plurality of SiGe layers increases along the growth direction of at least one of the SiGe layers. In one or more embodiments above and below, the base epitaxial layer and the semiconductor nanostructure are made of the same material. In one or more embodiments above and below, the plurality of epitaxial semiconductor layers are SiP layers having different P contents from each other. In one or more embodiments above and below, the P content of at least one of the SiP layers increases along a growth direction of the SiP layer.

[0109] According to another aspect of the present invention, a semiconductor device includes: a semiconductor nanostructure, arranged above a substrate; a source / drain epitaxial layer, in contact with the semiconductor nanostructure; a gate dielectric layer, arranged on each channel region of the semiconductor nanostructure and wrapping each channel region of the semiconductor nanostructure; a gate electrode layer, arranged on the gate dielectric layer and wrapping each channel region; and insulating spacers, respectively arranged in the intervals. The intervals are defined by adjacent semiconductor nanostructures, gate electrode layers, and source / drain regions. The source / drain epitaxial layer includes an undoped base epitaxial layer that is not in contact with the bottommost one of the insulating spacers and a first epitaxial semiconductor layer formed on the base epitaxial layer. In one or more embodiments above and below, the first epitaxial layer is in contact with the semiconductor nanostructure and the insulating spacer. In one or more embodiments above and below, the source / drain epitaxial layer also includes a second epitaxial layer having a different composition from the first epitaxial layer and formed on the first epitaxial layer, and a third epitaxial layer having a different composition from the second epitaxial layer and formed on the second epitaxial layer. In one or more embodiments above and below, the second epitaxial layer is not in contact with the semiconductor nanostructure and the substrate epitaxial layer. In one or more embodiments above and below, the third epitaxial layer is not in contact with the first epitaxial layer. In one or more embodiments above and below, the second epitaxial layer is not in contact with the semiconductor nanostructure and the substrate epitaxial layer. In one or more embodiments above and below, the substrate epitaxial layer and the semiconductor wire or sheet are made of the same material. In one or more embodiments above and below, the same material is Si. In one or more embodiments above and below, the same material is SiGe. In one or more embodiments above and below, the bottom of the substrate epitaxial layer has a V-shape or a U-shape.

[0110] According to another aspect of the present invention, a semiconductor device includes an n-type field effect transistor (FET) and a p-type FET. Each of the n-type FET and the p-type FET includes: a semiconductor nanostructure, disposed above a substrate; a source / drain epitaxial layer, in contact with the semiconductor nanostructure; a gate dielectric layer, disposed on each channel region of the semiconductor nanostructure and wrapping each channel region of the semiconductor nanostructure; a gate electrode layer, disposed on the gate dielectric layer and wrapping each channel region; and an insulating spacer, respectively disposed in the interval, the interval being defined by adjacent semiconductor nanostructures, gate electrode layers, and source / drain regions. The source / drain epitaxial layer includes an undoped substrate epitaxial layer, the source / drain epitaxial layer includes an undoped substrate epitaxial layer, the source / drain epitaxial layer of the n-type FET includes a plurality of SiP layers having different P contents and formed on the undoped substrate epitaxial layer, and the source / drain epitaxial layer of the p-type FET includes a plurality of SiGe layers having different Ge contents and formed on the undoped substrate epitaxial layer. In one or more embodiments above and below, the substrate epitaxial layer and the semiconductor nanostructure are made of the same material. In one or more embodiments above and below, the undoped base epitaxial layer does not contact a bottommost one of the insulating spacers.

[0111] The features of several embodiments or examples are summarized above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments or examples introduced herein. Those skilled in the art should also appreciate that this equivalent construction does not deviate from the spirit and scope of the present invention, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present invention.

Claims

1. A method for manufacturing a semiconductor device, comprising: forming a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked; forming a sacrificial gate structure over the fin structure; etching source / drain regions of the fin structure not covered by the sacrificial gate structure to form source / drain spacers; forming a base epitaxial layer at the bottom of the source / drain spacer; and forming a source / drain epitaxial layer on the base epitaxial layer, Wherein, the base epitaxial layer comprises undoped semiconductor material, Wherein, the second semiconductor layer is made of silicon germanium, and forming the source / drain epitaxial layer includes: forming a first epitaxial layer made of silicon germanium on the base epitaxial layer, wherein the germanium content of the first epitaxial layer is equal to the germanium content of the second semiconductor layer; forming a second epitaxial layer having a higher germanium content than the first epitaxial layer on the first epitaxial layer; and A third epitaxial layer having a lower germanium content than the second epitaxial layer is formed on the second epitaxial layer.

2. The method according to claim 1, wherein: The second semiconductor layer and the base epitaxial layer are made of the same semiconductor material.

3. The method according to claim 1, wherein: The first epitaxial layer, the second epitaxial layer, and the third epitaxial layer are successively formed in the same chamber by changing one or more deposition conditions.

4. The method according to claim 1, wherein: The undoped semiconductor material is undoped silicon germanium.

5. The method according to claim 1, further comprising: laterally etching the first semiconductor layer through the source / drain spacer; as well as forming an inner spacer made of a dielectric material on each end of the etched first semiconductor layer, Wherein, the base epitaxial layer is formed after the inner spacer is formed.

6. The method according to claim 5, wherein: The base epitaxial layer does not contact the inner spacer.

7. The method according to claim 1, wherein: The thickness of the base epitaxial layer is in the range of 5 nm to 50 nm.

8. The method according to claim 1, further comprising: Before forming the base epitaxial layer, a first cleaning operation is performed using a gas including NH.

9. The method according to claim 1, wherein: The first epitaxial layer includes B, and a concentration of B in the first epitaxial layer increases as the first epitaxial layer is grown.

10. A method for manufacturing a semiconductor device, comprising: forming a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked; forming a sacrificial gate structure over the fin structure; etching source / drain regions of the fin structure not covered by the sacrificial gate structure to form source / drain spacers; laterally etching the first semiconductor layer through the source / drain spacer; as well as forming an inner spacer made of a dielectric material on each end of the etched first semiconductor layer; forming a base epitaxial layer at the bottom of the source / drain spacer; and forming a source / drain epitaxial layer on the base epitaxial layer, wherein, after forming the base epitaxial layer and before forming the source / drain epitaxial layer, at least one process selected from the group consisting of a photolithography process and an etching process is performed, Wherein, the second semiconductor layer is made of silicon germanium, and forming the source / drain epitaxial layer includes: forming a first epitaxial layer made of silicon germanium on the base epitaxial layer, wherein the germanium content of the first epitaxial layer is equal to the germanium content of the second semiconductor layer; forming a second epitaxial layer having a higher germanium content than the first epitaxial layer on the first epitaxial layer; and A third epitaxial layer having a lower germanium content than the second epitaxial layer is formed on the second epitaxial layer.

11. The method according to claim 10, wherein: The base epitaxial layer includes undoped semiconductor material.

12. The method according to claim 11, wherein: The second semiconductor layer and the base epitaxial layer are made of the same semiconductor material.

13. The method of claim 10, wherein: The first epitaxial layer, the second epitaxial layer, and the third epitaxial layer are successively formed in the same chamber by changing one or more deposition conditions.

14. The method according to claim 10, wherein: The base epitaxial layer is formed of HCl and at least one selected from the group consisting of SiH4, SiH2Cl2 and GeH4.

15. The method according to claim 14, wherein: Forming the base epitaxial layer includes alternating deposition phases and etching phases.

16. A semiconductor device comprising: a semiconductor nanostructure disposed above a substrate; a source / drain epitaxial layer in contact with the semiconductor nanostructure; A gate dielectric layer, disposed on each channel region of the semiconductor nanostructure and wrapping each channel region of the semiconductor nanostructure; a gate electrode layer, disposed on the gate dielectric layer and wrapping each channel region; as well as Insulating spacers are respectively disposed in spaces defined by adjacent semiconductor nanostructures, the gate electrode layer and the source / drain regions, The source / drain epitaxial layer includes an undoped base epitaxial layer and a plurality of epitaxial semiconductor layers having different compositions formed on the base epitaxial layer. Wherein, the semiconductor nanostructure is made of silicon germanium, and the plurality of epitaxial semiconductor layers are silicon germanium layers having different Ge contents from each other, including: A first epitaxial layer, located above the base epitaxial layer, wherein the germanium content of the first epitaxial layer is equal to the germanium content of the semiconductor nanostructure; a second epitaxial layer located above the first epitaxial layer and having a higher germanium content than the first epitaxial layer; and The third epitaxial layer is located above the second epitaxial layer and has a lower germanium content than that of the second epitaxial layer.

17. The semiconductor device according to claim 16, wherein: The base epitaxial layer and the semiconductor nanostructure are made of the same material.

18. The semiconductor device according to claim 17, wherein: The germanium content of at least one of the silicon germanium layers increases along a growth direction of the silicon germanium layer.

19. The semiconductor device according to claim 17, wherein: At least one of the silicon germanium layers includes B, and a B content of at least one of the plurality of silicon germanium layers increases along a growth direction of the at least one of the silicon germanium layers.

20. The semiconductor device according to claim 16, wherein The base epitaxial layer and the semiconductor nanostructure are made of the same material.

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