Imaging device with gated time-of-flight pixel having fast charge transfer

Abstract

The pixel array includes a plurality of pixels. Each pixel includes a photoelectric conversion region that converts incident light into electric charges and a charge transfer portion connected to the photoelectric conversion region and having line symmetry along a first axis in a plan view. The charge transfer portion includes a first transfer transistor connected to a first floating diffusion region and the photoelectric conversion region and located on a first side of the photoelectric conversion region, and a second transfer transistor connected to a second floating diffusion region and the photoelectric conversion region and located on the first side of the photoelectric conversion region.

Description

Technical Field

[0001] The exemplary embodiments relate to imaging devices, imaging apparatuses and operating methods thereof, and more particularly, to imaging devices, imaging apparatuses and methods for depth sensing. Background Art

[0002] Depth sensing has applications in many fields, including object tracking, environment rendering, etc. Some depth sensors use the principle of time of flight (ToF) to detect the distance of one or more objects in a scene. Typically, a ToF depth sensor includes a light source and an imaging device including multiple pixels for sensing reflected light. In operation, the light source emits light (e.g., infrared light) to one or more objects in the scene, and the pixels detect the light reflected from one or more objects. The time elapsed between the initial emission of light and the reflected light being received by each pixel can correspond to the distance from one or more objects. A direct ToF imaging device can measure the elapsed time itself to calculate the distance, while an indirect ToF imaging device can measure the phase delay between the emitted light and the reflected light and convert the phase delay into a distance. The distance to an object or objects is then determined by the imaging device using the depth value of the pixel, which can be used to create a three-dimensional scene of the captured object or objects. Summary of the invention

[0003] Example embodiments relate to imaging devices, imaging apparatuses, and methods thereof that allow fast charge transfer from a photodiode to a pixel circuit, fast overflow reset, and the like.

[0004] At least one exemplary embodiment relates to a pixel array including a plurality of pixels, each pixel including a photoelectric conversion region that converts incident light into electric charge; and a charge transfer portion that is connected to the photoelectric conversion region and has line symmetry along a first axis in a plan view. The charge transfer portion includes a first transfer transistor that is connected to a first floating diffusion region and the photoelectric conversion region and is located on a first side of the photoelectric conversion region; and a second transfer transistor that is connected to a second floating diffusion region and the photoelectric conversion region and is located on the first side of the photoelectric conversion region.

[0005] According to at least one example embodiment, the charge transfer section includes a third transfer transistor connected to the overflow region and located at the first side of the photoelectric conversion region and between the first transfer transistor and the second transfer transistor.

[0006] According to at least one exemplary embodiment, the first axis passes through a gate of the third transfer transistor.

[0007] According to at least one example embodiment, the gate of the third transfer transistor is located farther from the center of the pixel than the gates of the first transfer transistor and the second transfer transistor.

[0008] According to at least one example embodiment, the gate of the first transfer transistor and the gate of the second transfer transistor are equidistant from the center of the pixel.

[0009] According to at least one example embodiment, the gate of the third transfer transistor is closer to the center of the pixel than the gates of the first transfer transistor and the second transfer transistor.

[0010] According to at least one exemplary embodiment, each pixel further includes a transistor portion in which a plurality of transistors are disposed, and the transistor portion has line symmetry along the first axis.

[0011] According to at least one example embodiment, the plurality of transistors include third and fourth transfer transistors and first and second reset transistors.

[0012] According to at least one example embodiment, the plurality of transistors include first and second selection transistors and first and second amplification transistors.

[0013] According to at least one exemplary embodiment, the photoelectric conversion region includes a main portion and an extension portion extending from the main portion, and the first side of the photoelectric conversion region includes the extension portion.

[0014] According to at least one exemplary embodiment, the extension portion includes a first edge, a second edge, and a third edge connecting the first edge and the second edge, and the first transfer transistor is located at the first edge, the second transfer transistor is located at the second edge, and the third transfer transistor is located at the third edge.

[0015] According to at least one example embodiment, the third transistors of at least some of the plurality of pixels share a drain region.

[0016] According to at least one example embodiment, in the plan view, the charge transfer sections of adjacent pixels are aligned with each other along a second axis perpendicular to the first axis.

[0017] According to at least one example embodiment, a portion of the photoelectric conversion region closest to the first and second transfer transistors has a greater impurity concentration than a portion of the photoelectric conversion region farthest from the first and second transfer transistors.

[0018] According to at least one example embodiment, the first axis passes through the center of the pixel.

[0019] At least one exemplary embodiment relates to a system, the system including a light source and an imaging device, the imaging device including a pixel array, the pixel array including a plurality of pixels. Each pixel includes a photoelectric conversion region, which converts incident light into electric charge; and a charge transfer portion, which is connected to the photoelectric conversion region and has line symmetry along a first axis in a plan view. The charge transfer portion includes a first transfer transistor, which is connected to a first floating diffusion region and the photoelectric conversion region and is located on a first side of the photoelectric conversion region; and a second transfer transistor, which is connected to a second floating diffusion region and the photoelectric conversion region and is located on the first side of the photoelectric conversion region.

[0020] According to at least one example embodiment, the charge transfer section includes a third transfer transistor connected to the overflow region and located at the first side of the photoelectric conversion region and between the first transfer transistor and the second transfer transistor.

[0021] According to at least one exemplary embodiment, the first axis passes through a gate of the third transfer transistor.

[0022] According to at least one example embodiment, the gate of the third transfer transistor is located farther from the center of the pixel than the gates of the first transfer transistor and the second transfer transistor.

[0023] At least one exemplary embodiment relates to a system, the system including a light source and an imaging device, the imaging device including a pixel array, the pixel array including a plurality of pixels. Each pixel includes a photoelectric conversion region, which converts incident light into electric charge; and a charge transfer portion, which is connected to the photoelectric conversion region and has line symmetry along a first axis in a plan view. The charge transfer portion includes a first transfer transistor, which is connected to a first floating diffusion region and the photoelectric conversion region and is located on a first side of the photoelectric conversion region; and a second transfer transistor, which is connected to a second floating diffusion region and the photoelectric conversion region and is located on the first side of the photoelectric conversion region. The system includes a signal processor, which is configured to determine the distance to an object based on the charge. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] FIG. 1 is a block diagram of an imaging device according to at least one example embodiment.

[0025] Figure 2 According to at least one exemplary embodiment, Figure 1 An exemplary schematic diagram of a pixel.

[0026] Figure 3 A plan view of an array of pixels according to at least one example embodiment is shown.

[0027] Figure 4 A plan view of a portion of a single pixel according to at least one example embodiment is shown.

[0028] Figure 5 A plan view of a portion of a single pixel according to at least one example embodiment is shown.

[0029] Figure 6 A plan view of a portion of a single pixel according to at least one example embodiment is shown.

[0030] Figure 7 A plan view of a portion of a single pixel according to at least one example embodiment is shown.

[0031] Figure 8 The use of at least one exemplary embodiment is shown Figure 5 The array layout of the pixel design is shown in FIG.

[0032] Fig. 9 The use of at least one exemplary embodiment is shown Figure 5 The array layout of the pixel design is shown in FIG.

[0033] Fig.10 The use of at least one exemplary embodiment is shown Figure 5 The array layout of the pixel design is shown in FIG.

[0034] Fig.11 The use of at least one exemplary embodiment is shown Figure 6 The array layout of the pixel design is shown in FIG.

[0035] Fig.12 The use of at least one exemplary embodiment is shown Figure 6 The array layout of the pixel design is shown in FIG.

[0036] Fig.13 The use of at least one exemplary embodiment is shown Figure 6 The array layout of the pixel design is shown in FIG.

[0037] Fig.14 The use of at least one exemplary embodiment is shown Figure 7 The array layout of the pixel design is shown in FIG.

[0038] Fig.15 The use of at least one exemplary embodiment is shown Figure 7The array layout of the pixel design is shown in FIG.

[0039] Fig.16 An array layout using a different pixel design than that shown in the other figures is shown according to at least one example embodiment.

[0040] Fig.17 An exemplary array layout using a different pixel design than that shown in the other figures is shown according to at least one exemplary embodiment.

[0041] Fig.18 An exemplary array layout using a different pixel design than that shown in the other figures is shown according to at least one exemplary embodiment.

[0042] Fig.19 An exemplary array layout using a different pixel design than that shown in the other figures is shown according to at least one exemplary embodiment.

[0043] Fig. 20 An exemplary array layout of a shared drain according to at least one exemplary embodiment is shown.

[0044] Fig.21 is a block diagram illustrating an example of a ranging module according to at least one example embodiment.

[0045] Fig. 22 is a diagram illustrating a use example of an imaging device according to at least one exemplary embodiment. DETAILED DESCRIPTION

[0046] FIG. 1 is a block diagram of an imaging device according to at least one example embodiment.

[0047] The pixel 51 includes a photoelectric conversion region PD such as a photodiode or other photosensor, transfer transistors TG0 and TG1 , floating diffusion regions FD0 and FD1 , reset transistors RST0 and RST1 , amplification transistors AMP0 and AMP1 , and selection transistors SEL0 and SEL1 .

[0048] Figure 1 The imaging device 1 shown in FIG. 1 may be an imaging sensor of a front surface or rear surface illumination type, and, for example, is provided in an imaging apparatus having a ranging function (or a distance measuring function).

[0049] The imaging device 1 has a pixel array unit (or pixel array or pixel portion) 20 formed on a semiconductor substrate (not shown) and a peripheral circuit integrated on the same semiconductor substrate as the pixel array unit 20. For example, the peripheral circuit includes a tap driving unit (or tap driver) 21, a vertical driving unit (or vertical driver) 22, a column processing unit (or column processing circuit) 23, a horizontal driving unit (or horizontal driver) 24, and a system control unit (or system controller) 25.

[0050] The imaging device 1 is further provided with a signal processing unit (or signal processor) 31 and a data storage unit (or data storage or memory or computer-readable storage medium) 32. It should be noted that the signal processing unit 31 and the data storage unit 32 may be mounted on the same substrate as the imaging device 1 or may be arranged on a substrate separate from the imaging device 1 in the imaging apparatus.

[0051] The pixel array unit 20 has a configuration in which pixels 51 that generate charges corresponding to the amount of light received and output signals corresponding to the charges are arranged two-dimensionally in a matrix shape in the row direction and the column direction. That is, the pixel array unit 20 has a plurality of pixels 51 that perform photoelectric conversion on incident light and output signals corresponding to the charges thus obtained. Here, the row direction refers to the arrangement direction of the pixels 51 in the horizontal direction, and the column direction refers to the arrangement direction of the pixels 51 in the vertical direction. The row direction is the horizontal direction in the figure, and the column direction is the vertical direction in the figure.

[0052] The pixel 51 receives light incident from the external environment, for example, infrared light, performs photoelectric conversion on the received light, and outputs a pixel signal according to the charge thus obtained. The pixel 51 may include a first charge collector (charge collector) and a second charge collector, the first charge collector detecting the charge obtained by photoelectric conversion PD by applying a predetermined voltage (first voltage) to the pixel 51, and the second charge collector detecting the charge obtained by photoelectric conversion by applying a predetermined voltage (second voltage) to the pixel 51. The first and second charge collectors may include a tap A and a tap B, respectively. Although two charge collectors (e.g., tap A and tap B) are shown, more or fewer charge collectors may be included according to design preferences.

[0053] The tap driving unit 21 applies a predetermined first voltage to the first charge collector of each pixel 51 of the pixel array unit 20 through the predetermined voltage supply line 30, and applies a predetermined second voltage to the second charge collector thereof through the predetermined voltage supply line 30. Therefore, two voltage supply lines 30 including the voltage supply line 30 transmitting the first voltage and the voltage supply line 30 transmitting the second voltage are wired to one pixel column of the pixel array unit 20.

[0054] In the pixel array unit 20, for a matrix-shaped pixel array, a pixel drive line 28 is wired for each pixel row along the row direction, and two vertical signal lines 29 are wired for each pixel column along the column direction. For example, the pixel drive line 28 transmits a drive signal for driving when a signal is read from a pixel. It should be noted that although Figure 1 One wiring is shown for the pixel driving line 28, but the pixel driving line 28 is not limited to one. One end of the pixel driving line 28 is connected to the output end of the vertical driving unit 22 corresponding to each row.

[0055] The vertical driving unit 22 includes a shift register, an address decoder, etc. The vertical driving unit 22 drives each of all pixels of the pixel array unit 20 simultaneously or in units of rows, etc. That is, the vertical driving unit 22 includes a driving unit that controls the operation of each pixel of the pixel array unit 20 together with a system control unit 25 that controls the vertical driving unit 22.

[0056] A signal output from each pixel 51 of the pixel row in response to drive control of the vertical drive unit 22 is input to the column processing unit 23 through the vertical signal line 29. The column processing unit 23 performs predetermined signal processing on the pixel signal output from each pixel 51 through the vertical signal line 29 and temporarily holds the pixel signal after the signal processing.

[0057] Specifically, the column processing unit 23 performs noise removal processing, sample and hold (S / H) processing, analog-to-digital (AD) conversion processing, and the like as signal processing.

[0058] The horizontal driving unit 24 includes a shift register, an address decoder, etc., and sequentially selects unit circuits corresponding to pixel columns of the column processing unit 23. The column processing unit 23 sequentially outputs pixel signals obtained through signal processing for each unit circuit through selective scanning of the horizontal driving unit 24.

[0059] The system control unit 25 includes a timing generator and the like, which generates various timing signals and drives and controls the tap driving unit 21, the vertical driving unit 22, the column processing unit 23, the horizontal driving unit 24, and the like based on the various generated timing signals.

[0060] The signal processing unit 31 has at least a calculation processing function and performs various signal processing such as calculation processing on the basis of the pixel signal output from the column processing unit 23. The data storage unit 32 temporarily stores data required for signal processing in the signal processing unit 31. The signal processing unit 31 can control the overall function of the imaging device 1. For example, the tap driving unit 21, the vertical driving unit 22, the column processing unit 23, the horizontal driving unit 24, and the system control unit 25, as well as the data storage unit 32 can be controlled by the signal processing unit 31. The signal processing unit or the signal processor 31, alone or in combination Figure 1 The other elements of the system can control all operations of the system discussed in more detail below with reference to the drawings. Therefore, the terms "signal processing unit" and "signal processor" can also refer to a collection of elements 21, 22, 23, 24, 25 and / or 31.

[0061] Figure 2 Shown from Figure 1 Schematic diagram of an exemplary pixel 51. The pixel 51 includes a photoelectric conversion region PD such as a photodiode or other light sensor, transfer transistors TG0 and TG1, floating diffusion regions FD0 and FD1, reset transistors RST0 and RST1, amplification transistors AMP0 and AMP1, and selection transistors SEL0 and SEL1. The pixel 51 may further include an overflow transistor OFG, transfer transistors FDG0 and FDG1, and floating diffusion regions FD2 and FD3.

[0062] The pixel 51 can be driven according to the control signal or transfer signal GD0, GD90, GD180 and GD270 applied to the gate or tap A / B of the transfer transistor TG0 / TG1, the reset signal RSTDRAIN, the overflow signal OFGn, the power supply signal VDD, the selection signal SELn and the vertical selection signals VSL0 and VSL1. These signals are driven by the Figure 1 The various elements (eg, tap driver 21, vertical driver 22, system controller 25, etc.) are provided.

[0063] like Figure 2 As shown, transfer transistors TG0 and TG1 are connected to the photoelectric conversion region PD and have taps A / B that transfer charges due to application of a transfer signal.

[0064] These transmission signals GD0, GD90, GD180, and GD270 may have different phases relative to the phase of the modulation signal from the light source (e.g., phases that differ by 0, 90, 180, and / or 270 degrees). The transmission signals may be applied in a manner that allows depth information (or pixel values) to be captured in a desired number of frames (e.g., one, two, four, etc.). One of ordinary skill in the art will understand how to apply the transmission signals in order to calculate the distance to an object using the collected charge.

[0065] It should be understood that, if necessary, transfer transistors FDG0 / FDG1 and floating diffusion regions FD2 / FD3 are included to expand the charge capacity of pixel 51. However, if necessary, these elements may be omitted or not used. An overflow transistor OFG is included to transfer overflow charges from the photoelectric conversion region PD, but if necessary, the overflow transistor OFG may be omitted or not used. Furthermore, if only one tap is required, the elements associated with the other taps (e.g., TG1, FD1, FDG1, RST1, SEL1, AMP1) may not be used or omitted.

[0066] It should be understood that Figures 3 to 20 The substantially accurate relative positional relationship of the elements described therein is shown and can serve as support for such positional relationship. For example, the drawings provide support for the selection transistor SEL and the amplifier transistor AMP to be aligned with each other in the vertical direction, and the transistors FDG and RST to be aligned with each other in the vertical direction. As another example, the drawings provide support for the transistor on the right side of the figure to be aligned with the transistor on the left side of the figure in the horizontal direction. As yet another example, the drawings are generally accurate in showing the positions of overlapping elements.

[0067] In addition, where it is appropriate to refer to a general element or group of elements rather than a specific element, the description may refer to the element or group of elements by its root term. For example, when it is not necessary to refer to a specific pass transistor TG0 or TG1, the description may refer to the pass transistor "TG".

[0068] Figures 3 to 7 An exemplary overview of the inventive concept is shown.

[0069] Figure 3 A plan view of an array 300 of pixels 51 in an imaging device 1 according to at least one exemplary embodiment is shown. Nine pixels 51 are shown, but exemplary embodiments are not limited thereto and may include more or fewer pixels. Each pixel 51 may include a photoelectric conversion region PD (octagonal) that converts incident light into electric charge, and each photoelectric conversion region PD may be isolated from an adjacent photoelectric conversion region PD by an isolation structure that reflects light and / or blocks light from entering an adjacent photoelectric conversion region PD.

[0070] exist Figures 3 to 7 In the embodiment, it should be understood that the transfer transistors TG0 / TG1 are on the same side (or the same half) of the photoelectric conversion region PD, which can improve the charge transfer rate and / or the OFG reset time (e.g., to reset the overflow region). Figure 3 As shown, the impurity concentration of the photoelectric conversion region can vary across the region of the photoelectric conversion region PD. For example, the impurity concentration can increase in the direction toward TG0, TG1, and OFG, which can cause faster transfer of charge to FD0, FD1, and / or the overflow region and fast OFG reset. Figure 3 An example is shown in which each photoelectric conversion region PD has a U-shaped region closest to TG0, OFG, and TG1. The U-shaped region can have a higher impurity concentration than the rest of the photoelectric conversion region PD. The higher concentration impurity region can be created by a mask designed to induce a potential gradient that can drive charge from the photoelectric conversion region toward FD0 and / or FD1. Although in Figure 6 to Figure 21 It is not explicitly shown in the drawings, but it should be understood that these designs may also include increasing impurity concentration in the direction toward the transfer transistors TG0 / TG1 and the overflow transistor OFG.

[0071] Figure 4 Shown from Figure 3 A plan view of a portion of a single pixel 51. Figure 4 4 shows a charge transfer section 400 including transistors TG0, TG1, and OFG and floating diffusion regions FD0 and FD1. As shown, the charge transfer section 400 has line symmetry along an axis 405 passing through a center 410 of the pixel 51. Typically, the center 410 may be the center of the photoelectric conversion region PD. However, the center 410 may also be a portion including the photoelectric conversion region and the floating diffusion regions FD0 and FD1. Figure 2 The center of the entire pixel or pixel area of ​​one or more additional transistors. That is, the center of the pixel can be defined by drawing a boundary (e.g., an arbitrary boundary) around the photoelectric conversion region of the pixel 51 and optionally one or more transistors, and then selecting a point in the middle of the pixel when measured in the horizontal direction. Additionally or alternatively, according to an embodiment, the center can be determined as a point through which the axis passing through it causes the linear symmetry of the charge transfer portion. As discussed in more detail below, the charge transfer portion of the pixel can have linear symmetry and each pixel or pixel area including the charge transfer portion and one or more transistors can have linear symmetry.

[0072] Throughout the description, even if not explicitly shown in the drawings, the charge transfer section is generally referred to as transistors TG0 and TG1 with or without transistor OFG.

[0073] Figure 5A plan view of a portion of a single pixel 51 is shown, in which the photoelectric conversion region PD has Figure 1 The charge transfer section 500 may have a different shape, for example, a rectangular shape including an extended portion of the charge transfer section 500. As shown in the figure, the charge transfer section 500 has a line symmetry along an axis 505 passing through a center 510 of the pixel 51. Here, the center 510 may be the center of the photoelectric conversion region PD. However, the center 510 may also be a portion including the photoelectric conversion region and the portion from the Figure 2 Thus, according to at least one exemplary embodiment, each pixel region may have line symmetry.

[0074] Here, it should be understood that Figure 5 It is further shown that the photoelectric conversion region PD includes a main portion 520 and an extension portion 525 extending from the main portion 520 . Figure 5 The extension portion 525 includes a first edge, a second edge, and a third edge connecting the first edge and the second edge. The transfer transistor TG0 is located at the first edge, the transfer transistor TG1 is located at the second edge, and the overflow transistor (or third transfer transistor) OFG is located at the third edge.

[0075] Reference Figures 3 to 7 Each pixel 51 may include two transfer transistors TG0 and TG1 for transferring charges generated by the photoelectric conversion region PD. The transfer transistors TG0 / TG1 may be configured to transfer charges generated by a driver (e.g., from Figure 1 The corresponding drive signals generated by the elements (element of the device) are turned on and off so that, for example, charges are transferred by TG0 and TG1 at different times. Each pixel 51 may further include two floating diffusion regions FD0 and FD1 and an overflow transistor OFG for holding the charges transferred by the respective transfer transistors TG0 / TG1. The overflow transistor OFG may be a transistor that allows charge to overflow from the PD to the overflow region (having the same or similar function as the floating diffusion region). The charge captured in the overflow region may be discharged (for example, discharged to the ground without being read out) in some cases or read out as part of the collected charge in other cases. In one example, if the collected charge is caused by a bright surrounding environment or other conditions that produce a signal of no interest, the charge in the overflow region may be discharged. In another example, if the collected charge represents a signal of interest, the charge in the overflow region may be read out.

[0076] Figure 6FIG. 6 is a plan view of a portion of a single pixel 51 according to at least one exemplary embodiment. As shown, the charge transfer portion 600 has line symmetry along an axis 605 offset from a center 610 of the pixel 51. Here, the center 610 may be the center of the photoelectric conversion region PD. However, the center 610 may also be a portion including the photoelectric conversion region and the charge transfer portion 605 from the pixel 51. Figure 2 The center of the entire pixel area of ​​one or more additional transistors.

[0077] exist Figure 6 In FIG. 1 , it should be understood that the pixel region is asymmetric because the transfer transistors TG0 / TG1 , the floating diffusion regions FD0 / FD1 , and the overflow transistor OFG are offset to one side of the photoelectric conversion region PD. Figure 6 A left offset is shown, but exemplary embodiments may also employ a right offset.

[0078] Figure 7 FIG. 1 shows a plan view of a portion of a single pixel 51 according to at least one exemplary embodiment. As shown, the charge transfer portion 700 has line symmetry along an axis 705 passing through a center 710 of the pixel 51. Here, the center 710 may be the center of the photoelectric conversion region PD. However, the center 710 may also be a portion including the photoelectric conversion region and the charge transfer portion 700 from the pixel 51. Figure 2 Thus, according to at least one exemplary embodiment, each pixel region may have line symmetry (eg, diagonal symmetry).

[0079] Figures 4 to 7 Further shown are modulation regions 415, 515, 615, and 715, which are regions (e.g., doped regions) near the gates of transistors TG0 and TG1 that may receive control signals to assist in directing charge to TG0 or TG1. The charge separation efficiency, i.e., the modulation contrast between the active and inactive regions, is referred to as Cmod. Cmod is calculated by {|I0-II| / (I0+I1)}×100, where I0 is the signal detected in one of the two taps TG0 and TG1, and I1 is the signal detected in the other of the two taps TG0 or TG1. Generally, it is desired that Cmod be higher and / or matched between taps TG0 / TG1 to improve image quality. Because Figures 4 to 7 The pixel design includes a charge transfer section with line symmetry, so the Cmod of each tap TG0 and TG1 is matched or closely matched. In addition, the positions of transistors TG0, TG1 and OFG cause fast charge transfer operation of transistors TG0 and TG1 and fast reset operation of transistor OFG.

[0080] Although not explicitly shown, Figure 6 and Figure 7Each photoelectric conversion region PD in includes Figure 5 Main and extended parts shown.

[0081] Figures 8 to 10 Shows the use of Figure 5 The exemplary array layouts 800, 900 and 1000 of the pixel designs are shown in FIG. Figure 8 and Fig. 9 In the overflow transistor OFG, the drain is not shared, but in Fig.10 In , the overflow transistors OFG of the two photoelectric conversion regions PD are adjacent to each other to allow a shared drain (eg, a shared overflow region). Figures 8 to 10 It should be understood that any empty space between PDs may include Figure 2 Other elements of the pixel circuit (e.g., transistors SEL, AMP, RST, etc.).

[0082] Figure 8 The pixels 51 are shown oriented adjacent to each other such that each charge transfer section 500 of horizontally adjacent pixels 51 is aligned, and such that each charge transfer section 500 of vertically adjacent pixels 51 is aligned.

[0083] Fig. 9 The following configuration is shown, in which the extension of each photoelectric conversion region PD is in a cross configuration so that each charge transfer section 500 is aligned in the horizontal direction, but the direction of orientation is alternated between adjacent pixels 51. The charge transfer section 500 is aligned so that a straight line passes through the transistor TG0 / TG1 of each pixel 51.

[0084] Fig.10 A configuration is shown in which the extended portions of vertically adjacent pixels face each other so as to allow the overflow transistors OFG to share a drain. The charge transfer sections 500 of horizontally adjacent pixels 51 are aligned with each other in the horizontal direction.

[0085] Figure 11 to Figure 13 Shows the use of Figure 6 Exemplary array layouts 1100, 1200, and 1300 of pixel designs are shown in FIG. Fig.11 and Fig.13 An example is shown in which the overflow transistors OFG do not share a drain, but Fig.12 An example is shown in which the overflow transistors OFG of two photoelectric conversion regions PD are adjacent to each other to allow drain sharing. Fig.12 and Fig.13 Although not shown, it should be understood that in the open central area created by the array layout, it is possible to include Figure 2 Other elements of the pixel circuit (e.g., selection transistor, reset transistor, amplification transistor, etc.).

[0086] Fig.11 A layout is shown in which the extended portions of each pixel 51 are arranged crosswise. This layout enables horizontally adjacent pixels to have the charge transfer sections 600 aligned with each other in the horizontal direction.

[0087] Fig.12 The layout in FIG. 5 shows a layout in which vertically adjacent pixels 51 have extended portions facing each other to allow the overflow transistors OFG to share a drain. The charge transfer portions 600 of vertically adjacent pixels 51 are aligned with each other in the vertical direction, and the charge transfer portions 600 of horizontally adjacent pixels are aligned with each other in the horizontal direction.

[0088] Fig.13 The layout arranges pixels 51 so that each extended portion of each PD faces the main portion of another PD.

[0089] Fig.14 and Fig.15 Shows the use of Figure 7 The exemplary array layouts 1400 and 1500 of the pixel design are shown in FIG. Fig.14 In the overflow transistor OFG, the drain is not shared, but in Fig.15 All four overflow transistors OFG can share the same drain.

[0090] Fig.14 The layout of FIG. 5 shows pixels 51 having extensions that all extend in the same diagonal direction, while Fig.15 The layout of FIG. 4 shows extensions extending in different directions so that all four overflow transistors OFG can share a drain.

[0091] Fig.16 An exemplary array layout 1600 is shown that uses a different pixel design than that shown in the other figures. Fig.16 A transistor region TR including transfer transistors TG0 , TG1 , an overflow transistor OFG, transfer transistors FDG0 / FDG1 , reset transistors RST0 / RST1 , selection transistors SEL0 / SEL1 , and amplification transistors AMP0 / AMP1 is shown. Fig.16 The photoelectric conversion region PD in can be used to sense light in two spectrums (eg, visible spectrum and invisible spectrum). Fig.16 In FIG. 1 , there is line symmetry for the charge transfer section including the transistors TG0 , TG1 , and OFG, and there is also line symmetry for at least some transistors (eg, RST0 , FDG0 , RST1 , and FDG1 ) in the transistor region TR.

[0092] Fig.17An example array layout 1700 is shown that uses a different pixel design than that shown in the other figures. Fig.17 Included with Fig.16 Similar components, except Fig.17 The photoelectric conversion area PD ratio Fig.16 So, for example, Fig.17 It can be used as a ToF sensor to sense light in a single spectrum (e.g., the invisible spectrum). Fig.17 In FIG. 1 , there is line symmetry for the charge transfer section including the transistors TG0 , TG1 , and OFG, and there is also line symmetry for at least some transistors (eg, RST0 , FDG0 , RST1 , and FDG1 ) in the transistor region TR.

[0093] Fig.18 and 19 Shows that with Figures 4 to 7 Compared to other exemplary array layouts 1800 and 1900 of photoelectric conversion regions PD of different shapes. Fig.18 In FIG. 1 , there is line symmetry for the charge transfer section including transistors TG0 , TG1 , and OFG, and there is line symmetry for at least some transistors (eg, RST0 , FDG0 , RST1 , FDG1 , SEL0 , and AMP0 ) in the transistor region TR. Fig.19 There is line symmetry for the charge transfer section including transistors TG0, TG1, and OFG, and there is also line symmetry for all transistors in the transistor region TR (e.g., RST0, FDG0, RST1, FDG1, SEL0, AMP0, SEL1, and AMP1).

[0094] Fig. 20 An exemplary array layout with a shared drain for reset transistors RST, OFG, and power supply VDD (e.g., applied to RST) is shown. For example, the reset transistor RST0 of one pixel 51 can share a drain with the reset transistor RST0 of another vertically adjacent pixel. The same is true for the adjacent reset transistor RST1. Similarly, the amplifier transistor AMP0 of one pixel can share a drain with the amplifier transistor AMP0 of another vertically adjacent pixel. The same is true for the adjacent amplifier transistor AMP1.

[0095] Fig. 20 It is further shown how two PDs can share the drain of their respective overflow transistors OFG. Fig. 20 In the example of FIG. 1 , the overflow transistor OFG is located between the photoelectric conversion regions PD of two pixels. In a plan view, each photoelectric conversion region PD is separated from an adjacent PD by an isolation material.

[0096] A system / apparatus which may incorporate the imaging device described above will now be described.

[0097] Fig.21 is a block diagram illustrating an example of a ranging module according to at least one example embodiment.

[0098] The distance measuring module 5000 includes a light emitting unit 5011 , a light emitting control unit 5012 , and a light receiving unit 5013 .

[0099] The light emitting unit 5011 has a light source that emits light having a predetermined wavelength and illuminates an object with illumination light whose brightness changes periodically. For example, the light emitting unit 5011 has a light emitting diode that emits infrared light having a wavelength range of 780 nm to 1000 nm as a light source, and generates illumination light in synchronization with a rectangular wave light emission control signal CLKp provided from the light emission control unit 5012.

[0100] It should be noted that the light emission control signal CLKp is not limited to a rectangular wave, as long as the control signal CLKp is a periodic signal. For example, the light emission control signal CLKp may be a sine wave.

[0101] The light emission control unit 5012 provides a light emission control signal CLKp to the light emission unit 5011 and the light receiving unit 5013 and controls the irradiation timing of the irradiation light. For example, the frequency of the light emission control signal CLKp is 20 megahertz (MHz). It should be noted that the frequency of the light emission control signal CLKp is not limited to 20 megahertz (MHz) and can be 5 megahertz (MHz) or the like.

[0102] The light receiving unit 5013 receives reflected light reflected from an object, calculates distance information of each pixel according to the light reception result, generates a depth image in which the distance to the object is represented by a grayscale value of each pixel, and outputs the depth image.

[0103] The imaging device 1 described above is used for the light receiving unit 5013, and for example, the imaging device 1 serving as the light receiving unit 5013 calculates distance information of each pixel from the signal intensity detected by each tap A / B on the basis of the light emission control signal CLKp.

[0104] As mentioned above, Figure 1 The imaging device 1 shown in the figure can be incorporated into the light receiving unit 5013 of the distance measuring module 5000 which obtains and outputs information related to the distance to the subject by the indirect ToF method. By adopting the imaging device 1 of one or more embodiments described above, one or more distance measurement characteristics (e.g., distance accuracy, measurement speed, etc.) of the distance measuring module 5000 can be improved.

[0105] Fig. 22is a diagram showing a use example of the imaging device 1 according to at least one exemplary embodiment.

[0106] For example, the imaging device 1 (image sensor) described above can be used in various situations of sensing light such as visible light, infrared light, ultraviolet light, and X-rays as described below. The imaging device 1 may be included in the following devices: devices for capturing images such as digital cameras and portable devices with camera functions; devices for traffic, such as vehicle-mounted sensors that capture images of vehicles to enable automatic parking, recognition of driver status, measurement of distance, etc. The imaging device 1 may be included in devices for home appliances such as TVs, refrigerators, and air conditioners, so as to capture user gestures and perform device operations according to the gestures. The imaging device 1 may be included in devices for medical care, such as endoscopes and devices for angiography by receiving infrared light, etc. The imaging device 1 may be included in devices for security, such as security monitoring cameras and personal authentication cameras, etc. The imaging device 1 may be included in devices for beauty, such as skin measurement devices that capture skin, etc. The imaging device 1 may be included in devices for sports, such as action cameras, wearable cameras for sports, etc. The imaging device 1 may be included in devices for agriculture, such as cameras used to monitor the conditions of farms or crops, etc.

[0107] Reference Figures 1 to 22 , it should be understood that at least one exemplary embodiment relates to an imaging device 1 of a pixel array 300 including a plurality of pixels 51. Each pixel 51 may include a photoelectric conversion region PD that converts incident light into electric charge and a charge transfer section 400 / 500 / 600 / 700 connected to the photoelectric conversion region PD and having line symmetry along a first axis 405 / 505 / 605 / 705 in a plan view. Each charge transfer section may include a first transfer transistor TG0 connected to a first floating diffusion region FD0 and the photoelectric conversion region PD and located on a first side of the photoelectric conversion region PD. Each charge transfer section includes a second transfer transistor TG1 connected to a second floating diffusion region FD1 and the photoelectric conversion region PD and located on a first side of the photoelectric conversion region PD. In other words, the transfer transistors TG0 / TG1 are on the same half of the pixel 51. As shown in the figure, each charge transfer section includes a third transfer transistor OFG connected to an overflow region and located on a first side of the photoelectric conversion region PD and between the first transfer transistor TG0 and the second transfer transistor TG1. As shown in the figure, the first axis 405 / 505 / 605 / 705 passes through the gate of the third transfer transistor OFG.

[0108] like Figures 4 to 7As shown, for example, the gate of the third transfer transistor OFG can be located farther away from the center of the pixel 51 than the gate of the first transfer transistor and the gate of the second transfer transistor. In some examples, the gate of the first transfer transistor TG0 and the gate of the second transfer transistor TG1 are equidistant from the center of the pixel 51 (for example, see Figure 4 , Figure 5 and Figure 7 ).

[0109] In some examples, the gate of the third transfer transistor OFG is closer to the center of the pixel 51 than the gate of the first transfer transistor TG0 and the gate of the second transfer transistor TG1 (eg, see Fig.18 ).

[0110] In at least one exemplary embodiment, each pixel 51 further includes a transistor portion TR in which a plurality of transistors are disposed, and the transistor portion has a line symmetry along the first axis. For example, the plurality of transistors include third and fourth transfer transistors FDG0 / FDG1 and first and second reset transistors RST0 / RST1 (see, for example, Fig.16 and Fig.17 In at least one exemplary embodiment, the plurality of transistors include first and second selection transistors SEL0 / SEL1 and first and second amplifier transistors AMP0 / AMP1 (see, for example, Fig.19 ).

[0111] According to at least one exemplary embodiment, the photoelectric conversion region includes a main portion and an extension portion extending from the main portion. The first side of the photoelectric conversion region PD includes the extension portion (see Figures 5 to 7 ). In this case, the extension portion includes a first edge, a second edge, and a third edge connecting the first edge and the second edge. The first transfer transistor TG0 is located at the first edge, the second transfer transistor TG1 is located at the second edge, and the third transfer transistor OFG is located at the third edge.

[0112] According to at least one exemplary embodiment, the third transistors OFG of at least some of the plurality of pixels 51 share a drain region (eg, see Fig.10 , Fig.12 , Fig.15 and Fig. 20 ). In a plan view, the charge transfer sections of adjacent pixels are aligned with each other along a second axis perpendicular to the first axis (see, for example, Figures 8 to 12 , Fig.14 and Figures 16 to 20 ).

[0113] like Figure 3As shown, the impurity concentration of a portion of the photoelectric conversion region PD closest to the first transfer transistor TG0 and the second transfer transistor TG1 is greater than the impurity concentration of a portion of the photoelectric conversion region PD farthest from the first transfer transistor and the second transfer transistor.

[0114] As shown in various figures, the first axis passes through the center of the pixel 51.

[0115] At least one exemplary embodiment is directed to a system including the imaging device described above and a light source (eg, within light emitting unit 5011).

[0116] In addition, it should be understood that elements from different figures may be combined in any manner understood by a person of ordinary skill in the art.

[0117] Any processing device, control unit, processing unit, etc. discussed above may correspond to one or more computer processing devices, such as a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), any other type of integrated circuit (IC) chip, a collection of IC chips, a microcontroller, a collection of microcontrollers, a microprocessor, a central processing unit (CPU), a digital signal processor (DSP), or a plurality of microprocessors configured to execute an instruction set stored in a memory, etc.

[0118] As will be appreciated by those skilled in the art, various aspects of the present disclosure may be shown and described herein in any of a number of patentable categories or contexts, including any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereto. Therefore, various aspects of the present disclosure may be implemented entirely by hardware, entirely by software (including firmware, resident software, microcode, etc.), or a combination of software and hardware implementations, which may all be generally referred to herein as "circuits," "modules," "components," or "systems." In addition, various aspects of the present disclosure may take the form of a computer program product, which is contained in one or more computer-readable media having a computer-readable program code contained thereon.

[0119] Any combination of one or more computer-readable media may be used. A computer-readable medium may be a computer-readable signal medium or a computer-readable storage medium. For example, a computer-readable storage medium may be, but is not limited to, an electronic, magnetic, optical, electromagnetic or semiconductor system, device or apparatus, or any suitable combination of the above. More specific examples (a non-exhaustive list) of computer-readable storage media will include the following: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a suitable optical fiber with a repeater, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the context of this document, a computer-readable storage medium may be any tangible medium that may contain or store a program used by or in conjunction with an instruction execution system, device or apparatus.

[0120] A computer readable signal medium may include a propagated data signal containing a computer readable program code, for example, in baseband or as part of a carrier wave. Such propagated signals may take any of a variety of forms, including, but not limited to, electromagnetic, optical, or any suitable combination thereof. A computer readable signal medium may be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transmit a program used by or in conjunction with an instruction execution system, device, or apparatus. The program code contained on a computer readable signal medium may be transmitted using any suitable medium, including, but not limited to, wireless, wired, fiber optic cable, RF, etc., or any suitable combination of the foregoing.

[0121] Computer program code for performing operations of various aspects of the present disclosure may be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java, Scala, Smalltalk, Eiffel, JADE, Emerald, C++, C#, VB.NET, Python, etc.; traditional procedural programming languages ​​such as "C" programming language, Visual Basic, Fortran2003, Perl, COBOL 2002, PHP, ABAP, etc.; dynamic programming languages ​​such as Python, Ruby and Groovy; or other programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer through any type of network including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., through the Internet using an Internet Service Provider) or in a cloud computing environment or as a service, such as Software as a Service (SaaS).

[0122] Various aspects of the present disclosure are described herein with reference to the flow chart and / or block diagram of the method, device (system) and computer program product according to the embodiments of the present disclosure.It should be understood that each block of the flow chart and / or block diagram and the combination of the blocks of the flow chart and / or block diagram can be realized by computer program instructions.These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer or other programmable data processing device to produce a machine, so that the instructions executed by the processor of a computer or other programmable instruction execution device create a mechanism for realizing the function / action specified in the flow chart and / or block diagram block.

[0123] These computer program instructions may also be stored in a computer-readable medium that can direct a computer, other programmable data processing device, or other device to operate in a specific manner when executed, so that the instructions, when stored in the computer-readable medium, produce an article of manufacture including instructions, which, when executed, cause the computer to implement the functions / actions specified in the flowchart and / or block diagram. The computer program instructions may also be loaded onto a computer, other programmable instruction execution device, or other device so that a series of operating steps are executed on the computer, other programmable device, or other device to produce a computer-implemented process, so that when the instructions are executed on the computer or other programmable device, a process for implementing the functions / actions specified in the flowchart and / or block diagram is provided.

[0124] As used herein, the phrases "at least one," "one or more," "or," and "and / or" are open-ended expressions that are both conjunctions and separators in operation. For example, each of the expressions "at least one of A, B, and C," "at least one of A, B, or C," "one or more of A, B, and C," "one or more of A, B, or C," "A, B and / or C," and "A, B, or C" means A only, B only, C only, A and B together, A and C together, B and C together, or A, B, and C together.

[0125] The term "a" or "an" entity refers to one or more of that entity. Therefore, the terms "a" (or "an"), "one or more" and "at least one" can be used interchangeably herein. It should also be noted that the terms "comprising", "including" and "having" can be used interchangeably.

[0126] The foregoing discussion is presented for illustration and description. The foregoing is not intended to limit the present disclosure to the form disclosed herein. In the foregoing detailed description for examples, in order to simplify the present disclosure, various features of the present disclosure are combined together in one or more aspects, embodiments and / or configurations. The features of the various aspects, embodiments and / or configurations of the present disclosure can be combined in alternative aspects, embodiments and / or configurations other than those discussed above. This disclosure method should not be interpreted as reflecting the intention that the claims require more features than those explicitly stated in each claim. On the contrary, as reflected in the appended claims, the inventive aspects rely on less than all the features of a single previously disclosed aspect, embodiment and / or configuration. Therefore, the appended claims are hereby incorporated into this detailed description, wherein each claim exists independently as an embodiment of the present disclosure.

[0127] In addition, although the description includes descriptions of one or more aspects, embodiments and / or configurations and certain variations and modifications, other variations, combinations and modifications are also within the scope of the present disclosure, i.e., as may be within the skill and knowledge of those skilled in the art after understanding the present disclosure. It is intended to obtain rights including alternative aspects, embodiments and / or configurations within the permitted scope, including claimed alternative, interchangeable and / or equivalent structures, functions, scopes or steps, whether or not these alternative, interchangeable and / or equivalent structures, functions, scopes or steps are disclosed herein, and it is not intended to publicly specify any patentable subject matter.

[0128] An exemplary embodiment may be configured as follows:

[0129] (1) An imaging device comprising:

[0130] A pixel array comprising a plurality of pixels, each pixel comprising:

[0131] a photoelectric conversion region that converts incident light into electric charges; and

[0132] a charge transfer section connected to the photoelectric conversion region and having line symmetry along a first axis in a plan view, the charge transfer section comprising:

[0133] a first transfer transistor connected to the first floating diffusion region and the photoelectric conversion region and located on a first side of the photoelectric conversion region; and

[0134] A second transfer transistor is connected to the second floating diffusion region and the photoelectric conversion region and is located on the first side of the photoelectric conversion region.

[0135] (2) The imaging device according to (1), wherein the charge transfer section includes a third transfer transistor connected to the overflow region and located on the first side of the photoelectric conversion region and between the first transfer transistor and the second transfer transistor.

[0136] (3) The imaging device according to one or more of (1) to (2), wherein the first axis passes through a gate of the third transfer transistor.

[0137] (4) The imaging device according to one or more of (1) to (3), wherein the gate of the third transfer transistor is located farther from the center of the pixel than the gate of the first transfer transistor and the gate of the second transfer transistor.

[0138] (5) The imaging device according to one or more of (1) to (4), wherein the gate of the first transfer transistor and the gate of the second transfer transistor are equidistant from the center of the pixel.

[0139] (6) The imaging device according to one or more of (1) to (5), wherein the gate of the third transfer transistor is closer to the center of the pixel than the gate of the first transfer transistor and the gate of the second transfer transistor.

[0140] (7) The imaging device according to one or more of (1) to (6), wherein each pixel further includes a transistor portion in which a plurality of transistors are provided, and wherein the transistor portion has line symmetry along the first axis.

[0141] (8) The imaging device according to one or more of (1) to (7), wherein the plurality of transistors include third and fourth transfer transistors and first and second reset transistors.

[0142] (9) The imaging device according to one or more of (1) to (8), wherein the plurality of transistors include first and second selection transistors and first and second amplification transistors.

[0143] (10) The imaging device according to one or more of (1) to (9), wherein the photoelectric conversion region includes a main portion and an extension portion extending from the main portion, and wherein the first side of the photoelectric conversion region includes the extension portion.

[0144] (11) An imaging device according to one or more of (1) to (10), wherein the extended portion includes a first edge, a second edge, and a third edge connecting the first edge and the second edge, wherein the first transfer transistor is located at the first edge, the second transfer transistor is located at the second edge, and the third transfer transistor is located at the third edge.

[0145] (12) The imaging device according to one or more of (1) to (11), wherein the third transistors of at least some of the plurality of pixels share a drain region.

[0146] (13) The imaging device according to one or more of (1) to (12), wherein in the plan view, the charge transfer sections of adjacent pixels are aligned with each other along a second axis perpendicular to the first axis.

[0147] (14) An imaging device according to one or more of (1) to (13), wherein the impurity concentration of a portion of the photoelectric conversion region closest to the first transfer transistor and the second transfer transistor is greater than the impurity concentration of a portion of the photoelectric conversion region farthest from the first transfer transistor and the second transfer transistor.

[0148] (15) The imaging device according to one or more of (1) to (14), wherein the first axis passes through the center of the pixel.

[0149] (16) A system comprising:

[0150] light source; and

[0151] An imaging device, the imaging device comprising:

[0152] A pixel array comprising a plurality of pixels, each pixel comprising:

[0153] a photoelectric conversion region that converts incident light into electric charges; and

[0154] a charge transfer section connected to the photoelectric conversion region and having line symmetry along a first axis in a plan view, the charge transfer section comprising:

[0155] a first transfer transistor connected to the first floating diffusion region and the photoelectric conversion region and located on a first side of the photoelectric conversion region; and

[0156] A second transfer transistor is connected to the second floating diffusion region and the photoelectric conversion region and is located on the first side of the photoelectric conversion region.

[0157] (17) The system according to (16), wherein the charge transfer section includes a third transfer transistor connected to the overflow region and located on the first side of the photoelectric conversion region and between the first transfer transistor and the second transfer transistor.

[0158] (18) The system of one or more of (16) to (17), wherein the first axis passes through a gate of the third transfer transistor.

[0159] (19) A system according to one or more of (16) to (18), wherein the gate of the third transfer transistor is located farther from the center of the pixel than the gate of the first transfer transistor and the gate of the second transfer transistor.

[0160] (20) A system comprising:

[0161] light source;

[0162] An imaging device, the imaging device comprising:

[0163] A pixel array comprising a plurality of pixels, each pixel comprising:

[0164] a photoelectric conversion region that converts incident light into electric charges; and

[0165] a charge transfer section connected to the photoelectric conversion region and having line symmetry along a first axis in a plan view, the charge transfer section comprising:

[0166] a first transfer transistor connected to the first floating diffusion region and the photoelectric conversion region and located on a first side of the photoelectric conversion region; and

[0167] a second transfer transistor connected to a second floating diffusion region and the photoelectric conversion region and located on the first side of the photoelectric conversion region; and

[0168] A signal processor is configured to determine a distance to an object based on the charge.

[0169] Any one or more of the aspects / embodiments are substantially disclosed herein.

[0170] Any one or more of the aspects / embodiments substantially disclosed herein are arbitrarily combined with any one or more other aspects / embodiments substantially disclosed herein.

[0171] One or more means are suitable for carrying out any one or more of the above aspects / embodiments substantially disclosed herein.

Claims

1. An imaging device, comprising: A pixel array comprising a plurality of pixels, each pixel comprising: a photoelectric conversion region that converts incident light into electric charges; and a charge transfer section connected to the photoelectric conversion region and having line symmetry along a first axis in a plan view, the charge transfer section comprising: a first transfer transistor connected to the first floating diffusion region and the photoelectric conversion region and located at a first side of the photoelectric conversion region; a second transfer transistor connected to a second floating diffusion region and the photoelectric conversion region and located on the first side of the photoelectric conversion region; and A third transfer transistor is connected to the photoelectric conversion region and the overflow region and is located on the first side of the photoelectric conversion region and between the first transfer transistor and the second transfer transistor. 2 . The imaging device according to claim 1 , wherein the first axis passes through a gate of the third transfer transistor. 3 . The imaging device according to claim 2 , wherein the gate of the third transfer transistor is located farther from a center of the pixel than the gate of the first transfer transistor and the gate of the second transfer transistor. 4 . The imaging device according to claim 2 , wherein a gate of the first transfer transistor and a gate of the second transfer transistor are equidistant from a center of the pixel. 5 . The imaging device according to claim 2 , wherein the gate of the third transfer transistor is closer to a center of the pixel than the gates of the first transfer transistor and the second transfer transistor. 6 . The imaging device according to claim 1 , wherein each pixel further includes a transistor portion in which a plurality of transistors are provided, and wherein the transistor portion has line symmetry along the first axis. 7 . The imaging device according to claim 6 , wherein the plurality of transistors include fourth and fifth transfer transistors and first and second reset transistors. 8 . The imaging device according to claim 7 , wherein the plurality of transistors include first and second selection transistors and first and second amplification transistors. 9 . The imaging device according to claim 1 , wherein the photoelectric conversion region includes a main portion and an extension portion extending from the main portion, and wherein the first side of the photoelectric conversion region includes the extension portion.

10. The imaging device according to claim 9, wherein the extension portion includes a first edge, a second edge, and a third edge connecting the first edge and the second edge, wherein the first transfer transistor is located at the first edge, the second transfer transistor is located at the second edge, and the third transfer transistor is located at the third edge. 11 . The imaging device according to claim 9 , wherein the third transfer transistors of at least some of the plurality of pixels share a drain region.

12. The imaging device according to claim 9, wherein: In the plan view, the charge transfer sections of adjacent pixels are aligned with each other along a second axis perpendicular to the first axis.

13. An imaging device according to any one of claims 1 to 12, wherein an impurity concentration of a portion of the photoelectric conversion region closest to the first transfer transistor and the second transfer transistor is greater than an impurity concentration of a portion of the photoelectric conversion region farthest from the first transfer transistor and the second transfer transistor.

14. The imaging device according to any one of claims 1 to 12, wherein the first axis passes through the center of the pixel.

15. A system comprising: light source; and An imaging device, the imaging device comprising: A pixel array comprising a plurality of pixels, each pixel comprising: a photoelectric conversion region that converts incident light into electric charges; and a charge transfer section connected to the photoelectric conversion region and having line symmetry along a first axis in a plan view, the charge transfer section comprising: a first transfer transistor connected to the first floating diffusion region and the photoelectric conversion region and located at a first side of the photoelectric conversion region; a second transfer transistor connected to a second floating diffusion region and the photoelectric conversion region and located on the first side of the photoelectric conversion region; and A third transfer transistor is connected to the photoelectric conversion region and the overflow region and is located on the first side of the photoelectric conversion region and between the first transfer transistor and the second transfer transistor.

16. The system of claim 15, wherein the first axis passes through a gate of the third pass transistor. 17 . The system of claim 16 , wherein the gate of the third transfer transistor is located farther from a center of the pixel than the gates of the first transfer transistor and the second transfer transistor.

18. A system comprising: light source; An imaging device, the imaging device comprising: A pixel array comprising a plurality of pixels, each pixel comprising: a photoelectric conversion region that converts incident light into electric charges; and a charge transfer section connected to the photoelectric conversion region and having line symmetry along a first axis in a plan view, the charge transfer section comprising: a first transfer transistor connected to the first floating diffusion region and the photoelectric conversion region and located at a first side of the photoelectric conversion region; a second transfer transistor connected to a second floating diffusion region and the photoelectric conversion region and located on the first side of the photoelectric conversion region; and a third transfer transistor connected to the photoelectric conversion region and the overflow region and located at the first side of the photoelectric conversion region and between the first transfer transistor and the second transfer transistor; and A signal processor is configured to determine a distance to an object based on the charge.

Images