LED chip and preparation method thereof

Abstract

The present invention relates to the field of semiconductor manufacturing technology, and more specifically, to an LED chip and a method for manufacturing the same. The LED chip comprises a substrate, an epitaxial layer, a current blocking layer, a current spreading layer, a first P-type electrode, a first N-type electrode, a first insulating layer, a second P-type electrode, a second N-type electrode, a second insulating layer, a third P-type electrode, a third N-type electrode, a P-type pad, and an N-type pad. The LED chip improves the electrode design of a flip-chip by adding a third N-type electrode and a third P-type electrode. The third N-type electrode and the P-type pad do not overlap in space, and similarly, the third P-type electrode and the N-type pad do not overlap in space, preventing contact between the two. This eliminates the problem of silicon oxide fractures due to any reason, which could lead to interconnection of P and N-type electrodes of different polarities and cause leakage failure, thereby improving chip reliability.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to an LED chip and a preparation method thereof. Background Art

[0002] As a new generation of light sources, LEDs are widely used in lighting, display, backlighting, and even optical communications. Flip-chip LEDs, offering higher light efficiency, are increasingly popular among users. However, flip-chip manufacturing involves complex processes and complex manufacturing processes, which place higher demands on reliability and present challenges.

[0003] Conventional ODR structures, such as Figure 1 As shown, the P-type metal electrode layer extends below the N-type pad, and the two are separated by a SiO2 insulating layer, forming the area shown in the dotted box. If the insulating layer breaks or cracks for some reason, it may cause the P-type electrode and N-type pad to connect, resulting in leakage and reducing the reliability of existing LEDs.

[0004] In view of this, the present invention is proposed. Summary of the Invention

[0005] The first purpose of the present invention is to provide an LED chip. Compared with the conventional ODR structure, by improving the electrode design of the flip chip and adopting a double-layer homogeneous electrode, the chip failure problem caused by solder paste electromigration or insulation layer breakage is avoided, thereby improving the reliability of the chip.

[0006] The second object of the present invention is to provide a method for preparing an LED chip as described above, wherein the method adds a third N-type electrode and a third P-type electrode, and the third N-type electrode and the P-type pad do not overlap in space. Similarly, the third P-type electrode and the N-type pad do not overlap in space, and the two are not likely to contact each other. There is no problem of leakage failure caused by the insulation layer breaking due to any reason, which leads to the interconnection of P and N-type electrodes with different polarities.

[0007] In order to achieve the above-mentioned purpose of the present invention, the following technical solutions are adopted:

[0008] The present invention provides an LED chip, comprising:

[0009] substrate;

[0010] An epitaxial wafer with a PN step, the epitaxial wafer comprising an N-type semiconductor layer, a light-emitting layer and a P-type semiconductor layer;

[0011] at least one first P-type electrode, located on the PN step and electrically connected to the P-type semiconductor layer;

[0012] at least one first N-type electrode, located on the N-type semiconductor layer and electrically connected to the N-type semiconductor layer;

[0013] a first insulating layer, covering the first N-type electrode, the PN step, the first P-type electrode, and the N-type semiconductor layer, and provided with a plurality of first through holes and a plurality of second through holes;

[0014] a second P-type electrode, disposed on the first insulating layer and electrically connected to the first P-type electrode through the first through-hole;

[0015] a second N-type electrode, disposed on the first insulating layer and electrically connected to the first N-type electrode through the second through hole;

[0016] a second insulating layer, covering the second P-type electrode, the second N-type electrode and the first insulating layer, and provided with a plurality of third through holes and a plurality of fourth through holes;

[0017] a third P-type electrode, disposed on the second insulating layer and electrically connected to the second P-type electrode through the third through hole;

[0018] a third N-type electrode, disposed on the second insulating layer and electrically connected to the second N-type electrode through the fourth through hole;

[0019] a P-type pad, disposed on the third P-type electrode and electrically connected to the third P-type electrode;

[0020] The N-type pad is disposed on the third N-type electrode and is electrically connected to the third N-type electrode.

[0021] In a preferred embodiment of the present invention, in the vertical cross-sectional view direction, at least a third N-type electrode is provided between the N-type pad and the second P-type electrode;

[0022] And / or, at least the third P-type electrode is disposed between the P-type pad and the second N-type electrode.

[0023] In a preferred embodiment of the present invention, the second layer directly below the N pad is a second insulating layer and / or a second N-type electrode;

[0024] Preferably, the projection of the N pad on the horizontal plane is located within the projection of the third N-type electrode on the horizontal plane.

[0025] In a preferred embodiment of the present invention, the LED chip further comprises a third insulating layer, wherein the third insulating layer covers the third P-type electrode and the third N-type electrode;

[0026] The third insulating layer is provided with a plurality of fifth through holes and a sixth through hole;

[0027] The P-type pad is electrically connected to the third P-type electrode through the fifth through hole, and the N-type pad is electrically connected to the third N-type electrode through the sixth through hole.

[0028] In a preferred embodiment of the present invention, the distance between the third P-type electrode and the third N-type electrode is greater than 15 μm;

[0029] and / or; the total area of ​​the third P-type electrode and the third N-type electrode accounts for 50% to 75% of the area of ​​the entire LED chip;

[0030] and / or; the total area of ​​the P-type pad and the N-type pad accounts for 30% to 55% of the area of ​​the entire LED chip.

[0031] In a preferred embodiment of the present invention, the shortest distance between the second P-type electrode region and the side surface of the PN step is D1, the shortest distance between the third N-type electrode and the side surface of the PN step is D2, and the shortest distance between the N-type pad and the side surface of the PN step is D3, and D1<D2<D3;

[0032] Preferably, D1>5μm, D2>8μm, and D3>15μm.

[0033] In a preferred embodiment of the present invention, a plurality of the first P-type electrodes are spaced apart and arranged on the PN steps; and a plurality of the first N-type electrodes are spaced apart and arranged on the N-type semiconductor layer.

[0034] In a preferred embodiment of the present invention, a gap is formed between one or more of the second N-type electrodes and the second P-type electrode, and a portion of the second N-type electrodes is located on the PN step.

[0035] In a preferred embodiment of the present invention, the first insulating layer is silicon oxide and a DBR reflective layer;

[0036] Preferably, the thickness of the first insulating layer is 2 μm to 7 μm, and more preferably, the thickness is 3.5 μm to 5.5 μm.

[0037] In a preferred embodiment of the present invention, the second insulating layer and / or the third insulating layer comprises at least one of silicon oxide, silicon nitride and silicon oxynitride;

[0038] Preferably, the thickness of the second insulating layer and / or the third insulating layer is

[0039] The method for preparing the LED chip provided by the present invention comprises the following steps:

[0040] (a) providing a substrate, and sequentially depositing an N-type semiconductor layer, a light-emitting layer, and a P-type semiconductor layer on the substrate to form an epitaxial layer;

[0041] (b) depositing SiO2 on the epitaxial layer, and obtaining a current blocking layer by photolithography, and then depositing a current spreading layer, and obtaining a PN step by etching;

[0042] (c) depositing a plurality of first P-type electrodes and a plurality of first N-type electrodes alternately on the surface of the chip, and then depositing a first insulating layer;

[0043] (d) photolithographically forming a first through hole and a second through hole above the first P-type electrode and the first N-type electrode, respectively, and depositing a second P-type electrode at the first through hole and a second N-type electrode at the second through hole, wherein the second P-type electrode and the second N-type electrode are isolated from each other;

[0044] (e) depositing a second insulating layer, and photolithographically forming a third through hole and a fourth through hole above the second P-type electrode and the second N-type electrode, respectively, and depositing a third P-type electrode at the third through hole and a third N-type electrode at the fourth through hole, wherein the third P-type electrode and the third N-type electrode are isolated from each other, and the second P-type electrode extends below the third N-type electrode;

[0045] (f) depositing a third insulating layer, and photolithographically obtaining a fifth through hole and a sixth through hole above the third P-type electrode and the third N-type electrode, respectively, depositing a P-type pad at the fifth through hole, and depositing an N-type pad at the sixth through hole.

[0046] Compared with the prior art, the present invention has the following beneficial effects:

[0047] The present invention relates to an LED chip. Compared with a conventional ODR structure, the electrode design of a flip chip is improved by adding a third N-type electrode and a third P-type electrode. The third N-type electrode and the P-type pad do not overlap in space. Similarly, the third P-type electrode and the N-type pad do not overlap in space. There is no possibility of contact between the two. There is no problem of leakage failure caused by the interconnection of P and N-type electrodes with different polarities due to the breakage of silicon oxide for any reason, thereby improving the reliability of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0049] Figure 1 This is a cross-sectional view of a flip-chip LED chip with an existing ODR structure;

[0050] Figure 2 A schematic diagram of the planar structure of an LED chip provided by an embodiment of the present invention;

[0051] Figure 3 The LED chip provided by the embodiment of the present invention is along Figure 1 Cross-sectional view of cutting method A;

[0052] Figure 4 The LED chip provided by the embodiment of the present invention is along Figure 1 Cross-sectional view of cutting by method B;

[0053] Figure 5 A schematic diagram of the distances between the third P-type electrode, the third N-type electrode, the fourth P-type electrode, and the fourth N-type electrode of the LED chip provided by an embodiment of the present invention;

[0054] Figure 6 This is a schematic diagram of the planar structure of an LED chip provided by another embodiment of the present invention.

[0055] Reference numerals:

[0056] 100-substrate; 200-epitaxial layer; 210-N-type semiconductor layer;

[0057] 211-PN step; 220-light-emitting layer; 230-P-type semiconductor layer;

[0058] 300-current blocking layer; 400-current spreading layer; 510-first P-type electrode;

[0059] 511 - first through hole; 520 - first N-type electrode; 521 - second through hole;

[0060] 600 - first insulating layer; 710 - second P-type electrode; 711 - third through hole;

[0061] 720 - second N-type electrode; 721 - fourth through hole; 800 - second insulating layer;

[0062] 910-third P-type electrode; 920-third N-type electrode; 1000-NP pad group;

[0063] 1100-P type pad; 1200-N type pad; 1300-third insulation layer. DETAILED DESCRIPTION

[0064] The technical scheme of the present invention will be clearly and completely described below in conjunction with the accompanying drawings and specific embodiments, but it will be understood by those skilled in the art that the following described embodiments are part of embodiments of the present invention, rather than all embodiments, and are only used to illustrate the present invention, and should not be considered as limiting the scope of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative work are within the scope of protection of the present invention. Those who do not specify specific conditions in the embodiments are carried out according to normal conditions or the conditions recommended by the manufacturer. Those whose reagents or instruments are not specified by the manufacturer are conventional products that can be purchased commercially.

[0065] For reagents or instruments without indicating the manufacturer, they are all conventional products that can be purchased on the market.

[0066] In the description of the present invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate and simplify the description of the present invention. They are not intended to indicate or imply that the devices or components referred to must have, be constructed, or operate in a specific orientation, and therefore should not be construed as limitations on the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0067] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they may refer to fixed, detachable, or integral connections; mechanical or electrical connections; direct or indirect connections through an intermediate medium; and internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on the specific circumstances.

[0068] Figure 2 A schematic diagram of the planar structure of an LED chip provided by an embodiment of the present invention; Figure 3 The LED chip provided by the embodiment of the present invention is along Figure 1 Cross-sectional view of cutting method A, Figure 4 The LED chip provided by the embodiment of the present invention is along Figure 1 Cross-sectional view of cutting by way B. Figure 2 and Figure 3 The LED chip provided by the embodiment of the present invention includes:

[0069] substrate 100;

[0070] An epitaxial wafer having a PN step 211, wherein the epitaxial wafer includes an N-type semiconductor layer 210, a light-emitting layer 220, and a P-type semiconductor layer 230;

[0071] At least one first P-type electrode 510 , located on the PN step 211 and electrically connected to the P-type semiconductor layer 230 ;

[0072] at least one first N-type electrode 520 , located on the N-type semiconductor layer 210 and electrically connected to the N-type semiconductor layer 210 ;

[0073] A first insulating layer 600 , covering the first N-type electrode 520 , the PN step 211 , the first P-type electrode 510 , and the N-type semiconductor layer 210 , and provided with a plurality of first through holes 511 and a plurality of second through holes 521 ;

[0074] a second P-type electrode 710 disposed on the first insulating layer 600 and electrically connected to the first P-type electrode 510 through the first through hole 511;

[0075] a second N-type electrode 720 disposed on the first insulating layer 600 and electrically connected to the first N-type electrode 520 through the second through hole 521;

[0076] a second insulating layer 800 covering the second P-type electrode 710 , the second N-type electrode 720 and the first insulating layer 600 and provided with a plurality of third through holes 711 and a plurality of fourth through holes 721 ;

[0077] a third P-type electrode 910 disposed on the second insulating layer 800 and electrically connected to the second P-type electrode 710 through the third through hole 711;

[0078] a third N-type electrode 920 disposed on the second insulating layer 800 and electrically connected to the second N-type electrode 720 through the fourth through hole 721;

[0079] A P-type pad 1100 is disposed on the third P-type electrode 910 and electrically connected to the third P-type electrode 910;

[0080] The N-type pad 1200 is disposed on the third N-type electrode 920 and is electrically connected to the third N-type electrode 920 .

[0081] The epitaxial layer 200 includes a PN step 211, an upper step surface of the PN step 211 is a P-type semiconductor layer 230, and a lower step surface is an N-type semiconductor layer 210, and the upper step surface and the lower step surface are connected to form a side surface of the PN step 211;

[0082] In the process of designing the LED chip, a third N-type electrode 920 and a third P-type electrode 910 are added, and the third N-type electrode 920 and the P-type pad 1100 have no overlap in the vertical space or any other direction. Similarly, the third P-type electrode 910 and the N-type pad 1200 have no overlap in the vertical space or any other direction. There is no possibility of contact between the two, and there is no problem of leakage failure due to any break in the insulating layer, which leads to the interconnection of P and N-type electrodes with different polarities, thereby improving the reliability of the chip.

[0083] Furthermore, the substrate 100 may be a sapphire substrate 100 , but is not limited thereto. In addition, a patterned substrate 100 may also be selected.

[0084] Furthermore, the material of the N-type semiconductor layer 210 may be N-type doped gallium nitride, and the material of the P-type semiconductor layer 230 may be P-type doped gallium nitride, but they are not limited to these two semiconductor types.

[0085] Furthermore, the light-emitting layer 220 includes, but is not limited to, quantum wells and quantum barriers alternately stacked. The light-emitting layer 220 includes, but is not limited to, a red light-emitting layer 220, a yellow light-emitting layer 220, a green light-emitting layer 220, or a blue light-emitting layer 220. The quantum wells include, but are not limited to, InGaN quantum wells or AlInGaN quantum wells.

[0086] Furthermore, the current blocking layer 300 includes but is not limited to SiO 2 .

[0087] Furthermore, the current spreading layer 400 includes, but is not limited to, one of ITO, ZITO, ZIO, GIO, ZTO, FTO, AZO and GZO.

[0088] Furthermore, the current spreading layer 400 has a thickness of For example, it can be Furthermore, the current spreading layer 400 can be deposited by magnetron sputtering or evaporation.

[0089] In a preferred embodiment of the present invention, the current spreading layer 400 occupies 70% to 90% of the area of ​​the LED chip.

[0090] Furthermore, based on the patterned photoresist topography, multiple first P-type electrodes 510 and multiple first N-type electrodes 520 are deposited on the chip surface. The first P-type electrodes and first N-type electrodes 520 are preferably finger-shaped electrodes (finger electrodes). The first P-type electrodes 510 and first N-type electrodes 520 are isolated from each other by an isolation trench. Furthermore, preferably, the electrode structure of the first P-type electrodes 510 and first N-type electrodes 520 can be a metal electrode structure such as Cr / Al / Ti / Ni / Pt / Au, and can be a single metal layer or a composite layer of several metals.

[0091] In a preferred embodiment of the present invention, to improve the operational stability of the LED chip, a second electrode with the same polarity as the pad layer is sandwiched between the second electrode layer and the pad layer, ensuring that the second electrode layer and the pad layer do not contact each other. Specifically, at least a third N-type electrode 920 is disposed between the N-type pad 1200 and the second P-type electrode 710; and / or at least the third P-type electrode 910 is disposed between the P-type pad 1100 and the second N-type electrode 720. Furthermore, the second layer directly below the N-type pad is the second insulating layer 800 and / or the second N-type electrode 720.

[0092] Preferably, the projection of the N pad on the horizontal plane is located within the projection of the third N-type electrode 920 on the horizontal plane, so as to ensure that the third N-type electrode 920 and the P-type pad 1100 do not overlap in space. Similarly, the third P-type electrode 910 and the N-type pad 1200 do not overlap in space, and there is no possibility of contact between the two. There is no problem of silicon oxide breaking due to any reason, which leads to the interconnection of P and N-type electrodes with different polarities and leakage failure, thereby improving the reliability of the chip.

[0093] In a preferred embodiment of the present invention, an insulating layer can be further wrapped outside the third electrode layer. The LED chip also includes a third insulating layer 1300, and the third insulating layer 1300 covers the third P-type electrode 910 and the third N-type electrode 920; a plurality of fifth through holes and sixth through holes are provided on the third insulating layer 1300; the P-type pad 1100 is electrically connected to the third P-type electrode 910 through the fifth through hole, and the N-type pad 1200 is electrically connected to the third N-type electrode 920 through the sixth through hole.

[0094] In a preferred embodiment of the present invention, a gap is formed between one or more of the second N-type electrodes 720 and the second P-type electrode 710 , and some of the second N-type electrodes 720 are located on the PN step 211 .

[0095] In a preferred embodiment of the present invention, Figure 5In the example shown in P3, the distance between the third P-type electrode 910 and the third N-type electrode 920 is greater than 15 μm;

[0096] The total area of ​​the third P-type electrode 910 and the third N-type electrode 920 accounts for 50% to 75% of the area of ​​the entire LED chip, for example, 50%, 60%, 70%, or 75%.

[0097] The total area of ​​the P-type pad 1100 and the N-type pad 1200 accounts for 30% to 55% of the area of ​​the entire LED chip, for example, 30%, 40%, 45%, or 55%.

[0098] In a preferred embodiment of the present invention, the shortest distance between the second P-type electrode 710 and the side of the PN step 211 is D1, the shortest distance between the third N-type electrode 920 and the side of the PN step 211 is D2, and the shortest distance between the N-type pad 1200 and the side of the PN step 211 is D3, and D1<D2<D3;

[0099] Preferably, D1>5μm, D2>8μm, and D3>15μm.

[0100] Furthermore, a plurality of first P-type electrodes 510 are spaced apart on the PN step 211; a plurality of first N-type electrodes 520 are spaced apart on the N-type semiconductor layer 210; further, there are one or more second N-electrode regions, and the second N-electrode regions each have a gap with the second P-electrode region, wherein part of the second N-electrode region is located above the PN step 211.

[0101] In a preferred embodiment of the present invention, the first insulating layer 600 is silicon oxide and a DBR reflective layer.

[0102] Preferably, the DBR reflective layer includes but is not limited to any one or more of SiO2, TiO2 and Ti3O5, for example, SiO2 and / or TiO2, or SiO2 and / or Ti3O5. Furthermore, the DBR reflective layer can be formed by alternately depositing SiO2 and Ti3O5.

[0103] Furthermore, a first through-hole 511 directly through the first P-type electrode 510 and a second through-hole 521 directly through the first N-type electrode 520 are etched on the DBR reflective layer. A second P-type electrode 710 is formed at the first through-hole 511 by electron beam evaporation, and a second N-type electrode 720 is formed at the second through-hole 521 by electron beam evaporation. The second P-type electrode 710 and the second N-type electrode 720 form an optically conductive (ODR) structure with the DBR reflective layer, ensuring a reflectivity of this electrode layer between 60% and 95%. The metal electrode angle of this layer is required to be between 30° and 75°.

[0104] Preferably, the thickness of the first insulating layer 600 is 2 μm to 7 μm, for example, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, or 7 μm, and more preferably, 3.5 μm to 5.5 μm.

[0105] In a preferred embodiment of the present invention, the second insulating layer 800 and / or the third insulating layer 1300 include at least one of silicon oxide, silicon nitride and silicon oxynitride; for example, silicon oxide and / or silicon nitride, or silicon nitride and / or silicon oxynitride.

[0106] Preferably, the thickness of the second insulating layer 800 and / or the third insulating layer 1300 is For example,

[0107] Furthermore, the P-type pad 1100 and the N-type pad 1200 may be made of one or a combination of several metal layers selected from Ti, Al, Pt, Ni, and Au. Furthermore, the thickness of Al is The thickness of Pt is The thickness of Ti is The thickness of Ni is The thickness of Au is

[0108] Furthermore, the P-type pad 1100 and the N-type pad 1200 can be bump electrodes, and the electrode composition is Sn. Furthermore, the bump electrodes can be made by printing, electroplating or evaporation. The height of the bump electrodes is ≥5μm, and the height of the solder paste is ≥20μm;

[0109] In a preferred embodiment of the present invention, the total area of ​​the P-type pad 1100 and the N-type pad 1200 accounts for 30% to 55% of the area of ​​the entire LED chip, for example, 50%, 60%, 70%, or 75%.

[0110] In a preferred embodiment of the present invention, the sum of the areas of the third P-type electrode 910 and the third N-type electrode 920 is greater than the sum of the areas of the P-type pad 1100 and the N-type pad 1200 .

[0111] The embodiment of the present invention further provides a specific method for preparing the LED chip, comprising the following steps:

[0112] (1) providing a substrate 100, and sequentially fabricating an N-type semiconductor layer 210, a light-emitting layer 220, and a P-type semiconductor layer 230 on the substrate 100 to form an epitaxial layer 200;

[0113] (2) SiO2 is deposited on the epitaxial layer 200, and a current blocking layer 300 is obtained by yellow light and etching, and then a current blocking layer 300 is deposited by magnetron sputtering or evaporation with a thickness of An ITO film is formed to obtain a current spreading layer 400, a PN step 211 is obtained by etching, and an isolation groove is formed by deep etching;

[0114] (3) A photoresist is formed according to the pattern, and a first P-type electrode 510 and a first N-type electrode 520 are deposited alternately on the chip surface, and then a first insulating layer 600 is deposited;

[0115] (4) A first through hole 511 and a second through hole 521 are formed by photolithography above the first P-type electrode 510 and the first N-type electrode 520, respectively, and a second P-type electrode 710 is deposited at the first through hole 511. The first through hole 511 and the second through hole 521 are separated from each other without any extension or intersection; a second N-type electrode 720 is deposited at the second through hole 521. The second P-type electrode 710 and the second N-type electrode 720 are isolated from each other. The second P-type electrode 710 is connected to the first P-type electrode 510 through the first through hole, and the second N-type electrode 720 is connected to the first N-type electrode 520 through the first through hole, so that the electrode reflectivity is between 60% and 95%. The metal electrode angle of this layer is required to be between 30° and 75°.

[0116] (5) Deposit a second insulating layer 800 with a thickness of A third through hole 711 and a fourth through hole 721 are formed above the second P-type electrode 710 and the second N-type electrode 720 by yellow light and ICP dry etching, respectively. A third P-type electrode 910 is deposited at the third through hole 711, and a third N-type electrode 920 is deposited at the fourth through hole 721, so that the electrode reflectivity is 60% to 95%. To ensure subsequent thin film coverage, the metal electrode angle of this layer is required to be 30° to 75°.

[0117] The third P-type electrode 910 and the third N-type electrode 920 are isolated from each other, and the second P-type electrode 710 extends below the third N-type electrode 920. In addition, except for the third through hole 711 and the fourth through hole 721, the second insulating layer 800 has no broken parts on the rest of the front chip, thereby ensuring that the upper third N-type electrode 920 and the lower second P-type electrode 710 extending below the third N-type electrode 920 are separated, cutting off the leakage path.

[0118] (6) Deposit a third insulating layer 1300, and photoetch to obtain a fifth through hole and a sixth through hole above the third P-type electrode 910 and the third N-type electrode 920, respectively. The etching angle is required to be 20° to 80°. Deposit a P-type pad 1100 at the fifth through hole, and deposit an N-type pad 1200 at the sixth through hole.

[0119] (7) Grinding, scratching, etc. are performed to form core particles, wherein the grinding thickness ranges from 80 μm to 300 μm.

[0120] This results in a flip-chip LED chip. The P-type pad 1100 is interconnected to the third P-type electrode 910 via the fifth through-hole in the third insulating layer 1300. The N-type pad 1200 is interconnected to the third N-type electrode 920 via the sixth through-hole in the third insulating layer 1300. Furthermore, the surface of the fourth P-type pad 1100 facing the substrate 100 is connected only to the third P-type electrode 910, while the surface of the N-type pad 1200 facing the substrate 100 is connected only to the third N-type electrode 920. From a horizontal or vertical perspective, no surface of the P-type pad 1100 directly or indirectly contacts the third N-type electrode 920, and no extension or intersection occurs. The same principle applies to the N-type pad 1200 and the third P-type electrode 910. Therefore, there is no risk of leakage failure due to interconnection of PN-type electrodes of different polarity caused by silicon oxide fracture.

[0121] Another embodiment of the present invention also provides a specific method for preparing the LED chip. The structure diagram of the prepared LED chip is as shown in FIG. Figure 6 As shown, the N-type pad 1200 and the P-type pad 1100 are in the form of two pads, such as the NP pad group 1000 shown in the figure, and the size of each pad is 688 μm*244 μm.

[0122] Although the present invention has been illustrated and described using specific embodiments, it should be appreciated that the above embodiments are merely intended to illustrate the technical solutions of the present invention rather than to limit them. Those skilled in the art should understand that the technical solutions described in the above embodiments may be modified, or some or all of the technical features thereof may be replaced by equivalents, without departing from the spirit and scope of the present invention. However, these modifications or replacements do not deviate from the essence of the corresponding technical solutions within the scope of the technical solutions of the embodiments of the present invention. Therefore, this means that all such replacements and modifications within the scope of the present invention are included in the appended claims.

Claims

1. LED chip, characterized in that, include: substrate; An epitaxial wafer with PN steps, the epitaxial wafer comprising an N-type semiconductor layer, a light-emitting layer and a P-type semiconductor layer; a current spreading layer is provided on the P-type semiconductor layer; at least one first P-type electrode, located on the PN step and electrically connected to the P-type semiconductor layer; at least one first N-type electrode, located on the N-type semiconductor layer and electrically connected to the N-type semiconductor layer; a first insulating layer, covering the first N-type electrode, the PN step, the first P-type electrode, and the N-type semiconductor layer, and provided with a plurality of first through holes and a plurality of second through holes; a second P-type electrode, disposed on the first insulating layer and electrically connected to the first P-type electrode through the first through-hole; a second N-type electrode, disposed on the first insulating layer and electrically connected to the first N-type electrode through the second through hole; a second insulating layer, covering the second P-type electrode, the second N-type electrode and the first insulating layer, and provided with a plurality of third through holes and a plurality of fourth through holes; a third P-type electrode, disposed on the second insulating layer and electrically connected to the second P-type electrode through the third through hole; a third N-type electrode, disposed on the second insulating layer and electrically connected to the second N-type electrode through the fourth through hole; a P-type pad, disposed on the third P-type electrode and electrically connected to the third P-type electrode; an N-type pad, disposed on the third N-type electrode and electrically connected to the third N-type electrode; In the vertical cross-sectional view direction, at least the third N-type electrode is disposed between the N-type pad and the second P-type electrode, and at least the third P-type electrode is disposed between the P-type pad and the second N-type electrode.

2. The LED chip according to claim 1, wherein: The second layer directly below the N-type pad is a second insulating layer and / or a second N-type electrode.

3. The LED chip according to claim 2, wherein: The projection of the N-type pad on the horizontal plane is located within the projection of the third N-type electrode on the horizontal plane.

4. The LED chip according to claim 1, wherein The LED chip further includes a third insulating layer, wherein the third insulating layer covers the third P-type electrode and the third N-type electrode; The third insulating layer is provided with a plurality of fifth through holes and a sixth through hole; The P-type pad is electrically connected to the third P-type electrode through the fifth through hole, and the N-type pad is electrically connected to the third N-type electrode through the sixth through hole.

5. The LED chip according to claim 1, wherein: The distance between the third P-type electrode and the third N-type electrode is greater than 15 μm; and / or; the total area of ​​the third P-type electrode and the third N-type electrode accounts for 50% to 75% of the area of ​​the entire LED chip; and / or; the area of ​​the P-type pad and the N-type pad together accounts for 30% to 55% of the area of ​​the entire LED chip.

6. The LED chip according to claim 1, wherein: The shortest distance between the second P-type electrode region and the side of the PN step is D1, the shortest distance between the third N-type electrode and the side of the PN step is D2, the shortest distance between the N-type pad and the side of the PN step is D3, and D1<D2<D3.

7. The LED chip according to claim 6, characterized in that The D1>5μm, D2>8μm, and D3>15μm.

8. The LED chip according to claim 1, wherein: A plurality of first P-type electrodes are spaced apart and arranged on the PN steps; a plurality of first N-type electrodes are spaced apart and arranged on the N-type semiconductor layer; and / or; A gap is formed between one or more of the second N-type electrodes and the second P-type electrode, respectively, wherein a portion of the second N-type electrodes is located on the PN step.

9. The LED chip according to claim 1, wherein: The first insulating layer is silicon oxide and a DBR reflective layer.

10. The LED chip according to claim 9, characterized in that: The thickness of the first insulating layer is 2 μm to 7 μm.

11. The LED chip according to claim 9, wherein: The thickness of the first insulating layer is 3.5 μm to 5.5 μm.

12. The LED chip according to claim 4, characterized in that The second insulating layer and / or the third insulating layer includes at least one of silicon oxide, silicon nitride and silicon oxynitride.

13. The LED chip according to claim 12, wherein: The thickness of the second insulating layer and / or the third insulating layer is 1KÅ~20KÅ.

14. The method for preparing an LED chip according to any one of claims 1 to 13, wherein: The following steps are involved: (a) providing a substrate, and sequentially depositing an N-type semiconductor layer, a light-emitting layer, and a P-type semiconductor layer on the substrate to form an epitaxial layer; (b) depositing SiO2 on the epitaxial layer, and obtaining a current blocking layer by photolithography, and then depositing a current spreading layer, and obtaining a PN step by etching; (c) depositing a plurality of first P-type electrodes and a plurality of first N-type electrodes alternately on the chip surface, and then depositing a first insulating layer; (d) photolithographically forming a first through hole and a second through hole above the first P-type electrode and the first N-type electrode, respectively, and depositing a second P-type electrode at the first through hole and a second N-type electrode at the second through hole, wherein the second P-type electrode and the second N-type electrode are isolated from each other; (e) depositing a second insulating layer, and photolithographically forming a third through hole and a fourth through hole above the second P-type electrode and the second N-type electrode, respectively, and depositing a third P-type electrode at the third through hole and a third N-type electrode at the fourth through hole, wherein the third P-type electrode and the third N-type electrode are isolated from each other, and the second P-type electrode extends below the third N-type electrode; (f) depositing a third insulating layer, and photolithographically forming a fifth through hole and a sixth through hole above the third P-type electrode and the third N-type electrode, respectively, depositing a P-type pad at the fifth through hole and an N-type pad at the sixth through hole.

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