Clock synchronization system

Abstract

The present application relates to a clock synchronization system. The system includes: at least one first device, the first device is configured to perform clock synchronization through a global positioning system and a time synchronization protocol; at least one second device, the second device is configured to perform clock synchronization through a time synchronization protocol; at least one of the first devices and at least one of the second devices are sequentially connected through a network interface, the first device performs clock synchronization through the global positioning system, and the second device connected to the first device uses the clock synchronized by the first device as the main clock source; when at least one second device is connected to the second device, each of the second devices uses the clock synchronized by the previous second device as the main clock source for clock synchronization until the clock synchronization of all the second devices is completed. This system can realize a high-precision clock synchronization method for devices step by step.

Description

Technical Field

[0001] The present application relates to the technical field of power detection, and in particular to a clock synchronization system. Background Art

[0002] With the development of power detection technology, NTP Ethernet timing has emerged. The general NTP Ethernet timing method has only millisecond-level synchronization accuracy. However, in applications such as long-distance transmission line fault ranging and hidden danger location, the monitoring equipment deployed at the line terminal is required to have an accurate synchronous clock source. Therefore, the NTP Ethernet timing method is far from meeting the needs of precise positioning.

[0003] Based on this, GNSS synchronization clock source is generally used in places with good outdoor wireless communication, and PTP optical fiber synchronization clock source is generally used in places such as cable tunnels. However, due to the complexity of the laying environment of power transmission lines in various places, especially hybrid lines, the same type of clock source is difficult to apply. Therefore, it is of great significance to design a multi-source reliable high-precision synchronization method for these monitoring equipment and unify the clock source. Summary of the invention

[0004] Based on this, it is necessary to provide a clock synchronization system that can synchronize the clocks of different devices step by step to address the above technical problems.

[0005] A clock synchronization system, the clock synchronization system comprising:

[0006] at least one first device, the first device being configured to perform clock synchronization via a global positioning system and a time synchronization protocol;

[0007] at least one second device, the second device being configured to perform clock synchronization via a time synchronization protocol;

[0008] At least one of the first devices and at least one of the second devices are sequentially connected through a network interface, the first device performs clock synchronization through the global positioning system, and the first device uses the clock synchronized through the global positioning system as a master clock source of the second device connected to the first device later;

[0009] When at least one second device is connected to the second device, the second device connected to the first device synchronizes the clock of the next second device connected according to the master clock source, and uses the synchronized clock of the next second device as the master clock source to continue to synchronize the clocks of the second devices connected in sequence until the clock synchronization of all the second devices is completed.

[0010] In one embodiment, the first device is a device arranged above ground, and the second device is a device arranged underground.

[0011] In one embodiment, the first device includes a global positioning system and a first crystal oscillator, and the first device performs clock synchronization through a signal sent by the global positioning system and a signal output by the first crystal oscillator.

[0012] In one embodiment, the first device further includes a first clock synchronization module, a second clock synchronization module and at least one first slave clock source module; the input end of the first clock synchronization module is connected to the first output end of the global positioning system, and the output end is respectively connected to the first input end of at least one first slave clock source module, the input end of the second clock synchronization module is connected to the second output end of the global positioning system, and the output end is connected to the input end of the first crystal oscillator;

[0013] The first clock synchronization module is used to read and parse the global positioning system message, and send the parsed first message timestamp to at least one of the first slave clock source modules; the second clock synchronization module is used to correct the frequency error of the first crystal oscillator, and the first crystal oscillator is used to send the first relative timestamp to at least one of the first slave clock source modules after the frequency error is corrected by the second clock synchronization module.

[0014] In one embodiment, the first clock synchronization module includes a first interrupt unit and a first information processing unit; the input end of the first interrupt unit is connected to the first output end of the global positioning system, and the output end is connected to the input end of the first information processing unit, and the output end of the first information processing unit is respectively connected to the first input end of at least one of the first slave clock source modules;

[0015] The first interrupt unit is used to interrupt the pulse signal sent by the global positioning system, and the first information processing unit is used to read the message carried in the pulse signal, and after parsing the message to obtain a first message timestamp, latch the first message timestamp, and send the first message timestamp to at least one of the first slave clock source modules.

[0016] In one embodiment, the second clock synchronization module includes a first listening unit and a first data processing unit; the input end of the first listening unit is connected to the second output end of the global positioning system, the first output end is connected to the control end of the first interrupt unit, the second output end is connected to the input end of the first data processing unit, and the output end of the first data processing unit is connected to the input end of the first crystal oscillator;

[0017] The first monitoring unit is used to determine whether the global positioning system sends a pulse signal and control the first interrupt unit to implement an interrupt operation. The first data processing unit is used to calculate and correct the frequency error of the first crystal oscillator according to the pulse signal sent by the global positioning system.

[0018] In one embodiment, the second device includes a master clock source module, a second slave clock source module and a second crystal oscillator, and the second device performs clock synchronization through a signal sent after synchronization by the master clock source module and a signal output by the second crystal oscillator;

[0019] The master clock source module is used to receive a synchronization timestamp sent by the first device or the previous second device, and perform clock synchronization on the second slave clock source module according to the synchronization timestamp and a signal output by the second crystal oscillator.

[0020] In one embodiment, the second device further includes a third clock synchronization module and a fourth clock synchronization module; the input end of the third clock synchronization module is connected to the first output end of the master clock source module, and the output end is connected to the first input end of the second slave clock source module; the input end of the fourth clock synchronization module is connected to the second output end of the master clock source module, and the output end is connected to the input end of the second crystal oscillator;

[0021] The third clock synchronization module is used to read and latch the second message timestamp, and send the latched second message timestamp to the second slave clock source module; the fourth clock synchronization module is used to correct the frequency error of the second crystal oscillator, and the second crystal oscillator is used to send the second relative timestamp to the second slave clock source module after the frequency error is corrected by the second clock synchronization module;

[0022] The second slave clock source module is used to calculate a synchronization timestamp according to the second message timestamp and the second relative timestamp, and send the calculated synchronization timestamp to the next second device.

[0023] In one embodiment, the third clock synchronization module includes a second interrupt unit and a second information processing unit; the input end of the second interrupt unit is connected to the first output end of the second master-end clock source module, the output end is connected to the input of the second information processing unit, and the output end of the second information processing unit is connected to the first input end of the second slave-end clock source module;

[0024] The second interrupt unit is used to interrupt the pulse signal emitted by the second master-end clock source module, and the second information processing unit is used to read the message carried by the pulse signal emitted by the second master-end clock source, and parse the message to obtain the second message timestamp, latch the second message timestamp, and send the second message timestamp to the second slave-end clock source module.

[0025] In one embodiment, the fourth clock synchronization module includes a second listening unit and a second data processing unit; the input end of the second listening unit is connected to the second output end of the second master clock source module, the first output end is connected to the control end of the second interrupt unit, the second output end is connected to the input end of the second data processing unit, and the output end of the second data processing unit is connected to the input end of the second crystal oscillator;

[0026] The second listening unit is used to determine whether the second master-end clock source module sends a pulse signal and control the second interrupt unit to implement an interrupt operation. The second data processing unit is used to calculate and correct the frequency error of the second crystal oscillator according to the pulse signal sent by the second master-end clock source module.

[0027] The above-mentioned clock synchronization system is first synchronized by the first device through the global positioning system, and the synchronized clock is used as the main clock source of the second device; when the second device is subsequently connected to at least one second device, the current second device synchronizes the clock of the next second device according to the clock synchronized with the first device, and uses the synchronized clock of the next second device as the main clock source to continue to synchronize the clocks of the connected second devices in turn, thereby realizing the clock synchronization of the devices step by step. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 A schematic diagram of clock synchronization of different devices in one embodiment;

[0029] Figure 2 A schematic diagram of a hybrid transmission line according to an embodiment;

[0030] Figure 3 is a structural block diagram of a first device in an embodiment;

[0031] Figure 4 is a structural block diagram of a first device in another embodiment;

[0032] Figure 5 FIG. 4 is a structural block diagram of a second device in an embodiment. DETAILED DESCRIPTION

[0033] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0034] In one embodiment, if Figure 1 As shown, a clock synchronization system is provided, which includes: at least one first device 100 and at least one second device 200. Among them, at least one first device 100 and at least one second device 200 are connected in sequence through network interfaces. Preferably, the network interfaces are connected through optical fibers. One point to be explained is that, in combination with Figure 2 , wherein the order of the first device 100 and the second device 200 can be arbitrary, for example Figure 2 Two first devices 100 are on the ground, followed by multiple second devices 200 underground. Optionally, in other embodiments, only at least one first device 100 or at least one second device 200 may be included, or the first device 100 and the second device 200 may be mixed and connected, but the order and number of connections are not specifically limited.

[0035] The first device 100 is configured to perform clock synchronization through the global positioning system and the time synchronization protocol, and the second device 200 is configured to perform clock synchronization through the time synchronization protocol. The first device 100 performs clock synchronization through the global positioning system, and uses the clock of the first device 100 synchronized through the global positioning system as the master clock source of the second device 200 connected to the first device 100. When only one second device 200 is connected to the first device 100, the synchronization ends.

[0036] Alternatively, if Figure 1 As shown, when at least one second device 200 is connected to the second device 200, the second device 200 connected to the first device 100 uses the clock synchronized by the first device 100 through the global positioning system as the main clock source to perform clock synchronization on the next connected second device 200, and uses the synchronized clock of the next second device 200 as the main clock source to perform clock synchronization on the next connected second device 200 in turn until all the second devices complete clock synchronization.

[0037] Specifically, combined Figure 1The first device 100 performs clock synchronization through a global positioning system, such as GNSS, so that the crystal oscillator meets the requirements, and then sends the synchronized clock to the second device 200 connected to the first device 100. The second device 200 uses the received clock as the master clock for clock synchronization to obtain the synchronized clock of the second device 200, and the second device 200 uses the clock as the master clock of the next second device 200, that is, the second device 200 sends the clock to the next second device, and the next second device continues to repeat the above clock synchronization process until the clock synchronization of all second devices is completed. After the synchronization is completed, the clocks of all devices are the same as the clock of the first device 100.

[0038] It should be noted that both the first device 100 and the second device 200 are provided with a crystal oscillator, through which the clock is counted to correct the crystal oscillator error, thereby achieving clock synchronization. In order to ensure accuracy, preferably, the crystal oscillators in the first device 100 and the second device 200 can be the same.

[0039] Combination Figure 1 , the first device 100 selects GNSS as the main clock source, and uses its PPS second pulse signal and a 100MHz constant temperature crystal oscillator to achieve clock synchronization. The synchronized precise clock is used as the clock source of PTP (based on the time synchronization protocol). PTP is connected to the next second device 200 through an optical fiber via a network interface, and a master-slave relationship is established in accordance with the IEEE1588 protocol, thereby synchronizing the PTP slave clock (i.e., PTPS) of the second device 200. The synchronized PTPS clock of the second device 200 generates a precise PPS second pulse signal to synchronize its PTPM clock. Subsequent devices are synchronized in turn until the last second device 200. After successful synchronization, the clock source of all devices is the GNSS clock source of the first first device 100.

[0040] The above-mentioned clock synchronization system is first synchronized by the first device 100 through the global positioning system, and the synchronized clock is used as the main clock source of the second device 200; when the second device 200 is subsequently connected to at least one second device, the current second device 200 synchronizes the clock of the next second device 200 according to the clock synchronized with the first device 100, and uses the synchronized clock of the next second device 200 as the main clock source to continue to synchronize the clocks of the connected second devices 200 in turn, thereby realizing the clock synchronization of the devices step by step.

[0041] In one embodiment, if Figure 2 As shown, the first device is a device arranged above ground, and the second device is a device arranged underground.

[0042] The first device is arranged in an outdoor place with good wireless communication, and the second device is arranged in a cable tunnel or other places. The second device uses a time synchronization protocol clock source, and the first device uses a dual clock source of a global positioning system and a time synchronization protocol. The first device uses the global positioning system as the main clock source to synchronize the clock of the time synchronization protocol clock source, and then synchronizes to the underground device, i.e., the second device, through an optical fiber. Optionally, the first device and the second device are the same device, both of which can support the global positioning system and the time synchronization protocol clock source. During installation, the clock source of the configuration device can be selected as needed.

[0043] In the above embodiment, the first device and the second device are respectively deployed according to the communication conditions above ground and underground, and different devices use different clock sources so as to achieve better clock synchronization.

[0044] In one embodiment, the first device includes a global positioning system and a first crystal oscillator, and the first device performs clock synchronization through a signal sent by the global positioning system and a signal output by the first crystal oscillator.

[0045] Among them, the global positioning system is the main clock source of the first device, the global positioning system can send out a pulse signal, preferably the pulse signal is a second pulse signal, the first device can read the first message timestamp according to the message information carried by the pulse signal sent by the global positioning system; the first crystal oscillator can correct the frequency error according to the pulse signal sent by the global positioning system, the first crystal oscillator after correcting the frequency error outputs the first relative timestamp, and the first device performs clock synchronization according to the first message timestamp and the first relative timestamp. Preferably, the first crystal oscillator can be a 100MHz constant temperature crystal oscillator, and in other embodiments, the parameters of the crystal oscillator can be set as needed, and no specific limitation is made here.

[0046] In the above embodiment, clock synchronization of the first device is achieved based on the global positioning system and the timestamp output by the first crystal oscillator.

[0047] In one embodiment, in combination Figure 3As shown, the first device also includes a first clock synchronization module, a second clock synchronization module and at least one first slave-end clock source module; the input end of the first clock synchronization module is connected to the first output end of the global positioning system, and the output end is respectively connected to the first input end of the at least one first slave-end clock source module, the input end of the second clock synchronization module is connected to the second output end of the global positioning system, and the output end is connected to the input end of the first crystal oscillator; the first clock synchronization module is used to read and parse the global positioning system message, and send the parsed first message timestamp to at least one first slave-end clock source module; the second clock synchronization module is used to correct the frequency error of the first crystal oscillator, and the first crystal oscillator is used to send the first relative timestamp to at least one first slave-end clock source module after the second clock synchronization module corrects the frequency error.

[0048] The first clock synchronization module is used to latch the first message timestamp in seconds according to the signal output by the global positioning system. The second clock synchronization module is used to make the first crystal oscillator output the first relative timestamp in seconds according to the signal output by the global positioning system. The first slave clock source module is used to synchronize its own complete timestamp, that is, the signal latched in seconds by the global positioning system and the signal output in nanoseconds by the first crystal oscillator to the second device connected to the first device. The first slave clock source is within the first device. The global positioning system outputs the master clock source, so the clock source that is synchronized is the slave clock source.

[0049] Among them, the first clock synchronization module reads the message information carried in the pulse signal sent by the global positioning system through the first output end of the global positioning system, parses out the first message timestamp, and latches the first message timestamp and sends it to the first input end of at least one first slave clock source module; the second clock synchronization module triggers the pulse counting of the first crystal oscillator and corrects the frequency error of the first crystal oscillator after receiving two consecutive pulse signals sent by the global positioning system. After the first crystal oscillator corrects the frequency error through the second clock synchronization module, the first relative timestamp is sent to the second input end of at least one first slave clock source module. After the first and second input ends of at least one first slave clock source receive the first message timestamp and the first relative timestamp, the clock synchronization with the global positioning system is completed.

[0050] Preferably, the first clock synchronization module reads the global positioning system message information through the serial port and parses the first timestamp as a coordinated universal time (UTC) second-level timestamp, and the first relative timestamp sent by the first crystal oscillator after the frequency error is corrected by the second clock synchronization module is a nanosecond-level timestamp.

[0051] In the above embodiment, the first clock synchronization module and the second clock module of the first device respectively obtain the first message timestamp and the first relative timestamp through the pulse signal sent by the global positioning system, so that the first slave clock source module performs high-precision clock synchronization with the global positioning system through the first message timestamp and the first relative timestamp.

[0052] In one embodiment, in combination Figure 3 The first clock synchronization module includes a first interrupt unit and a first information processing unit; the input end of the first interrupt unit is connected to the first output end of the global positioning system, and the output end is connected to the input end of the first information processing unit, and the output ends of the first information processing unit are respectively connected to the first input end of at least one first slave clock source module; the first interrupt unit is used to interrupt the pulse signal sent by the global positioning system, and the first information processing unit is used to read the message carried in the pulse signal, and after parsing the message to obtain the first message timestamp, latch the first message timestamp, and send the first message timestamp to at least one first slave clock source module respectively.

[0053] The first interrupt unit generates an interrupt to the pulse signal sent by the global positioning system, and the first information processing unit immediately reads the message information carried in the pulse signal sent by the global positioning system through the serial port after the first interrupt unit generates an interrupt to the pulse signal sent by the global positioning system, and immediately latches the first message timestamp after parsing the message information to obtain the first message timestamp, and sends the latched first message timestamp to at least one first slave clock source module. Optionally, the specific Figure 4 As shown, if the first device includes two first slave clock source modules, then after obtaining the message timestamp, the first information processing unit sends the latched first message timestamp to the first input end of the first slave clock source module through the first and second output ends respectively.

[0054] In the above embodiment, after the first interrupt unit generates an interrupt, the first information processing unit promptly reads and parses the message information carried in the pulse signal sent by the global positioning system, and immediately latches the first message timestamp after obtaining the first message timestamp, and sends the latched first message timestamp to at least one first slave clock source module, thereby enabling the first device to achieve clock synchronization with at least one first slave clock source module.

[0055] In one embodiment, the second clock synchronization module includes a first listening unit and a first data processing unit; the input end of the first listening unit is connected to the second output end of the global positioning system, the first output end is connected to the control end of the first interrupt unit, the second output end is connected to the input end of the first data processing unit, and the output end of the first data processing unit is connected to the input end of the first crystal oscillator; the first listening unit is used to determine whether the global positioning system sends a pulse signal and control the first interrupt unit to implement an interrupt operation, and the first data processing unit is used to calculate and correct the frequency error of the first crystal oscillator according to the pulse signal sent by the global positioning system.

[0056] Among them, after receiving two consecutive pulse signals sent by the global positioning system, the first listening unit controls the first interrupt unit to generate an interrupt, and sends a pulse notification to the first data processing unit. After receiving the pulse notification sent by the first interrupt unit, the first data processing unit triggers the pulse counting of the first crystal oscillator, and after obtaining the frequency of the first crystal oscillator based on the pulse count, corrects the pulse error of the first crystal oscillator.

[0057] Among them, combined Figure 3 The first data processing unit includes a first pulse counting subunit and a first crystal oscillator correction subunit. The first input end of the first pulse counting subunit is connected to the output end of the first listening unit, the second input end is connected to the second output end of the first crystal oscillator, the output end is connected to the input end of the first crystal oscillator correction subunit, and the output end of the first crystal oscillator correction subunit is connected to the input end of the first crystal oscillator.

[0058] After receiving the pulse information sent by the first listening unit, the first pulse counting subunit counts the pulses of the first crystal oscillator and calculates the time error of the first crystal oscillator according to the pulse count between two consecutive pulse signals. The first pulse counting unit sends the calculated time error of the first crystal oscillator to the first crystal oscillator correction subunit. The first correction subunit calculates the frequency error of the first crystal oscillator according to the crystal oscillator error and corrects the frequency of the first crystal oscillator. After correcting the frequency error, the first crystal oscillator sends the first relative timestamp to the second input end of at least one first slave clock source.

[0059] In the above embodiment, the first listening unit and the first data processing unit correct the frequency error of the first crystal oscillator according to the pulse information sent by the global positioning system. After the first crystal oscillator corrects the frequency error, the first relative timestamp is sent to at least one first slave clock source module respectively, thereby enabling the first device to achieve clock synchronization with at least one first slave clock source module.

[0060] Specifically, in order to enable those skilled in the art to fully understand the operation of the first device, Figure 3 and Figure 4 It is introduced in detail as shown.

[0061] The global positioning system of the first device outputs a pulse signal and serial port information. By counting the pulses of the first crystal oscillator triggered by two consecutive pulse signals, the time error of the first crystal oscillator can be calculated, and then the frequency error of the first crystal oscillator can be calculated to correct the crystal oscillator frequency. At the same time, an interrupt is generated by the pulse, and the global positioning system message information is read in time through the serial port, and the first message timestamp is decoded and immediately latched. The first slave clock source module communicates with the slave device through the IEEE1588 protocol, and synchronizes its own complete timestamp information to the second device at a regular interval. Its complete timestamp information includes the first relative count timestamp output by the first crystal oscillator and the first message timestamp previously output and latched by the global positioning system.

[0062] Combination Figure 4 The first device has 1 global positioning system and 2 first slave clock source modules. The global positioning system is used as the master clock source to synchronize the first slave clock source module, and the first slave clock source module can be used as the master clock source to synchronize the clocks of the two second devices at the back end.

[0063] In one embodiment, the second device includes a master clock source module, a second slave clock source module and a second crystal oscillator, and the second device performs clock synchronization through a signal sent after synchronization with the master clock source module and a signal output by the second crystal oscillator; wherein the master clock source module is used to receive a synchronization timestamp sent by the first device or the previous second device, and perform clock synchronization on the second slave clock source module according to the synchronization timestamp and the signal output by the second crystal oscillator.

[0064] Among them, the master clock source module performs clock synchronization with the first device or the previous second device after receiving the synchronization timestamp sent by the first device or the previous second device, and serves as the master clock source of the second device after completing the clock synchronization with the first device. The second device can read the message timestamp according to the message information carried by the pulse signal sent by the master clock module; the second crystal oscillator can correct the frequency error according to the pulse signal sent by the master clock source, and the second crystal oscillator outputs the second relative timestamp after correcting the frequency error. The second slave clock source module performs clock synchronization with the master clock source according to the first message timestamp and the first relative timestamp. Preferably, the second crystal oscillator can be a 100MHz constant temperature crystal oscillator. In other embodiments, the parameters of the crystal oscillator can be set as needed, and no specific limitation is made here.

[0065] It should be noted that the master clock source module and the second slave clock source module in the second device are relative. When the second device is clock synchronized with the first device, the master clock source module serves as the master clock source of the second device, and the synchronized device is the slave clock source. If there is at least one second device connected to the current second device, the second slave clock source module of the current second device serves as the master clock source of the next second device for clock synchronization.

[0066] In the above embodiment, the first message timestamp and the first relative timestamp are obtained according to the pulse signal output by the main clock source module that completes clock synchronization with the first device or the previous second device, thereby performing high-precision clock synchronization with the second device.

[0067] In one embodiment, in combination Figure 5 As shown, the second device also includes a third clock synchronization module and a fourth clock synchronization module; the input end of the third clock synchronization module is connected to the first output end of the master clock source module, and the output end is connected to the first input end of the second slave clock source module, the input end of the fourth clock synchronization module is connected to the second output end of the master clock source module, and the output end is connected to the input end of the second crystal oscillator; the third clock synchronization module is used to read and latch the second message timestamp, and send the latched second message timestamp to the second slave clock source module; the fourth clock synchronization module is used to correct the frequency error of the second crystal oscillator, and the second crystal oscillator is used to send the second relative timestamp to the second slave clock source module after the frequency error is corrected by the second clock synchronization module; wherein the second slave clock source module is used to calculate the synchronization timestamp based on the second message timestamp and the second relative timestamp, and send the calculated synchronization timestamp to the next second device.

[0068] The third clock synchronization module is used to latch the second message timestamp according to the signal output by the main clock source module. The fourth clock synchronization module is used to make the second crystal oscillator output the second relative timestamp according to the signal output by the main clock source module. The second slave clock source module is used to synchronize its own complete timestamp, i.e. the latched second message timestamp and the second relative timestamp to the next second device. The second slave clock source is in the second device. The main clock source module after synchronization with the first device or the previous second device outputs the master clock source. The clock source that is domesticated and synchronized is the slave clock source.

[0069] Among them, the third clock synchronization module reads the second message timestamp in the message information carried in the pulse signal emitted by the master-end clock source module through the first output end of the master-end clock source module, and sends the second message timestamp to the first input end of the second slave-end clock source after latching the second message timestamp; the fourth clock synchronization module triggers the pulse counting of the second crystal oscillator and corrects the frequency error of the second crystal oscillator after receiving two consecutive pulse signals emitted by the master-end clock source; the second crystal oscillator error is corrected for the frequency error by the fourth clock synchronization module and the second relative timestamp is sent to the second input end of the second slave-end clock source; the second slave-end clock source completes clock synchronization with the master clock source module after receiving the second message timestamp and the second relative timestamp.

[0070] Preferably, the first clock synchronization module reads the global positioning system message information through the serial port and parses the first timestamp as a UTC second timestamp, and the first relative timestamp sent by the first crystal oscillator after the frequency error is corrected by the second clock synchronization module is a nanosecond timestamp.

[0071] In the above embodiment, after the master clock source module first sends a pulse signal, the second message timestamp and the second relative timestamp are obtained through the third clock synchronization module and the fourth clock module, so that the second slave clock source module completes the clock synchronization with the master clock source module through the second message timestamp and the second relative timestamp.

[0072] In one embodiment, if Figure 5 As shown, the third clock synchronization module includes a second interrupt unit and a second information processing unit; the input end of the second interrupt unit is connected to the first output end of the second master-end clock source module, the output end is connected to the input of the second information processing unit, and the output end of the second information processing unit is connected to the first input end of the second slave-end clock source module; the second interrupt unit is used to interrupt the pulse signal emitted by the second master-end clock source module, and the second information processing unit is used to read the message carried by the pulse signal emitted by the second master-end clock source, and after parsing the message to obtain the second message timestamp, latch the second message timestamp, and send the second message timestamp to the second slave-end clock source module.

[0073] Among them, the second interrupt unit interrupts the pulse signal sent by the main clock source module, and the second information processing unit immediately reads the message information carried in the pulse signal sent by the main clock source module through the serial port after the second interrupt unit interrupts the pulse signal sent by the main clock source module, and parses the message to obtain the second message timestamp, then immediately latches the second message timestamp, and sends the latched second message timestamp to the first input end of the second slave clock source module.

[0074] In the above embodiment, after the second interrupt unit generates an interrupt, the second information processing unit promptly reads and parses the message information carried in the main clock source module, and sends the parsed second message timestamp to the second slave clock source module, thereby enabling the second slave clock source module to achieve clock synchronization with the main clock source module.

[0075] In one embodiment, the fourth clock synchronization module includes a second listening unit and a second data processing unit; the input end of the second listening unit is connected to the second output end of the second master-end clock source module, the first output end is connected to the control end of the second interrupt unit, the second output end is connected to the input end of the second data processing unit, and the output end of the second data processing unit is connected to the input end of the second crystal oscillator; the second listening unit is used to determine whether the second master-end clock source module sends a pulse signal and control the second interrupt unit to implement an interrupt operation, and the second data processing unit is used to calculate and correct the frequency error of the second crystal oscillator according to the pulse signal sent by the second master-end clock source module.

[0076] Among them, combined Figure 4 After receiving two consecutive pulse signals from the main clock source module, the second listening unit controls the second interrupt unit to generate an interrupt and sends a pulse notification to the second data processing unit. After receiving the pulse notification sent by the second interrupt unit, the second data processing unit triggers the pulse counting of the second crystal oscillator, and after obtaining the frequency of the second crystal oscillator based on the pulse count, corrects the pulse error of the second crystal oscillator.

[0077] The first data processing unit includes a second pulse counting subunit and a second crystal oscillator correction subunit. The first input end of the second pulse counting subunit is connected to the output end of the second listening unit, the second input end is connected to the second output end of the second crystal oscillator, the output end is connected to the input end of the second crystal oscillator correction subunit, and the output end of the second crystal oscillator correction subunit is connected to the input end of the second crystal oscillator.

[0078] Among them, after receiving the pulse information sent by the second listening unit, the second pulse counting subunit counts the pulses of the second crystal oscillator and calculates the time error of the second crystal oscillator according to the pulse count between two consecutive pulse signals. The second pulse counting unit sends the calculated time error of the second crystal oscillator to the second crystal oscillator correction subunit. The second correction subunit calculates the frequency error of the second crystal oscillator according to the time error of the second crystal oscillator and corrects the frequency of the second crystal oscillator. After correcting the frequency error, the second crystal oscillator sends the second relative timestamp to the second input end of the second slave clock source module.

[0079] In the above embodiment, the second listening unit and the second data processing unit correct the frequency error of the second crystal oscillator according to the pulse information sent by the global positioning system. After the second crystal oscillator corrects the frequency error, the second relative timestamp is sent to the second slave clock source module respectively, thereby enabling the second slave clock source module to achieve clock synchronization with the master clock source module.

[0080] Specifically, in order to enable those skilled in the art to fully understand the operation of the second device, Figure 5 It is introduced in detail as shown.

[0081] The second device has two PTP clock sources, which are the slave PTPS, i.e., the master clock source module of the second device, and the master PTPM, i.e., the second slave clock source module of the second device, which correspond to the two PTP optical fiber links before and after, and both support the IEEE1588 protocol. PTPS receives the synchronization timestamp of the first device or the previous second device, and PTPM sends its own synchronization timestamp to the next second device. After PTPS performs clock synchronization with the first device or the previous second device, PTPS, as the master clock source of the second device, performs clock synchronization on PTPM. In order to maintain a unified clock, the pulse signal generated by PTPS is used as the synchronization clock source of the second crystal oscillator. After two consecutive pulse signals trigger the pulse count of the second crystal oscillator, the frequency error of the second crystal oscillator is obtained and corrected. After the frequency error is corrected, the second crystal oscillator sends the second relative timestamp to PTPM. At the same time, the pulse signal of PTPS generates an interrupt, and its second-level first message timestamp is read and latched by the third clock synchronization module. The first message timestamp and the second relative timestamp form the complete timestamp of PTPM, which is synchronously output to the next second device.

[0082] In one embodiment, the clock synchronization system may include the following steps:

[0083] like Figure 1 As described above, if only one first device and two second devices are connected in sequence through network interfaces, for the convenience of introduction, the two second devices are respectively referred to as second device 1 and second device 2.

[0084] First, the global positioning system in the first device sends a pulse signal. After receiving two consecutive pulse signals sent by the global positioning system, the first listening unit controls the first interrupt unit to interrupt the pulse signal and sends the pulse notification to the first pulse counting unit. After the first interrupt unit generates an interrupt, the first information processing unit immediately reads the message information carried in the pulse signal sent by the global positioning system through the serial port, and after parsing the message information to obtain the first message timestamp, immediately latches the first message timestamp and sends the latched first message timestamp to the first input end of the first slave clock source module; after receiving the pulse information sent by the first listening unit, the first pulse counting unit counts the pulses of the first crystal oscillator, and calculates the time error of the first crystal oscillator according to the pulse count between two consecutive pulse signals. The first pulse counting unit sends the calculated first crystal oscillator time error to the first crystal oscillator correction subunit. The first correction subunit calculates the frequency error of the first crystal oscillator according to the crystal oscillator error and corrects the frequency of the first crystal oscillator. After correcting the frequency error, the first crystal oscillator sends the first relative timestamp to the second input end of the first slave clock source module. The first slave clock source module performs clock synchronization with the global positioning system after receiving the first message timestamp and the first relative timestamp, and sends the calculated synchronization timestamp to the second device 1. The master clock source module 1 of the second device 1 performs clock synchronization with the first device after receiving the synchronization timestamp sent by the first device, and serves as the master clock source of the second device 1 after completing the clock synchronization with the first device. After receiving the pulse signal sent by the master clock source module 1 twice in a row, the second listening unit 1 in the second device 1 controls the second interrupt unit 1 to generate an interrupt, and sends a pulse notification to the second data processing unit 1. After the second interrupt unit 1 generates an interrupt, the second information processing unit 1 immediately reads the message information carried in the pulse signal sent by the main clock source module through the serial port, and after parsing the message to obtain the second message timestamp 1, it immediately latches the second message timestamp 1 and sends the latched second message timestamp 1 to the first input end of the second slave clock source module 1; the second pulse counting subunit 1 counts the pulses of the second crystal oscillator 1 after receiving the pulse information sent by the second listening unit 1, and calculates the time error of the second crystal oscillator 1 according to the pulse count between two consecutive pulse signals, and the second pulse counting unit 1 calculates the second crystal oscillator 1. The time error of the two crystal oscillators is sent to the second crystal oscillator correction subunit 1. The second correction subunit 1 calculates the frequency error of the second crystal oscillator 1 according to the time error of the second crystal oscillator 1, and corrects the frequency of the second crystal oscillator 1. After correcting the frequency error, the second crystal oscillator 1 sends the second relative timestamp 1 to the second input end of the second slave clock source module 1. After receiving the second message timestamp 1 and the second relative timestamp 1, the second slave clock source module 1 performs clock synchronization with the main clock source module 1. After the second slave clock source module 1 completes the clock synchronization with the main clock source module 1, the synchronization timestamp is calculated and sent to the second device 2.After receiving the synchronization timestamp sent by the second device 1, the master clock source module of the second device 2 completes clock synchronization with the second device 1 and serves as the master clock source of the second device 2. The second listening unit 2 in the second device 2 sends a pulse notification to the second data processing unit 2 after receiving two consecutive pulse signals sent by the master clock source module 1. After receiving the pulse information sent by the second listening unit 2, the second pulse counting subunit 2 counts the pulses of the second crystal oscillator 2 and calculates the time error of the second crystal oscillator 2 according to the pulse count between two consecutive pulse signals. The second pulse counting unit 2 sends the calculated second crystal oscillator time error to the second crystal oscillator correction subunit 2. The second correction subunit 2 calculates the frequency error of the second crystal oscillator 2 according to the time error of the second crystal oscillator 2 and corrects the frequency of the second crystal oscillator 2. At this time, the first device, the second device 1 and the second device 2 complete clock synchronization.

[0085] The first message timestamp and the second message timestamp 1 are both UTC second-level timestamps, and the first relative timestamp and the second relative timestamp 2 are both nanosecond-level relative timestamps.

[0086] Among them, the clock synchronization between devices establishes a master-slave relationship through the IEEE1588 protocol. The master and slave devices regularly send and receive 1588 protocol messages to keep the hardware clock synchronized at all times. When the message enters and exits the physical layer, it will automatically add a nanosecond-level accurate timestamp. The slave compares the timestamp in the master's message with its own clock and corrects the clock according to the difference, thereby achieving accurate synchronization of the master and slave time.

[0087] In the above embodiment, the first device is first synchronized through the global positioning system, and the synchronized clock is used as the master clock source of the second device 1. The second device 1 synchronizes the clock of the second device 2 according to the master clock source, so that all devices in the same network system have a precise and unique clock source.

[0088] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0089] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A clock synchronization system, characterized in that: The clock synchronization system comprises: at least one first device, the first device being configured to perform clock synchronization via a global positioning system and a time synchronization protocol; at least one second device, the second device being configured to perform clock synchronization via a time synchronization protocol; At least one of the first devices and at least one of the second devices are sequentially connected through a network interface, the first device performs clock synchronization through the global positioning system, and the first device uses the clock synchronized through the global positioning system as a master clock source of the second device connected to the first device later; When at least one second device is connected to the second device, the second device connected to the first device performs clock synchronization on the clock of the next second device connected according to the master clock source, and uses the synchronized clock of the next second device as the master clock source to continue to perform clock synchronization on the second devices connected in sequence until the clock synchronization of all the second devices is completed; the first device includes a global positioning system and a first crystal oscillator, and the first device performs clock synchronization through a signal sent by the global positioning system and a signal output by the first crystal oscillator; The first device further includes a first clock synchronization module, a second clock synchronization module and at least one first slave clock source module; the input end of the first clock synchronization module is connected to the first output end of the global positioning system, and the output end is respectively connected to the first input end of at least one first slave clock source module, the input end of the second clock synchronization module is connected to the second output end of the global positioning system, and the output end is connected to the input end of the first crystal oscillator; The first clock synchronization module is used to read and parse the global positioning system message, and send the parsed first message timestamp to at least one of the first slave clock source modules; the second clock synchronization module is used to correct the frequency error of the first crystal oscillator, and the first crystal oscillator is used to send the first relative timestamp to at least one of the first slave clock source modules after the frequency error is corrected by the second clock synchronization module.

2. The clock synchronization system according to claim 1, characterized in that: The first device is a device arranged above ground, and the second device is a device arranged underground.

3. The clock synchronization system according to claim 1, characterized in that: The first clock synchronization module includes a first interrupt unit and a first information processing unit; the input end of the first interrupt unit is connected to the first output end of the global positioning system, and the output end is connected to the input end of the first information processing unit, and the output end of the first information processing unit is respectively connected to the first input end of at least one of the first slave clock source modules; The first interrupt unit is used to interrupt the pulse signal sent by the global positioning system, and the first information processing unit is used to read the message carried in the pulse signal, and after parsing the message to obtain a first message timestamp, latch the first message timestamp, and send the first message timestamp to at least one of the first slave clock source modules.

4. The clock synchronization system according to claim 3, characterized in that: The second clock synchronization module includes a first listening unit and a first data processing unit; the input end of the first listening unit is connected to the second output end of the global positioning system, the first output end is connected to the control end of the first interrupt unit, the second output end is connected to the input end of the first data processing unit, and the output end of the first data processing unit is connected to the input end of the first crystal oscillator; The first monitoring unit is used to determine whether the global positioning system sends a pulse signal and control the first interrupt unit to implement an interrupt operation. The first data processing unit is used to calculate and correct the frequency error of the first crystal oscillator according to the pulse signal sent by the global positioning system.

5. The clock synchronization system according to claim 1, characterized in that: The second device comprises a master clock source module, a second slave clock source module and a second crystal oscillator, and the second device performs clock synchronization through a signal sent after synchronization by the master clock source module and a signal output by the second crystal oscillator; The master clock source module is used to receive a synchronization timestamp sent by the first device or the previous second device, and perform clock synchronization on the second slave clock source module according to the synchronization timestamp and a signal output by the second crystal oscillator.

6. The clock synchronization system according to claim 5, characterized in that: The second device also includes a third clock synchronization module and a fourth clock synchronization module; The input end of the third clock synchronization module is connected to the first output end of the master clock source module, and the output end is connected to the first input end of the second slave clock source module; the input end of the fourth clock synchronization module is connected to the second output end of the master clock source module, and the output end is connected to the input end of the second crystal oscillator; The third clock synchronization module is used for reading and latching the second message timestamp, and sending the latched second message timestamp to the second slave clock source module; The fourth clock synchronization module is used to correct the frequency error of the second crystal oscillator, and the second crystal oscillator is used to send the second relative timestamp to the second slave clock source module after the second clock synchronization module corrects the frequency error; The second slave clock source module is used to calculate a synchronization timestamp according to the second message timestamp and the second relative timestamp, and send the calculated synchronization timestamp to the next second device.

7. The clock synchronization system according to claim 6, characterized in that: The third clock synchronization module includes a second interrupt unit and a second information processing unit; the input end of the second interrupt unit is connected to the first output end of the second slave clock source module, the output end is connected to the input of the second information processing unit, and the output end of the second information processing unit is connected to the first input end of the second slave clock source module; The second interrupt unit is used to interrupt the pulse signal emitted by the second master-end clock source module, and the second information processing unit is used to read the message carried by the pulse signal emitted by the second master-end clock source, and parse the message to obtain the second message timestamp, latch the second message timestamp, and send the second message timestamp to the second slave-end clock source module.

8. The clock synchronization system according to claim 7, characterized in that: The fourth clock synchronization module includes a second listening unit and a second data processing unit; the input end of the second listening unit is connected to the second output end of the second slave clock source module, the first output end is connected to the control end of the second interrupt unit, the second output end is connected to the input end of the second data processing unit, and the output end of the second data processing unit is connected to the input end of the second crystal oscillator; The second listening unit is used to determine whether the second slave clock source module sends a pulse signal and control the second interrupt unit to implement an interrupt operation. The second data processing unit is used to calculate and correct the frequency error of the second crystal oscillator according to the pulse signal sent by the second slave clock source module.

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