Method, apparatus, and readable storage medium for deriving an address based on a control flow graph

Abstract

The present disclosure relates to a method, an apparatus, and a readable storage medium for deriving an address in a control flow graph. The computing device of the present disclosure is included in an integrated circuit device, which includes a general-purpose interconnect interface and other processing devices. The computing device interacts with the other processing devices to jointly complete a computing operation specified by a user. The integrated circuit device may further include a storage device, which is respectively connected to the computing device and the other processing devices and is used for data storage of the computing device and the other processing devices.

Description

Technical Field

[0001] The present disclosure generally relates to the field of computers. More specifically, the present disclosure relates to a method, an apparatus, and a readable storage medium for deriving an address based on a control flow graph. Background Art

[0002] Traditional general-purpose processors have a mechanism for automatically managing storage. For accessing data, simply using load or store instructions can load the data from a register into an on-chip register for processing, and the result after processing is then stored back into memory through the register to achieve an accelerated execution speed for data processing of off-chip memory.

[0003] However, for special-purpose chips such as those for artificial intelligence, due to considerations of performance, area, power consumption, etc., an automatic storage management mechanism is not adopted. Instead, the on-chip space is explicitly managed by instructions. When accessing data, it is often necessary to set the address space operated by the memory access instruction in an additional field or parameter, which increases the programming difficulty. Therefore, a more effective address derivation scheme is urgently needed. Summary of the Invention

[0004] To at least partially solve the technical problems mentioned in the background art, the solution of the present disclosure provides a method, an apparatus, and a readable storage medium for deriving a pointer address based on a control flow graph.

[0005] In one aspect, the present disclosure discloses a method for deriving an address based on a control flow graph, where the control flow graph includes a plurality of basic blocks, the plurality of basic blocks include at least one instruction, and the pointer included in the instruction carries an address. The method includes: traversing the plurality of basic blocks to obtain all possible address spaces of the pointer; determining whether all possible address spaces are deduced to a single address space; if so, setting the pointer to access the address space.

[0006] In another aspect, the present disclosure discloses a computer-readable storage medium having stored thereon computer program code for accessing using a general address in a system. When the computer program code is run by a processor, the foregoing method is executed.

[0007] In another aspect, the present disclosure discloses a computing device including a processor core that executes the foregoing method.

[0008] The solution of the present disclosure is directed to special-purpose processors such as those for artificial intelligence, simplifies their hardware complexity, facilitates programming, and further ensures the performance of the program with the help of pointer derivation. Brief Description of the Drawings

[0009] By reading the following detailed description with reference to the accompanying drawings, the above and other objects, features, and advantages of the exemplary embodiments of the present disclosure will become readily understood. In the drawings, several embodiments of the present disclosure are shown by way of example and not limitation, and like or corresponding reference numerals denote like or corresponding parts, wherein:

[0010] Figure 1 is a flowchart showing an embodiment of the present disclosure;

[0011] Figure 2 is a control flow diagram showing an example of an embodiment of the present disclosure;

[0012] Figure 3 is a control flow diagram showing another example of an embodiment of the present disclosure;

[0013] Figure 4 is a flowchart showing another embodiment of the present disclosure;

[0014] Figure 5 is a control flow diagram showing another example of an embodiment of the present disclosure;

[0015] Figure 6 is a flowchart showing another embodiment of the present disclosure;

[0016] Figure 7 is a flowchart showing another embodiment of the present disclosure;

[0017] Figure 8 is a flowchart showing another embodiment of the present disclosure;

[0018] Figure 9 is a schematic diagram of a computing device showing another embodiment of the present disclosure;

[0019] Figure 10 is a structural diagram of an integrated circuit device showing another embodiment of the present disclosure; and

[0020] Figure 11 is a structural diagram of a board showing another embodiment of the present disclosure. Detailed Description of Specific Embodiments

[0021] Next, the technical solutions in the embodiments of the present disclosure will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of the present disclosure without creative efforts fall within the scope of protection of the present disclosure.

[0022] It should be understood that the terms "first", "second", "third", "fourth", etc. in the claims, the specification and the drawings of the present disclosure are used to distinguish different objects, rather than to describe a specific order. The terms "comprising" and "including" used in the specification and claims of the present disclosure indicate the presence of the described features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or their combinations.

[0023] It should also be understood that the terms used in the specification of the present disclosure are merely for the purpose of describing specific embodiments and are not intended to limit the present disclosure. As used in the specification and claims of the present disclosure, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include the plural forms. It should be further understood that the term "and / or" used in the specification and claims of the present disclosure refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0024] As used in the present specification and claims, the term "if" may be interpreted as "when", "once", "in response to determining", or "in response to detecting" depending on the context.

[0025] The specific embodiments of the present disclosure will be described in detail below with reference to the drawings.

[0026] In order for a computer to perform a specific operation, a programmer must input the ideas, methods and means for solving the problem to be solved into the computer in a form that the computer can understand, so that the computer can execute in sequence according to the instructions. This channel of communication between humans and computers is called programming. Programming languages are divided into three categories: machine language, high-level language and assembly language.

[0027] Machine language is an operation code that a machine can directly recognize. Each operation code has a corresponding circuit inside the computer to complete it. Generally, a series of 0 and 1 instructions are used to directly control the potentials of the computer components to complete the expected tasks. Programs written in machine language, since each instruction corresponds to a specific basic action of the computer, occupy less memory and have high execution efficiency. However, the disadvantages are that the programming workload is large, it is error-prone, difficult to interpret, and dependent on the specific computer structure. Therefore, the generality and portability of the program are not good.

[0028] High-level languages have nothing to do with the hardware structure and instruction system of computers. They are based on human logic and grammar, so they have stronger expressive power, are convenient for expressing data operations and program control structures, can intuitively describe various algorithms, and are easy to learn and master. Currently popular programming languages such as java, c++, python, etc. are all high-level languages. Since high-level languages are programmed from a human perspective, they are relatively indirect to computers, so the opcodes generated after compilation are often longer than machine language program codes and are executed more slowly. Not only that, high-level languages "cannot see" the hardware structure of computers, so they cannot directly control system software that accesses hardware resources. For this reason, some high-level languages use assembly language as an external process or function of the high-level language.

[0029] Assembly language is between machine language and high-level language. Compared with machine language, it is easier for programmers to understand and program. Compared with high-level language, it has more direct machine relevance and achieves high speed and efficiency. Today, when high-level languages are highly developed, assembly language is usually used at the bottom level for program optimization or hardware operation.

[0030] Codes written in high-level languages and assembly languages need to be converted into machine codes by a compiler to drive the computer.

[0031] When running, artificial intelligence chips need to access a large amount of memory and move data between memories to perform computing tasks. For example, after image or voice information is converted into a matrix, the matrix data will be copied from the off-chip memory to the on-chip memory for calculation.

[0032] The present disclosure is aimed at application-specific integrated circuits (ASICs), especially artificial intelligence chips. During the code writing stage, no additional fields or parameters are required to define the access address space. Memory addresses can be derived during compilation and access to universal addresses can be achieved, so as to achieve the purpose of streamlining computing resources and shortening computing time.

[0033] One embodiment of the present disclosure is a method for deriving addresses based on a control flow graph, and more specifically, a method for deriving pointers based on a control flow graph is implemented through a fixed point algorithm. A control flow graph (CFG) is an abstract data structure used in a compiler, representing all possible execution paths of a program, and reflecting the possible flow of all basic blocks in a process in the form of a flow chart.

[0034] A control flow graph is composed of nodes and the relationships between nodes. A node, also known as a basic block (BB), is a sequence of statements that are executed sequentially to the maximum extent in a program. Each basic block has only one entry and one exit. When executed, it enters from its entry and exits from its exit. The characteristic of a basic block is that as long as the first instruction is executed, all instructions within the basic block will be executed in sequence.

[0035] Each basic block contains at least one instruction. The instructions in a basic block may use a pointer to point to a specific register or memory. A pointer is a variable used to store the address of a specific address space. Through a pointer, a programmer can load data into the space at the specific address pointed to by the pointer, or retrieve data from the specific address pointed to by the pointer.

[0036] Predicate, jump, loop and other conditional situations often occur in a control flow graph. A predicate refers to a delegate that includes a method function for judging whether a condition is met. A jump means that through a judgment instruction, the process branches. When the condition is met, one type of instruction is executed, and when the condition is not met, another type of instruction is executed. A loop is to continuously execute the same instruction under certain condition restrictions until the condition is satisfied and then stop.

[0037] When there are multiple memories in the system and the control flow graph contains conditional instructions including but not limited to the foregoing, memory access will be uncertain unless specific situations and conditions are considered for comparison. When it is not possible to determine which memory a pointer corresponds to, generally the pointer is set to access a general address. The compiler of this embodiment makes the address space accessed by the pointer originally set to a general address explicit through the derivation of the address space pointed to by the pointer. Once it is determined at compile time, unnecessary execution steps can be reduced to optimize the performance of the program.

[0038] Figure 1 is a flowchart showing this embodiment.

[0039] In step 101, the compiler traverses multiple basic blocks to obtain all possible address spaces of the pointer. In this embodiment, all basic blocks in the control flow graph are traversed to respectively obtain the address spaces pointed to by the pointers used in the instructions in each basic block. For the same pointer, all its possible address spaces are obtained.

[0040] When traversing, the order of the data flow can adopt the reverse postorder method. Taking the reverse postorder as an example, it is obtained by first traversing in the postorder manner and then inverting the result. The reverse postorder can converge earlier. The traversal order is not limited in this embodiment, but preferably the reverse postorder traversal is adopted.

[0041] In step 102, the compiler determines whether all these possible address spaces are deduced to a single address space. The compiler obtains the pointer variables of the pointer in the basic block. This step is to determine whether these pointers can be deduced to a single address space after going through the process of the control flow graph.

[0042] Optionally, the compiler can sequentially obtain all possible address spaces of the pointers used in the instructions of all the predecessor basic blocks of each basic block according to the control flow graph, and determine whether all possible address spaces of the pointers used in the instructions of these predecessor basic blocks can be deduced to a single address space. Among them, in the control flow graph, when a basic block is executed before another basic block, then this basic block can be considered as the predecessor basic block of the other basic block. For example, Figure 2 both the third basic block and the fourth basic block in

[0043] are the predecessor basic blocks of the fifth basic block. It should be noted that although some variables may seem different on the surface, these variables may be aliases, that is, different variables but accessing the same address space. Before making a judgment in this step, the compiler can perform alias analysis to find out the address variables with aliases to determine whether the address pointed to by the pointer is unique. If the compiler does not have the function of alias analysis, this embodiment can simulate the process of alias analysis and make a judgment based on the variable information pointed to by the pointer recorded in the intermediate representation (IR) of each instruction.

[0044] If it is deduced to a single address space, then step 103 is executed, and the compiler sets this pointer to access the address space.

[0045] However, if it is not deduced to a single address space, then step 104 is executed, and the compiler sets the pointer to access a general address. Not being deduced to a single address space means that there may be multiple possibilities for this pointer in the control flow graph and it will access different address spaces under different conditions, so it remains to access a general address.

[0046] Repeat the above steps 101 to 104 until the address spaces accessed by each pointer remain unchanged, and record the finally pointed address spaces of each pointer. After executing the foregoing steps, the compiler can set and generate a memory access instruction according to the finally pointed address space of the pointer, so as to implement access operations for various data such as images, voices, or texts according to the memory access instruction.

[0047] Figure 2It is an example showing a control flow graph for illustrating the flowchart of this embodiment. This control flow graph 200 includes five basic blocks, namely the first basic block 201, the second basic block 202, the third basic block 203, the fourth basic block 204, and the fifth basic block 205. The first basic block 201 is the entrance of this control flow graph 200. The exit of the first basic block 201 is connected to the entrance of the second basic block 202. The exit of the second basic block 202 is simultaneously connected to the entrances of the third basic block 203 and the fourth basic block 204, which means there is a judgment in the exit of the second basic block 202, such as a jump. If a specific condition is met, it jumps to the third basic block 203; if the specific condition is not met, it jumps to the fourth basic block 204. The exits of the third basic block 203 and the fourth basic block 204 are both connected to the entrance of the fifth basic block 205. The exit of the fifth basic block 205 is the exit of the entire control flow graph 200 and is also connected back to the entrance of the second basic block 202.

[0048] In step 101, the compiler traverses all the basic blocks of the control flow graph 200 to obtain all possible address spaces of the pointers in each basic block. For the convenience of illustration, only one pointer p in the control flow graph 200 is taken as an example here. After traversing all the basic blocks in the control flow graph 200, for the pointer p, all its possible address spaces are obtained as follows: In the first basic block 201, the pointer p is not clearly pointed to, so it is a general address access; in the second basic block 202 and the third basic block 203, a is assigned to the pointer p; in the fourth basic block 204, b is assigned to the pointer p; in the fifth basic block 205, the variable c is the value taken out from the address pointed to by the pointer p. Generally speaking, the pointer p may be the variable a or b, which directly affects the value of the variable c.

[0049] In step 102, the compiler can sequentially judge according to the control flow graph whether all possible address spaces of the pointers in all the predecessor basic blocks of each basic block are deduced to a single address space. In one case, if the address spaces corresponding to the variable a and the variable b are the same, for example, both are in the on-chip memory, then step 103 is executed. The compiler sets the pointer p to access a specific address space, that is, the on-chip memory. At the exit of the fifth basic block 205, the pointer p points to the on-chip memory. Such a setting follows the loop of the control flow graph 200 back to the entrance of the second basic block 202. At this time, the pointer p is updated to access the on-chip memory, and then continue to execute according to the Figure 1 process of the control flow graph 200 for iteration until the address space pointed to by the pointer p no longer changes.

[0050] When the address space pointed to by the pointer p no longer changes, the compiler can generate a memory access instruction according to the address space pointed to by the pointer, so as to implement access operations of various data such as images, voices, or texts according to the memory access instruction.

[0051] In another case, if the address spaces corresponding to variable a and variable b are different, for example, variable a is stored in on-chip memory while variable b is stored in off-chip memory and they do not correspond to the same address space, then step 104 is executed, and the compiler sets pointer p for general address access. At the exit of the fifth basic block 205, that is, after the confluence of the multiple basic blocks, pointer p is updated to general address access. Such a setting follows the loop of the control flow graph 200 back to the entry of the second basic block 202 and continues to iterate until the address space accessed by pointer p no longer changes.

[0052] Figure 3 FIG. 3 is another example showing a control flow graph, also used to illustrate the flowchart of this embodiment. This control flow graph 300 also includes five basic blocks, and the connection relationships of these basic blocks are the same as those of the control flow graph 200. The difference lies in the instructions related to pointer p in each basic block.

[0053] In step 101, the compiler traverses all the basic blocks of the control flow graph 300 to obtain all possible address spaces of the pointers in each basic block. For pointer p, after traversing all the basic blocks in the control flow graph 300, all its possible pointers are obtained as follows: In the first basic block 301, variable a is assigned to pointer p; in the second basic block 302, variable c is the value taken from the address pointed to by pointer p, and the address is the value of variable a; in the fourth basic block 304, the pointer of p has an offset of b.

[0054] In step 102, the compiler can sequentially determine according to the control flow graph whether all possible address spaces of the pointers in all the predecessor basic blocks of each basic block are deduced to a single address space. In this example, pointer p points to the address space storing variable a, for example, all in on-chip memory. Although in the fourth basic block 304, the specific address has an offset of b, it is still in the same address space. Therefore, all possible address deductions of the pointer in the predecessor basic block of the fifth basic block are deduced to a single address space, that is, on-chip memory, then step 103 is executed, and the compiler sets pointer p to access on-chip memory. At the exit of the fifth basic block 305, pointer p is updated to point to on-chip memory. Such a setting follows the loop of the control flow graph 300 back to the entry of the second basic block 302 for iteration until the address space accessed by pointer p no longer changes. In this example, pointer p will no longer change, and it can be determined to access on-chip memory.

[0055] The conditional instructions of the control flow graph also include function calls. A function call is to call a subroutine. When a function call is encountered, it will jump to the subroutine to execute, and after executing the subroutine, it will return to the main program to execute the next instruction. Another embodiment of the present disclosure is an address space deduction method applicable to function calls, and its flowchart is as Figure 4as shown

[0056] In step 401, the compiler traverses multiple basic blocks to obtain all possible address spaces of the pointer. In this embodiment, all basic blocks in the control flow graph are traversed, and for the same pointer, all its possible address spaces are obtained.

[0057] In step 402, the compiler determines whether the pointer is involved in a function call. If it is involved in a function call, step 403 is executed, and the compiler determines whether the function is read-only. If it is not a read-only function, the result of the function call cannot be confirmed during the compilation phase. Therefore, step 404 is executed, and the compiler sets the pointer for general address access.

[0058] In step 403, if it is determined that the function is a read-only function, since a read-only function does not change the accessed address space, or in step 402, it is determined that there is no function call involved, then step 405 is executed, and the compiler determines whether all these possible address spaces are deduced to a single address space. If not deduced to a single address space, step 404 is executed, and the compiler sets the pointer for general address access. If deduced to a single address space, step 406 is executed, and the compiler sets this pointer to access the address space.

[0059] In another embodiment, when executing step 402, when the compiler determines that the pointer is involved in a function call, step 403 may not be executed, and step 404 is directly executed, and the compiler sets the pointer for general address access.

[0060] The compiler can repeatedly execute the above steps 401 to 406 until the address space pointed to by the pointer remains unchanged. After that, the compiler can generate a memory access instruction according to the address space pointed to by the pointer to implement access operations for various data such as images, voices, or texts according to the memory access instruction.

[0061] Figure 5 is another example showing a control flow graph for explaining the flowchart of this embodiment. This control flow graph 500 also includes five basic blocks, and the connection relationship of these basic blocks is the same as that of the control flow graph 300. The only difference is that the fifth basic block 305 becomes a function call 505.

[0062] In step 401, the compiler traverses multiple basic blocks to obtain all possible address spaces of the pointer. In the first basic block 501, the variable a is assigned to the pointer p. Assuming that the variable a is stored in the memory of a specific chip, the pointer p should access the memory of that specific chip. The control flow passes through the second basic block 502, the third basic block 503, and the fourth basic block 504 without changing the address space accessed by the pointer p. Therefore, all possible address spaces of the pointer p are the memory of that specific chip.

[0063] In step 402, the compiler determines whether the pointer involves a function call. Since this control flow graph 500 involves a function call 505, step 403 is executed, and the compiler determines whether the function is read-only. Assuming that the function call 505 is not a read-only function, step 404 is executed, and the compiler sets the pointer p to a general address access. In other words, at the exit of the function call 505, the pointer p is updated to a general address access, and such a setting follows the loop of the control flow graph 500 back to the entry of the second basic block 502 for iteration until the address space accessed by the pointer p no longer changes. In this example, the pointer p will be set to a general address access during compilation.

[0064] In the foregoing embodiment, during the compilation stage, through address space deduction, the pointer that can be deduced to access a single address space is made explicit, reducing the program running time and thus optimizing the program performance.

[0065] When the pointer is set to a general address access, the present disclosure also provides a method that does not require setting additional fields or parameters. When defining a variable, only the address space where the variable is located needs to be explicitly declared, and its access operation is completed by the general address access mechanism. More specifically, since the artificial intelligence chip does not have a memory management mechanism, when encountering a general address access, the specific memory information cannot be directly obtained. Another embodiment of the present disclosure is a general address access method for declaring the address space where the variable is located, which uses software to simulate hardware to simplify the hardware design complexity.

[0066] The application scenario of this embodiment is an artificial intelligence chip, which includes a first memory and a second memory. The storage space of the first memory is defined by a first address to a second address, and the storage space of the second memory is defined by a third address to a fourth address. Among them, the first memory can be an off-chip memory, and the second memory can be an on-chip memory. Furthermore, the addresses of the off-chip memory and the on-chip memory are arranged consecutively. For example, the first memory has 128 storage spaces, which are respectively pointed to by 128 addresses between the first address addr0 and the second address addr127. The second memory also has 128 storage spaces, which are consecutively pointed to by 128 addresses between the third address addr128 and the fourth address addr255. That is to say, although the first memory and the second memory are not in the same place, the third address addr128 is the second address addr127 plus one. In this embodiment, the pointer within the basic block has been set to a general address access through a process such as Figure 1 or Figure 4 . The flowchart of this embodiment is as Figure 6 shown.

[0067] In step 601, the compiler determines whether the general address falls between the first address and the second address. Since the addresses of the first memory and the second memory are arranged consecutively, it is only necessary to determine whether the general address is less than the third address to know whether the general address falls between the first address and the second address. If it falls between the first address and the second address, step 602 is executed, and the compiler sets the first variable to true. If it does not fall between the first address and the second address, step 603 is executed, and the compiler sets the first variable to false.

[0068] Then in step 604, the compiler determines whether the first variable is true. If the first variable is true, it means that the address of the pointer is in the first memory, so step 605 is executed, and the compiler sets the pointer to access the first memory. If the first variable is false, it means that the address of the pointer is in the second memory, so step 606 is executed, and the compiler sets the pointer to access the second memory.

[0069] After executing the foregoing steps, the compiler can generate a memory access instruction according to the setting to implement the access operations of various data such as images, voices, or texts according to the memory access instruction.

[0070] This embodiment compares the variable value of the pointer with the address range of the memory to obtain the information of which memory the address is located in, and then determines the address space that the pointer should access during the compilation stage.

[0071] When executing the foregoing process, it can be implemented by writing code using predicates. One kind of operable code is as follows:

[0072] setp.lt s%addr 0xXXXXX (1)

[0073] @s ld.offchip (2)

[0074] !@s ld.onchip (3)

[0075] Among them, setp.lt is a judgment instruction for less-than operation, s is a predicate register (i.e., the foregoing first variable), %addr is the value of the pointer p, that is, the address, 0xXXXXX represents the value 128, @s is a judgment formula to judge whether s is true, and!@s is also a judgment formula to judge whether s is false. ld.offchip is to load from off-chip memory, and ld.onchip is to load from on-chip memory.

[0076] Instruction (1) represents: Judge whether the value of pointer p is less than 128. If so, set s to 1, that is, true; if not, set s to 0, that is, false. Instruction (2) represents: If s is true, load data from off-chip memory. Instruction (3) represents: If s is false, load data from on-chip memory. Whether loading data from off-chip memory or on-chip memory, the address is the value of pointer p % addr.

[0077] Although this example is described with load instructions, the present invention is not limited to the type of instructions, and any instruction that needs to access memory is applicable to the above process.

[0078] This embodiment does not require adding additional fields or parameters. By simply judging whether the value in the predicate register is true or false, information about which memory the address pointed to by pointer p is located in can be obtained during the compilation stage, and a general address access mechanism can be established.

[0079] When there are more than two system memories, the corresponding address space can also be found using the method of the present invention. Another embodiment of the present invention is to implement the general address access method in three memories. In this embodiment, multiple basic blocks in a control flow graph can access the first memory, the second memory, and the third memory. The storage space of the first memory is defined by the first address to the second address, the storage space of the second memory is defined by the third address to the fourth address, and the storage space of the third memory is defined by the fifth address to the sixth address. Among them, the first memory and the second memory can be different off-chip memories, and the third memory is an on-chip memory. Similarly, the addresses of these memories are arranged consecutively. For example: The first memory has a total of 128 storage spaces, which are represented by 128 addresses between the first address addr0 and the second address addr127. The second memory also has 128 storage spaces, which are consecutively represented by 128 addresses between the third address addr128 and the fourth address addr255. The third memory also has 128 storage spaces, which are consecutively represented by 128 addresses between the fifth address addr256 and the sixth address addr383. In other words, the third address addr128 is the second address addr127 plus one, and the fifth address addr256 is the fourth address addr255 plus one. The flowchart of this embodiment is as Figure 7 shown.

[0080] In step 701, the compiler judges whether the general address falls between the first address and the second address. That is, it judges whether the general address is less than the third address. If it falls between the first address and the second address, step 702 is executed, and the compiler sets the first variable to true. If it does not fall between the first address and the second address, step 703 is executed, and the compiler sets the first variable to false.

[0081] Next, step 704 is executed. The compiler determines whether the general address falls between the fifth address and the sixth address. That is, it determines whether the general address is greater than the fourth address. If it falls between the fifth address and the sixth address, step 705 is executed, and the compiler sets the second variable to true. If it does not fall between the fifth address and the sixth address, step 706 is executed, and the compiler sets the second variable to false.

[0082] Next, in step 707, the compiler determines whether the first variable is true. If the first variable is true, it means that the address of the pointer is in the first memory, so step 708 is executed, and the compiler sets the pointer to access the first memory. If the first variable is false, then step 709 is executed, and the compiler determines whether the second variable is true. If the second variable is true, it means that the address of the pointer is in the third memory, so step 710 is executed, and the compiler sets the pointer to access the third memory. If the second variable is false, then in step 711, the compiler determines whether both the first variable and the second variable are false. If so, it means that the address is not in the first memory and the third memory, so step 712 is executed, and the compiler sets the pointer to access the second memory.

[0083] Logically speaking, since the address must be in the first memory, the second memory, or the third memory, at least one of the judgment steps in step 707, step 709, and step 711 will be judged as yes. In other words, in step 711, there should be no situation where the first variable or the second variable is not false. If such a situation really occurs, this process will return to step 707, and the compiler will re-determine the truth or falsehood of the first variable and the second variable.

[0084] After executing the foregoing steps, the compiler can generate a memory access instruction according to the setting, so as to implement access operations of various data such as images, voices, or texts according to the memory access instruction.

[0085] From the above process, it can be seen that in this embodiment, by comparing the variable value of the pointer with the address range, it can be known which memory the address is in, and then the value is accessed according to the address.

[0086] Figure 7 The process can be implemented by the following code:

[0087] setp.lt s%addr 0xXXXXX (4)

[0088] setp.gt t%addr 0xYYYYY (5)

[0089] @s ld.chip1 (6)

[0090] @t ld.chip (7)

[0091] !@s&!@t ld.chip2 (8)

[0092] Instruction (4) represents: Determine whether the value of pointer p %addr is less than 128. If so, set the value of the s predicate register (i.e., the first variable) to 1. If not, set it to 0. Instruction (5) represents: Determine whether the value of pointer p %addr is less than 256 (0xYYYYY). If so, set the value of the t predicate register (i.e., the second variable) to 1. If not, set it to 0. Instruction (6) represents: If s is true (i.e., s = 1), load data from the first memory. Instruction (7) represents: If t is true (i.e., t = 1), load data from the third memory. Instruction (8) represents: If s is false (i.e., s = 0) and t is false (i.e., t = 0), load data from the second memory.

[0093] Instruction (8) involves the operation of predicates, but not all compilers can support the operation of predicates. In the case where the compiler does not support it, the equivalent effect can be achieved by means of predicate assignment. Another embodiment of the present invention is a method for using predicate assignment to determine the specific address space of a general address in three memories. Figure 8 is a flowchart showing this embodiment, where steps 801 to 810 respectively correspond to Figure 7 steps 701 to 710 of, which will not be elaborated here.

[0094] When it is determined in step 807 that the first variable is true, step 811 is executed after step 808, and the compiler sets the third variable to false. Similarly, when it is determined in step 809 that the second variable is true, step 811 is executed after step 810, and the compiler sets the third variable to false. When it is determined in step 809 that the second variable is not true, step 812 is executed, and the compiler sets the third variable to true. After steps 811 and 812, step 813 is executed, and the compiler determines whether the third variable is true. If it is true, it means that both the first and second variables are false, and step 814 is executed, and the compiler sets the pointer to access the second memory. If it is false, it means that the process has passed through step 808 or step 810, and the pointer has been set to access the first memory or the second memory, so the process ends in step 815.

[0095] After executing the foregoing steps, after compilation is completed, according to the setting, calculate the image or voice data.

[0096] When Instruction (8) is represented in the form of predicate assignment, it can be completed with the following four instructions:

[0097] u = 1 (9)

[0098] @!s u = 0 (10)

[0099] @!t u = 0 (11)

[0100] @u ld.chip1 (12)

[0101] Instruction (9) represents: setting the third variable u to true; Instruction (10) represents: if s is not false, setting the third variable to false; Instruction (11) represents: if t is not false, setting the third variable to false; Instruction (12) represents: if the third variable is true, loading the second memory.

[0102] The three memories in this embodiment are only examples. Those skilled in the art can apply the present invention to scenarios with more than three memories without creative labor, and these scenarios are all within the scope disclosed by the present invention.

[0103] Another embodiment of the present invention is a computing device of an artificial intelligence chip. Figure 9 The internal structural schematic diagram of such a computing device 900 is shown. The computing device 900 has a total of sixteen processor cores (processor core 0 to processor core 15) for performing matrix calculation tasks. Every four processor cores form a processing unit group, that is, a cluster. More specifically, processor core 0 to processor core 3 form the first cluster 902, processor core 4 to processor core 7 form the second cluster 904, processor core 8 to processor core 11 form the third cluster 906, and processor core 12 to processor core 15 form the fourth cluster 908. The computing device 130 basically executes calculation tasks in units of clusters.

[0104] The computing device 900 further includes a storage unit core 910 and a shared storage unit 912. The storage unit core 910 is mainly used to control data exchange and serves as a channel for the computing device 900 to communicate with off-chip memory. The shared storage unit 912 is an on-chip memory for temporarily storing the calculation intermediate values of these clusters 902, 904, 906, 908.

[0105] Processor cores 0 to 15 are used to execute the methods of the foregoing embodiments. Specifically, they include but are not limited to Figure 1 , Figure 4 , Figure 6 , Figure 7 and Figure 8 's processes.

[0106] Figure 10 is a structural diagram showing an integrated circuit device 1000 according to an embodiment of the present disclosure. As Figure 10 shown, the integrated circuit device 1000 includes a computing device 900, a general interconnection interface 1004, and other processing devices 1006.

[0107] The general interconnect interface 1004 can be used to transfer data and control instructions between the computing device 900 and other processing devices 1006. For example, the computing device 900 can obtain the required input data from other processing devices 1006 via the general interconnect interface 1004 and write it into the shared storage unit 912 on the chip of the computing device 900. Further, the computing device 900 can obtain control instructions from other processing devices 1006 via the general interconnect interface 1004 and write them into the control cache on the chip of the computing device 900.

[0108] The other processing devices 1006 can be one or more types of processors such as general-purpose and / or special-purpose processors like central processing units, graphics processing units, artificial intelligence processors, etc., and the number thereof is not limited but determined according to actual needs. The other processing devices 1006 serve as the interface between the computing device 900 and external data and control, and perform basic controls including but not limited to data transfer and starting and stopping the computing device 900. The other processing devices 1006 can also cooperate with the computing device 900 to jointly complete computing tasks.

[0109] The integrated circuit device 1000 further includes off-chip memory 1008, which can be connected to the computing device 900 and other processing devices 1006 respectively. The off-chip memory 1008 is used to store the data of the computing device 900 and other processing devices 1006, especially suitable for data that cannot be fully stored in the internal storage of the computing device 900 or other processing devices 1006.

[0110] According to different application scenarios, the integrated circuit device 1000 can be used as a system-on-chip (SOC) of devices such as mobile phones, robots, drones, video capture, etc., thereby effectively reducing the core area of the control part, improving the processing speed and reducing the overall power consumption. In this case, the general interconnect interface 1004 of the integrated circuit device 1000 is connected to certain components of the device. Such certain components can be, for example, cameras, displays, mice, keyboards, network cards or wifi interfaces.

[0111] The present disclosure also discloses a chip or an integrated circuit chip, which includes the integrated circuit device 1000. The present disclosure also discloses a chip packaging structure, which includes the above chip.

[0112] Another embodiment of the present disclosure is a board card, which includes the above chip packaging structure. Refer to Figure 11 , in addition to including a plurality of the above chips 1102, the board card 1100 can also include other supporting components, and the supporting components include storage devices 1104, interface devices 1106 and control devices 1108.

[0113] The storage device 1104 is connected to the chip 1102 within the chip package structure via a bus 1114 for storing data. The storage device 1104 may include multiple groups of memory cells 1110. Each group of memory cells 1110 may be the aforementioned off-chip memory.

[0114] The interface device 1106 is electrically connected to the chip 1102 within the chip package structure. The interface device 1106 is used to implement data transfer between the chip 1102 and an external device 1112 (such as a server or a computer). In this embodiment, the interface device 1106 is a standard PCIe interface. The data to be processed is transferred from the server to the chip 1102 through the standard PCIe interface to achieve data transfer. The calculation result of the chip 1102 is also transmitted back to the external device 1112 by the interface device 1106.

[0115] The control device 1108 is electrically connected to the chip 1102 to monitor the state of the chip 1102. Specifically, the chip 1102 and the control device 1108 may be electrically connected through an SPI interface. The control device 1108 may include a microcontroller ("MCU", Micro Controller Unit).

[0116] Another embodiment of the present disclosure is an electronic device or apparatus, which includes the above-mentioned board 1100. According to different application scenarios, the electronic device or apparatus may include a data processing device, a robot, a computer, a printer, a scanner, a tablet computer, a smart terminal, a mobile phone, a driving recorder, a navigator, a sensor, a camera, a server, a cloud server, a camera, a video camera, a projector, a watch, a headset, a mobile storage, a wearable device, a vehicle, a household appliance, and / or a medical device. The vehicle includes an airplane, a ship, and / or a vehicle; the household appliance includes a television, an air conditioner, a microwave oven, a refrigerator, a rice cooker, a humidifier, a washing machine, a light, a gas stove, a range hood; the medical device includes a nuclear magnetic resonance instrument, a B-ultrasound instrument, and / or an electrocardiogram instrument.

[0117] Although this embodiment is described by taking an artificial intelligence chip as an example, those skilled in the art can understand that these methods can also be implemented using a general-purpose processor.

[0118] Another embodiment of the present disclosure is a computer-readable storage medium, on which computer program code for accessing using a general address is stored. When the computer program code is run by a processor, the methods described in the foregoing embodiments are executed.

[0119] Through the demonstrations of the foregoing embodiments, the present invention concretizes the address space of a general address during the compilation stage, determines the memory access, simplifies the hardware complexity, facilitates programming, and ensures the performance of the program. The artificial intelligence chip performs matrix calculations based on the compiled operation codes to complete the calculation tasks of input data (such as image or voice data). Due to the preprocessing of the general address by the present invention, the calculation process will be more streamlined and efficient.

[0120] The foregoing can be better understood in accordance with the following clauses:

[0121] Clause A1. A method for deriving an address based on a control flow graph, the control flow graph including a plurality of basic blocks, the plurality of basic blocks including pointers, the pointers carrying addresses. The method includes: traversing the plurality of basic blocks to obtain all possible address spaces of the pointers; determining whether all the possible address spaces are deduced to a single address space; if so, setting the pointers to access the address space.

[0122] Clause A2. According to the method described in Clause A1, the method further includes: if not, setting the pointer to access as a general address.

[0123] Clause A3. According to the method described in Clause A2, it further includes: determining whether the pointer is involved in a function call; and if involved in a function call, setting the pointer to access as a general address.

[0124] Clause A4. According to the method described in Clause A2 or 3, the plurality of basic blocks access a first memory and a second memory, the storage space of the first memory is defined by a first address to a second address, and the storage space of the second memory is defined by a third address to a fourth address. The method further includes: determining whether the general address falls between the first address and the second address; if it falls between the first address and the second address, setting a first variable to true; if it does not fall between the first address and the second address, setting the first variable to false; determining whether the first variable is true; and if the first variable is true, setting the pointer to access the first memory.

[0125] Clause A5. According to the method described in Clause A4, wherein the third address is the second address plus one.

[0126] Clause A6. According to the method described in Clause A5, wherein if the first variable is false, setting the pointer to access the second memory.

[0127] Clause A7. According to the method described in Clause A5, wherein the step of determining the general address includes: determining whether the general address is less than the third address.

[0128] Clause A8. The method according to Clause A4, wherein the plurality of basic blocks further access a third memory, the storage space of the third memory being defined by a fifth address to a sixth address, and the method further includes: determining whether the general address falls between the fifth address and the sixth address; if the general address falls between the fifth address and the sixth address, setting a second variable to true; determining whether the second variable is true; and if the second variable is true, setting the pointer to access the third memory.

[0129] Clause A9. The method according to Clause A8, wherein the third address is the second address plus one, and the fifth address is the fourth address plus one.

[0130] Clause A10. The method according to Clause A9, wherein the step of determining whether the general address falls between the fifth address and the sixth address includes: determining whether the general address is greater than the fourth address.

[0131] Clause A11. The method according to Clause A8, further includes: if the general address does not fall between the fifth address and the sixth address, setting the second variable to false; wherein, if both the first variable and the second variable are false, setting the pointer to access the second memory.

[0132] Clause A12. The method according to Clause A8, further includes: setting a third variable to true; if it is determined that the first variable is true, setting the third variable to false; if it is determined that the second variable is true, setting the third variable to false; determining whether the third variable is true; and if the third variable is true, setting the pointer to access the second memory.

[0133] Clause A13. The method according to Clause A1, wherein the determining step includes: obtaining the pointer variables of the pointer in all basic blocks; and determining whether the pointer variables all correspond to the address space.

[0134] Clause A14. The method according to Clause A1, wherein the setting step is executed after the plurality of basic blocks converge.

[0135] Clause A15. The method according to Clause A1, wherein when the control flow graph includes an iterative algorithm, the determining step is executed after the address of the pointer remains unchanged.

[0136] Clause A16. The method according to Clause A1, wherein the control flow graph is a jump control or a loop control.

[0137] Clause A17. A computer-readable storage medium storing computer program code for accessing in a system using a general address, which, when run by a processor, performs the method according to any one of Clauses A1-16.

[0138] Clause A18. A computing device including a processor core that performs the method according to any one of Clauses A1-16.

[0139] The embodiments of the present disclosure have been described in detail above. Specific examples are used herein to illustrate the principle and implementation manner of the present disclosure. The description of the above embodiments is only for helping to understand the method and its core idea of the present disclosure; at the same time, for those of ordinary skill in the art, according to the idea of the present disclosure, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present disclosure.

Claims

1. A method for deriving an address based on a control flow graph, the control flow graph including a plurality of basic blocks, the plurality of basic blocks including at least one instruction, and the pointer included in the instruction carrying an address, the method comprising: Traversing the plurality of basic blocks to obtain all possible address spaces of the pointer; Determining whether all possible address spaces are deduced to a single address space; And If so, setting the pointer to access the address space; Wherein the traversing step, the determining step and the setting step are repeatedly executed until the address of the pointer remains unchanged.

2. The method according to claim 1, the method further comprising: If not, setting the pointer to access a general address.

3. The method according to claim 2, further comprising: Determining whether the pointer is involved in a function call; And If it is involved in a function call, setting the pointer to access a general address.

4. The method according to claim 2 or 3, the plurality of basic blocks accessing a first memory and a second memory, the storage space of the first memory being defined by a first address to a second address, and the storage space of the second memory being defined by a third address to a fourth address, the method further comprising: Determining whether the general address falls between the first address and the second address; If it falls between the first address and the second address, setting a first variable to true; If it does not fall between the first address and the second address, setting the first variable to false; Determining whether the first variable is true; and If the first variable is true, setting the pointer to access the first memory.

5. The method according to claim 4, wherein the third address is the second address plus one.

6. The method according to claim 5, wherein if the first variable is false, setting the pointer to access the second memory.

7. The method according to claim 5, wherein the step of determining the general address includes: Determining whether the general address is less than the third address.

8. The method according to claim 4, wherein the plurality of basic blocks further access a third memory, the storage space of the third memory being defined by a fifth address to a sixth address, the method further comprising: Determining whether the general address falls between the fifth address and the sixth address; If the general address falls between the fifth address and the sixth address, setting a second variable to true; Determining whether the second variable is true; and If the second variable is true, setting the pointer to access the third memory.

9. The method according to claim 8, wherein the third address is the second address plus one, and the fifth address is the fourth address plus one.

10. The method according to claim 9, wherein the step of determining whether the general address falls between the fifth address and the sixth address includes: Determining whether the general address is greater than the fourth address.

11. The method according to claim 8, further comprising: If the general address does not fall between the fifth address and the sixth address, setting the second variable to false; Wherein, if both the first variable and the second variable are false, set the pointer to access the second memory.

12. The method according to claim 8, further comprising: Set a third variable to true; If it is determined that the first variable is true, set the third variable to false; If it is determined that the second variable is true, set the third variable to false; Determine whether the third variable is true; and If the third variable is true, set the pointer to access the second memory.

13. The method according to claim 1, wherein the determining step comprises: Obtain the pointer variables of the pointer in all basic blocks; Determine whether the pointer variables all correspond to the address space.

14. The method according to claim 1, wherein the setting step is performed after the plurality of basic blocks converge.

15. The method according to claim 1, wherein the control flow graph is jump control or loop control.

16. A computer-readable storage medium having stored thereon computer program code for accessing using a general address in a system, which when run by a processor, executes the method according to any one of claims 1-15.

17. A computing device comprising a processor core, the processor core executing the method according to any one of claims 1-15.

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