A method and device for processing exceptions or interrupts under a heterogeneous instruction set architecture

Abstract

The present application provides a method for handling exceptions or interrupts under a heterogeneous instruction set architecture, and the physical host to which the method is applied can support two instruction set architectures. When an exception or interrupt is triggered by a slave architecture virtual machine, the virtual machine monitor can convert the encoding of the exception or interrupt under the slave instruction set architecture into the encoding of the exception or interrupt under the main instruction set architecture, and the virtual machine monitor can identify the encoding of the exception or interrupt under the main instruction set architecture. Therefore, the virtual machine monitor identifies the type of exception or interrupt triggered by the slave architecture virtual machine through the converted encoding, and thus processes it. In this way, the virtual machine monitor can identify and handle exceptions or interrupts triggered by slave architecture virtual machines, which can ensure the stability of the system, enable the heterogeneous instruction set virtual machines to operate normally, and build a diversified software ecosystem.

Description

Technical Field

[0001] The present application relates to the field of computers, and in particular to a method for processing an exception or interruption. Background Art

[0002] The instruction set is a set of instructions stored in the processor to guide the processor to perform addition and subtraction operations and control the computer operating system. The instruction set or instruction set architecture is also a set of instructions that the processor can support. At present, the common instruction set architectures (ISA) include X86 architecture, advanced reduced instruction set machine (ARM) architecture and RISC-V architecture. Different processors may support different instruction set architectures. If the processor wants to support a new instruction set architecture, it is necessary to modify the hardware circuit. If the software wants to support a new instruction set, it is necessary to modify the program and recompile. When it is necessary to execute business on the new instruction set architecture, the application and operating system that support the original instruction set architecture cannot be directly run on the processor that supports the new instruction set architecture, but need to be redeveloped to support the new instruction set architecture. For example, the binary file of a software under the X86 instruction set architecture cannot be directly run in the hardware or software environment that supports the ARM instruction set architecture. It needs to be redeveloped and compiled based on the ARM instruction set architecture to obtain a new binary file of the software.

[0003] In a virtualization scenario, if you need to start a new virtual machine that supports the ARM architecture on the server, but the virtualization platform on the server and the virtual machines running on the virtualization platform both support the X86 architecture, you need to replace the virtualization platform that supports the X86 architecture with the virtualization platform that supports the ARM architecture, and then start the virtual machine that supports the ARM architecture on the virtualization platform that supports the ARM architecture. In addition, the server's hardware devices, including the processor, need to be replaced with hardware devices that support the ARM architecture. This replacement of the entire set of hardware and software is too costly and is not conducive to building a diversified software ecosystem.

[0004] If you want to run multiple virtual machines that support different instruction set architectures on a virtualization platform that supports one instruction set architecture and build a diversified software ecosystem, you need to allow the instructions of the virtual machines that support heterogeneous instruction set architectures to be executed or processed, especially exceptions or interrupts. Since the virtual machines that support heterogeneous instruction set architectures and the virtualization platform each support different instruction set architectures, and the virtualization platform can only identify exceptions or interrupts triggered under the instruction set architecture supported by the virtualization platform, the interrupts or exceptions triggered under the heterogeneous instruction set architecture cannot be properly identified and processed, which will cause the system to crash. Summary of the invention

[0005] The exception or interrupt handling method provided in the present application can be applied to a physical host that supports virtual machines of heterogeneous instruction sets, and can handle exceptions or interrupts triggered by virtual machines of heterogeneous instruction sets, thereby improving the stability of the system.

[0006] In the first aspect, the embodiment of the present application provides an abnormal processing method. The method is applied to a physical host supporting a heterogeneous instruction set virtual machine, and the heterogeneous instruction set architecture refers to at least two different instruction set architectures---the main instruction set architecture and the slave instruction set architecture, such as the RISC-V architecture and the ARM architecture mentioned in the embodiment of the present application. That is to say, virtual machines supporting different instruction set architectures, the main architecture virtual machine (such as an ARM virtual machine) and the slave architecture virtual machine (such as a RISC-V virtual machine) can be run on the physical host. The processor of the physical host includes a main processing core supporting the main instruction set architecture and a slave processing core supporting the slave instruction set architecture. Among them, the main processing core and the slave processing core are logical cores in the processor that support different instruction set architectures, and the logical core is a processing unit logically divided on the physical core; in each embodiment of the present application, the processing core is also referred to as processing logic.

[0007] The method includes:

[0008] When an exception or interrupt is triggered by a slave architecture virtual machine, the state information of the exception or interrupt is obtained; wherein the state information of the exception or interrupt is a first code of the exception or interrupt, the first code is used to indicate the type of the exception or interrupt under the slave instruction set architecture, and the first code is used to indicate the type of the exception or interrupt in the specification of the slave instruction set architecture. The second code of the exception or interrupt triggered by the slave architecture virtual machine is obtained from the exception mapping relationship or the interrupt mapping relationship, and the type of the exception or interrupt triggered by the slave architecture virtual machine is identified according to the second code of the exception or interrupt, so that the exception or interrupt can be processed.

[0009] Under different instruction set architectures, the encoding for the same type of exception or the same type of interrupt is different. Under different instruction set architectures, different encodings are used to represent the type of the same type of exception or the same type of interrupt. The difference in encoding includes different formats and different encoding values; or the difference in encoding lies in the number of fields included in the encoding and the value of each field is different. In the specification of the slave instruction set architecture, the type of such exception or interrupt triggered by the slave architecture virtual machine is represented by a first encoding; and in the specification of the master instruction set architecture, the second encoding is used to represent the type of such exception or interrupt. The first encoding and the second encoding are different. The exception mapping relationship and the interrupt mapping relationship can be stored in a storage space (such as memory) accessible to the master architecture virtual machine monitor. The exception mapping relationship records the correspondence between the first encoding and the second encoding of each type of exception in multiple types of exceptions. This correspondence represents the correspondence between the type of exception under the master instruction set architecture and the type of exception under the slave instruction set architecture. For example, for any one of the corresponding relationships, it can represent the second encoding of the same or similar type of exception in the specification of the master instruction set architecture and the first encoding in the specification of the slave instruction set architecture. The interrupt mapping relationship records the correspondence between the first code and the second code of each type of interrupt in multiple types of interrupts. This correspondence represents the correspondence between the type of interrupt under the main instruction set architecture and the type of interrupt under the slave instruction set architecture. For example, any one of the correspondences may represent the second code of the same or similar type of interrupt in the specification of the main instruction set architecture and the first code in the specification of the slave instruction set architecture. Among them, the interrupt triggered by the slave architecture virtual machine may include a physical interrupt received from the processing core and a virtual interrupt received from the virtual processor of the slave architecture virtual machine.

[0010] The method described in the first aspect and any of the following implementations of the first aspect can be executed by a virtual machine monitor that supports the main instruction set architecture and runs on a physical host. Since the virtual machine monitor supports the main instruction set architecture, it is not possible to directly identify the type of exception triggered from the architecture virtual machine based on the first code of the exception. Therefore, the virtual machine monitor obtains the second code of the exception triggered from the architecture virtual machine from the exception mapping relationship, identifies the type of exception triggered from the architecture virtual machine based on the second code of the exception, and can handle the exception. The virtual machine monitor can be called a virtual machine monitor, VMM, or a hypervisor.

[0011] Since the processor includes a main processing core that supports the main instruction set architecture and a slave processing core that supports the slave instruction set architecture, the instructions of the slave architecture virtual machine can be directly executed by the slave processing core without instruction translation, which can avoid the instruction expansion problem caused by instruction translation. And for the exception or interrupt triggered by the slave architecture virtual machine, the virtual machine monitor can convert the unrecognizable first code into a recognizable second code according to the exception mapping table or the interrupt mapping table, and then obtain the type of the exception or interrupt according to the second code for processing. This method can ensure the normal operation of the virtual machine of the heterogeneous instruction set architecture, and the exception or interrupt of the slave architecture virtual machine can be accurately identified and processed; it will not cause the system to crash because the virtual machine monitor cannot identify the type of the exception or interrupt and cannot handle the exception or interrupt. Therefore, this method can improve the stability of the system, enable the heterogeneous instruction set virtual machine to operate normally, and build a diversified software ecosystem.

[0012] Furthermore, the virtual machine monitor identifies the type of the exception or interrupt based on the encoding of the exception or interrupt under the main instruction set architecture corresponding to the exception or interrupt triggered by the slave architecture virtual machine, and the virtual machine monitor itself can handle the exception or interrupt triggered by the main architecture virtual machine that supports the main instruction set architecture, and has corresponding processing logic for different types of exceptions or interrupts. Therefore, the process of the physical host processing the exception or interrupt triggered by the slave architecture virtual machine can reuse the software processing logic for the exception or interrupt triggered by the main architecture virtual machine. Compared to setting up the exception or interrupt processing logic that supports two instruction set architectures, the method provided in the embodiment of the present application can handle the exceptions or interrupts triggered by virtual machines of two instruction set architectures using only the virtual machine monitor that supports the main instruction set architecture, which is less difficult to implement and does not increase the complexity and cost of software design.

[0013] In one implementation, a physical host includes a hardware device that supports hardware-assisted virtualization, and the hardware device supports a main instruction set architecture. Hardware-assisted virtualization refers to a platform virtualization method that can use the help from hardware functions to achieve effective virtualization. In hardware-assisted virtualization, the hardware provides structural support to help create a virtual machine monitor and allow the client operating system to run independently. For example, the EPT and the second-level address translation (called Two-StageAddressTranslation in the RISC architecture and stage 2translations in the ARM architecture) in the MMU under the X86 architecture are used to speed up the mapping process of virtual addresses to physical addresses; for example, the hardware interrupt controller is used to obtain interrupt requests from other hardware devices and send them to the processor.

[0014] The method processes the exception or interruption, including: processing the exception or interruption by a hardware device supporting hardware-assisted virtualization, thereby improving the processing speed of the exception. Since the hardware device supporting hardware-assisted virtualization under the main instruction set architecture is reused, the complexity and cost of the hardware involved will not be increased.

[0015] In one implementation, the physical host further includes a slave architecture register; the aforementioned obtaining of status information of an exception or interrupt triggered by a slave architecture virtual machine includes:

[0016] The status information of the exception or interrupt is obtained from the shared memory or shared register. The shared memory or shared register is a communication channel between the slave processing core and the main processing core, which is shared by the slave processing core and the main processing core. It is a storage space accessible to both the slave processing core and the main processing core, and is used to store the status information of the exception. The status information of the exception or interrupt is copied from the slave architecture register to the shared memory by the slave processing core. Since the slave architecture register is a register that complies with the slave instruction set architecture specification, and the virtual machine monitor that supports the main instruction set architecture cannot directly read the status information of the exception from the slave architecture register, the method designs a shared memory to transmit the status information of the exception or interrupt.

[0017] In another implementation, the physical host further includes a shared register; the aforementioned obtaining of the status information of the exception or interrupt triggered by the slave architecture virtual machine includes: obtaining the status information of the exception or interrupt from the shared register, wherein the shared register is shared by the slave processing core and the master processing core, and is a register for storing the status information of the exception triggered by the slave architecture virtual machine. Unlike existing registers that only support a single instruction set architecture specification, the shared register can comply with both the master and slave instruction set architecture specifications and can be accessed by the master processing core and the slave processing core. For the slave architecture side, the shared register can be used to store the status information of the exception or interrupt triggered by the slave architecture virtual machine, and from the master architecture side, the master architecture virtual machine monitor can obtain the status information of the exception or interrupt from the shared register.

[0018] In one implementation, the status information of the exception also includes at least one of the instruction that triggers the exception or the address that triggers the exception; it may also include other status information. For different types of exceptions, the exception status information may be different. The exception status information indicates the information required to handle the exception, and is used to indicate the state of the system when the exception is triggered. For example, an exception triggered by a system call instruction, the status information of the exception is the parameter of the system call, which is stored in the slave architecture register. Among them, the instruction that triggers the exception is the instruction that causes the slave architecture virtual machine to trigger the exception, or the instruction that is being executed when the slave architecture virtual machine triggers the exception; the address that triggers the exception is the address that causes the slave architecture virtual machine to trigger the exception, or the memory address that the slave architecture virtual machine wants to access when the slave architecture virtual machine triggers the exception. The exception mapping relationship or interrupt mapping relationship also includes the correspondence between the slave architecture register and the master architecture register. The master architecture register is a register that complies with the master instruction set architecture specification, and the slave architecture register is a register that complies with the slave instruction set architecture specification and is used to store the status information of the exception.

[0019] Before identifying the type of the exception or interrupt according to the second code of the exception and processing the exception or interrupt, the method further includes: finding the master architecture register corresponding to the slave architecture register according to the exception mapping relationship or the interrupt mapping relationship; writing the second code of the exception and at least one of the instruction triggering the exception and the address triggering the exception into the master architecture register; or writing the second code of the interrupt into the master architecture register;

[0020] Correspondingly, according to the second code of the exception or interruption, the type of the exception or interruption is identified and the exception or interruption is processed, including: reading the second code of the exception, and at least one of the instruction that triggers the exception and the address that triggers the exception from the main architecture register, and processing the exception according to the second code of the exception, and at least one of the instruction that triggers the exception and the address that triggers the exception; or reading the second code of the interruption from the main architecture register, and according to the second code of the interruption, identifying the type of the interruption and processing the interruption. When the virtual machine monitor processes the exception or interruption triggered by the main architecture virtual machine, it reads the status information of the exception or interruption from the main architecture register, thereby processing the exception or interruption. In order to modify the software logic of the original virtual machine monitor less, in this method, after the virtual machine monitor finds the second code of the exception or interruption triggered by the slave architecture virtual machine, the second code, the instruction that triggers the exception, and the address that triggers the exception are written into the main architecture register, so that the virtual machine monitor can treat the exception or interruption triggered by the slave architecture virtual machine as the exception triggered by the main architecture virtual machine.

[0021] Of course, in another implementation, the virtual machine monitor can directly identify and handle the exception or interruption based on the obtained second encoding of the exception or interruption and the instruction that triggers the exception and the address of the exception that is triggered obtained from the shared memory or shared register, without first storing the above information in the main architecture register and then reading it from the main architecture register to identify or handle the exception or interruption.

[0022] In a second aspect, the present application provides a computing node, which includes a memory and a processor, the processor including a master processing core supporting a master instruction set architecture and a slave processing core supporting a slave instruction set architecture, the memory stores computer instructions, and the master processing core runs the computer instructions to execute the method described in the first aspect and any one of the implementation methods.

[0023] In a third aspect, the present application provides a computer-readable storage medium, which stores computer instructions, and the computer instructions are called by a processor to execute the method described in the first aspect and any one of the implementations.

[0024] In a fourth aspect, the present application provides a physical host, which includes: a conversion module and a simulation module. The specific implementation of the conversion module can refer to the conversion module 304 or the RISC-V conversion module 404 in the specific embodiment; the specific implementation of the simulation module for handling exceptions can refer to the RISC-V exception simulation module 406 or the exception simulation module 306 in the specific embodiment; the specific implementation of the simulation module for handling interrupts can refer to the RISC-V interrupt simulation module 407 or the interrupt simulation module 307 in the specific embodiment.

[0025] The conversion module is used to:

[0026] When a slave architecture virtual machine triggers an exception or interrupt, the state information of the exception or interrupt is obtained. The slave architecture virtual machine is a virtual machine running on a physical host and supporting a slave instruction set architecture; the state information of the exception includes a first code of the exception; the first code of the exception indicates the type of the exception under the slave instruction set architecture; the state information of the interrupt includes a first code of the interrupt; the first code of the interrupt indicates the type of the interrupt under the slave instruction set architecture;

[0027] The second code of the exception or interrupt is obtained from the exception mapping relationship or the interrupt mapping relationship. The second code of the exception indicates the type of the exception under the main instruction set architecture; the second code of the interrupt indicates the type of the interrupt under the main instruction set architecture; the exception mapping relationship includes the correspondence between the first code and the second code of each type of exception in multiple types of exceptions, and the interrupt mapping relationship includes the correspondence between the first code and the second code of each type of interrupt in multiple types of interrupts.

[0028] The simulation module is used to: identify the type of the exception or interruption according to the second code of the exception or interruption; and process the exception or interruption.

[0029] In one implementation, the physical host further includes a slave architecture register, and the conversion module is further configured to:

[0030] Obtain the status information of the exception or interrupt from the shared memory, wherein the shared memory is shared by the slave processing core and the master processing core, and the status information of the exception or interrupt is copied from the slave architecture register to the shared memory; the slave architecture register is a register that complies with the slave instruction set architecture specification and is used to store the status information of the exception or interrupt triggered by the slave architecture virtual machine.

[0031] In one implementation, the physical host further includes a shared register, and the conversion module is further configured to:

[0032] The state information of the exception or interrupt is obtained from a shared register, wherein the shared register is shared by the slave processing core and the master processing core, and the shared register stores the state information of the exception or interrupt.

[0033] In one implementation, the physical host further includes a slave architecture register and a master architecture register, the interrupt mapping relationship further includes a correspondence between the slave architecture register and the master architecture register, the master architecture register is a register that complies with the master instruction set architecture specification; the slave architecture register is a register that complies with the slave instruction set architecture specification and is used to store the status information of the interrupt;

[0034] The conversion module is also used to: search for the master architecture register corresponding to the slave architecture register according to the interrupt mapping relationship; write the second code of the interrupt into the master architecture register;

[0035] The simulation module is used for: reading the second code of the interrupt from the main architecture register; and processing the interrupt according to the second code of the interrupt.

[0036] In one implementation, the physical host further includes a slave architecture register and a master architecture register, the abnormal status information further includes at least one of an instruction triggering the abnormality or an address triggering the abnormality, the abnormal mapping relationship further includes a corresponding relationship between the slave architecture register and the master architecture register, the master architecture register is a register that complies with the master instruction set architecture specification, and the slave architecture register is a register that complies with the slave instruction set architecture specification and is used to store the abnormal status information;

[0037] The conversion module is further used to: search for a master architecture register corresponding to the slave architecture register according to the exception mapping relationship; write the second code of the exception into the master architecture register, and write at least one of the instruction that triggers the exception and the address that triggers the exception into the master architecture register;

[0038] The simulation module is used to: read the second code of the exception, and at least one of the instruction that triggers the exception and the address that triggers the exception from the main architecture register; and process the exception according to the second code of the exception, and at least one of the instruction that triggers the exception and the address that triggers the exception.

[0039] In one implementation, the physical host includes a hardware device that supports hardware-assisted virtualization, and the hardware device supports the main instruction set architecture;

[0040] The simulation module is used to: handle exceptions through hardware devices that support hardware-assisted virtualization.

[0041] In a fifth aspect, the present application provides a computer program product, which includes computer instructions, and the computer instructions are called by a processor to execute the method described in the first aspect or the second aspect and any one of the implementations.

[0042] In a sixth aspect, the present application provides a chip, comprising a master processing core supporting a master instruction set architecture and a slave processing core supporting a slave instruction set architecture, the master processing core being configured to execute the method described in the first aspect and any one of the implementation modes. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 A schematic diagram of the structure of a computing node 100 provided in an embodiment of the present application;

[0044] Figure 2 A schematic diagram of the structure of the computing node 203 provided in an embodiment of the present application;

[0045] Figure 3 A schematic diagram of the structure of a computing node 300 provided in an embodiment of the present application;

[0046] Figure 4 A schematic diagram of the structure of a computing node 400 provided in an embodiment of the present application;

[0047] Figure 5 A flowchart of processing an exception triggered by a RISC-V virtual machine provided in an embodiment of the present application;

[0048] Figure 6 A flowchart of processing an interrupt triggered by a RISC-V virtual machine provided in an embodiment of the present application;

[0049] Figure 7 A schematic diagram of the structure of the cause register in the RISC-V architecture specification provided in an embodiment of the present application;

[0050] Figure 8 A schematic diagram of the structure of the esr_el2 register in the ARM architecture specification provided in an embodiment of the present application;

[0051] Fig. 9 A schematic diagram of the structure of a computing node 700 provided in an embodiment of the present application;

[0052] Fig.10 A schematic diagram of the structure of a multi-core processor 80 provided in an embodiment of the present application. DETAILED DESCRIPTION

[0053] In order to facilitate understanding of the various embodiments of the present application, first Figure 1 The computing node 100 shown is used as an example to introduce some basic concepts in the virtualization field involved in this application.

[0054] Virtualization is the process of virtualizing the hardware resources in the hardware layer of a computing node (such as processors, storage space in memory, and network resources) and sharing them with multiple virtual computers. A virtual computer is a general term for the operating environment virtualized by software in all types of virtualization devices, including virtual machines and containers.

[0055] like Figure 1 As shown, computing node 100 includes hardware layer 112, host machine layer 109 and virtualization layer, and virtualization layer includes virtual machines 101 and 102. The number of virtual machines can be more or less, and only two are taken as an example. Hardware layer 112 includes processor 114, memory 113, communication interface 115 and interrupt controller 116.

[0056] A virtual machine (VM) is one or more virtual computers simulated on a physical computing node through virtualization software. These virtual machines run in a completely isolated environment and work just like real computers. Figure 1 A guest operating system (guest OS) can be installed on 101 and 102) Figure 1 105 and 106), one or more application programs ( Figure 1 103 and 104). The virtual machine can also access network resources. For the application running in the virtual machine, it is like working in a real computer.

[0057] Virtual processors (such as Figure 1107 and 108): In virtualization technology, it refers to a physical processing unit that is provided to a virtual computer in a shared or sharded manner, such as a virtual central processing unit (vCPU). A virtual computer can have one or more virtual processors serving it. When there are multiple virtual processors, there is usually one virtual processor as the master virtual processor and the others as slave virtual processors. The virtual memory and other virtual hardware resources contained in the virtual machine are in Figure 1 It is not shown in the figure. It should be understood that a virtual machine is equivalent to an independent computer, so the action performed by the virtual machine can also be considered as the action performed by the virtual processor. The virtual processor is virtualized by virtualization software, and its operation is actually realized by the processor or physical core of the host machine reading and running the software program. For example, a physical core reads a software program and runs the software program in a specific mode of hardware-assisted virtualization of the physical core (such as non-root mode of x86) to realize a virtual processor. Multiple virtual processors of a virtual machine can be located on different physical cores.

[0058] Virtual processor trap and virtual processor trap out: The virtualization system includes two modes: host mode and guest mode. When a virtual processor enters guest mode, it is called trap (virtual); when the virtual processor leaves guest mode, it is called trap out (virtual). After the virtual processor traps out, the physical processor will temporarily not execute the code of the virtual processor, so it can be understood that the virtual processor is not running at this time. For a physical processor, if the virtual processor running on it is trapped, it can be considered that the physical processor is in guest mode and runs the code of the virtual processor. When the virtual processor running on it traps out to host mode, it can be considered that the physical processor is in host mode and runs host-related code, such as a virtual machine monitor.

[0059] The host layer 109 is used as a management layer to complete the management and allocation of hardware resources, present a virtual hardware platform to the virtual machine, and realize the scheduling and isolation of the virtual machine. In some implementations, the host layer 109 may include a host operating system 111 and a virtual monitoring device, such as a virtual machine monitor 110 (virtual machine monitor, VMM). The virtual monitor 110 may be deployed within the host operating system 111 or outside the host operating system 111. In other virtualization architectures, the virtual monitoring device may also be called a hypervisor or other types of virtual monitoring devices. In other implementations, such as in the virtualization architecture Xen, the host layer 109 may also include a privileged virtual machine. The virtual hardware platform provides various hardware resources, such as virtual processors, virtual memory, virtual disks, virtual network cards, etc., to each virtual computer running on it. The virtual computer runs on the virtual hardware platform prepared for it by the host layer. The host layer 109 may also be called a virtualization platform, and sometimes the host layer may also be referred to as a host.

[0060] Hardware layer 112: the hardware platform on which the virtualized environment runs. The hardware layer may include a variety of hardware, such as Figure 1 As shown, the hardware layer may include a processor 114 and a memory 113, and may also include a communication interface 115, such as a network interface card (NIC); an interrupt controller 116, an input / output (I / O) device, etc. The processor 114 may include multiple physical cores, such as core 1 and core 0.

[0061] Processor 114 is sometimes referred to as a physical processor. A physical core represents the smallest processing unit in a processor, such as Figure 1 As shown, in this embodiment, the processor may have two physical cores: core 0 and core 1, and multiple registers. In some other embodiments, the number of cores included in the processor may be more or less, and the number of cores included in each processor may also be different. A processor with multiple physical cores is called a multi-core processor. Depending on whether the kernel architecture is the same, it can be divided into homogeneous multi-core and heterogeneous multi-core. The virtual processor and the physical core may be in a binding relationship, that is, a virtual processor is fixed to run on a certain physical core and cannot be scheduled to run on other physical cores, then the virtual processor is a bound core; a virtual processor can be scheduled to run on different physical cores as needed, then the virtual processor is a non-bound core.

[0062] Interrupt controller 116: It is set between the hardware that triggers the interrupt request and the processor, and is mainly used to collect the interrupt requests generated by various hardware and send them to the processor according to certain priorities or other rules, such as advanced programmable interrupt controller (APIC).

[0063] An interruption is an instruction that suspends the current program and executes the interrupt service routine instead.

[0064] An interrupt service routine (ISR) is a program used to handle interrupt requests. When the processor receives an interrupt request, it temporarily stops the execution of the current program and executes the interrupt service routine corresponding to the interrupt request.

[0065] Interrupt request: An interrupt request refers to an event generated by hardware. The hardware sends the event to the processor. When the processor receives the event, it temporarily stops the execution of the current program and executes the program corresponding to the event instead. The hardware may generate an interrupt request triggered by the hardware itself, or it may be triggered by software. Interrupt requests are sometimes referred to as interrupts. Some hardware in the computer (such as network cards, sound cards, mice, hard disks, etc.) can complete certain tasks without the intervention of the processor, but these hardware still need to interrupt the processor regularly to let the processor do some specific work for them. The interrupt number is an identifier for an interrupt request, and is represented by IRQ ID in English in this application.

[0066] The hardware layer 112 may also include a memory management unit (MMU). MMU is a computer hardware responsible for processing memory access requests. Its functions include conversion of virtual addresses to physical addresses (i.e., virtual memory management), memory protection, and control of the CPU cache. MMU usually uses an associative cache of a translation lookaside buffer (TLB) to convert virtual page numbers to physical page numbers.

[0067] The storage space (address space) provided by the memory 113 is divided into virtual machines and host machines for use. The host physical address (HPA) refers to the physical address space that can be used by the local host (host); the host virtual address (HVA) is the virtual address space that can be used by the local host (host). The guest physical address (GPA) is the physical address space that can be used by the client operating system of the virtual machine; the guest virtual address (GVA) is the virtual address space that can be used by the client operating system of the virtual machine.

[0068] When the virtual machine requests access to GVA, the MMU needs to convert GVA to GPA, and then convert GPA to HPA. The shadow page table is used to complete the direct conversion from GVA to HPA. The extended page table (EPT) is used to complete the conversion from GPA to HPA, and the conversion from GVA to GPA uses the client page table for address conversion. The EPT is maintained by the VMM, and the conversion process of the EPT is completed by hardware, so it is more efficient than the shadow page table conversion. The process used to accelerate the mapping of virtual addresses to physical addresses has different names in different architectures. It is called EPT in the X86 architecture, Two-Stage Address Translation in the RISC architecture, and stage 2 translations in the ARM architecture.

[0069] Figure 2 A system architecture 200 applicable to the present application is shown, and the system architecture 200 can be applied to the scenarios of public cloud, private cloud or terminal cloud. The system architecture 200 includes a cloud management platform 201, one or more computing nodes 203 and a cloud network 202. The cloud management platform 200 can communicate with one or more computing nodes 203 through the cloud network 202, so as to configure and manage these computing nodes. The computing nodes can also be communicated and connected through the cloud network. The computing node 203 can be a physical device, such as a server or a terminal device. The terminal device can be a handheld device with a wireless connection function, or other processing device connected to a wireless modem. For example, it can be a mobile phone, a computer, a tablet computer, a personal digital assistant (PDA), a mobile Internet device (MID), a wearable device and an e-book reader, etc.; it can also be a portable, pocket-sized, handheld, computer-built-in or vehicle-mounted mobile device.

[0070] Figure 2 The computing node 203 may include Figure 1 Some or all components of the computing node 100 in. Multiple virtual machines supporting different instruction set architectures, namely, a master architecture virtual machine and a slave architecture virtual machine, can be run on the computing node 203. Different instruction set architectures include a master instruction set architecture (referred to as the master architecture) and a slave instruction set architecture (referred to as the slave architecture). The master architecture and the slave architecture can be any two instruction set architectures, such as any two of the X86 architecture, the ARM architecture, and the RISC-V architecture. The RISC-V architecture is an open source instruction set architecture based on reduced instruction set computing (RISC).

[0071] Among them, computer instructions are instructions and commands that direct the work of the machine, and the program is a series of instructions arranged in a certain order. The process of executing the program is the working process of the computer. The instruction set is a set of instructions used in the CPU to calculate and control the computer system. Each CPU specifies a series of instruction systems that match its hardware circuits when it is designed. The strength of instructions is also an important indicator of the CPU. The instruction set is one of the most effective tools to improve the efficiency of the microprocessor. Common instruction set architectures ISA include complex instruction set computing (CISC) and reduced instruction set computing (RISC). Among them, the typical representative of CISC is X86, and the typical representatives of RISC are the advanced reduced instruction set machine (ARM) architecture and the microprocessor without interlocked pipelined stages (MIPS) architecture.

[0072] The virtualization platform software is located between the virtual machine and the hardware layer and is used to manage and control the virtual machines running on it. The virtualization platform may include Figure 1 The virtualization platform software can run virtual machines that support different instruction set architectures, such as Figure 2The master architecture virtual machine and the slave architecture virtual machine in the computing node 203. The computing node 203 may have only run the master architecture virtual machine before. When the user needs a virtual machine that supports the new instruction set, the user can send a request to the computing node 203 through the cloud management platform 201 to create a slave architecture virtual machine, and the slave architecture virtual machine supports the new instruction set architecture. After receiving the request, the virtualization platform software can create and start the slave architecture virtual machine, and the slave architecture virtual machine runs an operating system and application that supports the slave architecture instruction set. The user only needs to start the virtual machine that supports the new instruction set on the original virtualization platform, and there is no need to completely replace the application and operating system of the master architecture virtual machine, so as to achieve the compatibility of the computing node with virtual machines of different instruction set architectures, which reduces the cost compared to full replacement.

[0073] In order for the slave architecture virtual machine to run normally, the key is to enable the instructions of the slave architecture virtual machine to be executed by the processor at the hardware layer, especially the handling of exceptions or interrupts under the slave architecture.

[0074] Since the processor only supports a single instruction set architecture (primary architecture), it is unable to recognize the meaning of the instructions of the slave architecture virtual machine. Therefore, the existing instruction translation scheme is to use an emulator to translate the instructions of the slave architecture virtual machine into instructions under the primary instruction set architecture, and then the emulator processes the translated instructions through pure software simulation. The emulator can be implemented at the host machine layer. For an instruction of the slave architecture virtual machine, the instruction translation scheme first translates the instruction of the slave architecture virtual machine into an abstract internal representation of the emulator, and then the emulator translates the abstract internal representation into a semantically equivalent instruction of the primary architecture. The translated instructions of the primary architecture have the same semantics as the instructions of the slave architecture virtual machine.

[0075] The execution process of the translated master architecture instruction is related to the instruction type of the slave architecture virtual machine. The types of instructions before and after translation are the same, that is, if the instruction of the slave architecture virtual machine is a non-privileged instruction, then the translated master architecture instruction is also a non-privileged instruction; if the instruction of the slave architecture virtual machine is a privileged instruction, then the translated master architecture instruction is also a privileged instruction. If the instruction of the slave architecture virtual machine is a non-privileged instruction, the translated master architecture instruction can be directly executed to achieve the simulation effect; if the instruction of the slave architecture virtual machine is a privileged instruction, the simulator is required to assist in processing the translated master architecture instruction. Among them, privileged instructions are a type of instructions related to system security. In a computer system, some instructions are related to system security, such as memory clearing instructions. If a program can use such instructions, it means that the program can arbitrarily clear the memory data of other programs. Therefore, the computer system classifies instructions and divides them into privileged instructions (such as memory clearing instructions) and non-privileged instructions (such as ordinary operation instructions). Privileged instructions are instructions with special permissions, which are used to call system functions or system software, such as clearing memory, setting clocks, allocating system resources, modifying the segment table and page table of virtual memory, and modifying user access rights.

[0076] If the translated master architecture instruction is a privileged instruction and is used to request access to virtual hardware resources, the emulator supporting the master architecture needs to simulate the execution process of the slave architecture virtual machine accessing the virtual hardware resources according to the slave architecture hardware device specification. The slave architecture hardware device specification and the master architecture hardware device specification are different due to the different instruction set architectures they support.

[0077] If the translated master architecture instruction further triggers an exception, the emulator under the master architecture simulates the execution process of handling the exception under the slave architecture through software simulation. It should be noted that in the instruction translation scheme, since the instructions of the slave architecture virtual machine are directly translated by the emulator and processed through software simulation, the emulator is implemented in the host machine and is a fully simulated virtualization scheme. It does not use the hardware acceleration module in the hardware-assisted virtualization scheme (such as the page table and interrupt controller used for virtual address to physical address conversion in the MMU), so the hardware resources presented to the virtual machine are all purely software-implemented. In the hardware-assisted virtualization scheme, the virtual machine monitor is required to participate in handling exceptions or interrupts, while the instruction translation scheme implemented by the emulator does not involve the problem of requiring the master architecture virtual machine monitor to identify and handle exceptions or interrupts triggered under the slave architecture. However, the instruction translation scheme will first encounter the problem of an increase in the number of instructions. Multiple main architecture instructions are required to achieve semantics equivalent to those of the slave architecture virtual machine instructions. For example, after an instruction of a slave architecture virtual machine is translated, multiple main architecture instructions will be obtained to represent the same semantics as the instruction of the slave architecture virtual machine. Secondly, the emulator needs to determine whether the translated main architecture instruction triggers an exception, and the emulator requires additional judgment logic. Furthermore, the emulator simulates the processing logic of the slave architecture virtual machine accessing virtual hardware resources through full software simulation, and the performance of this full software simulation method is poor.

[0078] Each manufacturer has proposed hardware-assisted virtualization technology for its own instruction set architecture. Hardware-assisted virtualization technology uses hardware modules to accelerate the process of virtual machines accessing virtual hardware resources and improve the performance of virtual machines. For example, extended page tables (EPT) are used to accelerate the conversion process from GPA to HPA; The VT-X (virtualization technology) technology introduces new privileged instructions and operation modes to accelerate the execution of privileged instructions of virtual machines; the interrupt controller supports processing virtual interrupts, which can accelerate the processing of interrupts to virtual machines. When an exception or interrupt is triggered in a virtualization scenario using hardware-assisted virtualization technology, the virtual machine monitor handles the exception or interrupt. The processor reads the exception or interrupt information registered in the register by the virtual machine monitor from the hardware register and notifies the virtual machine monitor to handle the exception or interrupt. The virtual machine monitor needs to handle the exception or interrupt based on the status information of the exception or interrupt.

[0079] The status information of the exception includes the type of exception, the instruction that triggered the exception, and the address that triggered the exception. An exception is a processing request after an instruction fails to execute. For example, one type of exception is a page fault exception, which is an exception that occurs when the virtual machine accesses virtual memory. If the virtual machine monitor needs to handle the exception, it needs to obtain the address of the virtual memory that triggers the page fault exception. The instruction that triggers the exception refers to the instruction that is currently being executed when the exception occurs. For example, one type of exception is an illegal instruction exception, and the illegal instruction is the instruction that triggers the exception. When the virtual machine monitor obtains the instruction that triggers the exception, it can know which instruction triggered the exception so as to handle the exception.

[0080] The status information of the interrupt includes the type of interrupt. Common interrupt types include inter-core interrupts, local interrupts (including clock interrupts, performance monitoring interrupts (PMI), and external interrupts (mainly interrupts triggered by peripherals such as disks and network cards). For example, when a slave architecture virtual machine executes an instruction, if the slave architecture processing logic receives an external interrupt from an external device, or an inter-core interrupt sent between virtual processors of the slave architecture virtual machine, these interrupts can be called slave architecture interrupts, that is, interrupts are triggered in the software or hardware environment of the slave architecture.

[0081] The virtual machine monitor needs to obtain the type of exception or interrupt in order to handle it separately for the specific type. The encoding used to represent the type of exception or interrupt has different definitions under the specifications of different instruction set architectures. For the same type of interrupt or exception, the encoding under different instruction set architectures is different, for example, the encoding value may be different, and the format of storing the encoding value may also be different. The format of storing the encoding value can be understood as the different fields and the number of fields storing the encoding value. For example, under the RISC-V architecture, the encoding and encoding format representing the stage 2 instruction page fault exception is "interrupt=(0), Exception Code=(20)", the encoding value is 0 and 20, and it is represented by the two fields of interrupt and Exception Code. The encoding and encoding format of the stage 2 instruction page fault exception under the ARM architecture is "RES0=(0x0), EC=(0x20), IL=(0x1), ISS=(0x8E)", the encoding value is 0x0, 0x20, 0x1 and 0x8E, and these encoding values ​​are recorded by the four fields of RES0, EC, IL and ISS.

[0082] Furthermore, in different instruction set architectures, the registers storing the status information of exceptions or interrupts are also different. For example, the status information of exceptions or interrupts in the ARM architecture is stored in registers that comply with the ARM architecture specification; the status information of exceptions or interrupts in the RISC-V architecture is stored in registers that comply with the RISC-V architecture specification. A virtual machine monitor that supports the ARM architecture obtains the code from a register that complies with the ARM architecture specification, and a virtual machine monitor that supports the RISC-V architecture obtains the code from a register that complies with the RISC-V architecture specification, and determines the specific type of exception or interrupt and handles different types separately.

[0083] Therefore, in a system that supports heterogeneous instruction set architecture virtual machines, when an interrupt or exception occurs in a slave architecture virtual machine, the code representing the type of interrupt or exception cannot be recognized by the master architecture virtual machine monitor that supports the master instruction set architecture, and the master architecture virtual machine monitor cannot accurately identify the specific type of the interrupt or exception. In addition, the master architecture virtual machine monitor cannot obtain the status information required to handle the exception or interrupt. This results in the master architecture virtual machine monitor being unable to handle the exception or interrupt triggered by the slave architecture virtual machine. The lack of exception or interrupt processing results in the inability of hardware-assisted virtualization technology to be applied in scenarios that support heterogeneous instruction set architecture virtual machines.

[0084] In the system architecture provided by the embodiment of the present application, the processor (such as the processor of the computing node 203) can support multiple instruction set architectures, and can directly execute the instructions of the main architecture instruction set and the instructions of the slave architecture instruction set. Therefore, there is no need to perform instruction translation on the slave architecture instructions, and the instruction expansion problem caused by instruction translation is avoided. When an exception or interruption is triggered from the architecture, the present application converts the encoding of the exception or interruption according to the stored mapping relationship, and the converted encoding meets the main architecture specification, and the converted encoding is the definition of this type of exception or interruption in the main architecture specification. The present application finds the encoding for representing the type of this type of exception or interruption in the main architecture specification, so that the virtual machine monitor of the main architecture can identify the exception or interruption under the slave architecture, and the hardware module supporting hardware-assisted virtualization under the main architecture can be reused for processing.

[0085] Figure 3 Another structural diagram of the computing node 300 provided in an embodiment of the present application. Figure 3 The computing node 300 shown may be Figure 1 and Figure 2 Some or all of the compute nodes in .

[0086] The computing node 300 can be divided into a software layer and a hardware layer. The hardware layer includes a processor 308 and an interrupt controller 312; the software layer includes a master architecture virtual machine 301, a slave architecture virtual machine 302, and a virtual machine monitor 303. The instruction set architectures supported by the master architecture virtual machine and the slave architecture virtual machine running on the computing node 300 are different. The master architecture virtual machine 301 supports the master instruction set architecture (master architecture), and the slave architecture virtual machine 302 supports the slave instruction set architecture (slave architecture). The processes executed in the slave architecture virtual machine 302 and the processes running in the master architecture virtual machine 301 also support different instruction set architectures. The virtual machine monitor 303 runs under the master architecture and supports the master instruction set architecture. The operating environment of the slave architecture virtual machine 302 is prepared and started by the virtual machine monitor 303 of the master architecture.

[0087] The processor 308 includes a master architecture processing logic 308 and a slave architecture processing logic 309. The processor 308 may be a multi-core processor. The master architecture processing logic 308 or the slave architecture processing logic 309 may be a processing core, or a CPU core. The master architecture processing logic 308 may be referred to as a master processing core, and the slave architecture processing logic 309 may be referred to as a slave processing core. The processing logic may also be referred to as a logical core, which is a core at the logical level within the same physical core. For the relationship between the master architecture processing logic and the slave architecture processing logic in a multi-core processor, please refer to the following Fig.10 and its corresponding description.

[0088] The address space (e.g., shared memory) or register that can be accessed by the master architecture processing logic 309 and the slave architecture processing logic 310 can be used as a communication channel 311 between the master architecture and the slave architecture. The part of the processor 308 that can be used to execute instructions of the master instruction set architecture (master architecture instructions) is the master architecture processing logic 309, and the part that can be used to execute instructions of the slave instruction set architecture (slave architecture instructions) is the slave architecture processing logic 310. Therefore, the processor 308 can recognize the meaning of instructions of the two instruction set architectures without translating the slave architecture instructions into master architecture instructions that can be recognized by the processor. For instructions that do not trigger interrupts or exceptions, both privileged instructions and non-privileged instructions can be directly processed by the slave architecture processing logic 309.

[0089] When the slave architecture virtual machine 302 triggers an exception or interruption, the slave architecture processing logic 310 suspends the execution of the slave architecture virtual machine 302, the slave architecture processing logic 310 stores the status information of the exception or interruption in the communication channel 311 between the master and slave architectures, the slave architecture processing logic 310 notifies the virtual machine monitor 303 of the master architecture to handle the exception or interruption, and waits for the virtual machine monitor 303 to handle the interruption or exception. (Step ①) The slave architecture processing logic is a processing unit that supports the slave architecture, and the master architecture processing logic is a processing unit that supports the master architecture.

[0090] It should be noted that the interrupt triggered from the architecture virtual machine may include the interrupt received from the architecture processing logic 310 and the virtual interrupt generated from the architecture virtual machine; the interrupt received from the architecture processing logic 310 is a physical interrupt sent from the main architecture interrupt controller 312 to the slave architecture processing logic 310 during the operation of the slave architecture virtual machine 302, or is called a hardware interrupt; the virtual interrupt generated from the architecture virtual machine is an interrupt triggered by the virtual processor of the slave architecture virtual machine, such as an inter-core interrupt sent from the virtual processor VCPU1 to VCPU2. The exception triggered from the architecture virtual machine 302 refers to the exception triggered during the operation of the slave architecture virtual machine 302, such as a page fault exception triggered by the slave architecture virtual machine 302 accessing the virtual memory or an illegal instruction exception triggered by the slave architecture virtual machine 302 executing an illegal instruction.

[0091] After the virtual machine monitor 303 receives the notification, the conversion module 304 obtains the status information of the exception or interrupt triggered from the slave architecture from the communication channel 311. At this time, in the status information of the exception or interrupt obtained by the conversion module 304, the code indicating the type of the exception or interrupt complies with the slave architecture specification and does not comply with the master architecture specification. The conversion module 304 finds the code used to represent the type of interrupt or exception in the master architecture specification according to the mapping table, wherein the mapping table stores the correspondence between the codes representing different types of exceptions or interrupts in the master architecture specification and the codes representing different types of exceptions or interrupts in the slave architecture specification. Then the conversion module 304 saves the code used to represent the type of interrupt or exception found in the master architecture specification, the address that triggers the exception, and the instruction that triggers the exception in the master architecture hardware register or memory accessible to the virtual machine monitor 303. (Step ②) Among them, the master architecture hardware register refers to the hardware register that supports the master architecture hardware specification.

[0092] The simulation module 305 obtains the status information from the hardware register or memory of the main architecture, and determines whether the slave architecture virtual machine trigger is an exception or an interrupt and the specific type of interrupt or exception according to the code in the status information. (Step ③)

[0093] If the slave architecture virtual machine triggers an interrupt, the interrupt simulation module 307 obtains the specific type of the interrupt from the master architecture hardware register or memory, and then uses the master architecture interrupt controller 312 to process the interrupt of this type. (Step ④)

[0094] The interrupt simulation module 307 sends a virtual interrupt to the slave architecture virtual machine by simulating the behavior of the interrupt controller defined by the slave architecture specification, such as managing the mapping relationship and priority relationship of the virtual interrupt, and the delivery process of the virtual interrupt. The interrupt simulation module 307 can be used to manage the virtual interrupt mapping relationship, which includes the mapping relationship between the virtual interrupt of the slave architecture virtual machine and the slave architecture virtual processor, and the mapping relationship between the slave architecture virtual processor and the physical processor (or physical core). The interrupt simulation module 307 can manage the priority relationship of multiple virtual interrupts for each slave architecture virtual processor. When there are multiple virtual interrupts that need to be sent to the virtual processor, the interrupt simulation module 307 obtains the virtual interrupt with the highest priority according to the priority relationship. The interrupt simulation module 307 obtains the physical processor (or physical core) where the slave architecture virtual processor is located according to the virtual interrupt mapping relationship. The interrupt is sent to the physical processor (or physical core) through the main architecture interrupt controller 312. The physical processor stores the information of the virtual interrupt in the hardware register of the slave architecture processing logic to complete the delivery of the virtual interrupt. The information of the virtual interrupt includes: the type of virtual interrupt.

[0095] If the slave virtual machine triggers an exception, the exception simulation module 306 obtains the specific type of the exception from the master hardware register or memory, and uses the master processing logic 309 and the hardware-assisted virtualization capability to process the slave virtual machine exception. (Step ⑤)

[0096] The exception simulation module 306 is used to simulate the exceptions triggered during the operation of the slave architecture virtual machine. According to the corresponding situations of the master architecture exceptions and the slave architecture exceptions, there are three types:

[0097] 1). If the main architecture virtual machine monitor 303 can handle exceptions of the same type as those of the slave architecture (the main architecture exception corresponding to the slave architecture exception can be found in the mapping table), such as memory access exceptions, the exception handling method of the main architecture virtual machine monitor can be directly reused, including software logic and hardware-assisted virtualization capabilities on the hardware.

[0098] 2). If the main architecture virtual machine monitor 303 can handle exceptions similar to those of the slave architecture (the main architecture exceptions corresponding to the slave architecture exceptions can be found in the mapping table), such as illegal instruction exceptions triggered by TLB refresh instructions and illegal instruction exceptions triggered by debug instructions, the exception simulation module 306 can read the status information of the converted exceptions and obtain the information required to simulate the exception type, such as the slave architecture instruction that triggers the exception and the parameter information attached to the slave architecture instruction. Then select the instructions or exception handling modules with similar functions of the main architecture, and fill in the information required for the exception simulation according to the specifications of the main architecture instructions or the input parameter specifications of the exception handling module, and finally call the instructions or exception handling module of the main architecture for processing.

[0099] 3). If there is no exception type that is the same or similar to the slave architecture exception in the main architecture virtual machine monitor 303 (the main architecture exception corresponding to the slave architecture exception is not found in the mapping table), such as exceptions triggered by hypercall instructions, exceptions triggered by privileged instructions unique to the slave architecture, and exceptions in accessing the address space of the virtual device, the exception simulation module 306 uses pure software simulation to handle it according to the hardware specifications of the slave architecture.

[0100] After the simulation module 305 completes the processing of the exception or interruption of the slave architecture virtual machine, it stores the processing result in the communication channel 311 and notifies the slave architecture processing logic 310 to resume execution. (Step ⑥)

[0101] After the slave virtual machine is resumed, the processing result is obtained from the communication channel 311 and the subsequent instructions are continued to be executed. (Step ⑦)

[0102] The following takes the ARM architecture as the main architecture and the RISC-V architecture as the slave architecture as an example to introduce the method for running a virtual machine under a heterogeneous instruction set architecture provided by the present application. The method can be applied to the computing node 400. The execution flow of the method is as follows: Figure 5 and Figure 6 shown. Figure 4 FIG. 4 shows the structure of computing node 400. The structure of computing node 400 is similar to Figure 3 The illustrated computing node 300 is similar.

[0103] The hardware layer of the computing node 400 includes a processor 411 , an ARM interrupt controller, and a shared memory 412 .

[0104] The processor 411 may include an ARM processing logic 409 capable of processing instructions of the ARM instruction set and a RISC-V processing logic 410 capable of processing instructions of the RISC-V instruction set. Since the hardware registers used to store the status information of exceptions or interrupts under different instruction set architectures are different, the processor 411 in this application also includes one or more ARM registers 413 that comply with the ARM architecture specification, which are used to store the type of exceptions or interrupts occurring under the ARM architecture, the address that triggers the exception, and the instruction that triggers the exception; and one or more RISC-V registers 414 that comply with the RISC-V architecture specification, which are used to store the type of exceptions or interrupts under the RISC-V architecture, the address that triggers the exception, and the instruction that triggers the exception. Among them, the exception or interrupt under a certain instruction set architecture or the exception or interrupt triggered under a certain instruction set architecture refers to an exception triggered by a virtual machine that supports the instruction set architecture or an interrupt received by a processing logic that supports the instruction set architecture. The RISC-V register 414 or ARM register 413 storing the status information of the exception or interrupt may be specifically a status control register (Control and Status Registers, CSRs). There may be multiple status control registers, which are used to store the type of exception or interrupt, the instruction that triggers the exception, and the address that triggers the exception.

[0105] Since the ARM processing logic 409 cannot directly read the RISC-V register 414 to obtain the status information of the exception or interrupt under the RISC-V architecture, the embodiment of the present application uses the shared memory 412 to transmit the status information of the exception or interrupt under the RISC-V architecture. The shared memory 412 can be accessed by the ARM processing logic and the RISC-V processing logic, and is used to transmit the type of the exception or interrupt under the RISC-V architecture, the address that triggers the exception, and the instruction that triggers the exception, as well as the processing result of the exception or interrupt by the ARM Hypervisor and the hardware under the ARM architecture.

[0106] For the state control register 414, floating-point register and general register under the RISC-V architecture, the design specification of the shared memory 412 defines the address range for storing the values ​​of each register. In other words, the type of exception or interrupt under the RISC-V architecture, the address that triggers the exception and the instruction that triggers the exception, these data stored in one or more state registers, and the data stored in the floating-point register and the general register are fixed in the storage address in the shared memory 412. And the ARM processing logic 409 can obtain the type of exception or interrupt under the RISC-V architecture, the address that triggers the exception and the instruction that triggers the exception from the corresponding storage address in the shared memory 412. In the embodiment of the present application, the ARMHypervisor 402 specifically obtains these data from the shared memory 412.

[0107] The software layer of the computing node 400 includes an ARM virtual machine 401, a RISC-V virtual machine 403, and an ARM Hypervisor 402. The RISC-V virtual machine 403 supports the RISC-V instruction set architecture, the ARM virtual machine 401 supports the ARM instruction set architecture, and the ARM Hypervisor 402 supports the Hypervisor of the ARM instruction set architecture.

[0108] In the present application, the RISC-V conversion module 404 in the ARM Hypervisor 402 can determine the type of exception or interrupt under the ARM architecture corresponding to the type of exception or interrupt triggered under the RISC-V architecture according to the ARM&RISC-V mapping table, and store the status information of the exception or interrupt under the RISC-V architecture in the corresponding one or more ARM registers 413.

[0109] The ARM&RISC-V mapping table may include an exception mapping table and an interrupt mapping table.

[0110] The exception mapping table is used to record the corresponding relationship between the encoding of one or more exceptions under the RISC-V architecture and the encoding of one or more exceptions under the ARM architecture. Each corresponding relationship recorded in the exception mapping table is the encoding of a class of exceptions in the ARM specification and the encoding of the class of exceptions in the RISC-V specification. Among them, the encoding of the exception is used to indicate the type of exception, which is a unique encoding of a type of exception under an instruction set architecture to distinguish different types of exceptions. The encoding of a class of exceptions under the RISC-V architecture refers to the type used to indicate the type of exception in the RISC-V instruction set specification; the encoding of a class of exceptions under the ARM architecture refers to the type used to indicate the type of exception in the ARM instruction set specification. Therefore, the RISC-V conversion module 404 can convert the encoding of the exception under the slave architecture into the encoding of the exception that can be recognized by the ARM Hypervisor 402 according to the exception mapping table, and the ARM Hypervisor 402 can identify the specific type of the exception under the slave architecture.

[0111] The exception mapping table is also used to record the correspondence between one or more RISC-V registers 414 and one or more ARM registers 413. For example, the correspondence between the register storing the instruction that triggers the exception under the RISC-V architecture and the state control register for storing the instruction that triggers the exception under the ARM architecture, the correspondence between the register storing the address that triggers the exception under the RISC-V architecture and the state control register for storing the address that triggers the exception under the ARM architecture, and the correspondence between the register storing the exception code under the RISC-V architecture and the register storing the exception code under the ARM architecture. Therefore, the state information required for handling the exception can be stored in the ARM register 413, so that the ARM Hypervisor 402 obtains the state information required for handling the exception from the ARM register 413 and handles the exception.

[0112] The interrupt mapping table is used to record the corresponding relationship between the encoding of one or more types of interrupts under the RISC-V architecture and the encoding of one or more types of interrupts under the ARM architecture. Each corresponding relationship recorded in the interrupt mapping table is the encoding of a class of interrupts in the ARM specification and the encoding of the class of interrupts in the RISC-V specification. Among them, the encoding of the interrupt indicates the type of interrupt, which is the only encoding of a class of interrupts under an instruction set architecture to distinguish different types of interrupts. The encoding of a class of interrupts under the RISC-V architecture refers to the type used to indicate the type of interrupt in the RISC-V instruction set specification; the encoding of a class of interrupts under the ARM architecture refers to the type used to indicate the type of interrupt in the ARM instruction set specification. Therefore, the RISC-V conversion module 404 can convert the encoding of the interrupt under the slave architecture into the encoding of the interrupt that can be recognized by the ARM Hypervisor 402 according to the interrupt mapping table, and the ARM Hypervisor 402 can identify the specific type of interrupt under the slave architecture.

[0113] The interrupt mapping table is also used to record the correspondence between the RISC-V register 414 for storing interrupt codes under the RISC-V architecture and the ARM register 413 for storing interrupt codes under the ARM architecture. Therefore, the state information required for processing the interrupt can be stored in the ARM register 413, so that the ARM Hypervisor 402 obtains the state information required for processing the interrupt from the ARM register 413 and processes the interrupt.

[0114] Figure 5 Indicates the process of handling exceptions triggered by the RISC-V virtual machine.

[0115] Step 501: When the RISC-V virtual machine triggers an exception, the processor 411 notifies the ARM Hypervisor to handle the exception;

[0116] When the RISC-V virtual machine requests to access the GVA to obtain data stored in the memory, since the virtual machine will eventually obtain data based on the HPA, the MMU will convert the GVA into a GPA, and then convert the GPA into an HPA. If an exception occurs during the conversion process from GPA to HPA, such as requesting access to an illegal virtual address or requesting access to a legal virtual address but the virtual address has not yet been assigned a physical page (no GPA to HPA mapping table has been established), a page fault exception (Page Fault) may be triggered. Since the ARM Hypervisor 402 does not support the RISC-V architecture and does not have an MMU that supports the RISC-V specification, this exception cannot be handled under the RISC-V architecture and needs to be handled by the ARM Hypervisor 402.

[0117] Step 502: The RISC-V virtual machine suspends execution and waits for the ARM Hypervisor to handle the exception. The RISC-V processing logic 410 saves the system state in the shared memory.

[0118] The system status includes information in the status control register, general register, and floating-point register. General registers and floating-point registers can store the running status information of the vCPU of the RISC-V virtual machine, such as the data generated during the instruction operation, the local variables temporarily applied by the system, and the intermediate results of floating-point calculations.

[0119] The code representing the exception type as a page fault exception and the virtual address (such as GVA) that triggers the page fault exception can be stored in different RISC-V state control registers (RISC-V register 414) respectively. The address that triggers the page fault exception refers to the virtual address that the RISC-V virtual machine 403 requests to access when the page fault exception is triggered.

[0120] The shared memory 412 is provided with storage addresses for the information in the state control register, the general register and the floating point register, for example, the address range of 0x1000-0x13e0 with respect to the starting address of the shared memory 412 is used to store the information in the general register and the floating point register; the address range of 0x2000-0x11140 with respect to the starting address of the shared memory is used to store the information in one or more state control registers, that is, to store the encoding of the page fault exception and the address that triggers the page fault exception. Specifically, an address mapping table is provided in the shared memory 412, and the addresses of the state control register, the general register and the floating point register are stored in the address mapping table. The ARM Hypervisor can read the value in the register or update the value in the register according to the address of each register recorded in the address mapping table.

[0121] Step 503: ARM Hypervisor 402 obtains abnormal status information from shared memory 412;

[0122] The RISC-V virtual machine generates a page fault exception. After the processor 411 notifies the ARM Hypervisor 402 to handle the page fault exception, the ARM Hypervisor writes an exception handling function entry address in the hardware register under the ARM architecture. The processor 411 reads the exception handling function entry address from the hardware register and executes the operation of obtaining the exception status information from the shared memory 412.

[0123] The ARM Hypervisor obtains the encoding representing the type of exception triggered by the RISC-V virtual machine based on the address of the status control register (RISC-V register 414) recorded in the shared memory 412.

[0124] Step 504: The RISC-V conversion module 404 searches for the exception type under the ARM architecture corresponding to the exception type under the RISC-V architecture according to the exception mapping table.

[0125] Since the RISC-V architecture and the ARM architecture have different definitions for the encoding representing the type of exception, the encoding used to represent the type of exception triggered by the RISC-V virtual machine does not conform to the specifications of the ARM architecture, so the ARM Hypervisor 402 cannot directly identify the type of exception triggered by the RISC-V virtual machine based on the encoding of the exception obtained from the shared memory. Therefore, the RISC-V conversion module 404 finds the exception encoding corresponding to the exception encoding that conforms to the RISC-V architecture specification and conforms to the definition of the ARM architecture specification according to the exception mapping table, thereby identifying the type of exception triggered by the RISC-V virtual machine. The RISC-V architecture and the ARM architecture mentioned here have different definitions for the encoding representing the type of exception, which means that for the same type of exception, the specifications of the two instruction set architectures use different encoding values ​​to represent it, and the encoding format is also different. In the RISC-V architecture specification, a two-field format is used to represent the exception, which is different from the definition of the format of the encoding of the page fault exception in the RISC-V architecture specification. The ARM architecture specification uses four fields to represent the page fault exception.

[0126] In the RISC-V architecture specification, the encoding used to represent the types of exceptions and interrupts is stored in the cause register. Figure 7The figure shows the structure of the scale register. When the interrupt value of the scale register bit 1 is 1, it indicates an interrupt, and when the interrupt value is 0, it indicates an exception. The exception code of the scale register bit 0 is used to indicate the specific type of exception or interrupt. Taking the stage 2 instruction page fault exception as an example, the interrupt value of the scale register bit 1 is 0, and the Exception Code value of the scale register bit 0 is 20, which means that the encoding of the stage 2 instruction page fault exception is interrupt = (0), Exception Code = (20).

[0127] In the ARM architecture specification, the code used to represent the type of exception or interrupt is stored in the esr_el2 register. The structure of the esr_el2 register is as follows Figure 8 As shown. RES0 is a reserved field, and its value is usually 0; the EC (Exception Class) field indicates the exception class, the IL (Instruction Length for synchronous exceptions) indicates the length of the instruction, and the ISS (Instruction Specific Syndrome) field is used to record the subclasses under the exception class and some special fields. Taking the page fault exception as an example, the encoding of the stage 2 instruction page fault exception in the ARM architecture is "RES0 = (0x0), EC = (0x20), IL = (0x1), ISS = (0x8E)".

[0128] In the RISC-V architecture specification, the register used to store the address that triggers the exception is the htval register. In the ARM architecture specification, the register used to store the address that triggers the exception is the hpfar_el2 register.

[0129] The scause register, esr_el2 register, htval register, and hpfar_el2 register are status control registers used to store different information.

[0130] The exception mapping table records the correspondence between the encoding of multiple types of exceptions in the RISC-V architecture and the encoding of multiple types of exceptions in the ARM architecture. The exception encoding code indicates the type of exception. In the table, an exception encoding in the RISC-V architecture corresponds to an exception encoding in the ARM architecture. Each of the multiple correspondences represents the correspondence between the encoding of a type of exception in the RISC-V architecture and the encoding of the same type of exception in the ARM architecture.

[0131] Taking the stage 2 instruction page fault exception as an example, the exception mapping table records the correspondence between the exception code "interrupt = (0), Exception Code = (20)" and the exception code "RES0 = (0x0), EC = (0x20), EL = (0x1), ISS = (0x8E)".

[0132] The RISC-V conversion module 404 obtains the code "interrupt = (0), Exception Code = (20)" of the stage 2 instruction page fault exception under the RISC-V architecture from the shared memory 412, and finds the code "RES0 = (0x0), EC = (0x20), EL = (0x1), ISS = (0x8E)" corresponding to the code "interrupt = (0), Exception Code = (20)" according to the exception mapping table. The code "RES0 = (0x0), EC = (0x20), EL = (0x1), ISS = (0x8E)" complies with the ARM architecture specification, so the ARM Hypervisor 402 can identify that the exception type triggered under the RISC-V architecture is the stage 2 instruction page fault exception based on the code.

[0133] Step 505 , the exception simulation module 406 writes the converted exception code, the instruction triggering the exception, and the address triggering the exception into the corresponding ARM register or into the memory accessible to the ARM Hypervisor.

[0134] In one implementation, considering that the changes to the original code of the ARM architecture should be as small as possible to avoid too many invasive modifications, the conversion module in the ARM Hypervisor writes the converted exception code, the instruction that triggers the exception, and the address that triggers the exception into the ARM register, so that the exception simulation module 406 in the ARM Hypervisor can obtain the above information required for handling the exception from the ARM register.

[0135] The exception mapping table records the correspondence between the registers for storing exception codes under the RISC-V architecture and the registers for storing exception codes under the ARM architecture, as well as the correspondence between the registers for storing the addresses for triggering exceptions under the RISC-V architecture and the registers for storing exception codes under the ARM architecture. Taking the stage 2 instruction page fault exception as an example, the exception mapping table records the correspondence between the cause register and the esr_el2 register, as well as the correspondence between the htval register and the hpfar_el2 register. Therefore, the exception simulation module 406 can write the code corresponding to the code stored in the cause register to the esr el2 register, that is, write the code "RES0 = (0x0), EC = (0x20), EL = (0x1), ISS = (0x8E)" to the esr_el2 register; and can write the value in the htval register (the address that triggers the exception) obtained from the shared memory to the hpfar_el2 register. Among them, the code and the address that triggers the exception are written to the corresponding fields in the register according to the specifications of the ARM architecture.

[0136] There is a special scenario in the page fault exception, which is the page fault exception triggered by accessing the memory address space MMIO. To handle this type of exception, the ARM Hypervisor needs to obtain the instruction that triggers the exception. Under the RISC-V architecture, the instruction that triggers the exception is stored in the htinst register (a status control register). Since there is no register specifically used to store the instruction that triggers the exception corresponding to the htinst register on the ARM architecture, the ARM Hypervisor can store the information of the instruction that triggers the exception read from the shared memory of ARM&RISC-V in a general register or in the memory allocated to the ARM Hypervisor.

[0137] In another implementation, the ARM Hypervisor writes the converted exception code, the instruction triggering the exception, and the address triggering the exception into a memory accessible to the ARM Hypervisor, so that the exception simulation module 406 can directly obtain the information required for handling the exception.

[0138] Taking the illegal instruction exception triggered by the instruction when the RISC-V virtual machine executes the TLB refresh instruction or EBREAK as an example, the status information of the exception includes the type of exception, the instruction that triggers the exception, and the parameter information attached to the instruction (such as the address space identifier (ASID) and the virtual address range). The exception simulation module writes the above information into the register used to store this information under the ARM architecture or stores it in the memory according to the specifications of the ARM architecture.

[0139] Step 506: The ARM Hypervisor identifies and processes the exception according to the exception code;

[0140] The converted exception code is the code of the exception triggered by the RISC-V virtual machine under the ARM architecture. Therefore, the ARM Hypervisor identifies and handles the exception triggered by the RISC-V virtual machine according to the converted exception code.

[0141] Taking the page fault exception as an example, the exception simulation module 406 calls the data abort exception handling logic of the ARM Hypervisor to handle the page fault exception triggered by the virtual machine accessing the GVA under the RISC-V architecture. For example, if the page fault exception is caused by an exception in the conversion process from GPA to HPA, the ARM Hypervisor establishes a mapping relationship from GPA to HPA, where the mapping relationship can be recorded in the stage 2 address translation page table, which is used in the MMU under the ARM architecture to convert GPA to HPA. The processor executes the instruction that triggers the page fault exception again or re-accesses the address that triggers the page fault exception. At this time, the MMU can find the HPA through the re-established stage 2 address translation page table representing the mapping relationship from GPA to HPA, and obtain the data stored in the memory. Thus, the stage 2 address translation page table in the hardware-assisted virtualization technology is reused to accelerate the processing of accessing memory data.

[0142] For example, for exceptions triggered by TLB refresh instructions, ARM Hypervisor can use existing processing methods to complete the TLB refresh operation of the RISC-V virtual machine. For illegal instruction exceptions triggered by ECALL indicators, parse the ECALL instruction of the RISC-V architecture that triggers the exception, obtain the specific call type of the ECALL instruction, and the input parameters of the instruction. Use pure software simulation to simulate the execution of the ecall instruction of the RISC-V architecture.

[0143] For exceptions in the RISC-V architecture that do not have the same or similar exception handling functions in the ARM Hypervisor, such as exceptions triggered by ECALL instructions, exceptions triggered by privileged instructions unique to the RISC-V architecture, and exceptions to access to the address space of virtual devices. In the ARM Hypervisor, a pure software simulation method is used according to the hardware specifications of the RISC-V architecture to simulate RISC-V architecture exceptions. Taking the ECALL instruction exception as an example, this exception is triggered when an interface provided by the virtual machine monitor in the RISC-V architecture is called to complete a certain function. Since there is no virtual machine monitor that supports the RISC-V architecture in the system, and there is no such interface in the ARM Hypervisor. Then refer to the definition in the RISC-V architecture and implement an interface with the same function in the ARM Hypervisor.

[0144] Step 507: The ARM Hypervisor stores the result of processing the exception in the shared memory and passes it to the RISC-V virtual machine.

[0145] For a page fault exception, the processing result is the data in the memory that the RISC-V virtual machine wants to access when the page fault exception is triggered. The ARM Hypervisor stores the data that the RISC-V virtual machine wants to access in the shared memory and passes it to the RISC-V virtual machine. The RISC processing logic restores the state of the RISC-V virtual machine and continues to run the RISC-V virtual machine.

[0146] Since for the same type of exception, the encoding used to represent the type of the exception in different instruction set architectures is different, the ARM Hypervisor cannot directly identify the type of exception triggered by the RISC-V virtual machine. In an embodiment of the present application, by storing a one-to-one correspondence between the encodings of the various types of exceptions defined by the ARM architecture and the encodings of the various types of exceptions defined by the RISC-V architecture, the ARM Hypervisor can find the encoding of the type of exception triggered by the RISC-V virtual machine under the ARM architecture, so that the ARM Hypervisor can identify the type of exception triggered by the RISC-V virtual machine. In other words, the ARM Hypervisor finds the ARM encoding representing the type of exception triggered by the RISC-V virtual machine based on the RISC-V encoding and the corresponding relationship used to represent the type of exception triggered by the RISC-V virtual machine; wherein, the RISC-V encoding is the encoding of this type of exception in the specification of the RISC-V architecture, the ARM encoding is the encoding of this type of exception in the specification of the ARM architecture, and the ARM Hypervisor can directly identify the ARM encoding to determine the type of exception.

[0147] Figure 6Indicates the processing flow of the interrupt triggered by the RISC-V virtual machine, including:

[0148] Step 601: When the RISC-V virtual machine triggers an interrupt, the processor 411 notifies the ARM Hypervisor to handle the interrupt;

[0149] In the architecture of the present application, since the hardware layer does not have an interrupt controller that complies with the RISC-V specification, when the ARM interrupt controller 409 sends a physical interrupt to the RISC-V processing logic 410 or the vCPU1 of the RISC-V virtual machine sends an inter-core interrupt to vCPU2, the RISC-V processing logic 410 needs to notify the ARM Hypervisor 402 to handle the interrupt. The interrupts triggered by the RISC-V virtual machine include physical interrupts received by the RISC-V processing logic 410 and virtual interrupts received by the virtual processor in the RISC-V virtual machine.

[0150] Step 602: The RISC-V virtual machine suspends execution and waits for the ARM Hypervisor to process the interrupt. The RISC-V processing logic saves the current system state in the shared memory.

[0151] The system state includes information stored in hardware registers such as general registers, floating-point registers, and state control registers under the RISC-V architecture. The state control register stores the state information of the interrupt required for processing the interrupt. Under the RISC-V architecture, the state control register (RISC-V register 414) is specifically a virtualization supervisor interrupt register (VSIP). The general registers and floating-point registers store the state information of the current vCPU of the RISC-V virtual machine, such as data during the instruction operation process, temporarily applied local variables, and intermediate results of floating-point calculations. The state information of the vCPU stored in the general registers and floating-point registers can be used when the RISC-V virtual machine 403 switches the vCPU.

[0152] The status information of the interrupt includes the type of the interrupt, specifically, includes a code representing the type of the interrupt, and the code complies with the RISC-V architecture specification. The RISC-V processing logic reads the code representing the interrupt type from the RISC-V state control register 414 and stores the code in the shared memory 412.

[0153] The shared memory 412 is provided with storage addresses for the information in the state control register, the general register and the floating point register. For example, the address range of 0x1000-0x13e0 with respect to the starting address of the shared memory 412 is used to store the information in the general register and the floating point register; the address range of 0x2000-0x11140 with respect to the starting address of the shared memory is used to store the information in one or more state control registers, that is, to store the code representing the type of interrupt. Specifically, an address mapping table is provided in the shared memory 412, and the addresses of the state control register, the general register and the floating point register are stored in the address mapping table. The ARM Hypervisor can read the value in the register or update the value in the register according to the address of each register recorded in the address mapping table.

[0154] Step 603: ARM Hypervisor obtains interrupt status information from the shared memory;

[0155] The ARM Hypervisor obtains the encoding representing the type of interrupt triggered by the RISC-V virtual machine based on the address of the status control register (RISC-V register 414) recorded in the shared memory 412.

[0156] Step 604: The RISC-V conversion module searches the interrupt mapping table for the interrupt type under the ARM architecture that corresponds to the interrupt type under the RISC-V architecture.

[0157] RISC-V interrupt types can be identified as clock interrupts, software interrupts, and external interrupts. Among them, inter-core interrupts are a type of software interrupts.

[0158] Since the RISC-V architecture and the ARM architecture have different definitions for the codes representing the types of interrupts, the codes used to represent the types of interrupts triggered by the RISC-V virtual machine do not conform to the specifications of the ARM architecture, so the ARM Hypervisor 402 cannot directly identify the type of interrupts triggered by the RISC-V virtual machine based on the codes of the interrupts obtained from the shared memory. Therefore, the RISC-V conversion module 404 finds the exception codes corresponding to the interrupt codes that conform to the RISC-V architecture specifications and conform to the ARM architecture specifications according to the interrupt mapping table, thereby identifying the type of interrupts triggered by the RISC-V virtual machine. The different definitions of the codes representing the types of interrupts in the RISC-V architecture and the ARM architecture mentioned here refer to the fact that for the same type of interrupts, the specifications of the two instruction set architectures use different coding values ​​to represent them, and the coding formats are also different.

[0159] The interrupt mapping table records the corresponding relationship between the codes of multiple types of interrupts under the RISC-V architecture and the codes of multiple types of interrupts under the ARM architecture. The interrupt code represents the type of interrupt. In the interrupt mapping table, the code of an interrupt under the RISC-V architecture corresponds to the code of an interrupt under the ARM architecture.

[0160] Step 605, write the converted interrupt code into the corresponding ARM register or into the memory accessible to the ARM Hypervisor.

[0161] In one implementation, considering that the changes to the original code of the ARM architecture should be as small as possible to avoid too many invasive modifications, the conversion module in the ARM Hypervisor writes the converted interrupt code into the ARM register so that the interrupt simulation module 407 in the ARM Hypervisor can obtain the above information required for handling the exception from the ARM register.

[0162] The interrupt mapping table also records the correspondence between the registers used to store interrupt codes in the RISC-V architecture and the registers used to store interrupt codes in the ARM architecture.

[0163] Step 606: The ARM Hypervisor identifies and processes the interrupt according to the converted interrupt code.

[0164] The converted interrupt code is the code of the interrupt triggered by the RISC-V virtual machine under the ARM architecture. Therefore, the ARM Hypervisor identifies and processes the interrupt triggered by the RISC-V virtual machine according to the converted interrupt code.

[0165] The interrupt simulation module obtains the number of the RISC-V virtual processor, obtains the physical processor or physical core where the virtual processor is located from the number of the virtual processor, and notifies the physical processor or physical core through the ARM interrupt controller. The interrupt simulation module maintains the mapping relationship between RISC-V virtual interrupts and RISC-V virtual processors, as well as the mapping relationship between RISC-V virtual processors and physical processors / physical cores.

[0166] The interrupt simulation module also maintains the priority relationship of RISC-V virtual interrupts for each RISC-V virtual processor. When multiple interrupts are sent to the virtual processor at the same time, the interrupt simulation module obtains the interrupt with the highest priority based on the maintenance priority relationship. The interrupt simulation module obtains the physical processor / physical core where the RISC-V virtual processor is located based on the virtual interrupt mapping relationship. The interrupt notification is sent to the physical processor / physical core through the ARM interrupt controller. The ARM Hypervisor sets the interrupt with the highest priority to the hardware register of the RISC-V processor logic to complete the delivery of the virtual interrupt.

[0167] When the ARM Hypervisor recognizes that the RISC-V virtual machine triggers an inter-core interrupt, the interrupt simulation module parses the obtained interrupt status information and recognizes that it is an inter-core interrupt and is to be sent to VCPU2. The interrupt simulation module knows that vCPU2 is located on physical core 2 based on the virtual interrupt mapping relationship, and then sends the inter-core interrupt to physical core 2 through the ARM interrupt controller, thereby completing the inter-core interrupt triggered by the RISC-V virtual machine.

[0168] When the ARM Hypervisor recognizes that the RISC-V virtual machine triggers a clock interrupt, the ARM Hypervisor sets the Supervisor-level Time Interrupt Pending (STIP) of the RISC-V VSIP (RISC state control register) to complete the delivery of the RISC-V clock interrupt.

[0169] When the ARM Hypervisor recognizes that the RISC-V virtual machine triggers a software interrupt, the ARM Hypervisor sets the Supervisor-level Software Interrupt Pending (SSIP) bit of the VSIP register of the RISC-V processing logic to complete the delivery of the RISC-V software interrupt.

[0170] When the ARM Hypervisor recognizes that the RISC-V virtual machine triggers an external interrupt, the ARM Hypervisor sets the supervisor-level external interrupt pending bit (SEIP) of the VSIP register of the RISC-V processing logic to complete the delivery of the RISC-V external interrupt.

[0171] Since an address mapping table is set in the shared memory 412, the address mapping table stores the address of the state control register (such as VSIP), SSIP, STIP and SEIP are located in different bits in VSIP, and setting SSIP, STIP or SEIP means setting the value of the corresponding bit to 1, and the value of 1 on these bits of SSIP, STIP and SEIP represents that the interrupt is waiting to be processed. The ARM Hypervisor can set the value of SSIP, STIP or SEIP in VSIP to 1 according to the address of VSIP recorded in the address mapping table, so that the RISC processing logic triggers the corresponding interrupt according to the value of the bit in VSIP. For example, the position of STIP is that the ARM Hypervisor sets the value of STIP in VSIP to 1 according to the address of VSIP in the address mapping table, indicating that the clock interrupt is waiting to be processed. By reading the value of STIP in VSIP, the RISC processing logic knows that the interrupt type triggered by the RISC-V virtual machine is a clock interrupt.

[0172] Step 607: The RISC processing logic restores the state of the RISC-V virtual machine and continues to run the RISC-V virtual machine.

[0173] The RISC processing logic learns the type of interrupt triggered by RISC-V by reading the value of SSIP, STIP or SEIP in VSIP.

[0174] Since for the same type of interrupt, the codes used to represent the type of the interrupt in different instruction set architectures are different, the ARM Hypervisor cannot directly identify the type of interrupt triggered by the RISC-V virtual machine. In an embodiment of the present application, by storing a one-to-one correspondence between the codes of multiple types of interrupts defined by the ARM architecture and the codes of multiple types of interrupts defined by the RISC-V architecture, the ARM Hypervisor can find the code of the type of interrupt triggered by the RISC-V virtual machine under the ARM architecture, so that the ARM Hypervisor can identify the type of interrupt triggered by the RISC-V virtual machine. In other words, the ARM Hypervisor finds the ARM code representing the type of interrupt triggered by the RISC-V virtual machine based on the RISC-V code and the corresponding relationship used to represent the type of interrupt triggered by the RISC-V virtual machine; wherein, the RISC-V code is the code for this type of interrupt in the specification of the RISC-V architecture, the ARM code is the code for this type of interrupt in the specification of the ARM architecture, and the ARM Hypervisor can directly identify the ARM code to determine the type of interrupt.

[0175] In another implementation, if the RISC-V virtual machine triggers an exception or interrupt, and the ARM architecture specification does not have a code for such an exception or interrupt, the following processing method can be used:

[0176] 1) According to the ARM coding specification, customize the coding of this type of exception or interrupt under the ARM architecture. The corresponding relationship between the coding of this type of exception or interrupt under the RISC-V architecture and the customized coding of this type of exception or interrupt under the ARM architecture is added to the exception mapping table or interrupt mapping table.

[0177] 2) Add new functional modules directly in the ARM Hypervisor. The newly added functional modules are similar to the Hypervisor that supports the RISC-V architecture. Therefore, the newly added functional modules can refer to the processing logic of the RISC-V Hypervisor directly handling exceptions or interrupts to handle the exceptions or interrupts triggered by the RISC-V virtual machine, and there is no need to perform coding mapping.

[0178] Fig. 9 700 is a schematic diagram of the structure of a computing node 700. The computing node 700 may be part or all of the aforementioned computing nodes 100, 203, 300 or 400. The computing node 700 includes a processor 701, a memory 702 and a communication interface 703.

[0179] Processor 701 is the control center of computing node 700, and uses various interfaces and buses to connect various components of computing node 700. In some embodiments, processor 701 may include one or more processing units, or physical cores, such as Figure 1 The processor 114 in the embodiment includes core 0 and core 1. In some embodiments, the processor 701 may include a master architecture processing logic and a slave architecture processing logic, such as Figure 3 The master architecture processing logic 309 and the slave architecture processing logic 310 in Figure 4ARM processing logic 409 and RISC-V processing logic 410 in. Processor 701 may also include registers, which may be used to store status information of triggered exceptions or interrupts. And in some embodiments, the main architecture processing logic and the slave architecture processing logic have respective registers, and the registers of the main architecture processing logic may be used to store converted status information of converted exceptions or interrupts. Processor 701 may be a central processing unit (CPU), and the processor 701 may also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or the processor 701 may also be any conventional processor, etc.

[0180] The memory 702 stores a computer program. The processor 701 is configured to execute the computer program in the memory 702, thereby realizing the functions defined by the computer program. The memory 702 is a non-volatile storage medium, generally including internal memory and external memory. The internal memory includes but is not limited to random access memory (RAM), read-only memory (ROM), or cache, etc. The external memory includes but is not limited to flash memory, hard disk, optical disk, universal serial bus (USB) disk, etc. The computer program is usually stored in the external memory, and the processor loads the program from the external memory to the internal memory before executing the computer program. The memory 702 can be independent and connected to the processor 701 through a bus; the memory 702 can also be integrated into a chip subsystem with the processor 701.

[0181] The memory 702 stores an operating system 704, a virtualization software program 703, and other program modules. The operating system 704 may be the operating system of the computing node 700 itself, for example Figure 1 The host operating system 111 is shown. After the virtualization software program 705 is read and executed by the processor 701, the virtualization of the computing node 700 is realized, and the method for handling exceptions or interrupts of the virtual machine supporting the heterogeneous instruction set architecture provided in each embodiment of the present application is realized. The virtualization software program 705 can realize Figure 1 The virtual machine monitor 110 in Figure 2Virtualization platform in Figure 3 Virtual Machine Monitor 303 or Figure 4 Some or all of the functionality of the ARM Hvpervisor402 in.

[0182] The communication interface 703 uses a transceiver device such as a transceiver to implement communication between the computing node 700 and other devices or communication networks.

[0183] Fig.10 The schematic diagram of the structure of the multi-core processor provided in each of the above embodiments is shown in FIG. 1 . The multi-core processor 10 can be located in any electronic device, such as a computer, a mobile phone, a tablet, and other devices. The multi-core processor 10 can specifically be a chip or a chipset or a circuit board equipped with a chip or a chipset. The chip or chipset or the circuit board equipped with a chip or a chipset can work under the necessary software drive.

[0184] The multi-core processor 80 may include a main processing core 801, and one or more slave processing cores 802 coupled to the main processing core 801. The main processing core is equivalent to the aforementioned main architecture processing logic, and the slave processing core is equivalent to the aforementioned slave architecture processing logic. There may be N slave processing cores 802, including slave processing core 1 (Core1), slave processing core 2 (Core2), slave processing core 3 (Core3), slave processing core 4 (Core4), ... slave processing core (N-1) (Core (N-1)) and slave processing core N (CoreN). The N slave processing cores 802 all include configuration interfaces, namely configuration interface 1, configuration interface 2, configuration interface 3, ... configuration interface N-1, configuration interface N. The main processing core 801 can perform relevant configuration and control on the corresponding slave processing core 802 through the above configuration interface. Optionally, the main processing core 801 and the one or more slave processing cores 802 may be located in one or more ICs. For example, the main processing core 801 and the one or more slave processing cores 802 may be located in one integrated circuit (IC), or the main processing core 801 is located in one IC, and part or all of the one or more slave processing cores 802 are located in another IC. This embodiment of the present invention does not specifically limit this. It is understandable that the main processing core 801 and the N slave processing cores 802 may be coupled and communicated via a bus or other means. Fig.10 The connection relationships illustrated in the figure do not limit the coupling relationships therebetween.

[0185] The main processing core 801 and the N slave processing cores 802 support different instruction set architectures, the main processing core 801 supports a first instruction set, and the slave processing core 802 supports a second instruction set. Optionally, the main processing core 801 and any one of the N slave processing cores 102 are heterogeneous, that is, the first instruction set supported by the main processing core 801 is different from the second instruction set supported by any one of the slave processing cores 802. The N slave processing cores 802 can be isomorphic or heterogeneous, or partially isomorphic and partially heterogeneous, that is, the instruction sets supported by the N slave processing cores 802 can be the same or different, or partially the same and partially different, and the embodiment of the present invention does not specifically limit this. For example, in an application scenario, the main processing core 801 is a general-purpose processor core, and the N slave processing cores 802 are processing cores for multiple specific functions, for example, the main processing core is a general-purpose CPU, and the slave processing cores 802 are FPGAs, DSPs, etc. That is, each slave processing core 802 has its own unique structure, and thus each slave processing core has its own unique instruction set, and the specific instruction set determines the specific application of each slave processing core, so that each slave processing core has a type of program that it is good at processing. Therefore, the main processing core 801 can assign different types of computing tasks to different types of slave processing cores 802 for parallel processing, and thus the functions of different specific applications are simultaneously implemented in the same processor, thereby providing a more flexible and efficient processing mechanism for applications with different requirements.

[0186] Optionally, the first instruction set is the ARM instruction set, and the second instruction set is the RISC-V instruction set. For example, the main processing core 801 and the N slave processing cores 802 are CPU cores, but support different instruction sets. For example, the main processing core 101 supports the ARM instruction set, and the slave processing core 102 supports the RISC-V instruction set. Therefore, the main processing core 801 can be used to install and run a virtual machine monitor and a virtual machine based on the ARM instruction set; and the slave processing core 802 can run applications based on the RISC-V instruction set, such as a virtual machine based on the RISC-V instruction set, under the control of the main processing core 101, thereby supporting virtual machines of heterogeneous instruction sets in the same processor, i.e., the multi-core processor 80.

[0187] The terms "first", "second", "third" and "fourth" in the specification and claims of the present application and the drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally includes steps or units that are not listed, or optionally includes other steps or units inherent to these processes, methods, products or devices. Mentioning "embodiment" in this article means that the specific features, structures or characteristics described in conjunction with the embodiment may be included in at least one embodiment of the present application. The appearance of this phrase at various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0188] The terms "component", "module", "system", etc. used in this specification are used to represent computer-related entities, hardware, firmware, a combination of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable file, an execution thread, a program and / or a computer. By way of illustration, both applications running on a computing device and a computing device can be components. One or more components may reside in a process and / or an execution thread, and a component may be located on a computer and / or distributed between two or more computers. In addition, these components may be executed from various computer-readable media having various data structures stored thereon. Components may, for example, communicate through local and / or remote processes according to signals having one or more data packets (e.g., data from two components interacting with another component between a local system, a distributed system and / or a network, such as the Internet interacting with other systems through signals).

Claims

1. A method for handling exceptions. It is characterized in that The method is applied to a physical host, wherein a processor of the physical host includes a master processing core supporting a master instruction set architecture and a slave processing core supporting a slave instruction set architecture, and a virtual machine monitor supporting the master instruction set architecture, as well as a master architecture virtual machine supporting the master instruction set architecture and a slave architecture virtual machine supporting the slave instruction set architecture are running on the physical host, and the method includes: When the slave architecture virtual machine triggers an exception, the virtual machine monitor obtains state information of the exception; the state information of the exception includes a first code of the exception; the first code of the exception indicates the type of the exception under the slave instruction set architecture; The virtual machine monitor obtains the second code of the exception from the exception mapping relationship, where the second code of the exception represents the type of the exception under the main instruction set architecture; the exception mapping relationship includes a correspondence between the first code and the second code of each type of exception in multiple types of exceptions; The virtual machine monitor identifies the type of the exception according to the second code of the exception and handles the exception; The physical host also includes obtaining the abnormal state information from the architecture register and the virtual machine monitor, including: The virtual machine monitor obtains the exception status information from the shared memory; the shared memory is shared by the slave processing core and the master processing core; the exception status information is copied by the slave processing core from the slave architecture register to the shared memory; the slave architecture register is a register that complies with the slave instruction set architecture specification and is used to store the exception status information.

2. The method according to claim 1, It is characterized in that The physical host further includes a shared register, and the virtual machine monitor obtains the abnormal state information, including: The virtual machine monitor obtains the abnormal state information from the shared register, and the shared register is shared by the slave processing core and the master processing core; the shared register stores the abnormal state information.

3. The method according to claim 1, It is characterized in that The physical host further includes a master architecture register, the abnormal status information further includes at least one of an instruction triggering the abnormality or an address triggering the abnormality, the abnormal mapping relationship further includes a correspondence between the slave architecture register and the master architecture register, and the master architecture register is a register that complies with the master instruction set architecture specification; Before the virtual machine monitor identifies the type of the exception according to the second code of the exception and processes the exception, the method further includes: The virtual machine monitor searches for the master architecture register corresponding to the slave architecture register according to the exception mapping relationship; The virtual machine monitor writes the second encoding of the exception into the main architecture register, and writes at least one of the instruction triggering the exception and the address triggering the exception into the main architecture register; Correspondingly, the virtual machine monitor identifies the type of the exception according to the second code of the exception and processes the exception, including: The virtual machine monitor reads the second code of the exception and at least one of the instruction triggering the exception and the address triggering the exception from the main architecture register; The virtual machine monitor processes the exception according to the second encoding of the exception and at least one of the instruction triggering the exception and the address triggering the exception.

4. The method according to any one of claims 1 to 3, It is characterized in that The physical host includes a hardware device that supports hardware-assisted virtualization, and the hardware device supports the main instruction set architecture, and the virtual machine monitor processes the exception, including: The virtual machine monitor processes the exception through the hardware device supporting hardware-assisted virtualization.

5. A method for handling interruptions, It is characterized in that The method is applied to a physical host, wherein a processor of the physical host includes a master processing core supporting a master instruction set architecture and a slave processing core supporting a slave instruction set architecture, and a virtual machine monitor supporting the master instruction set architecture, as well as a master architecture virtual machine supporting the master instruction set architecture and a slave architecture virtual machine supporting the slave instruction set architecture are running on the physical host, and the method includes: When the slave architecture virtual machine triggers an interrupt, the virtual machine monitor obtains state information of the interrupt, where the state information includes a first code of the interrupt; the first code of the interrupt indicates a type of the interrupt under the slave instruction set architecture; The virtual machine monitor obtains a second code corresponding to the interrupt from the interrupt mapping relationship, wherein the second code of the interrupt represents the type of the interrupt under the main instruction set architecture; the interrupt mapping relationship includes a correspondence between the first code and the second code of each type of interrupt in multiple types of interrupts; The virtual machine monitor identifies the type of the interruption according to the second code of the interruption and processes the interruption; The physical host includes obtaining the interrupt status information from the architecture register and the virtual machine monitor, including: The virtual machine monitor obtains the status information of the interrupt from the shared memory, and the shared memory is shared by the slave processing core and the master processing core. The status information of the interrupt is copied by the slave processing core from the slave architecture register to the shared memory; the slave architecture register is a register that complies with the slave instruction set architecture specification and is used to store the status information of the interrupt.

6. The method according to claim 5, It is characterized in that The physical host further includes a shared register, and the virtual machine monitor obtains the state information of the interrupt, including: The virtual machine monitor obtains the interrupt status information from the shared register, and the shared register is shared by the slave processing core and the master processing core; the shared register stores the interrupt status information.

7. The method according to claim 5, It is characterized in that The physical host includes a master architecture register, the interrupt mapping relationship also includes a correspondence between the slave architecture register and the master architecture register, and the master architecture register is a register that complies with the master instruction set architecture specification; Before the virtual machine monitor identifies the type of the interrupt according to the second code of the interrupt and processes the interrupt, the method further includes: The virtual machine monitor searches for the master architecture register corresponding to the slave architecture register according to the interrupt mapping relationship; The virtual machine monitor writes the second code of the interrupt into the main architecture register; Correspondingly, the virtual machine monitor identifies the type of the interrupt and processes the interrupt according to the second code of the interrupt, including: The virtual machine monitor reads the second code of the interrupt from the main architecture register, identifies the type of the interrupt according to the second code of the interrupt, and processes the interrupt.

8. The method according to any one of claims 5 to 7, It is characterized in that The physical host includes a hardware device that supports hardware-assisted virtualization, and the hardware device supports the main instruction set architecture, and the virtual machine monitor processes the interrupt, including: The virtual machine monitor processes the interrupt through the hardware device supporting hardware-assisted virtualization.

9. A computing device, It is characterized in that The computing device includes a processor and a memory, the processor includes a master processing core supporting a master instruction set architecture and a slave processing core supporting a slave instruction set architecture, the memory stores computer instructions, and the master processing core executes the computer instructions to execute the method according to any one of claims 1 to 8.

10. A computer-readable storage medium, It is characterized in that The computer-readable storage medium stores computer instructions, and the computer instructions are called by a processor to execute the method according to any one of claims 1 to 8.

11. A physical host, It is characterized in that The physical host includes a conversion module and a simulation module. The conversion module is used to: when an exception is triggered by a slave architecture virtual machine, obtain the state information of the exception; the state information of the exception includes a first code of the exception; the first code of the exception indicates the type of the exception under the slave instruction set architecture; the slave architecture virtual machine is a virtual machine supporting the slave instruction set architecture running on the physical host; obtain the second code of the exception from the exception mapping relationship, the second code of the exception indicates the type of the exception under the master instruction set architecture; the exception mapping relationship includes a correspondence between the first code and the second code of each type of exception in multiple types of exceptions; The simulation module is used to: identify the type of the exception according to the second code of the exception; and process the exception; The physical host also includes a slave architecture register, and the conversion module is also used to obtain the status information of the exception from a shared memory; the shared memory is shared by the slave processing core and the master processing core; the status information of the exception is copied from the slave architecture register to the shared memory; the slave architecture register is a register that complies with the slave instruction set architecture specification and is used to store the status information of the exception triggered by the slave architecture virtual machine.

12. The physical host according to claim 11, It is characterized in that The physical host also includes a shared register; the conversion module is further used to obtain the abnormal status information from the shared register, and the shared register is shared by the slave processing core and the master processing core; the shared register stores the abnormal status information.

13. The physical host according to claim 11, It is characterized in that The physical host further includes a master architecture register, the abnormal status information further includes at least one of an instruction triggering the abnormality or an address triggering the abnormality, the abnormal mapping relationship further includes a correspondence between the slave architecture register and the master architecture register, and the master architecture register is a register that complies with the master instruction set architecture specification; The conversion module is further used to: search the master architecture register corresponding to the slave architecture register according to the exception mapping relationship; write the second encoding of the exception into the master architecture register, and write at least one of the instruction triggering the exception and the address triggering the exception into the master architecture register; The simulation module is used to: read the second code of the exception, and at least one of the instruction that triggers the exception and the address that triggers the exception from the main architecture register; and process the exception according to the second code of the exception, and at least one of the instruction that triggers the exception and the address that triggers the exception.

14. The physical host according to any one of claims 11 to 13, It is characterized in that The physical host includes a hardware device supporting hardware-assisted virtualization, and the hardware device supports the main instruction set architecture; The simulation module is used to: process the exception through the hardware device supporting hardware-assisted virtualization.

15. A physical host, It is characterized in that The physical host includes a conversion module and a simulation module. The conversion module is used to: when an interrupt is triggered by a slave architecture virtual machine, obtain the state information of the interrupt, the state information includes a first code of the interrupt; the first code of the interrupt indicates the type of the interrupt under the slave instruction set architecture; the slave architecture virtual machine is a virtual machine running on the physical host and supporting the slave instruction set architecture; obtain a second code corresponding to the interrupt from an interrupt mapping relationship, the second code of the interrupt indicates the type of the interrupt under the master instruction set architecture; the interrupt mapping relationship includes a correspondence between a first code and a second code of each type of interrupt in multiple types of interrupts; The simulation module is used to: identify the type of the interruption according to the second code of the interruption; and process the interruption; The physical host also includes a slave architecture register, The conversion module is used to: obtain the status information of the interrupt from the shared memory, the shared memory is shared by the slave processing core and the master processing core, and the status information of the interrupt is copied from the slave architecture register to the shared memory; the slave architecture register is a register that complies with the slave instruction set architecture specification, and is used to store the status information of the interrupt triggered by the slave architecture virtual machine.

16. The physical host according to claim 15, It is characterized in that The physical host also includes a shared register, The conversion module is further used for: acquiring the state information of the interrupt from the shared register, where the shared register is shared by the slave processing core and the master processing core; and the shared register stores the state information of the interrupt.

17. The physical host according to claim 15, It is characterized in that The physical host further includes a master architecture register, the interrupt mapping relationship further includes a correspondence between the slave architecture register and the master architecture register, and the master architecture register is a register that complies with the master instruction set architecture specification; The conversion module is further used to: search for the master architecture register corresponding to the slave architecture register according to the interrupt mapping relationship; write the second code of the interrupt into the master architecture register; The simulation module is used for: reading the second code of the interrupt from the main architecture register; and processing the interrupt according to the second code of the interrupt.

18. The physical host according to any one of claims 15 to 17, It is characterized in that The physical host includes a hardware device supporting hardware-assisted virtualization, and the hardware device supports the main instruction set architecture; the simulation module is used to: process the interrupt through the hardware device supporting hardware-assisted virtualization.

19. A chip, It is characterized in that The chip includes a master processing core supporting a master instruction set architecture and a slave processing core supporting a slave instruction set architecture, and the master processing core is configured to execute the method according to any one of claims 1-8.

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