Data driving apparatus, method and system for driving a display device

Abstract

The present disclosure relates to a data driving apparatus, method and system for driving a display device, and more particularly, to a data driving apparatus, method and system for providing an internal operating state of the data driving apparatus in response to a request of a data processing apparatus when driving a display device.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a data driving apparatus, method, and system for driving a display device. BACKGROUND

[0002] A display panel includes a plurality of pixels arranged in a matrix form, and each pixel includes a red (R) sub-pixel, a green (G) sub-pixel, a blue (B) sub-pixel, etc. Each sub-pixel emits light according to a gray value included in image data to display an image on the display panel.

[0003] Image data is transmitted from a data processing apparatus called a timing controller to a data driving apparatus called a source driver. The image data is transmitted in a digital value, and the data driving apparatus converts the image data into an analog voltage to drive each sub-pixel.

[0004] Since the image data individually or independently indicates each gray value for each pixel, the amount of image data increases as the number of pixels arranged in the display panel increases. In addition, as the frame rate increases, the amount of image data to be transmitted in a unit time increases.

[0005] Since a display panel has much higher resolution recently, the number of pixels arranged in the display panel and the frame rate increase. In addition, to process the increased amount of image data, the data transmission rate in the display device increases.

[0006] On the other hand, in initial driving of the data processing apparatus and the data driving apparatus, that is, immediately after power is applied to the display device, a high-speed communication environment for data transmission between the data processing apparatus and the data driving apparatus needs to be set.

[0007] Here, since there can be an error due to high speed in a case where processing for configuring a high-speed communication environment is performed using high-speed data communication, the processing for configuring the high-speed communication environment is performed using low-speed data communication having a communication frequency lower than a communication frequency of the high-speed data communication.

[0008] After low-speed data communication with the data processing apparatus, that is, after the processing for configuring the high-speed communication environment is performed, the data driving apparatus synchronizes a communication clock through clock training.

[0009] After the clock training is completed, the data processing apparatus can transmit an image data signal to the data driving apparatus in high-speed data communication so that the data driving apparatus can display an image on the display panel. That is, the display device can normally operate.

[0010] On the other hand, the data processing apparatus can receive a lock signal from the data driving apparatus while the display apparatus is operating, and check the operation state of the data driving apparatus by recognizing a voltage level of the lock signal.

[0011] Here, the lock signal can have a high level or a low level. When the lock signal has the high level, the data processing apparatus can determine that the operation state of the data driving apparatus is normal, and when the lock signal has the low level, the data processing apparatus can determine that the operation state of the data driving apparatus is abnormal.

[0012] In general, in a display apparatus, one data processing apparatus communicates with a plurality of data driving apparatuses. In order for the data processing apparatus to smoothly communicate data with the plurality of data driving apparatuses, the data processing apparatus needs to accurately recognize the operation state of each data driving apparatus.

[0013] However, according to the conventional art, the data processing apparatus determines only whether the operation state of the data driving apparatus is normal or abnormal using the lock signal, but cannot accurately determine the operation state of each data driving apparatus. SUMMARY

[0014] In this context, an aspect of the disclosure provides a technique in which a data driving apparatus provides an internal operation state to a data processing apparatus in response to a request of the data processing apparatus while a display apparatus is operating. To this end, in an aspect, the disclosure provides a driving method of a data driving apparatus, including: an image receiving step of receiving an image data signal from a data processing apparatus through a first communication line; a first transmitting step of transmitting a lock signal of a predetermined level through a second communication line; a command receiving step of receiving a state response command signal from the data processing apparatus while receiving the image data signal; and a second transmitting step of transmitting an operation state signal instead of the lock signal of the predetermined level through the second communication line, the operation state signal including operation state data indicating an operation state inside the data driving apparatus.

[0015] The method can further include, before the image receiving step, a step of optimizing a setting value of a clock recovery circuit included in a circuit for receiving the image data signal, according to a frequency of the image data signal.

[0016] The optimized setting value can include any one of a reference current value, a reference voltage value, and a gain adjustment value of an oscillator included in the clock recovery circuit, and the operation state data can include the optimized setting value.

[0017] The method can further include a step of optimizing a setting value of an equalizer included in a circuit for receiving the image data signal according to a characteristic of the first communication line, before the image receiving step.

[0018] The optimized setting value can include a gain level of the equalizer, and the operation state data can include the optimized setting value.

[0019] In the command receiving step, the data driving apparatus can receive the image data signal by frame, and can receive the state response command signal in a frame control interval between one frame and another frame. The data driving apparatus can repeat the second transmitting step N times from immediately after the state response command signal is received until another frame control interval starts, and then transmit a lock signal of a predetermined level again through the second communication line, where N is a natural number.

[0020] In the second transmitting step, the data driving apparatus can encode the operation state data into the operation state signal using a Manchester code.

[0021] The operation state signal can include a preamble, a start bit arranged after the preamble, the operation state data arranged after the start bit, and an end bit arranged after the operation state data, where a Manchester code corresponding to any one binary digit is repeated M times in the preamble, M being a natural number equal to or greater than 2.

[0022] In the second transmitting step, the data driving apparatus can perform an AND operation with respect to the operation state signal and a lock signal of a predetermined level received from an external apparatus, and transmit the operation state signal obtained by the AND operation through the second communication line.

[0023] In another aspect, the disclosure provides a data driving apparatus including: a communication circuit configured to receive an image data signal from a data processing apparatus through a first communication line, receive a state response command signal from the data processing apparatus when the image data signal is received, and process the state response command signal into state response command information; a lock control circuit configured to output a lock signal of a first level when the communication circuit receives the image data signal; and a logic gate configured to transmit an operation state signal related to an operation state of the communication circuit instead of the lock signal of the first level through a second communication line connected to an output terminal when the state response command information is received from the communication circuit.

[0024] The data driving apparatus can further include a signal selection circuit for outputting the first level of the lock signal to the logic gate when only the first level of the lock signal is received, and outputting the operation state signal to the logic gate when the operation state signal and the first level of the lock signal are received.

[0025] The logic gate can be an AND gate, and when the operation state signal is received from the signal selection circuit through an input terminal and the first level of the lock signal is received from the external apparatus through a second communication line connected to another input terminal, the AND gate can perform an AND operation with respect to the operation state signal and the lock signal from the external apparatus, and transmit the operation state signal obtained by the AND operation through a second communication line connected to the output terminal.

[0026] The logic gate can be an AND gate, and when the operation state signal is received from the signal selection circuit through an input terminal and the second level of the lock signal is received from the external apparatus through a second communication line connected to another input terminal, the AND gate can perform an AND operation with respect to the operation state signal and the lock signal from the external apparatus, and transmit the lock signal from the external apparatus obtained by the AND operation through a second communication line connected to the output terminal.

[0027] The data driving apparatus can further include a communication control circuit. The communication circuit can include a clock recovery circuit and an equalizer, and the communication control circuit can optimize a setting value of an oscillator included in the clock recovery circuit according to a frequency of the image data signal before the communication circuit receives the image data signal, and optimize a gain level of the equalizer according to a characteristic of the first communication line.

[0028] The operation state signal can include a set value of the oscillator and a gain level of the equalizer. In still another aspect, the disclosure provides a display device driving system including: a first data driving device for receiving a first image data signal through a 1-1 communication line, transmitting a first lock signal through a 2-1 communication line, and in a case where a state response command signal is received while the first image data signal is received, transmitting an operation state signal for indicating an operation state inside the first data driving device through the 2-1 communication line instead of the first lock signal; a second data driving device for receiving a second image data signal through a 1-2 communication line, generating a second lock signal, receiving the first lock signal through a 2-1 communication line, performing a logical operation with respect to the first lock signal and the second lock signal, transmitting a signal obtained by the logical operation through a 2-2 communication line, receiving the operation state signal through the 2-1 communication line, performing a logical operation with respect to the operation state signal and the second lock signal, and transmitting an operation state signal obtained by the logical operation through the 2-2 communication line; and a data processing device for transmitting the first image data signal through the 1-1 communication line, transmitting the second image data signal through the 1-2 communication line, transmitting the state response command signal through the 1-1 communication line, and subsequently receiving the operation state signal through the 2-2 communication line.

[0029] The data processing device can transmit a level fixing command signal through the 1-2 communication line to fix a level of the second lock signal when the state response command signal is transmitted through the 1-1 communication line.

[0030] The second data driving device can fix a level of the second lock signal to high when the level fixing command signal is received through the 1-2 communication line.

[0031] In a case where there is an error in receiving the second image data signal in a state where the lock signal is fixed to high, the second data driving device can change a level of the second lock signal to low, perform a logical operation with respect to the operation state signal and the second lock signal of low level, and transmit a signal of low level obtained by the logical operation through the 2-2 communication line.

[0032] As described above, according to the disclosure, a data processing device can check operation states of a plurality of data driving devices, and thus, the data processing device can efficiently manage the plurality of data driving devices. BRIEF DESCRIPTION OF DRAWINGS

[0033] The above and other aspects, features, and advantages of the disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0034] Figure 1 is a configuration diagram of a display device according to an embodiment;

[0035] Figure 2 is a diagram schematically showing a configuration of a system according to an embodiment;

[0036] Figure 3 is a diagram specifically showing a configuration of a system according to an embodiment;

[0037] Figure 4 is a diagram schematically showing a configuration of a high-speed communication circuit according to an embodiment;

[0038] Figure 5 and Figure 6 is a diagram showing a data transmission sequence through a first communication line according to an embodiment;

[0039] Figure 7 and Figure 8 is a diagram showing a data transmission sequence through a second communication line according to an embodiment;

[0040] Figure 9A and Figure 9B is a diagram showing an encoding method of a data driving device according to an embodiment; and

[0041] Figure 10 is a flowchart showing a process of transmitting and receiving data by a data driving device according to an embodiment. DETAILED DESCRIPTION

[0042] Figure 1 is a configuration diagram of a display device according to an embodiment.

[0043] Referring to Figure 1 , the display device 100 can include a display panel 110, a data driving device 120, a gate driving device 130, and a data processing device 140.

[0044] On the display panel 110, a plurality of data lines DL and a plurality of gate lines GL can be arranged, and a plurality of pixels can also be arranged. The pixel can include a plurality of sub-pixels SP. The sub-pixels can be red (R) sub-pixels, green (G) sub-pixels, blue (B) sub-pixels, and white (W) sub-pixels. The pixel can include RGB sub-pixels SP, RGBG sub-pixels SP, or RGBW sub-pixels SP.

[0045] The data driving device 120, the gate driving device 130, and the data processing device 140 are used to generate signals for displaying an image on the display panel 110.

[0046] The gate driving device 130 can provide a gate driving signal, such as a turn-on voltage or a turn-off voltage, through a gate line GL. When a gate driving signal of a turn-on voltage is provided to a sub-pixel SP, the sub-pixel SP is connected with a data line DL. When a gate driving signal of a turn-off voltage is provided to the sub-pixel SP, the sub-pixel SP is disconnected from the data line DL. The gate driving device 130 can be referred to as a gate driver.

[0047] The data driving device 120 can provide a data voltage V p to the sub-pixel SP through a data line DL. The data voltage V p provided through the data line DL can be provided to the sub-pixel SP according to a gate driving signal. The data driving device 120 can be referred to as a source driver (SD-IC).

[0048] The data driving device 120 can include at least one integrated circuit, and the at least one integrated circuit can be connected to a bonding pad of the display panel 110 in a tape automated bonding (TAB) manner or a chip on glass (COG) manner, formed directly on the display panel 110, or integrated on the display panel 110 as circumstances dictate. In addition, the data driving device 120 can be formed in a type of chip on film (COF).

[0049] According to an embodiment, when a driving voltage VCC is provided to the data driving device 120 and the data processing device 140, the data driving device 120 can perform low-speed communication with the data processing device 140 to establish a high-speed communication environment therebetween.

[0050] In other words, the data driving device 120 can receive a setting value data signal for a high-speed communication environment from the data processing device 140 in the low-speed communication. Here, the data driving device 120 can receive the setting value data signal in a CFG data interval of the data signal. Figure 5 According to an embodiment, the setting value data included in the setting value data signal can include a basic gain level of an equalizer included in the data driving device 120, scrambling information, row polarity information, and the like. Here, the scrambling information can include information about whether data is scrambled when the data processing device 140 transmits data to the data driving device 120, and the row polarity information can include information indicating a polarity of a first row of pixels.

[0051] The data driving device 120 can establish a high-speed communication environment using the setting value data and store the setting value data. Here, the data driving device 120 can store the setting value data in a memory circuit (not shown) included therein. The memory circuit (not shown) of the data driving device 120 can include at least one of a register and a random access memory (RAM).

[0052] On the other hand, the data driving device 120 can receive a clock mode for low-speed communication from the data processing device 140 in a preamble section arranged before the CFG data section, and perform clock training for low-speed communication. The data driving device 120 can receive a set value data signal and a clock mode for low-speed communication through the first communication line LN1. Here, the clock training can be a process of synchronizing an internal clock of the data driving device 120 with a communication clock.

[0053] When the clock training for low-speed communication is normally completed, the data driving device 120 can transmit a lock signal of a first level indicating that a communication state is stable to the data processing device 140. Here, the first level can be a high level (a high voltage level). The lock signal of the first level can be transmitted through the second communication line LN2.

[0054] As described above, after the clock training for low-speed communication is performed and a high-speed communication environment is established through low-speed communication with the data processing device, the data driving device 120 can perform high-speed communication with the data processing device.

[0055] For example, in a display mode section of Figure 5 , the data driving device 120 can receive an image data signal from the data processing device 140 through high-speed communication with the data processing device 140. Here, the image data signal can be transmitted or received through the first communication line LN1.

[0056] Before receiving the image data signal, the data driving device 120 can optimize a set value of a clock recovery circuit in a high-speed communication circuit according to a frequency of high-speed communication, that is, a frequency of the image data signal, to receive the image data signal.

[0057] The data driving device can also optimize a set value of an equalizer included in the high-speed communication circuit according to characteristics of the first communication line LN1.

[0058] A detailed description will be made with reference to Figure 5 and Figure 6 in this regard.

[0059] The data processing device 140 can provide a control signal to the gate driving device 130 and the data driving device 120. For example, the data processing device 140 can transmit a gate control signal GCS to the gate driving device 130 to initiate scanning, transmit an image data signal to the data driving device 120, and transmit a data control signal DCS to control the data driving device 120 to provide a data voltage V p to each sub-pixel SP. The data processing device 140 can be referred to as a timing controller (T-CON).

[0060] Figure 2FIG. 1 is a diagram schematically illustrating a configuration of a system according to an embodiment.

[0061] Referring to Figure 2 , the system can include at least one data processing device 140 and a plurality of data driving devices 120a, 120b, 120c, 120d.

[0062] The data processing device 140 can be disposed on a first printed circuit board PCB1 and connected with the plurality of data driving devices 120a, 120b, 120c, 120d through a first communication line LN1 and a second communication line LN2. The first communication line LN1 and the second communication line LN2 can reach the plurality of data driving devices 120a, 120b, 120c, 120d via the first printed circuit board PCB1 and a second printed circuit board PCB2. The first printed circuit board PCB1 and the second printed circuit board PCB2 can be connected with each other by a first film FL1 made of a flexible material. The first communication line LN1 and the second communication line LN2 can extend from the first printed circuit board PCB1 to the second printed circuit board PCB2 via the first film FL1.

[0063] Each of the data driving devices 120a, 120b, 120c, 120d can be disposed on a second film FL2 in a chip on film (COF) manner. The second film FL2 can be a support substrate made of a flexible material for connecting the second printed circuit board PCB2 and the display panel 110. The first communication line LN1 and the second communication line LN2 can extend from the second printed circuit board PCB2 to the data driving devices 120a, 120b, 120c, 120d, respectively, via the second film FL2.

[0064] The first communication line LN1 can connect the data processing device 140 and each of the plurality of data driving devices 120a, 120b, 120c, 120d in a 1:1 manner. In other words, the connection of the first communication line LN1 can be in a point-to-point manner.

[0065] The second communication line LN2 can connect two adjacent data driving apparatuses 120a, 120b, 120c, 120d or connect the data driving apparatus 120d with the data processing apparatus 140 without overlapping the first communication line LN1 on the panel. For example, the first data driving apparatus 120a can be connected with the second data driving apparatus 120b through the second communication line LN2, and the second data driving apparatus 120b can be connected with the third data driving apparatus 120c through the second communication line LN2. Here, the second data driving apparatus 120b and the third data driving apparatus 120c can be connected with different second printed circuit boards PCB2, respectively, and thus the second communication line LN2 disposed between the second data driving apparatus 120b and the third data driving apparatus 120c can connect the second data driving apparatus 120b with the third data driving apparatus 120c via the second printed circuit board PCB2, the first film FL1, the first printed circuit board PCB1, the first film FL1, and the second printed circuit board PCB2. The third data driving apparatus 120c can be connected with the fourth data driving apparatus 120d through the second communication line LN2, and the fourth driving apparatus 120d can be connected with the data processing apparatus 140 through the second communication line LN2. This connection method of the second communication line LN2 can be a cascading method.

[0066] The data processing apparatus 140 and the plurality of data driving apparatuses 120a, 120b, 120c, 120d can communicate with each other through the first communication line LN1 and the second communication line LN2.

[0067] In this way, the data processing apparatus 140 can transmit the image data signal to the data driving apparatuses 120a, 120b, 120c, 120d, respectively, through the first communication line LN1.

[0068] According to an embodiment, the data processing apparatus 140 can transmit a status response command signal to the data driving apparatuses to check the status of the data driving apparatuses while transmitting the image data signal to the plurality of data driving apparatuses 120a, 120b, 120c, 120d.

[0069] Among the plurality of data driving apparatuses 120a, 120b, 120c, 120d, the data driving apparatuses that receive the status response command signal through the first communication line LN1 can generate an operation status signal related to the internal operation status thereof and transmit the operation status signal to the data processing apparatus 140 through the second communication line LN2.

[0070] This aspect will be described in detail below.

[0071] Figure 3 is a diagram specifically showing a configuration of a system according to an embodiment.

[0072] Reference Figure 3 The configuration of the data driving device 120 and the configuration of the system will be described.

[0073] The data driving device 120 (i.e., each of the plurality of data driving devices 120a, 120b, 120c, 120d) can include a low-speed communication circuit 310, a high-speed communication circuit 320, a lock control circuit 330, a communication control circuit 340, an encoder 350, a signal selection circuit 360, and a logic gate 370.

[0074] The low-speed communication circuit 310 can perform low-speed communication with the data processing device 140 through the first communication line LN1. Here, the frequency of the low-speed communication can be lower (specifically, at least 1 / 10) than the frequency of the high-speed communication. For example, if the frequency of the high-speed communication is several gigabps, the frequency of the low-speed communication can be several megabps. The low-speed communication circuit 310 can receive a clock pattern for low-speed communication from the data processing device 140 and perform clock training for low-speed communication. Here, the low-speed communication circuit 310 can receive the clock pattern for low-speed communication in the preamble interval of Figure 5 .

[0075] After completing the clock training for low-speed communication, the low-speed communication circuit 310 can output a low-speed communication state signal CMD_L indicating a high level (a high voltage level) of a low-speed communication state.

[0076] After completing the clock training for low-speed communication, the low-speed communication circuit 310 can receive a setting value data signal for a high-speed communication environment from the data processing device 140.

[0077] The low-speed communication circuit 310 can process the setting value data signal into setting value data (e.g., decode the signal into data or arrange the data) and transmit the setting value data to the communication control circuit 340 to be described below. Here, the low-speed communication circuit 310 can receive the setting value data signal in the CFG data interval of Figure 5 .

[0078] When power is applied to the data driving device 120, the low-speed communication circuit 310 can be activated by the control of the communication control circuit 340. When the command pattern interval of Figure 5 is completed, the low-speed communication circuit 310 can be deactivated by the control of the communication control circuit 340.

[0079] The high-speed communication circuit 320 can perform high-speed communication with the data processing device 140 through the first communication line LN1. Through the high-speed communication, the high-speed communication circuit 320 can receive an image data signal from the data processing device 140. For example, the high-speed communication circuit 320 can receive the image data signal in the image data interval of Figure 5Image data signals are received within the display mode range.

[0080] In addition, the high-speed communication circuit 320 can process image data signals into image data.

[0081] like Figure 4 As shown, the high-speed communication circuit 320 may include an equalizer 410, a clock recovery circuit 420, and a parallelization circuit 430.

[0082] On the other hand, the high-speed communication circuit 320 can be used before receiving image data signals (e.g., in...). Figure 5 During the pre-clock training interval, a test signal with a high-speed communication frequency (i.e., the frequency of the image data signal) is received from the data processing device 140.

[0083] The high-speed communication circuit 320 can train the clock included in the test signal by changing the setting value of the oscillator included in the clock recovery circuit 420 at predetermined time intervals Ts under the control of the communication control circuit 340. Figure 5 (TR_CLK in the text).

[0084] The high-speed communication circuit 320 can also be used before receiving image data signals (e.g., in...). Figure 6 (during the EQ training interval) the EQ training signal is received from the data processing device 140. Here, the EQ training signal may include, for example, Figure 6 The diagram shows a training sequence repeated for each time interval. The training sequence may include a blank signal H with a predetermined level (e.g., high level), an EQ clock training signal EQCP following the blank signal, and an EQ test signal EQTP following the EQ clock training signal EQCP. Here, the blank signal H can be used to indicate the division of the time interval.

[0085] The EQ test signal EQTP can include a pseudo-random binary sequence (PRBS) mode. Here, the PRBS mode can be implemented as PRBS7 mode, PRBS9 mode, PRBS10 mode, etc.

[0086] The EQ test signal EQTP can include test data encoded using the DC balanced code method. Here, the test data encoded using the DC balanced code method can include multiple code groups, each code group having the same numbers "0" and "1".

[0087] In the high-speed communication circuit 320, the configuration of the equalizer 410 can be changed according to an EQ setting value in each of a plurality of time sections in which an EQ training signal is received. In the high-speed communication circuit 320, the configuration of the equalizer 410 can be changed in each of the time sections by control of the communication control circuit 340. Each of the EQ setting values can include a gain level of the equalizer 410, and also include a tap coefficient of the equalizer. The communication control circuit 340 can store a plurality of the EQ setting values.

[0088] According to the embodiment, the high-speed communication circuit 320 can repeatedly perform clock training in the pre-clock training section and the EQ training section, and thus can output the high-speed communication state signal CDR_L indicating the high-speed communication state by alternation of a high level (a high voltage level) and a low level (a low voltage level).

[0089] After the passage of the EQ training section, the high-speed communication circuit 320 can perform clock training and link training, which are general training for high-speed communication. After completion of the general clock training, the high-speed communication circuit 320 can output the high-speed communication state signal CDR_L of a high level.

[0090] Subsequently, the high-speed communication circuit 320 can receive an image data signal from the data processing device 140. Here, the image data signal can be transmitted or received through the first communication line LN1.

[0091] In a case where any clock loss occurs due to electrostatic discharge (ESD) when the high-speed communication circuit 320 receives the image data signal, the high-speed communication circuit 320 can output the high-speed communication state signal CDR_L of a low level.

[0092] On the other hand, the high-speed communication circuit 320 can receive a state response command signal from the data processing device 140 while receiving the image data signal.

[0093] Here, as shown in FIG. 6, the high-speed communication circuit 320 can receive the image data signal by frame, and receive the state response command signal in a frame control section CRT between one frame (for example, an n-1th frame in Figure 7 or Figure 8 frames) and another frame (for example, an nth frame in Figure 7 or Figure 8 . Figure 7 Figure 8 In other words, the state response command signal can be included in a frame control signal received by the high-speed communication circuit 320 in the frame control section CTR.

[0094] In other words, the state response command signal can be included in a frame control signal received by the high-speed communication circuit 320 in the frame control section CTR.

[0095] ​The high-speed communication circuit 320 can receive a response end command signal in another frame control section CTR after the above-mentioned frame control section CTR.

[0096] The high-speed communication circuit 320 can process the state response command signal into state response command information to transmit it to the communication control circuit 340, and process the response end command signal into response end command information to transmit it to the communication control circuit 340.

[0097] According to one embodiment, the high-speed communication circuit 320 can receive a level fixing command signal instead of the state response command signal in the frame control section CTR.

[0098] When the level fixing command signal is received in the frame control section CTR, the high-speed communication circuit 320 can receive a fixing release command signal in another frame control section CTR after the above-mentioned frame control section CTR. Here, the level fixing command signal and the fixing release command signal can be included in the frame control signal.

[0099] The high-speed communication circuit 320 can process the level fixing command signal and the fixing release command signal into level fixing command information and fixing release command information, respectively, to transmit them to the lock control circuit 330. According to an embodiment, when the low-speed communication circuit 310 is activated, the high-speed communication circuit 320 can be deactivated by the control of the communication control circuit 340. Conversely, when the low-speed communication circuit 310 is deactivated, the high-speed communication circuit 320 can be activated by the control of the communication control circuit 340.

[0100] The lock control circuit 330 can receive a low-speed communication state signal CMD_L from the low-speed communication circuit 310 and a high-speed communication state signal CDR_L from the high-speed communication circuit 320.

[0101] When the low-speed communication circuit 310 completes clock training for low-speed communication, the lock control circuit 330 can receive the low-speed communication state signal CMD_L of a high level from the low-speed communication circuit 310 and the high-speed communication state signal CDR_L of a low level from the high-speed communication circuit 320.

[0102] In this case, the lock control circuit 330 can output a lock signal of a first level as shown in Figure 5 or Figure 6 Here, the first level can be high.

[0103] When low-speed communication between the low-speed communication circuit 310 and the data processing apparatus is completed, the lock control circuit 330 can receive the low-speed communication state signal CMD_L of a low level from the low-speed communication circuit 310.

[0104] On the other hand, in a case where the high-speed communication section includes a pre-clock training section and an EQ training section, the lock control circuit 330 can receive the high-speed communication state signal CDR_L, which alternates between high and low levels, from the high-speed communication circuit 320, and receive the low-speed communication state signal CMD_L, which is at a low level, from the low-speed communication circuit 310.

[0105] In this case, as shown in FIG. 10A or 10B, the lock control circuit 330 can consistently output the lock signal at the first level. Figure 5 or Figure 6 The reason for this is that if the level of the lock signal is frequently changed according to the level change of the high-speed communication state signal CDR_L, the probability of an error in the transmission of the lock signal increases. When the high-speed communication circuit 320 completes the general clock training, the lock control circuit 330 can receive the high-speed communication state signal CDR_L, which is at a high level, from the high-speed communication circuit 320, and receive the low-speed communication state signal CMD_L, which is at a low level, from the low-speed communication circuit 310.

[0106] In this case, as shown in FIG. 10A or 10B, the lock control circuit 330 can consistently output the lock signal at the first level. Figure 5 or Figure 6 The reason for this is that if the level of the lock signal is frequently changed according to the level change of the high-speed communication state signal CDR_L, the probability of an error in the transmission of the lock signal increases. When the high-speed communication circuit 320 completes the general clock training, the lock control circuit 330 can receive the high-speed communication state signal CDR_L, which is at a high level, from the high-speed communication circuit 320, and receive the low-speed communication state signal CMD_L, which is at a low level, from the low-speed communication circuit 310.

[0107] Even in a case where the high-speed communication circuit 320 receives the status response command signal while receiving the image data signal, the lock control circuit 330 can consistently output the lock signal at the first level.

[0108] The lock control circuit 330 can receive the level fixing command information from the high-speed communication circuit 320. In this case, the lock control circuit 330 can output the lock signal having a level fixed to the first level. On the other hand, in a case where any clock loss occurs due to electrostatic discharge (ESD) after the high-speed communication circuit 320 receives the level fixing command signal, the signal processing of the high-speed communication circuit 320 can be abnormally performed.

[0109] In this case, the high-speed communication circuit 320 can not completely receive the fixing release command signal or can not process the fixing release command signal into the fixing release command information.

[0110] At this time, the lock control circuit 330 can receive the high-speed communication state signal CDR_L, which is at a low level, from the high-speed communication circuit 320. Then, the lock control circuit 330 can change the lock signal from the fixed first level to the second level according to the level change of the high-speed communication state signal CDR_L, and output the same.

[0111] In other words, when the locking control circuit 330 fixes the level of the locking signal to the first level through the level fixing command information, and the locking control circuit 330 only receives the low-level high-speed communication status signal CDR_L but does not receive the fixation release command information, the locking control circuit 330 can ignore the level fixing command information and change the level of the locking signal to the second level for output. Here, if the first level is high, the second level can be low.

[0112] According to the embodiment, when one of the low-speed communication circuit 310 and the high-speed communication circuit 320 is activated while the other is deactivated, the locking control circuit 330 can receive only the status signal CMD_L or CDR_L of the activated circuit and output a locking signal using only the status signal of the activated circuit.

[0113] For example, when the low-speed communication circuit 310 is activated and the high-speed communication circuit 320 is deactivated, the locking control circuit 330 can receive the low-speed communication status signal CMD_L from the low-speed communication circuit 310 only, and output a locking signal with the same level as the low-speed communication status signal CMD_L.

[0114] The communication control circuit 340 can control the low-speed communication circuit 310 and the high-speed communication circuit 320.

[0115] Specifically, the communication control circuit 340 can set the setting values ​​of the components included in the high-speed communication circuit 320 based on the setting value data sent from the low-speed communication circuit 310.

[0116] The high-speed communication circuit 320 receives including Figure 5 In the case of a test signal with clock TR_CLK, the communication control circuit 340 can change the setting value of the oscillator included in the clock recovery circuit 420 at predetermined intervals. For this purpose, the communication control circuit 340 can store multiple setting values ​​for the oscillator. Whenever the oscillator setting value is changed at each predetermined interval, the communication control circuit 340 can check the training result of the test signal's clock TR_CLK via the low-speed communication circuit 310 at each predetermined interval, and determine the optimal setting value for the frequency (i.e., the frequency of the image data signal) used for high-speed communication based on the training result at each predetermined interval.

[0117] In other words, before receiving image data signals from the high-speed communication circuit 320, the communication control circuit 340 can optimize the settings of the clock recovery circuit 420 included in the high-speed communication circuit 320 based on the frequency of the image data signal. Here, the optimized settings can be the settings of the oscillator, and can include one of the oscillator's reference current value, reference voltage value, and gain adjustment value. When the high-speed communication circuit 320 receives image data signals such as...Figure 6 With the EQ training signal as shown, the communication control circuit 340 can change the configuration of the equalizer 410 in each time interval Tp according to a plurality of EQ setting values during a plurality of time intervals in which the high-speed communication circuit 320 receives the EQ training signal. Here, each EQ setting value of the plurality of EQ setting values can include a gain level of the equalizer 410, and can also include a tap coefficient of the equalizer 410. The plurality of EQ setting values can be included in the setting value data, and the communication control circuit 340 can extract the plurality of EQ setting values from the previously stored setting value data to change the configuration of the equalizer 410 in each time interval Tp.

[0118] On the other hand, when the high-speed communication circuit 320 receives the status response command signal while receiving the image data signal, the communication control circuit 340 can receive the status response command information from the high-speed communication circuit 320. In this way, the communication control circuit 340 can generate operation state data related to an operation state inside the data driving device 120. Here, the operation state data can include the setting value data transmitted from the low-speed communication circuit 310, the setting value of the clock recovery circuit 420 optimized in the pre-clock training interval, and the setting value of the equalizer 410 optimized in the EQ training interval. The operation state data can also include the number of decoding errors related to the image data signal, the frame control data included in the frame control signal, etc. In the case where the data processing device 140 encodes the image data signal using 8B10B code, the number of decoding errors can be the number of errors when the image data signal is decoded using 8B10B code. The communication control circuit 340 can calculate a checksum of the operation state data after generating the operation state data, and include the checksum in a header area of the operation state data.

[0119] In other words, the operation state data can also include the checksum.

[0120] When the operation state data is generated, the communication control circuit 340 can output an operation control signal of a high level to the encoder 350 and the signal selection circuit 360.

[0121] In addition, the communication control circuit 340 can transmit the operation state data to the encoder 350.

[0122] Here, the communication control circuit 340 can generate the operation state data only once.

[0123] The communication control circuit 340 can also repeatedly generate the operation state data during a predetermined time.

[0124] For example, in the case where the high-speed communication circuit 320 receives the status response command signal while receiving the image data signal as shown in FIG. 6, the communication control circuit 340 can generate the operation state data in the time interval Tp2. Figure 8In a case where a state response command signal is received in the frame control section between the illustrated one frame (n-1th frame) and the other frame (nth frame), the communication control circuit 340 can generate N (N is a natural number) pieces of operation state data from immediately after the state response command signal is received until another frame control section disposed after the nth frame. The communication control circuit 340 can receive a response end command from the high-speed communication circuit 320 in the frame control section disposed after the nth frame. With the response end command, the communication control circuit 340 can end the generation of the operation state data.

[0125] In addition, the communication control circuit 340 can output a low-level operation control signal to the encoder 350 and the signal selection circuit 360.

[0126] In a case where the encoder 350 receives a high-level operation control signal from the communication control circuit 340, the encoder 350 can be activated.

[0127] Subsequently, the encoder 350 can encode the operation state data transmitted from the communication control circuit 340 into an operation state signal. Here, the encoder 350 can encode the operation state data into the operation state signal using Manchester code. When the operation state data is encoded using Manchester code, as illustrated in Figure 9A and Figure 9B The operation state signal can have a pulse change in each bit, and this can achieve easy recognition of synchronization timing in the data processing apparatus 140 that is a receiving side. For example, if a data bit corresponding to a binary digit "0" is repeated, or even if a data bit corresponding to a binary digit "1" is repeated, a voltage level can change at a middle position of each data bit. Figure 9A Figure 9B Thus, even when the transmission frequency of the data driving apparatus 120 changes, the data processing apparatus 140 can easily recognize synchronization timing in the operation state signal encoded using Manchester code.

[0128] Such an operation state signal can include a preamble in which Manchester code corresponding to any one of binary digits is repeated M times (M is a natural number equal to or greater than 2), a start bit disposed after the preamble, operation state data disposed after the start bit, and an end bit disposed after the operation state data.

[0129] In a case where the communication control circuit 340 generates the operation state data only once, the operation state signal encoded by the encoder 350 can be as illustrated in

[0130] Figure 7 ​​As shown in FIG. 4, the operation state signal encoded by the encoder 350 can be output to the logic gate 370 through the signal selection circuit 360. Figure 8 As shown in FIG. 4, the operation state signal encoded by the encoder 350 can be output to the logic gate 370 through the signal selection circuit 360.

[0131] In a case where the encoder 350 receives the operation control signal of the low level from the communication control circuit 340 after encoding the operation state data, the encoder 350 can be deactivated.

[0132] When only the lock signal is received from the lock control circuit 330, the signal selection circuit 360 can output the lock signal to the logic gate 370. Here, the lock signal can have the first level.

[0133] When the operation state signal from the encoder 350 and the lock signal from the lock control circuit 330 are received, the signal selection circuit 360 can output the operation state signal to the logic gate 370 through the control of the communication control circuit 340.

[0134] In other words, in a case where the signal selection circuit 360 receives the operation control signal of the low level from the communication control circuit 340, the signal selection circuit 360 can select the signal input and output path with respect to the lock control circuit 330.

[0135] In a case where the signal selection circuit 360 receives the operation control signal of the high level from the communication control circuit 340, the signal selection circuit 360 can select the signal input and output path with respect to the encoder 350. The signal selection circuit 360 can be a multiplexer for selecting one of a plurality of input signals to output it.

[0136] The logic gate 370 can transmit the lock signal of the first level to the second communication line LN2 connected to its output terminal, and subsequently transmit the operation state signal to the second communication line LN2 connected to its output terminal.

[0137] In other words, when the logic gate 370 receives the lock signal of the first level from the signal selection circuit 360 through one of its input terminals, and receives the lock signal of the first level from the external device through the second communication line LN2 connected to the other input terminal thereof, the logic gate 370 can perform a logical operation on the lock signal of the first level and the lock signal from the external device, and transmit the lock signal of the first level obtained through the logical operation to the second communication line LN2 connected to its output terminal.

[0138] When the logic gate 370 receives the operation state signal from the signal selection circuit 360 through one input terminal thereof and receives the lock signal of the first level from the external device through the second communication line LN2 connected to the other input terminal thereof, the logic gate 370 can perform a logical operation on the operation state signal and the lock signal of the first level from the external device, and transmit a signal obtained by the logical operation to the second communication line LN2 connected to the output terminal thereof. Here, the first level can be high, and the lock signal of the first level from the external device can be transmitted from a logic gate of another adjacent data driving device. The logic gate 370 can be an AND gate for performing an AND operation.

[0139] When the first level is low, the logic gate 370 can be an OR gate for performing an OR operation. When the logic gate 370 receives the operation state signal from the signal selection circuit 360 through one input terminal thereof and receives the lock signal of the second level from the external device through the second communication line LN2 connected to the other input terminal thereof, the logic gate 370 can perform a logical operation on the operation state signal and the lock signal of the second level from the external device, and transmit the lock signal of the second level from the external device obtained by the logical operation to the second communication line LN2 connected to the output terminal thereof. Here, the second level can be low.

[0140] Thus far, the configuration of the data driving device 120 has been described.

[0141] Hereinafter, the configuration of a system according to an embodiment will be described.

[0142] Referring to Figure 3 , each of the data processing device 140 and the plurality of data driving devices 120a, 120b, 120c, 120d can be connected in a point-to-point manner through the first communication line LN1.

[0143] The data processing device 140 can transmit image data signals to the plurality of data driving devices 120a, 120b, 120c, 120d, respectively, through the first communication line LN1, and can sequentially check the states of the plurality of data driving devices 120a, 120b, 120c, 120d while transmitting the image data signals.

[0144] For example, in order for the data processing device 140 to check the operation state of the data driving device 120c according to a predetermined order while transmitting the image data signals to the plurality of data driving devices 120a, 120b, 120c, 120d, respectively, the data processing device 140 can transmit the image data signal to the data driving device 120c through the first communication line LN1 while the data driving device 120c is in the operation state, and can transmit the image data signal to the data driving device 120c through the first communication line LN1 while the data driving device 120c is in the non-operation state. Figure 7 or Figure 8The illustrated frame control section CTR after the nth-1 frame transmits a state response command signal to the data driving device 120c. Here, the data processing device 140 can transmit the state response command signal to the data driving device 120c through the first-1 communication line LN1-1 (the first-1 communication line LN1-1 is the first communication line LN1 connected to the data driving device 120c).

[0145] At this time, the data processing device 140 can transmit a level fixing command signal to the other data driving devices 120a, 120b, and 120d instead of the state response command signal.

[0146] The other data driving devices 120a, 120b, and 120d that have received the level fixing command signal can fix the lock signal to be transmitted through the second communication line LN2 to the first level. Here, the first level can be high.

[0147] The data driving device 120c that has received the state response command signal from the data processing device 140 can generate an operation state signal including operation state data indicating an internal operation state thereof. Here, the operation state signal can be a signal encoded using Manchester code.

[0148] Subsequently, the data driving device 120c can transmit the operation state signal instead of the lock signal of the first level that has been transmitted in the past through the second-1 communication line LN2-1 connected to the other data driving device 120d. Here, the data driving device 120c can also receive the lock signal of the first level from the other data driving device 120b, perform a logical operation on the operation state signal and the lock signal of the first level, and transmit the operation state signal obtained by the logical operation through the second-1 communication line LN2-1. According to an embodiment, the logical operation can be an AND operation or an OR operation.

[0149] According to an embodiment, when the data driving device 120c transmits the operation state signal through the second-1 communication line LN2-1, the other data driving device 120d can fix the lock signal to the first level by the level fixing command signal received from the data processing device 140.

[0150] In this state, the data driving device 120d can perform a logical operation on the operation state signal received from the data driving device 120c through the second-1 communication line LN2-1 and its own lock signal.

[0151] In this manner, the data driving device 120d can transmit the operation state signal of the data driving device 120c through the second-2 communication line LN2-2.

[0152] The data processing device 140 can check the operation state by receiving the operation state signal of the data driving device 120c through the 2-2 communication line LN2-2 and processing the operation state signal into operation state data, and store the operation state data of the data driving device 120c.

[0153] Here, the operation state data can include a set value of the clock recovery circuit 420 optimized in the pre-clock training interval and a set value of the equalizer 410 optimized in the EQ training interval. In addition, the operation state data can further include the number of decoding errors of the image data signal, frame control data included in the frame control signal, etc.

[0154] According to an embodiment, in a case where the operation state data further includes a checksum, the data processing device 140 can determine whether there is any error in the operation state data using the checksum.

[0155] In a case where the data processing device 140 determines an error of the operation state data using the checksum, the data processing device 140 can transmit the state response command signal to the data driving device 120c again, and transmit the level fixing command signal to the data driving devices 120a, 120b, 120d.

[0156] On the other hand, in a case where the operation state signal includes a plurality of operation state signals, each operation state signal includes a preamble, a start bit, operation state data, and an end bit, and is repeated N times, as shown in Figure 8 And the operation state data includes the number of decoding errors, the data processing device 140 can check the decoding error rate of the image data signal transmitted to the data driving device 120c in real time, and thus, can perform an operation for reducing the decoding error rate of the image data signal. For example, when encoding the image data signal, the data processing device 140 can apply an encoding method to reduce the decoding error rate.

[0157] In this way, the data processing device 140 can check and store the operation state data of each of the plurality of data driving devices 120a, 120b, 120c, 120d.

[0158] When the display device 100 is being driven, after the data processing device 140 has stored the operation state data of each of the plurality of data driving devices 120a, 120b, 120c, 120d, when any clock loss occurs due to electrostatic discharge (ESD) in at least one of the plurality of data driving devices 120a, 120b, 120c, 120d, the lock signal received by the data processing device 140 can have a second level. In this case, the data processing device 140 and the plurality of driving devices 120a, 120b, 120c, 120d need to perform a clock recovery process. Here, the clock recovery process can meanFigure 5 or Figure 6 the processing from the preamble interval in the command mode interval to the link training interval in the display mode interval.

[0159] According to the embodiment, during the clock recovery processing, the data processing apparatus 140 can include the optimal setting value of the clock recovery circuit 420 (included in the operation state data of the corresponding data driving apparatus) and the optimal value of the equalizer 410 in the setting value data, and transmit such setting value data to the corresponding data driving apparatus in the command mode interval. In this way, the pre-clock training interval and the EQ training interval can be omitted during the clock recovery processing.

[0160] On the other hand, in the case where any clock loss occurs in at least one of the remaining data driving apparatuses 120a, 120b, 120d that respectively receive the level fixing command signal due to ESD or the like, the at least one data driving apparatus can not normally receive signals from the data processing apparatus 140 and can not normally process the signals, and thus, can not normally perceive the fixing release command signal.

[0161] In this case, even when there is clock loss, the at least one driving apparatus can maintain the lock signal fixed at the first level, and thus, the data processing apparatus 140 can not recognize that there is an abnormality in the at least one data driving apparatus.

[0162] According to the embodiment, in order to prevent such a case, in the case where any clock loss occurs in at least one of the remaining data driving apparatuses 120a, 120b, 120d that respectively receive the level fixing command signal, the at least one data driving apparatus can ignore the level fixing command signal and change the level of the lock signal to the second level.

[0163] Here, the data processing apparatus 140 can not receive the operation state signal from the one data driving apparatus 120c, but can receive the lock signal of the second level from another data driving apparatus 120d.

[0164] In this case, the data processing device 140 can transmit reset signals to the plurality of data driving devices 120a, 120b, 120c, 120d through the first communication line LN1, each of the reset signals being maintained at the first level or the second level during a predetermined time. In this way, the data processing device 140 and the plurality of data driving devices 120a, 120b, 120c, 120d can perform the clock recovery process. Here, the data processing device 140 can sequentially transmit the reset signals to the plurality of data driving devices 120a, 120b, 120c, 120d, respectively. According to an embodiment, in a case where the data processing device 140 initially transmits the status response command signal to one data driving device 120c and does not receive the operation state signal of the one data driving device 120c within a predetermined time, the data processing device 140 can transmit the status response command signal to the one data driving device 120c at least one more time.

[0165] In a case where the data processing device 140 does not receive the operation state signal from the data driving device 120c even after transmitting the status response command signal to the data driving device 120c at least one more time, the data processing device 140 can transmit the reset signal as described above to the plurality of data driving devices 120a, 120b, 120c, 120d to perform the clock recovery process in the plurality of data driving devices 120a, 120b, 120c, 120d.

[0166] As described above, since the data processing device 140 can check the operation state of each of the data driving devices 120a, 120b, 120c, 120d when driving the display device 100, the data processing device 140 can efficiently manage the plurality of data driving devices 120a, 120b, 120c, 120d.

[0167] Hereinafter, data transmission and reception processing of one data driving device 120c of the plurality of data driving devices 120a, 120b, 120c, 120d, which receives the status response command signal from the data processing device 140, will be described.

[0168] Figure 10 is a flowchart illustrating processing of transmitting and receiving data by a data driving device according to an embodiment. The one data driving device 120c can receive an image data signal through a 1-1 communication line (the 1-1 communication line is the first communication line) connected with the data processing device 140 (S1010). Here, the image data signal can be divided by frame.

[0169] When the image data signal is received, the one data driving device 120c can transmit a lock signal of a predetermined level (i.e., a first level) through the 2-1 communication line (S1020). Here, the first level can be high. The one data driving device 120c can receive a status response command signal from the data processing device 140 while receiving the image data signal by frame (S1030). The one data driving device 120c can receive the status response command signal in a frame control interval disposed between one frame and another frame of the image data signal.

[0170] The one data driving device 120c that has received the status response command signal can generate an operation status signal including operation status data related to its internal operation, and transmit the operation status signal instead of the lock signal of the predetermined level through the 2-1 communication line (S1040). Here, the operation status signal can be a signal encoded using a Manchester code.

[0171] After S1040, the one data driving device 120c can transmit the lock signal of the predetermined level through the 2-1 communication line again (S1050).

[0172] According to an embodiment, before S1010, the one data driving device 120c can optimize a set value of a clock recovery circuit included in a high-speed communication circuit that receives the image data signal according to a frequency of the image data signal. Here, the optimized set value of the clock recovery circuit can include one of a reference current value, a reference voltage value, and a gain adjustment value of an oscillator included in the clock recovery circuit, and the operation status data can include the optimized set value of the clock recovery circuit.

[0173] Before S1010, the one data driving device 120c can optimize a set value of an equalizer 410 included in the high-speed communication circuit according to a characteristic of the 1-1 communication line. Here, the optimized set value of the equalizer can include a gain level of the equalizer, and the operation status data can include the optimized set value of the equalizer.

[0174] In S1040, the one data driving device 120c can repeatedly generate and transmit the operation status signal during a predetermined time.

[0175] In S1050, the one data driving device 120c can receive a response end command signal in another frame control section after the above-described frame control section. The one data driving device can stop generating and transmitting the operation state signal by the response end command signal, and transmit the lock signal of the predetermined level again. In S1040, the one data driving device 120c can perform an AND operation on the lock signal of the predetermined level and the operation state signal received from the external device (for example, another data driving device 120b), and transmit the operation state signal obtained by the AND operation through the 2-2 communication line.

[0176] CROSS-REFERENCE TO RELATED APPLICATIONS

[0177] This application claims priority to Korean Patent Application No. 10-2020-0072284, filed on June 15, 2020, the entire contents of which are incorporated herein by reference.

Claims

1. A driving method for a data driving device, comprising: The image receiving step is used to receive image data signals from the data processing device via a first communication line; The first transmission step is used to transmit a lock signal of a predetermined level via the second communication line; The command receiving step is used to receive a status response command signal from the data processing device when receiving the image data signal; as well as The second transmission step involves transmitting an operation status signal instead of a predetermined level lock signal via the second communication line. The operation status signal includes operation status data representing the internal operation status of the data driving device. The data driving device is connected to the data processing device via another data driving device.

2. The driving method according to claim 1, further comprising the following steps before the image receiving step: The settings of the clock recovery circuit included in the circuit used to receive the image data signal are optimized based on the frequency of the image data signal.

3. The driving method according to claim 2, wherein, The optimized settings include any one of the reference current value, reference voltage value, and gain adjustment value of the oscillator included in the clock recovery circuit, and the operating status data includes the optimized settings.

4. The driving method according to claim 1, further comprising the following steps before the image receiving step: The settings of the equalizer included in the circuit for receiving the image data signal are optimized based on the characteristics of the first communication line.

5. The driving method according to claim 4, wherein, The optimized settings include the gain level of the equalizer, and the operating status data includes the optimized settings.

6. The driving method according to claim 1, wherein, In the command receiving step, the data driving device receives the image data signal frame by frame, and receives the status response command signal in the frame control interval between one frame and another.

7. The driving method according to claim 6, wherein, The data driving device repeats the second transmission step N times immediately after receiving the status response command signal until the start of another frame control interval, and then transmits a lock signal of a predetermined level again through the second communication line, where N is a natural number.

8. The driving method according to claim 1, wherein, In the second transmission step, the data driving device uses Manchester code to encode the operation status data into the operation status signal.

9. The driving method according to claim 8, wherein, The operation status signal includes a preamble, a start bit arranged after the preamble, operation status data arranged after the start bit, and an end bit arranged after the operation status data, wherein in the preamble, the Manchester code corresponding to any binary digit is repeated M times, where M is a natural number equal to or greater than 2.

10. The driving method according to claim 1, wherein, In the second transmission step, the data driving device performs an AND operation on the operation status signal and a predetermined level lock signal received from an external device, and transmits the operation status signal obtained through the AND operation via the second communication line.

11. A data-driven device, comprising: A communication circuit is configured to receive image data signals from a data processing device via a first communication line, receive a status response command signal from the data processing device when receiving the image data signals, and process the status response command signal into status response command information. A locking control circuit is used to output a first-level locking signal when the communication circuit receives the image data signal; as well as A logic gate is used to send an operation status signal related to the operation status of the communication circuit, instead of the first-level lock signal, via a second communication line connected to the output terminal, when the status response command information is received from the communication circuit. The data driving device is connected to the data processing device via another data driving device.

12. The data driving device of claim 11 further includes a signal selection circuit, the signal selection circuit being configured to output a first-level lock signal to the logic gate when only a first-level lock signal is input, and to output the operation status signal to the logic gate when the operation status signal and the first-level lock signal are input.

13. The data driving device according to claim 12, wherein, The logic gate is an AND gate, wherein when the operation status signal is received from the signal selection circuit via the input terminal and a lock signal of the first level is received from an external device via a second communication line connected to another input terminal, the AND gate performs an AND operation on the operation status signal and the lock signal, and transmits the operation status signal obtained by the AND operation via the second communication line connected to the output terminal.

14. The data driving device according to claim 12, wherein, The logic gate is an AND gate, wherein when the operation status signal is received from the signal selection circuit via the input terminal and a second-level lock signal is received from an external device via a second communication line connected to another input terminal, the AND gate performs an AND operation on the operation status signal and the lock signal, and sends the lock signal obtained by the AND operation via the second communication line connected to the output terminal.

15. The data driving device according to claim 11, further comprising a communication control circuit, wherein, The communication circuit includes a clock recovery circuit and an equalizer. The communication control circuit optimizes the setting value of the oscillator included in the clock recovery circuit according to the frequency of the image data signal before the communication circuit receives the image data signal, and optimizes the gain level of the equalizer according to the characteristics of the first communication line.

16. The data driving device according to claim 15, wherein, The operating status signal includes the oscillator setting value and the equalizer gain level.

17. A display device driving system, comprising: A first data driving device is configured to receive a first image data signal via a first-1 communication line, send a first lock signal via a second-1 communication line, and, in the event that a status response command signal is received while receiving the first image data signal, send an operation status signal instead of the first lock signal via the second-1 communication line to indicate the internal operation status of the first data driving device. A second data driving device is configured to receive a second image data signal via a first-second communication line, generate a second locking signal, receive a first locking signal via a second-first communication line, perform logical operations on the first locking signal and the second locking signal, transmit the signal obtained through the logical operations via a second-second communication line, receive the operation status signal via a second-first communication line, perform logical operations on the operation status signal and the second locking signal, and transmit the operation status signal obtained through the logical operations via a second-second communication line; and A data processing device is configured to transmit the first image data signal via a first-1 communication line, transmit the second image data signal via a first-2 communication line, transmit the status response command signal via a first-1 communication line, and subsequently receive the operation status signal via a second-2 communication line.

18. The display device driving system according to claim 17, wherein, When the status response command signal is sent through the 1-1 communication line, the data processing device sends a level fixing command signal through the 1-2 communication line to fix the level of the second locking signal.

19. The display device driving system according to claim 18, wherein, When the level-fixing command signal is received via the first-second communication line, the second data driving device fixes the level of the second locking signal to high.

20. The display device driving system according to claim 19, wherein, If an error occurs when receiving the second image data signal while the locking signal is fixed at a high level, the second data driving device changes the level of the second locking signal to low, performs a logical operation on the operation status signal and the low-level second locking signal, and transmits the low-level signal obtained through the logical operation through the 2-2 communication line.

Images